JP7125002B2 - Electronic component package manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing an electronic component package, which enables easy visual recognition of a fillet formed when the electronic component package is solder-mounted on a mounting substrate.

2. Description of the Related Art There is known a hollow electronic component package in which an electronic component such as a crystal oscillator is mounted and accommodated in a closed cavity, and metals and ceramics are used as materials thereof. When metal is used as the package material, leads are provided to connect the inside and outside of the package on a metal substrate, electronic components are mounted on the substrate, and a metal cap is soldered or welded to form a package. In addition, when ceramic is used as a package material capable of further reducing the height, through holes filled with metal paste for forming through electrodes that connect the inside and outside of the package and cavities for housing electronic components are formed. A laminate of green sheets having through holes and the like is fired to form a ceramic substrate having through electrodes. After that, external electrodes connected to the through electrodes are formed, electronic components are mounted on the ceramic substrate, and the package is formed by sealing with a metal cap or the like. In some cases, the through electrodes are formed by firing a laminate of green sheets, forming through holes, and filling the through holes with metal.

When these electronic component packages are mounted on a mounting board, the external electrodes formed on the surface of the package and the electrodes formed on the mounting board such as a printed wiring board are connected by soldering or the like to electrically connect the mounting board with the mounting board. Connected.

FIG. 17 shows a sectional view of a mounting structure of a conventional electronic component package. In a conventional electronic component package, wiring (not shown) formed on a mounting substrate 62 and external electrodes 64 of an electronic component 65 are connected using solder 63 . The external electrodes 64 are connected to internal electrodes 67 that are connected to the electronic component 65 via through electrodes 66 .

JP 2017-034328 A

By the way, as a method of forming a through-electrode for electrically connecting an electronic component or the like mounted in the cavity to an external electrode, a paste-like conductive material is filled in the through-hole by a screen printing method, and then the through-electrode is formed. There is a method of sintering. However, if air is entrapped or an unfilled region is generated when the paste-like conductive material is filled into the through-hole, a space will be formed in the through-electrode after sintering, which will reduce the reliability of the through-electrode. cause.

In addition, a conductive seed layer is formed on the surface of the through hole that opens on the package surface in which the through hole is formed, and the through hole is filled with a conductive material such as copper from the opening of the through hole using an electrolytic plating method. Thus, methods for forming through electrodes are known. However, since the through-holes extending from the front surface to the back surface of the package are deep, filling the through-holes with a conductive material by electroplating takes a long time, resulting in a decrease in productivity. In addition, an unfilled portion is generated in the through electrode, which also causes a decrease in the reliability of the through electrode.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an electronic component package which solves the above-mentioned problems and which can be made low-profile and which allows easy visual confirmation of bonding to a mounting substrate.

To achieve the above object, a method for manufacturing an electronic component package according to claim 1 of the present application provides an electronic component package having a silicon substrate, a cavity, a through electrode, and an external electrode connected to the through electrode, wherein the first silicon substrate is forming a first concave portion for forming the external electrode on one surface of the first silicon substrate; and forming the four adjacent electrons on the bottom of the first concave portion. forming four through-holes for forming the through-electrodes in each component package ; forming the through-electrodes in the through-holes; forming the through-electrodes in the through-holes; forming the external electrode continuous with part of the surface of the silicon substrate; preparing a second silicon substrate; forming the cavity in at least one of the first silicon substrate and the second silicon substrate; forming a cavity substrate having a storage cavity for forming a; mounting an electronic component on at least one of the first silicon substrate and the second silicon substrate; and forming an electronic component package substrate containing the electronic components in the cavity by joining the second silicon substrate and the four through electrodes formed in the bottom portion of the first concave portion; and a step of cutting the electronic component package substrate into pieces in a grid pattern at positions passing through the respective spaces .

A method of manufacturing a semiconductor device according to claim 2 of the present application is the method of manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate includes: The step is characterized by forming the storage cavity.

A method for manufacturing a semiconductor device according to claim 3 of the present application is the method for manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate is a step of forming the storage cavity in the second silicon substrate. It is characterized by

A method for manufacturing a semiconductor device according to claim 4 of the present application is the method for manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate includes forming the first silicon substrate having the first concave portion. forming another storage cavity on the surface of the second silicon substrate; and forming the cavity by each of the storage cavities.

According to the present invention, an existing method for manufacturing a semiconductor device can be used to manufacture an electronic component package using a silicon substrate. As a result, there is an advantage that a manufacturing method suitable for mass production can be provided rather than the conventional manufacturing method of electronic component packages. Furthermore, there is also the advantage that an electronic component package can be formed in which the fillet formed at the connecting portion of the external electrode can be easily visually recognized.

In particular, according to the present invention, the depth of the through-hole for forming the through-electrode is shallower than the thickness of the silicon substrate, and the conductive material does not remain unfilled in the through-hole, thereby improving the reliability of the through-hole. There is also the advantage that it is possible to prevent deterioration of the properties.

1 is a cross-sectional view of an electronic component package according to a first embodiment of the present invention; FIG. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 1st Example of this invention. 1 is a perspective view of an electronic component package according to an embodiment of the present invention; FIG. It is a figure explaining a mode that the electronic component package of the 1st Example of this invention was mounted in the mounting board. It is a figure explaining the manufacturing process of the electronic component package of the 2nd Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 2nd Example of this invention. It is a figure explaining the manufacturing process of the electronic component package of the 2nd Example of this invention. FIG. 4 is a cross-sectional view of an electronic component package according to a second embodiment of the present invention; It is a figure explaining the manufacturing process of the electronic component package of the 3rd Example of this invention. FIG. 5 is a cross-sectional view of an electronic component package according to a third embodiment of the present invention; 1 is a cross-sectional view of a mounting structure of a conventional electronic component package; FIG.

The method for manufacturing an electronic component package according to the present invention includes bonding a cavity substrate in which a recess serving as a cavity is formed in a silicon substrate and a lid substrate in which a recess is not formed in a silicon substrate, or bonding a cavity substrate and a cavity substrate to form a cavity. This is a method of collectively manufacturing a plurality of electronic component packages at the wafer level by mounting electronic components on the wafer and having through electrodes. Particularly, in the present invention, the formation of the through electrodes is facilitated by thinning the cavity substrate or the lid substrate on which the through electrodes are formed. Furthermore, by forming the external electrodes on the stepped portion formed on the surface of the electronic component package, the fillets formed on the connection portions of the external electrodes can be easily visually recognized even after mounting. Examples of the present invention will be described in detail below.

First, with regard to the first embodiment of the present invention, a method of manufacturing an electronic component package is taken as an example, in which a cavity substrate in which through electrodes and recesses serving as cavities are formed and a lid substrate on which electronic components are mounted are adhered and separated into individual pieces. , will be described in detail.

FIG. 9 is an explanatory diagram of the appearance of an electronic component package 50 formed by the manufacturing method of the present invention. The four corners of the surface of the first silicon substrate 1 of the electronic component package 50 are notched to form external electrodes 7 with stepped portions.

FIG. 1 is a cross-sectional view of a first electronic component package 51 schematically showing a cross section along a diagonal line of the electronic component package shown in FIG. In FIG. 1 , the external electrodes 7 connected to the through electrodes 6 are recessed inward from the surface of the first electronic component package 51 . Also, the first silicon substrate 1 (cavity substrate) having the first storage cavity 25 a and the second silicon substrate 11 (lid substrate) are connected by the first bonding portion 9 formed on the first silicon substrate 1 . and the second bonding portion 14 formed on the second silicon substrate 11, the first cavity 8a is formed. A second metal wiring 10a is arranged in the first cavity 8a, and a first electronic component 15a is mounted on the second metal wiring 10a.

FIG. 2 is an explanatory view showing the manufacturing method of the first cavity substrate. First, a first silicon substrate 1 having a thickness of 320 μm is prepared. A first insulating film 2 and a second insulating film 3 are formed on both surfaces of the first silicon substrate 1 . The first insulating film 2 and the second insulating film 3 are, for example, silicon oxide films formed by thermal oxidation (FIG. 2a).

Subsequently, according to a general photolithography process, a resist is formed on the surface of the first insulating film 2, and patterning is performed by exposure and development to form a mask that exposes the surface of the first silicon substrate 1 (Fig. omit). Using this mask, the first insulating film 2 is partially removed by dry etching to expose the surface of the first silicon substrate 1 . After that, the first recess 21 is formed by removing the exposed first silicon substrate 1 to a predetermined depth (for example, 160 μm) using a dry etching method (FIG. 2b).

Subsequently, according to a general photolithography process, a resist is formed on the surface of the first recess 21 and the surface of the first insulating film 2, and the bottom of the first recess 21 is patterned by exposure and development. A mask that partially exposes is formed (not shown). A dry etching method such as DRIE (Deep Reactive Ion Etching) is applied to the first silicon substrate 1 exposed in the openings of this mask to form the second insulating film 3 on a part of the bottom of the first concave portion 21 . A plurality of first openings 22 are formed by removing until exposed. The first openings 22 are formed as regions for forming through electrodes 6, which will be described later, and a part of the first silicon substrate 1 remaining between the adjacent first openings 22 is divided into individual pieces. It becomes the area to be removed (Fig. 2c).

Subsequently, a first insulating film 2 surface, a second insulating film 3 surface, and a surface of the first silicon substrate 1 exposed on the surface of the first recess 21 or the first opening 22 are subjected to the first etch. 3, an insulating film 4 is formed. The third insulating film 4 is, for example, a thermally oxidized silicon oxide film (FIG. 3a).

Next, a seed layer consisting of a laminated film of Ti (titanium) and Cu (copper) is formed on the surface by sputtering (not shown). At this time, Cr (chromium) or TiW (titanium tungsten) may be used instead of Ti, and AlSi (aluminum silicon) may be used instead of Cu. Furthermore, a first metal wiring 5 is formed on the seed layer. As a method for forming the first metal wiring 5, for example, either an electrolytic plating method or an electroless plating method may be used, but the electrolytic plating method is preferable in terms of throughput and cost. The plating metal used in the electrolytic plating method is selected from Au (gold), Cu (copper), Ni (nickel), Sn (tin), SnAg (tin-silver), AuSn (gold-tin), etc., and there are two types alone. You may mix above. In particular, since the first opening 22 is filled with the plating metal, either embedded plating or conformal plating may be used. The thickness of the first metal wiring 5 may be appropriately set so as not to break at the steps of the first recess 21 and the first opening 22 . The first metal wiring 5 filled in the first opening 22 becomes the through electrode 6 (FIG. 3b).

Subsequently, according to a general photolithography process, a resist is formed on the surface of the first metal wiring 5, and patterning is performed by exposure and development processing, thereby opening at least the external electrode formation scheduled region described later, and the first metal wiring is formed. A mask is formed to expose a portion of the wiring 5 (not shown). Au is deposited on the exposed first metal wiring 5 by plating, and the mask is removed to form an external electrode 7 made of Au on a part of the surface of the first metal wiring 5 . The external electrode 7 intermittently covers the surface of the first metal wiring 5 and forms a second recess 23 . The bottom of the second recess 23 is connected to the through electrode 6 via the first metal wiring 5 (FIG. 4a).

Subsequently, according to a general photolithography process, a resist is formed on the surface of the external electrode 7 and the surface of the first metal wiring 5, and patterning is performed by exposure and development to form a mask covering the external electrode 7. (illustration omitted). A portion of the first metal wiring 5 and the seed layer exposed in the openings of this mask are removed to expose the third insulating film 4 in the openings of the mask. The etching method is not particularly limited as long as each metal can be removed (Fig. 4b).

Subsequently, in order to form the first storage cavity 25a, after turning the first silicon substrate 1 shown in FIG. 4, a resist is formed on the surface, and patterning is performed by exposure and development to form a mask (not shown) that opens the region where the first storage cavity 25a is to be formed. After that, a first storage cavity 25a is formed by removing a part of the third insulating film 4 and the first silicon substrate 1 exposed in the opening of this mask. The depth of the first storage cavity 25a may be about 100 μm, and the depth can be appropriately selected according to the height of the electronic components to be stored therein.
Next, according to a general photolithography process, another resist is formed on the surface of the third insulating film 4, and patterning is performed by exposure and development, thereby forming a mask for exposing the previously formed through electrodes 6. forming (not shown). Using this mask, dry etching is performed to selectively remove the third insulating film 4 exposed in the mask opening, thereby forming a second opening 24 exposing a part of the through electrode 6 at the bottom. (Fig. 5a).

Subsequently, in order to form the first joint portion 9 connected to the through electrode 6, a metal layer is laminated on the surface of the first silicon substrate 1 and the surface of the third insulating film 4, and the second opening portion 24 is formed. is filled with a metal layer (not shown). The metal layer may be a single layer or a multilayer consisting of a plurality of metal films. For example, Ti and Au are laminated in order from the substrate side.
Next, according to a general photolithography process, a resist is formed on the surface of the metal layer, and patterning is performed by exposure and development to form a mask covering the first junction formation planned region (not shown). Using this mask, the Au film and the Ti film are sequentially removed, and then the mask is removed to form the first junction 9 . As a result, the first cavity substrate 31 having the first bonding portion 9 is completed (FIG. 5b).

Next, a method for manufacturing the first lid substrate 32 will be described. A fourth insulating film 12 and a fifth insulating film 13 are formed on both surfaces of a second silicon substrate 11 . The fourth insulating film 12 and the fifth insulating film 13 are silicon oxide films formed by thermal oxidation, for example. Since the first lid substrate 32 is made of a silicon substrate, it is possible to form semiconductor elements on the second silicon substrate 11 . In that case, in order to form an electrode connected to the semiconductor element, a resist is formed on the surface of the fourth insulating film 12 according to a general photolithography process, and patterning is performed by exposure and development to connect to the semiconductor element. A mask is formed (not shown) that opens regions where electrodes are to be formed. Using this mask, a portion of the fourth insulating film 12 is removed to form a third opening 26 (FIG. 6a).

Subsequently, a metal film is laminated on the surface of the fourth insulating film 12 (not shown). As the metal film to be laminated, Ti and Au are laminated in order from the substrate side. This metal film is not limited to the above-described ones, and other metal films may be used, but the metal film of the outermost surface layer is preferably a metal that can form a good connection with the first cavity substrate 31 described above.
Next, according to a general photolithography process, a resist is formed on the surface of the metal film, and patterning is performed by exposure and development to form a mask covering the electrode forming region (not shown). Using this mask, the Au film and the Ti film are removed. When the mask is removed, the third opening 26 is filled, and the second junction 14 and the second junction 14 are formed on the surface of the fourth insulating film 12 . A second metal wiring 10a connected to the joint portion 14 is formed, and a first lid substrate 32 is formed. If no semiconductor element is formed on the second silicon substrate 11, a metal film may be formed on the fourth insulating film 12 (FIG. 6b).

Subsequently, the first electronic component 15a is connected to the second metal wiring 10a. The first electronic component 15a and the second metal wiring 10a are connected by soldering, for example (FIG. 6c).

FIG. 7 is a cross-sectional view of a first electronic component package substrate 41 in which the first cavity substrate 31 and the first lid substrate 32 are joined together.
As shown in FIG. 7, a first bonding portion 9 formed on a first silicon substrate 1 and a second bonding portion 14 formed on a second silicon substrate 11 are bonded together to form a first bonding. A silicon substrate 1 and a second silicon substrate 11 are bonded together. As the bonding conditions, temperature, pressure, time, etc. may be appropriately selected according to the metal species used for the first joint portion 9 and the second joint portion 14 .
By this bonding, the first electronic component 15a is housed in the first cavity 8a. Further, by arranging the first joint portion 9 and the second joint portion 14 so as to continuously surround the periphery of the first cavity 8a while maintaining necessary insulation, the first cavity 8a is sealed. becomes. If the first bonding portion 9 and the second bonding portion 14 are bonded together in a decompressed state, the first cavity 8a is in a decompressed state, thereby improving the reliability of the first electronic component 15a. can also

FIG. 8 is a diagram showing a method of manufacturing the first electronic component package 51 by cutting the first electronic component package substrate 41 and singulating into individual electronic component packages. Four through electrodes 6 are formed for each of the four electronic components adjacent to the bottom of the second concave portion 23, and the external electrodes 7 are cut in a grid pattern at positions passing through the respective portions, thereby forming the external electrodes 7 into the first electrodes. can be arranged at the four corners of the electronic component package 51 .
When separating into individual pieces, the surface of the fourth insulating film 12 of the first electronic component package substrate 41 is attached to a dicing tape 60 made of polyimide or the like, and the through electrodes in the second recesses 23 formed on the surface are applied. A dicing saw 61 may be used to cut a position passing between 6 . A dotted line in the drawing indicates the planned cutting area. The first electronic component package 51 is obtained by cutting and singulating.

When cutting the first electronic component package substrate 41, a dicing saw is used in the above embodiment, but a cutting method using a laser or the like may be used.

FIG. 10 is a cross-sectional view when the first electronic component package 51 according to the manufacturing method of the present invention is connected to the mounting substrate 62 using solder 63. As shown in FIG. When the external electrodes 7 are solder-connected to electrodes (not shown) formed on the surface of the mounting substrate 62, they are not only connected to the bottom surface of the external electrodes 7 (the portion connected to the mounting substrate 62 via solder), but also to the side surfaces of the external electrodes 7. The mounting substrate 62 is connected by the solder 63 creeping up on (the surface rising in the direction substantially perpendicular to the bottom surface of the external electrode 7). At this time, the solder 63 may crawl up to the upper surface of the external electrode 7 (the surface extending substantially perpendicularly to the side surface of the external electrode 7). Since the height of the side surface from the bottom surface to the top surface of the external electrode 7 is, for example, about 150 μm, connection can be made using a sufficient amount of solder. 63 fillets are readily visible. Of course, the height of the external electrodes 7 is not limited to the above, and can be changed as appropriate.

In this embodiment, by appropriately adjusting the height (depth) of the first storage cavity 25a of the first silicon substrate 1 and the thickness of the second silicon substrate 11, the first electronic component package 51 is It is possible to reduce the height.

Next, a second embodiment of the present invention will be described in detail, taking as an example a method of manufacturing an electronic component package in which through electrodes can be formed more easily. Note that the description of the portions overlapping the description of the first embodiment will be omitted.

11A and 11B are diagrams showing a method of manufacturing the second cavity substrate 33. FIG. First, a third opening 26 is formed in the fourth insulating film 12 in the same manner as in FIG. 5(a). A portion of the second silicon substrate 11 is exposed at the bottom of the third opening 26 . Furthermore, a third storage cavity 27 is formed in the second silicon substrate 11 . An insulating film (not shown) is formed on the surface of the third storage cavity 27 (FIG. 11a).

Subsequently, a conductive material is used inside the third opening 26, part of the surface of the third storage cavity 27, and part of the surface of the fourth insulating film 12 to form the second bonding part 14 and the second bonding part 14 together. 3 metal wirings 10b are formed, and a second cavity substrate 33 is formed. In this case the third opening 26 is not absolutely necessary (Fig. 11b).

Subsequently, the first electronic component 15a is connected to the third metal wiring 10b. The first electronic component 15a and the third metal wiring 10b are connected by soldering, for example (FIG. 11c).

Subsequently, a second lid substrate 34 is formed from the substrate shown in FIG. 4(b). After turning the substrate shown in FIG. 4B upside down, a second opening 24 is formed in the surface of the third insulating film 4 in the same manner as in Example 1, and then a second connecting portion 14 is formed. to form In this case, since the second lid substrate 34 is not formed with a concave portion that serves as a cavity, the thickness of the substrate can be made thinner than that of the first cavity substrate 31 prepared in the first embodiment. Therefore, the through electrode 6 of the second lid substrate 34 is shallower than the through electrode 6 of the second cavity substrate 33, and can be easily formed (FIG. 12).

FIG. 13 is a cross-sectional view of a second electronic component package substrate 42 in which the second cavity substrate 33 and the second lid substrate 34 are joined together.
The second electronic component package substrate 42 forms a second cavity 8b, a third metal wiring 10b formed in the second cavity 8b, and a first metal wiring 10b mounted on the third metal wiring 10b. The electronic component 15a is accommodated (FIG. 13).

Four through-electrodes 6 are formed in advance for four electronic components adjacent to the bottom of the second recess 23, and the external electrodes 7 are cut at positions passing between them in a grid-like manner so that the external electrodes 7 are formed at the four corners. is completed.

FIG. 14 is a cross-sectional view of the second electronic component package 52. As shown in FIG. The second electronic component package 52 has the through electrodes 6 arranged at the corners of the electronic component package and the external electrodes 7 directly below the through electrodes 6, like the first electronic component package 51 described in the first embodiment. Place some. The external electrode 7 has a concave shape, and the height of the external electrode 7 is preferably 100 to 150 μm so that the fillet when soldered to the mounting substrate can be visually recognized from the outside. In the second electronic component package 52, the first electronic component 15a is mounted on the third metal wiring 10b formed in the second cavity 8b. Moreover, since no storage cavity is formed in the first silicon substrate 1 constituting the second lid substrate 34 , the second lid substrate 34 can be formed thinner than the first lid substrate 32 . As a result, the depth of the through electrode 6 formed on the second lid substrate 34 can be made shallower than that of the first electronic component package 51, and the productivity of the through electrode 6 is improved.

When the second electronic component package 52 manufactured according to the second embodiment was connected to the mounting substrate by soldering, the fillets were easily visible as in the first embodiment.

In the third embodiment, an electronic component package in which electronic components are mounted on the first cavity substrate and the second cavity substrate respectively will be described. Note that descriptions of portions overlapping those of the first and second embodiments will be omitted.

First, the second cavity substrate 33 shown in the second embodiment is prepared. The first electronic component 15a to be mounted is referred to as the second electronic component 15b. The second electronic component 15b is not particularly limited, but preferably has a height that does not protrude from the surface of the fifth insulating film 13 when mounted on the third metal wiring 10b.

15A and 15B are diagrams showing a method of manufacturing the third cavity substrate 35. FIG. First, a first bonding portion is formed in the second opening 24 of the first silicon substrate 1, part of the surface of the first storage cavity 25a, and the surface of the third insulating film 4 shown in FIG. 5(a). 9 and a fourth metal wiring 10c are formed to form a third cavity substrate 35 having a second storage cavity 25b (FIG. 15a).

Subsequently, the third electronic component 15c is connected to the fourth metal wiring 10c. The third electronic component 15c is not particularly limited, but preferably has a height that does not protrude from the surface of the third insulating film 4 when mounted on the fourth metal wiring 10c (FIG. 15b).

FIG. 16 is a cross-sectional view of the third electronic component package 53. As shown in FIG. By bonding the first bonding portion 9 and the second bonding portion 14 together, the second cavity substrate 33 and the third cavity substrate 35 are bonded together, and a grid pattern is formed at positions passing between the through electrodes 6 . By cutting and dividing into pieces, the second electronic component 15b and the third electronic component 15c are mounted in the third cavity 8c, and the external electrodes 7 are arranged at the four corners of the package. A component package 53 is obtained. Since a large number of electronic components can be mounted in the third electronic component package 53, multi-functionalization is possible. In FIG. 16, the electrodes of the second electronic component 15b and the third electronic component 15c are connected to each other and lead to the external electrodes 7 via through electrodes. is not limited to

Of course, in the third electronic component package 53 as well, when soldered to the mounting board, the fillets were easily visible as in the first and second embodiments.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to these. For example, in Example 1, the first electronic component 15a was mounted on the second metal wiring 10a formed on the surface of the first lid substrate 32, but it was formed on the surface of the first storage cavity 25a. It does not matter even on metal wiring. In the second embodiment, the first electronic component 15a is the third metal wiring 10b formed on the bottom of the third housing cavity 27 formed on the surface of the second cavity substrate 33. A metal wiring formed on the surface of the substrate 34 may be used.

Further, as described above, semiconductor elements may be formed on either the surface of the first silicon substrate 1 or the surface of the second silicon substrate 11 as required. By forming a semiconductor element, not only an electronic component package containing the electronic component 15a but also an electronic component package having a semiconductor function can be obtained.

In the above-described embodiment, the external electrodes 7 are arranged at the four corners of the electronic component package by cutting in a lattice pattern at positions passing between the four through-hole electrodes 6 when dividing into individual pieces. Formation of a plurality of through electrodes 6 is not limited to the above. An electronic component package in which the external electrodes 7 are positioned at the center of each of the four sides of the rectangular electronic component package may be obtained by cutting in the direction perpendicular to the space.

1: first silicon substrate, 2: first insulating film, 3: second insulating film, 4: third insulating film, 5: first metal wiring, 6: through electrode, 7: external electrode, 8a: first cavity, 8b: second cavity, 8c: third cavity, 9: first junction, 10a: second metal wiring, 10b: third metal wiring, 10c: fourth Metal wiring 11: second silicon substrate 12: fourth insulating film 13: fifth insulating film 14: second junction 15a: first electronic component 15b: second electronic component , 15c: third electronic component, 21: first recess, 22: first opening, 23: second recess, 24: second opening, 25a: first storage cavity, 25b: second 2 storage cavity, 26: third opening, 27: third storage cavity, 31: first cavity substrate, 32: first lid substrate, 33: second cavity substrate, 34: second Lid substrate 35: third cavity substrate 41: first electronic component package substrate 42: second electronic component package substrate 50: electronic component package 51: first electronic component package 52: second electronic component package electronic component package, 53: third electronic component package, 60: dicing tape, 61: dicing saw, 62: mounting board, 63: solder

Claims (4)

An electronic component package having a silicon substrate, a cavity, a through electrode, and an external electrode connected to the through electrode,
providing a first silicon substrate;
forming a first concave portion for forming the external electrode on one surface of the first silicon substrate;
forming four through-holes for forming the through-electrodes of the four adjacent electronic component packages in the bottom of the first recess;
forming the through electrode in the through hole, and further forming the external electrode continuous with the through electrode, the surface of the first concave portion, and a part of the surface of the first silicon substrate;
providing a second silicon substrate;
forming a cavity substrate having a storage cavity for forming the cavity in at least one of the first silicon substrate and the second silicon substrate;
mounting an electronic component on at least one of the first silicon substrate and the second silicon substrate;
forming an electronic component package substrate housing the electronic component in the cavity by bonding the first silicon substrate and the second silicon substrate;
a step of cutting the electronic component package substrate in a grid pattern at positions passing between the four through electrodes formed in the bottom portion of the first recess to separate the electronic component package substrate;
A method of manufacturing an electronic component package, comprising: 2. The method of manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate is a step of forming the storage cavity in the first silicon substrate on which the first concave portion is formed. A manufacturing method for an electronic component package. 2. The method of manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate is a step of forming the storage cavity in the second silicon substrate. . 2. The method of manufacturing an electronic component package according to claim 1, wherein the step of forming the cavity substrate includes forming the storage cavity in the first silicon substrate having the first concave portion, and forming the storage cavity in the first silicon substrate. A method of manufacturing an electronic component package, comprising the steps of: forming separate storage cavities on the surface of a silicon substrate; and forming the cavities by the respective storage cavities.

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