JP6791735B2 - Phase tracking receiver - Google Patents

Description

The present invention generally relates to radio receivers, in particular to phase tracking receivers based on digital controlled oscillators (DCOs) that provide automatic frequency offset cancellation.

Constant envelope FSK / PSK modulation is widely adopted in wireless standards such as Zigbee® and Bluetooth® low energy due to its low hardware complexity and excellent interference resistance. ing. Traditional I / Q-based FSK / GFSK receivers use frequency demodulation techniques such as difference and multiplication, zero cross detection, and quadrature correlation.

These receivers are high power consumption, use several analog blocks, and their performance is compromised by technology scaling. Sliding IF-based receivers that partially reduce power consumption are prone to image removal problems. Phase region receivers are becoming a better choice for ultra-low power and low voltage radios.

In its locked state, the phase-locked loop (PLL) maintains a constant phase difference between the output of an oscillator, usually a voltage controlled oscillator (VCO), and a reference signal. In other words, the PLL oscillator tracks the frequency of the reference signal. This phase / frequency tracking operation of the PLL can be used for frequency demodulation and the control signal to the oscillator can be used directly as a demodulated frequency signal for subsequent processing.

The VCO-based phase tracking FSK / GFSK receiver uses the PLL modulator as another block at the end of the receiver chain before the analog-to-digital converter (ADC) converts the signal into the digital domain. Alternatively, it can be integrated with other receiver blocks such as mixers, lowpass filters and variable gain amplifiers. In these approaches, the RF input signal is generally low frequency converted (downconverted) to the appropriate intermediate frequency and its amplitude is limited before it is passed to the PLL for demodulation. The oscillator control signal in the PLL is then digitized for digital baseband (DBB) processing.

VCO-based phase tracking receivers have few architectural issues. First of all, the PLL demodulator uses a free-running oscillator to synchronize with the input RF signal, and the radio standard allows the RF input signal to have a certain amount of dynamic frequency offset during data transmission. These input frequency deviations due to low frequency drift due to the frequency instability of the free running oscillator greatly affect the carrier recovery during demodulation, resulting in a high bit error rate. Therefore, the phase tracking FSK receiver has insufficient frequency deviation tolerance.

Second, a strong source of interference pulls the oscillator away from the desired carrier frequency, reducing demodulation performance. This can be partially addressed by suppressing the interfering source with a higher order channel selection filter. However, the long delays provided by higher order filters reduce demodulation performance and loop stability.

Finally, a high resolution ADC or high precision threshold detector is needed to identify the FSK data.

In view of the above, an object of the present invention is to provide a receiver with reduced power consumption, improved frequency tolerance and interference elimination.

According to the first aspect of the present invention, a receiver is provided. The receiver comprises a phase detector having first and second inputs, the first input being adapted to receive a modulated input signal. The receiver includes a comparator that has an input coupled to the output of the phase detector. The receiver includes a frequency offset cancel block that includes an input coupled to the output of the comparator. The receiver includes a digitally controlled oscillator having a control input coupled to the output of the comparator and the output of the frequency offset cancel block, and an output coupled to the second input of the phase detector.

As described above, the present invention is based on the idea of providing a receiver having a demodulation loop including a comparator and an automatic frequency offset cancel (AFC) loop, wherein the comparator and the automatic frequency offset cancel (AFC) loop are provided. Both units of the (AFC) loop reduce power consumption by controlling the DCO and improve the frequency tolerance and interference elimination of the DCO-based phase tracking receiver. The different parts of the receiver described below (instead called "units", "devices", "circuits" and / or "components") are hardware, software, or a combination of both. Can be carried out. In addition, the term "integrated" as used throughout the detailed description is executed on an electronic circuit or processor integrated on one or more small plates ("chips") of semiconductor material (usually silicon). It is implemented in a software code part that is integrated in the form of a control program that provides the functionality of each receiver part disclosed when it is done.

The term "phase detector" means any unit, device, circuit and / or component capable of producing an output signal that represents the phase difference between at least two input signals. The phase detector may be adapted to receive an analog or square wave digital signal and produce an output signal that represents the difference frequency between the signals. The phase detector is sensitive only to the relative timing of the edges of the received input signal and produces an output signal that represents the phase difference between the input signals when both signals are at the same frequency.

The term "comparator" is used herein to compare the value of an analog or digital input signal with an analog or digital reference value and provide an output signal indicating whether the value of the input signal is greater than or equal to the reference value. Means any unit, device, circuit, and / or component that can. The reference value may be provided inside the comparator or may be supplied from an external source at the input of the comparator. Frequency offset cancellation is preferably automatic so that the operating frequency offset cancel block can perform its function, eg, without intervention by the user of the receiver. For simplicity, the frequency offset cancel block is referred to below as the automatic frequency offset cancel block (AFC). The term "digitally controlled oscillator" here means an oscillator adapted to provide an input for receiving a digitally tuned word and provide a signal to its output, said signal being at least partially by the digitally tuned word. Has a frequency determined by. As a generalized example, the digital tuning word may be logic "1" or logic "0", where the frequency at the output of the digital controlled oscillator is first when the digital tuning word is "1". It is assumed that the frequency is set to the second frequency when the digital adjustment word is "0". Each component of the receiver may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software, or a combination of both.

The DCO preferably oscillates at a particular frequency based on the output of the comparator to eliminate the non-linear effect of the DCO gain. The comparator provides a capture effect and suppresses interference in the received signal. Interference can come from strong signals at higher frequencies, eg, from adjacent and alternative channels, or in circuits where the signal propagates (eg, low noise amplifier (LNA) preceding the phase detector, phase detector). It may be derived from non-ideal properties within itself and / or DCO). Such non-linear characteristics generate harmonics in the input signal and act as an interference source for the desired signal. The AFC loop in the negative feedback configuration estimates the frequency deviation due to the input frequency offset and the instability of the oscillator frequency, and cancels it by changing the center frequency of the DCO accordingly. This configuration may provide a receiver with reduced complexity, reduced power consumption, improved frequency tolerance and improved interference elimination.

The input of the comparator can be coupled to the output of the phase detector via a low pass filter (LPF).

The low-pass filter may be an analog or digital filter. The digital filter comprises an analog-to-digital converter (ADC) or precedes the digital filter. The filter can be implemented in many different ways. As an example, the lowpass filter can be a passive or active first or higher order RC, RL or LC filter, a switched capacitor filter, an FIR filter or an IIR filter.

The low-pass filter can suppress any signal outside its bandwidth, where the bandwidth of the low-pass filter is preferably set to be equal to the bandwidth of the input modulated signal. This arrangement reduces the interference of the signal fed to the comparator, which facilitates accurate detection of the state / value of the modulated signal, thus providing a receiver with a more reliable detector of the input data. Is achieved. The low-pass filter may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software or a combination of both.

The frequency offset cancel block may include an integrator.

In general, the term "integrator" here means any unit, device, circuit, and / or component that can provide an output signal that represents the time integration of its input signal. The integrator may be a first or higher order IIR or FIR integrator. As an example, the integrator may be a forward rectangular integrator, a reverse rectangular integrator, a trapezoidal integrator or a Simpson integrator. The integrator may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software or a combination of both.

The integrator facilitates the extraction of unwanted low frequency components from the comparator output, which are used to determine the residual frequency error / deviation within the loop.

The frequency offset cancel block may include a finite impulse response (FIR) filter that is adjustable over low frequencies.

In general, the term "adjustable FIR filter" means any unit, device, circuit and / or component that acts as a filter with controllable spectral characteristics, i.e., a filter with a variable cutoff frequency response. means. The filter can be designed using any suitable design method, for example by transformation or spectral parameter approximation. The filter is preferably a low frequency FIR filter of length M, where M is selected to provide an appropriate frequency response. The filter may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software or a combination of both.

An adjustable FIR filter facilitates the extraction of unwanted low frequency components from the output of the comparator, which output is used to determine the residual frequency error / deviation within the loop. Adjustable FIR filters can be used to make the AFC block programmable and to meet the receiver frequency tolerance set by the radio standard.

The frequency offset cancel block may include a variable gain amplifier.

In general, the term "variable gain amplifier" is used herein to amplify, pass or attenuate the signal supplied to its input, and any unit, device, designed to provide the signal processed at its output. Means a circuit and / or a component. The variable gain amplifier may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software or a combination of both.

By providing a variable gain amplifier, it is possible to adjust the bandwidth of the AFC loop and control the step response of the AFC block. Variable gain amplifiers can be used to make the AFC block programmable and to meet the receiver frequency tolerance set by the radio standard.

The frequency offset cancel block may include a delta-sigma modulator.

A delta-sigma modulator may be used to quantize filtered and amplified digital data into discrete steps that can be fed directly to the DCO. Delta-sigma modulators are used to improve the resolution of discrete steps by time averaging. The delta-sigma modulator may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software or a combination of both.

This arrangement improves the frequency resolution of the DCO provided by the delta-sigma modulator, so that a receiver with better frequency tracking characteristics can be achieved.

The integrator, adjustable finite impulse response filter, variable gain amplifier and delta-sigma modulator may be connected sequentially (sequentially, sequentially, continuously or sequentially).

The term "sequentially connected" understands that integrators, adjustable finite impulse response filters, variable gain amplifiers and delta-sigma modulators may be connected in any order from the point of view of signal propagation. I want to be.

This provision can increase the flexibility in realizing the receiver.

The frequency offset cancel block may be implemented or implemented in the digital domain.

The term "digital domain" is used herein to mean that a frequency offset cancel block is implemented or implemented in a digital circuit that acts on a digital signal to provide the digital signal. Digital circuits may be integrated on a single chip or distributed among multiple integrated circuits. The single chip may be provided as an integrated circuit. The digital circuit forming the frequency cancel block may be part of a larger chip that includes circuits associated with one or more other components of the receiver. The integrated circuits that form the frequency cancel block and / or receiver may be assembled on a substrate such as a printed circuit board. Alternatively, the frequency offset cancel block may be implemented or implemented in software that provides the functionality of the frequency offset cancel block when operating on the processor.

With this arrangement, it is possible to provide a receiver having a smaller number of analog blocks than a conventional FSK receiver. Therefore, the receiver consumes less power and can be mounted with minimal chip / substrate area.

The comparator supplies a digital signal to the control input of the digitally controlled oscillator, and the digitally controlled oscillator may be adapted to provide a signal of a first or second frequency to its output based on the digital signal. ..

The oscillator is preferably fitted with output signals of first and second frequencies that comply with the particular communication standard in which the receiver operates. As an example, if the receiver is used for Bluetooth® communication, the receiver may receive a signal transmitted over a particular channel, said first and second frequencies. , Selected based on the particular channel within the Bluetooth® standard, i.e. all channel frequencies are located within the 2.4 GHz ISM band and the frequency of the carrier within the channel carries the modulated signal. Is shifted to. The binary "1" is represented by a positive frequency deviation and the binary "0" is represented by a negative frequency deviation. Typically, the modulation index can vary between 0:28 and 0:35, which gives a frequency deviation between 0.140 MHz and 0.175 MHz from the carrier.

The oscillator is adapted to provide an output signal of the first or second frequency based on the signal provided by the comparator, thus avoiding the effects of any non-linearity on the DCO gain and thus avoiding the oscillator frequency. Will be done.

The control input of the digitally controlled oscillator can be coupled to the output of the comparator and the output of the automatic frequency offset cancel block via an adder.

In general, the term "additional point" is designed here to receive input data from two or more sources and provide output data that represents the sum of two or more input data streams. Means any unit, device, circuit and / or component. In particular, the point of addition can provide the sum of two or more serial or parallel data streams received at its input. The points of addition may be integrated with one or more other components of the receiver, or may be implemented by separate circuits, software, or a combination of both.

By providing additional points, the AFC loop, demodulation loop, and RF front end may share many components of the receiver. Therefore, it is possible to provide a compact receiver with reduced power consumption.

The signal at the input of the comparator has a first frequency and the comparator is adapted to sample the signal at a second higher frequency.

The comparator is adapted to sample the output of the LPF at a frequency higher than the bit rate of the modulated signal. That is, the comparator uses oversampling of the LPF signal at a sampling frequency well above the Nyquist frequency.

Oversampling achieves improved resolution, reduced noise, and avoiding aliasing and phase distortion by relaxing the performance requirements of the LPF.

The comparator is adapted to provide a demodulated output signal.

Here, the term "output signal" means that the output of the comparator is used for further data processing in the digital domain. Additional circuitry and / or software provides pulse shaping (ie, altering the waveform of the output signal) and / or adaptive processing (eg, changing the waveform of the output signal) before feeding the output signal from the comparator to subsequent circuitry. , Amplification, filtering, etc.) may be provided.

By supplying the demodulated signal from the comparator, it is possible to provide a less complicated, compact and efficient receiver.

The input signal may be a frequency shift keying modulation (FSK) signal or a phase shift keying modulation (PSK) signal.

In general, the receiver may be adapted to receive and demodulate any FSK / PSK signal. In particular, the receiver may be configured to demodulate any signal with constant envelope and binary frequency modulation. Such signals include Gaussian frequency shift keying (GFSK), binary frequency shift keying (BFSK), offset quadrature shift keying (HS-OQPSK) and Gaussian minimum shift keying (GMSK).

Due to the widespread use of FSK / PSK in modern communications, this offer can provide receivers suitable for use in a wide range of applications.

According to a second aspect of the present invention, there is provided a method of demodulating a received modulated signal. The method comprises receiving the modulated signal at the phase detector and supplying the output from the phase detector to the input of the comparator. The method comprises comparing the input of the comparator with a threshold and supplying the output of the comparator to the control input of the digital controlled oscillator and the input of the frequency cancel block. The method comprises supplying the output of the frequency cancel block to the control input of the digital controlled oscillator and supplying the output of the digital controlled oscillator to the phase comparator.

The advantages of the method of the present invention are similar to those of the receiver described above.

Other objects, features and advantages of the present invention will be apparent from the following detailed disclosure and will be apparent from the accompanying claims and drawings.

In general, all terms used in the claims should be construed according to their usual meaning in the art, unless explicitly defined. All references to "one or its [components, devices, means, means, steps, etc.]" refer to at least one instance of a component, device, component, means, step, etc., unless otherwise stated. Should be interpreted openly. The steps of any method disclosed herein need not be performed in the exact order in which they are disclosed, unless explicitly stated.

The above and additional objectives, features and advantages of the present invention will be better understood through the following exemplary and non-limiting detailed description of preferred embodiments of the present invention and with reference to the accompanying drawings. There will be. Here, the same reference number is used for similar components.

A PLL-based phase tracking receiver according to an embodiment of the present invention is shown graphically. The frequency offset correction block according to the embodiment of the present invention is shown graphically.

FIG. 1 shows a PLL-based phase tracking receiver 100 according to an embodiment of the present invention. The FSK / PSK modulated signal is received at the input of the receiver. The received modulated signal is amplified by the low noise amplifier 101 in order to provide a signal of sufficient amplitude to the subsequent functional blocks of the receiver 100. The bandwidth of the low noise amplifier 101 is set to provide sufficient amplification in the bandwidth of interest, where the bandwidth ranges from 2400 MHz to 2483.5 MHz, according to a preferred embodiment. Includes 4 GHz ISM band.

The phase detector (PD) 102 includes a first input 102a and a second input 102b, at which the first input 102a receives the output of the optional low noise amplifier 101. According to a preferred embodiment, the mixer is used as an analog phase detector 102 and outputs a signal proportional to the phase difference between the signals at its inputs 102a, 102b. According to an alternative embodiment, an analog multiplier or logic circuit can be used as the phase detector 102.

The output of the phase detector 102 is sent to the low-pass filter LPF103. The LPF 103 suppresses the interference signal in the input signal. The interference signal at the input of the LPF 103 usually has the following two sources (signal sources).
(1) A strong signal at a higher frequency from the input of the receiver, usually the signal from the adjacent channel and the alternative channel interferes with the desired signal.
(2) Non-ideal characteristics in the circuit of the receiver, for example, the low noise amplifier 101, the phase detector 102 and / or other parts of the receiver 100 may generate harmonics of the input signal. There is, which acts as a source of interference for the desired signal.
The LPF 103 suppresses signals outside its bandwidth, where the bandwidth of the LPF 103 is preferably set to be equal to the bandwidth of the input modulated signal.

The output from the LPF 103 is preferably transferred to the comparator CMP104, and the output signal preferably samples the output of the LPF 103 at a frequency higher than the bit rate of the modulated signal. The capture effect exhibited by the comparator 104 provides extra interference suppression, i.e., the comparator 104 responds to the instantaneous amplitude of the input signal. If the ratio of the interfering signal to the desired signal is less than a certain coefficient, the instantaneous amplitude of the input of the comparator 104 will be dominated by the desired signal. The comparator 104 responds only to the polarity of the output signal of the LPF 103, which relaxes the amplitude dependence, relaxes the gain control of the receiver 100, and causes the demodulation loop 108 to vary in amplitude (eg, analog gain variation or Make it insensitive to channel fading). The output from the comparator 104 represents the demodulated signal and is used for further data processing in the digital domain. The comparator 104 is clock synchronized at a frequency higher than the bit rate to produce a 1-bit oversampling digital output without the need for an additional ADC to provide threshold detection.

The output from the comparator 104 is transferred to the digitally controlled oscillator (DCO) 105. The DCO 105 oscillates only at a specific frequency based on the output of the comparator 104, eliminating the effect of non-linearity on the gain of the DCO 105. For example, for a BFSK application, the output of oscillator 105 is one of two predetermined frequencies corresponding to the mark frequency and space frequency in the BFSK scheme. The output of the 1-bit comparator 104 determines the oscillator frequency in the next sampling period by providing a digital tuning word to the input 105a of the DCO 105. The format of the digital adjustment word may vary based on the implementation of DCO105.

As an example, the digital adjustment word may be logic "1" or logic "0" in its simplest form, where the frequency at the output of the DCO 105 is the first when the digital adjustment word is "1". It takes a frequency of 1, and when the digital adjustment word is "0", it becomes the second frequency. Alternatively, the DCO 105 receives a frame-formatted digital adjustment word that dynamically allows the frequency of the DCO 105 to be drawn around the nominal value. The input 105a of the DCO 105 may be a serial interface that receives a data frame for writing one or more registers (not shown) to the DCO 105. The value written to the register controls the amount of frequency drawn from the nominal frequency.

The output of the DCO 105 is supplied to the second input 102b of the phase detector 102.

The DCO 105 preferably comprises an LC tank (not shown) containing a large number of capacitors with different values. The DCO 105 is adapted to connect one or more capacitors in the LC tank based on the digital tuning word, where the number of capacitors in the LC tank varies depending on the resolution required for the DCO 105. obtain.

In an alternative embodiment, a multi-bit ADC can be used instead of the 1-bit comparator. In this embodiment, the output of the multi-bit ADC is DCO105 so that it oscillates at two or more frequencies so that the receiver can also demodulate the M-ary frequency shift keying (M-FSK) modulation scheme. To control.

Undesirable frequency deviations (eg, frequency drift of the DCO 105) occupy primarily the low frequency domain in the spectrum of the output of the comparator 104. The negative feedback loop 109 via the automatic frequency offset cancel (AFC) block 106 cancels the low frequency components of the output of the comparator 104. The AFC loop 109 in the negative feedback configuration estimates the frequency deviation due to the input frequency offset and the frequency instability of the oscillator, and cancels it by changing the center frequency of the DCO 105 accordingly.

In a preferred embodiment, the outputs from the comparator 104 and the AFC block 106 are merged at the addition point 107. That is, the digital data supplied by the comparator 104 and the AFC block 106 are merged into a format suitable for controlling the DCO 105. Typically, the comparator 104 causes the comparator 105 to increase or decrease its frequency in larger steps so that the DCO 105 follows, for example, the mark and space frequencies of the BFSK scheme. The AFC block 106 typically increases or decreases the frequency in much smaller steps with respect to the DCO 105 to compensate for any frequency offset present in the input signal. The point of addition is that the DCO 105 has two inputs for receiving signals from the comparator 104 and the AFC block 106, or the DCO 105 has one input and is from the comparator 104 and the AFC block 106. Implemented on the DCO 105 to receive the data sequentially (ie, by combining its contributions internally within the DCO 105, eg, by adjusting the digital tuning words in one or more registers that control the frequency of the DCO 105). You may.

The AFC loop 109 shares the PD102, LPF103, comparator 104, and DCO105 with the main demodulation loop 108. The additional AFC block 106 within the AFC loop 109 is preferably mounted or implemented in the digital domain to facilitate the mounting of the AFC loop 109 and improve power efficiency.

FIG. 2 shows an automatic frequency offset correction block AFC200 according to an embodiment of the present invention. The AFC block 200 includes an integrator 201, an adjustable FIR filter 202, a variable gain amplifier 203, and a delta sigma modulator 204.

The integrator 201 and the adjustable FIR filter 202 are used to extract low frequency unwanted components from the output of the comparator 104 and determine the residual frequency error / deviation in loop 109.

The variable gain amplifier 203 is used to adjust the bandwidth of the AFC loop 109 and thus determines the step response of the AFC block 200. That is, the variable FIR filter 202 and the variable gain amplifier 203 can be used to make the AFC block 200 programmable and to meet the receiver frequency tolerance set by the radio standard (eg, Bluetooth®). ..

The delta-sigma modulator 204 is used to quantize the filtered and amplified digital data into discrete steps, which can be fed directly to the DCO 105. Delta-sigma modulator 204 improves the resolution of these discrete steps by time averaging. That is, from a functional point of view, the delta-sigma modulator performs the following two operations.
(1) Time average / dithering: Normally, the minimum DCO105 frequency step is limited by the minimum capacitor in the LC tank. A delta-sigma modulator 204 can be used to further reduce this minimum frequency step. In other words, it can increase the DCO frequency resolution.
(2) The quantization noise generated by the AFC 200 is pushed to a higher frequency and suppressed by the demodulation loop 108.

As mentioned above, receivers adapted to provide a demodulated output signal in response to an FSK / PSK modulated input signal are disclosed. The receiver includes a phase-locked loop with a digitally controlled oscillator that provides a demodulated output signal of the modulated input signal. The receiver further comprises a frequency offset cancel block adapted to supply a digital tuning word (or signal) to the digital control oscillator, where the digital control oscillator responds to the digital tuning word (signal) and digitally. It is adapted to change its frequency based on the tuning word, where the frequency canceling block provides a digital tuning word based on the demodulated output signal.

The present invention is primarily described above with reference to some embodiments. However, as will be readily appreciated by those skilled in the art, other embodiments other than those described above are equally possible within the scope of the invention and are provided by the appended claims.

Claims (14)

A phase detector having first and second inputs, wherein the first input is adapted to receive a modulated input signal.
A comparator having an input coupled to the output of the phase detector and
A frequency offset cancel block containing an input coupled to the output of the comparator,
A receiver equipped with a digitally controlled oscillator
The digitally controlled oscillator
A control input coupled to the output of the comparator and the output of the frequency offset cancel block,
A receiver having an output coupled to the second input of the phase detector. The receiver according to claim 1, wherein the input of the comparator is coupled to the output of the phase detector via a low-pass filter. The receiver according to claim 1 or 2, wherein the frequency offset cancel block includes an integrator. The receiver according to any one of claims 1 to 3, wherein the frequency offset cancel block includes a finite impulse response filter that can be adjusted by passing low frequencies. The receiver according to any one of claims 1 to 4, wherein the frequency offset cancel block includes a variable gain amplifier. The receiver according to any one of claims 1 to 5, wherein the frequency offset cancel block includes a delta-sigma modulator. Said frequency offset cancellation block, an integrator, an adjustable finite impulse response filter, a variable gain amplifier, and includes a delta-sigma modulator,
The receiver according to claim 1 or 2, wherein the integrator, an adjustable finite impulse response filter, a variable gain amplifier, and a delta-sigma modulator are sequentially connected. The receiver according to any one of claims 1 to 7, wherein the frequency offset cancel block is implemented in the digital domain. The comparator is configured to supply a digital signal to the control input of the digital control oscillator.
The digitally controlled oscillator according to any one of claims 1 to 8, which is adapted to supply a signal of a first or second frequency to the output of the digitally controlled oscillator based on the digital signal. Receiver. The control input of the digital controlled oscillator via a summing junction, the output of the comparator, or, according to any one of claims 1 to 9 coupled to the output of the frequency offset cancellation block Receiving machine. The signal at the input of the comparator has a first frequency and
The receiver according to any one of claims 1 to 10, wherein the comparator is adapted to sample the signal at a higher second frequency. The receiver according to any one of claims 1 to 11, wherein the comparator is adapted to provide a demodulated output signal. The receiver according to any one of claims 1 to 12, wherein the input signal is a frequency shift keying modulation signal or a phase shift keying modulation signal. A method of demodulating a received modulated signal, wherein the method is
The modulation signal is received at the input of the phase detector having the first and second inputs, and the output from the phase detector is supplied to the input of the comparator.
Comparing the input of the comparator with the threshold value
To provide the output of the comparator to the control input of the digital controlled oscillator and the input of the frequency cancel block,
To supply the output of the frequency cancel block to the control input of the digital control oscillator,
A method comprising supplying the output of the digitally controlled oscillator to the phase detector .

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