JP6680634B2 - Substrate for mounting semiconductor element and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor element mounting substrate for mounting a semiconductor element, and a semiconductor device using the same.

  2. Description of the Related Art In recent years, a semiconductor element mounting substrate that houses a semiconductor element that operates with a high-frequency signal has been known. When such a semiconductor element or the like is operated, heat is generated. In order to dissipate this heat to the outside, a semiconductor mounting substrate in which a semiconductor element or the like is mounted on the upper surface of a metal plate is disclosed (see Patent Document 1).

JP, 2008-109056, A

  The technique disclosed in Patent Document 1 is electrically connected to a semiconductor element formed on a substrate having a through hole, a metal plate provided so as to close the through hole, and the through hole. A semiconductor element mounting substrate provided with a through-hole conductor is described. A semiconductor element housed in the through hole is mounted on the upper surface of the metal plate.

  In the technique disclosed in Patent Document 1, a semiconductor element is connected to a through-hole conductor, and the through-hole conductor is filled with a conductor inside the through hole. However, since the through-hole conductor is formed, a large amount of heat is generated when a large current is applied to the semiconductor element, so that the through-hole conductor may be thermally expanded and deformed. Further, the through-hole conductor may be damaged due to the stress load due to the difference in thermal expansion coefficient from the substrate. If the through-hole conductor is deformed or damaged, current may not flow in the semiconductor element or the like.

  A semiconductor element mounting substrate according to an embodiment of the present invention is a substrate having a first through hole and a second through hole formed with a space between the first through hole, and a lower surface of the substrate, A first metallization layer that surrounds the outer edge of the first through hole, a second metallization layer that surrounds the outer edge of the second through hole that is the lower surface of the substrate, and a mounting area for mounting a semiconductor element in the center of the upper surface. And a peripheral area that surrounds the mounting area, the peripheral area overlaps with the first metallization layer and closes the first through hole, and is surrounded by the second through hole, A columnar body that is spaced apart from the inner surface of the second through hole, the lower portion of the columnar body is located below the lower surface of the substrate, and the entire circumference of the lower portion projects laterally. The entire circumference of the lower portion does not overlap the second metallization layer. Closes the second through hole Te, characterized in that a semiconductor element electrically connected to the through conductors.

  A semiconductor device according to an embodiment of the present invention is a semiconductor element mounting substrate described above, a semiconductor element mounted on an upper surface of the metal plate and electrically connected to the second through conductor, and the semiconductor element. It is characterized by comprising a frame body formed so as to surround the upper surface of the mounting substrate and a lid body joined to the upper end of the frame body.

According to the semiconductor element mounting substrate of one embodiment of the present invention, since the through conductor is formed so as to be spaced apart from the inner surface of the through hole, a semiconductor element that allows a large current to flow therethrough and be used. A mounting substrate and a semiconductor device using the same can be provided.

It is a perspective view from the upper surface showing the composition of the semiconductor device mounting substrate concerning one embodiment of the present invention. It is a perspective view from the lower surface showing the composition of the semiconductor device mounting substrate concerning one embodiment of the present invention. It is an exploded perspective view from the upper surface showing the composition of the semiconductor device mounting substrate concerning one embodiment of the present invention. FIG. 3 is an exploded perspective view from the bottom surface showing the configuration of the semiconductor element mounting substrate according to the embodiment of the present invention. It is a perspective view from the upper surface showing the composition of the semiconductor device mounting substrate concerning other embodiments of the present invention. It is a perspective view from the lower surface showing the composition of the semiconductor device mounting substrate concerning other embodiments of the present invention. It is an exploded perspective view from the upper surface showing the composition of the semiconductor device mounting substrate concerning other embodiments of the present invention. It is an exploded perspective view from the lower surface showing the composition of the semiconductor device mounting substrate concerning other embodiments of the present invention. It is a top view which shows the structure of the semiconductor element mounting substrate which is other embodiment of this invention, FIG.9 (a) is a top view from a top view, and FIG.9 (b) is a top view from a bottom surface. . FIG. 10 is a side view showing a configuration of a semiconductor element mounting substrate which is another embodiment of the present invention and a cross-sectional view of FIG. 9, FIG. 10 (a) is a side view, and FIG. 10 (b) is A of FIG. 9. 10A is a cross-sectional view taken along line A, FIG. 10C is a cross-sectional view taken along line BB of FIG. 10, FIG. 10D is a cross-sectional view taken along line CC of FIG. 9, and FIG. It is sectional drawing in the DD line of FIG. It is a perspective view of the structure in which the frame was provided in the semiconductor device mounting substrate which is another embodiment of the present invention. It is a perspective view showing the composition of the semiconductor device which is one embodiment of the present invention. It is an exploded perspective view showing composition of a semiconductor device which is one embodiment of the present invention.

  Hereinafter, a semiconductor element mounting substrate and a semiconductor device according to one embodiment of the present invention will be described in detail with reference to the drawings.

<Structure of substrate for mounting semiconductor element>
FIG. 1 is a perspective view from the upper surface of a semiconductor element mounting substrate 1 according to an embodiment of the present invention, and FIG. 2 is a perspective view from the lower surface of a semiconductor element mounting substrate 1 according to an embodiment of the present invention. There is. 3 and 4 are exploded perspective views from the upper surface of the semiconductor element mounting substrate 1 according to one embodiment of the present invention and exploded perspective views from the lower surface of the semiconductor element mounting substrate 1 according to one embodiment of the present invention, respectively. The figure is shown. In these figures, the semiconductor element mounting substrate 1 includes a substrate 2, a first metallized layer 31, a second metallized layer 32, a metal plate 3 and a through conductor 21.

  The substrate 2 has, for example, a rectangular shape in a plan view. The substrate 2 has a size in plan view of, for example, 5 mm × 50 mm to 5 mm × 50 mm in plan view, and a thickness of 0.5 mm to 5 mm. The substrate 2 is made of, for example, a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body or a silicon nitride sintered body, or a glass ceramic material. It is made of a resin material such as epoxy resin.

The substrate 2 has a plurality of through holes. The plurality of through holes formed in the substrate 2 are, for example, the first through hole 11 and the second through hole 12. Besides, the third through hole 13 and the fourth through hole 14 may be formed. A metallized layer is formed on the lower surface of the substrate 2. The first metallized layer 31 surrounds the outer edge of the first through hole 11, and the second metallized layer 32 surrounds the outer edge of the second through hole 12. When the third through hole 13 and the fourth through hole 14 are formed, the third metallized layer 33 and the fourth metallized layer 34 are formed on the lower surface of the substrate 2.

  The first metallization layer 31 is on the lower surface of the substrate 2 and surrounds the outer edge of the first through hole 11. The first metallized layer 31 has, for example, a rectangular shape in a plan view, and has a size of 2 mm × 40 mm to 2 mm × 40 mm. The thickness is 0.01 mm to 0.1 mm. The first metallization layer 31 is made of, for example, a metal material such as tungsten, molybdenum, and manganese, and is provided in the form of a metallization layer on the lower surface of the substrate 2 so as to surround the outer edge of the first through hole 11, and on the surface thereof. A plating layer made of a metal material such as gold or nickel is formed by electric field plating or electroless plating.

  The second metallization layer 32 is the lower surface of the substrate 2 and surrounds the outer edge of the second through hole 12. The second metallized layer 32 has, for example, a rectangular shape in a plan view, and has a size of 2 mm × 40 mm to 2 mm × 40 mm. The thickness is 0.01 mm to 0.1 mm. The first metallization layer 31 is made of, for example, a metal material such as tungsten, molybdenum, and manganese, and is provided in the form of a metallization layer on the lower surface of the substrate 2 so as to surround the outer edge of the first through hole 11, and on the surface thereof. A plating layer made of a metal material such as gold or nickel is formed by electric field plating or electroless plating.

  The first through hole 11 is formed in the substrate 2, and a first metallization layer 31 is formed around the lower surface of the substrate 2. It has, for example, a rectangular shape in a plan view and a size of 1 mm × 38 mm to 1 mm × 38 mm. Since the semiconductor element is accommodated in the first through hole 11, a sufficient size for accommodating the semiconductor element is ensured.

  Further, in plan view, the center of the first through hole 11 is located, for example, at the outer edge of the center of the substrate 2. That is, the first through holes 11 are formed in a biased manner with respect to the substrate 2 in a plan view. Therefore, it is possible to secure a space in the substrate 2 in a region where the first through hole 11 is not formed. As a result, the substrate 2 can secure a space for the electrode around the first through hole 11 on the upper surface of the substrate 2, which is electrically connected to the accommodated semiconductor element.

  Further, when the first through holes 11 are formed so as to be deviated from the substrate 2 in a plan view, the first metallized layer 31 is also formed so as to be deviated from the substrate 2 in a plan view. Therefore, in a plan view, the width from the outer edge of the first metallized layer 31 to the outer edge of the substrate 2 can be narrowed. Therefore, the stress due to the difference in the coefficient of thermal expansion between the substrate 2 and the first metallized layer 31 can be suppressed. Further, at this time, when the first metallized layer 31 is formed up to the outer edge of the substrate 2, plating can be efficiently applied when the surface is electroplated.

  The metal plate 3 is provided on the lower surface of the substrate 2 so as to close the first through hole 11. The metal plate 3 has a mounting region 3a for mounting a semiconductor element in the central portion of the upper surface and a peripheral region 3b surrounding the mounting region 3a. The peripheral region 3b overlaps the first metallization layer 31 and closes the first through hole 31. The metal plate 3 has, for example, a rectangular shape in a plan view, and has a size of 1.5 mm × 38.5 mm to 1.5 mm × 38.5 mm. The thickness is 0.5 mm to 3 mm. The metal plate 3 is made of, for example, a metal material made of iron, nickel, cobalt, chromium or the like, or an alloy containing these, and is made of a plated layer of gold, nickel or the like provided on the surface thereof by electric field plating or electroless plating. Since the metal plate 3 is made of a metal material, even if heat is generated when the semiconductor element mounted on the upper surface is used, the heat can be easily released to the external circuit board via the metal plate 3.

  The second through hole 12 is formed in the substrate 2 with a space between the second through hole 12 and the first through hole 11. A second metallization layer 32 is formed around the second through hole 12 on the lower surface of the substrate 2. The second through hole 12 has, for example, a rectangular shape in a plan view, and has a size of 1.5 mm × 18 mm to 1.5 mm × 18 mm. In the second through hole 12, a through conductor 21 that is electrically connected to the semiconductor element housed in the first through hole 11 is formed.

  The through conductor 21 is provided so as to cover the second through hole 12 from the inside of the second through hole 12 to the lower surface of the substrate 2. The through conductor 21 is surrounded by the second through hole 12 and is provided so as to be spaced apart from the inner surface of the second through hole 12. The penetrating conductor 21 is a columnar body, and the lower portion 21 a of the columnar body is located below the lower surface of the substrate 2. Further, the entire circumference of the lower portion 21a is projected laterally, and the entire circumference of the lower portion 21a overlaps with the second metallization layer 32 to close the second through hole 12. That is, the lower portion 21 a of the penetrating conductor 21 is exposed on the lower surface of the substrate 2.

  The penetrating conductor 21 has, for example, a rectangular shape in a plan view from the lower surface of the substrate 2, and has a size of 1.7 mm × 18 mm to 1.7 mm × 18 mm. The substrate 2 has, for example, a rectangular shape in a plan view from the upper surface and has a size of 1.3 mm × 17 mm to 1.3 mm × 17 mm. The thickness is 0.5 mm to 5 mm in the second through hole 12. Further, the thickness of the lower portion 21a exposed from the lower surface of the substrate 2 is 0.5 mm to 3 mm. The through conductor 21 is made of, for example, a metal material made of iron, nickel, cobalt, chromium, or the like, or an alloy containing these, and is made of a plated layer of gold, nickel, or the like provided on the surface thereof by electric field plating or electroless plating. The through conductor 21 is electrically connected to the semiconductor element mounted on the metal plate 3 by wire bonding or the like. For this reason, since the penetrating conductor 21 is made of a metal material, even if a large current flows and a large amount of heat is generated when the semiconductor element is used, the heat can be easily released to the outside and the semiconductor element mounting substrate 1 is also provided. It is possible to suppress disconnection of the current path in the.

  The through conductor 21 is surrounded by the second through hole 12 and is provided so as to be spaced apart from the inner surface of the second through hole 12. That is, there is a gap between the inner surface of the second through hole 12 and the side surface of the through conductor 21 located inside the second through hole 12. The distance between the outer edge of the through conductor 21 and the inner edge of the second through hole in a plan view is, for example, 0.1 to 1.5 mm. A semiconductor element generates a large amount of heat by flowing a large current during use. At this time, since the side surface of the through conductor 21 is provided so as to be spaced apart from the inner surface of the second through hole 12, when the through conductor 21 thermally expands and contracts, the through conductor 21 and the substrate 2 are separated from each other. The load of the stress caused by the difference in the coefficient of thermal expansion, and the crack of the substrate 2 caused by the stress are reduced. When the inner surface of the second through hole 12 and the side surface of the through conductor 21 located inside the second through hole 12 are spaced apart from each other, the through conductor 21 made of a metal material has a larger thermal expansion and thermal contraction than the substrate 2. This is because even if it does, it is reduced compared to the case where there is no contact or there is no gap after contact, so that the stress that is pulled or pressed by the substrate 2 is suppressed. Therefore, the electrical connection with the semiconductor element can be maintained. That is, a large current can be used, and damage to the semiconductor element mounting substrate 1 due to thermal stress can be suppressed.

At this time, it is preferable that the entire circumference of the side surface of the penetrating conductor 21 located inside the second through hole 12 be spaced apart from the inner surface of the second through hole 12. As a result, when a semiconductor element is used, a large current is passed to generate a large amount of heat, and when the through conductor 21 thermally expands and contracts, a stress load caused by a difference in thermal expansion coefficient from the substrate 2, And the crack of the board | substrate 2 which accompanies with it is reduced further. Therefore, the electrical connection with the semiconductor element can be maintained more effectively, and the damage to the semiconductor element mounting substrate 1 due to thermal stress can be suppressed.

  The side surface of the through conductor 21 located inside the second through hole 12 has a curved portion in a plan view. As a result, when compared with the case where the through conductor 21 has a corner in plan view, it is possible to make it difficult to deform even when a large amount of heat is generated. In addition, since the penetrating conductor 21 has the curved portion, it is possible to suppress the stress load due to thermal expansion and thermal contraction that tends to concentrate in the corner portion.

  The outer edge of the first metallized layer 31 is formed to be larger than the outer edge of the metal plate 3 in a plan view. The outer edge of the second metallized layer 32 is formed to be larger than the lower edge of the through conductor 21. This makes it possible to secure the joint area between the metal plate 3 and the penetrating conductor 21 even if displacement occurs during joining. Further, when the bonding material is provided up to the side surface of the metal plate 3 and the side surface of the lower portion 21a of the through conductor 21, the bonding strength can be improved.

  Further, in the width from the outer edge of the lower portion 21a of the through conductor 21 to the outer edge of the second metallization layer 32, the width from the outer edge of the lower portion 21a of the through conductor 21 of the second metallization layer 32 facing the outer edge of the substrate 2 is The width from the outer edge of the lower portion 21a of the penetrating conductor 21 of the first metallized layer 31 facing the second metallized layer 32 is formed to be larger. That is, the width of the metallization layers facing each other is narrowed. This can prevent the metallized layers from coming into contact with each other to cause a short circuit.

  Further, in a conductive bonding material such as a brazing material or a solder for bonding the through conductor 21 to the second metallized layer 32, a bonding material provided on the metallized layers where the first metallized layer 31 and the second metallized layer 32 face each other. The amount of the bonding material provided on the second metallization layer 32 on the side facing the outer edge of the substrate 2 can be increased. As a result, the bonding strength between the penetrating conductor 21 and the second metallization layer 32 can be maintained by the bonding material provided on the second metallization layer 32 on the side facing the outer edge of the substrate 2. Further, the substrate 2, the metal plate 3, the penetrating conductor 21, the first metallization layer 31, the second metallization layer 32, and the bonding locally generated at the location where the first metallization layer 31 and the second metallization layer 32 face each other and are close to each other. The stress due to the difference in thermal expansion from the material can be reduced.

  Further, in plan view, the first metallized layer 31 and the second metallized layer 32 are formed to the outer edge of the substrate 2. This makes it possible to efficiently apply the electric field plating when forming the metallized layer.

5 to 10 show the case where the third through hole and the fourth through hole are formed in the substrate 2 described above. 5 is a perspective view from the upper surface of a semiconductor element mounting substrate 1 according to another embodiment of the present invention, and FIG. 6 is a perspective view from the lower surface of a semiconductor element mounting substrate 1 according to another embodiment of the present invention. Shows. 7 and 8 are exploded perspective views from the upper surface of a semiconductor element mounting substrate 1 according to another embodiment of the present invention and from a lower surface of the semiconductor element mounting substrate 1 according to another embodiment of the present invention. The exploded perspective view is shown. FIG. 9 is a plan view showing a configuration of a semiconductor element mounting substrate according to another embodiment of the present invention, FIG. 9 (a) is a plan view from the top, and FIG. 9 (b) is a view from the bottom. It is a top view. 10 is a side view showing a configuration of a semiconductor element mounting substrate according to another embodiment of the present invention and a sectional view of FIG. 9, FIG. 10 (a) is a side view, and FIG. ) Is a sectional view taken along the line AA of FIG. 9, FIG. 10C is a sectional view taken along the line BB of FIG. 10, and FIG. 10D is a sectional view taken along the line CC of FIG. 9. FIG. 10E is a sectional view taken along the line DD of FIG. In these drawings, the semiconductor element mounting substrate 1 further includes a third through hole 13, a fourth through hole 14, a third metallized layer 33, a fourth metallized layer 34, a second through conductor 22, and a third through conductor 23. This is different from the semiconductor element mounting substrate 1 according to the embodiment of the present invention.

  The third metallization layer 33 is the lower surface of the substrate 2 and surrounds the outer edge of the third through hole 13. The third metallization layer 33 has, for example, a rectangular shape in a plan view, and has a size of 2 mm × 20 mm to 2 mm × 20 mm. The thickness is 0.01 mm to 0.1 mm. The third metallization layer 33 is made of, for example, a metal material such as tungsten, molybdenum, and manganese, is provided in the form of a metallization layer on the lower surface of the substrate 2 so as to surround the outer edge of the third through hole 13, and is provided on the surface thereof. A plating layer made of a metal material such as gold or nickel is formed by electric field plating or electroless plating.

  The fourth metallized layer 34 is the lower surface of the substrate 2 and surrounds the outer edge of the fourth through hole 14. The fourth metallized layer 34 has, for example, a rectangular shape in a plan view, and has a size of 2 mm × 20 mm to 2 mm × 20 mm. The thickness is 0.01 mm to 0.1 mm. The fourth metallization layer 34, like the fourth metallization layer 34, is made of a metal material such as tungsten, molybdenum, and manganese, and is formed on the lower surface of the substrate 2 so as to surround the outer edge of the fourth through hole 14. And a plating layer made of a metal material such as gold or nickel is formed on the surface by electroplating or electroless plating.

  The third through hole 13 is formed in the substrate 2, and a third metallization layer 33 is formed around the lower surface of the substrate 2. It has, for example, a rectangular shape in a plan view, and has a size of 1.5 mm × 18 mm to 1.5 mm × 18 mm. A second through conductor 22 is formed in the third through hole 13 and electrically connected to an electronic component mounted on the upper surface of the substrate 2.

  The second through conductor 22 is provided so as to cover the third through hole 13 from the inside of the third through hole 13 to the lower surface of the substrate 2. The second through conductor 22 is surrounded by the third through hole 13 and is provided so as to be spaced apart from the inner surface of the third through hole 13. The second penetrating conductor 22 is a columnar body, and the lower portion of the columnar body is located below the lower surface of the substrate 2. Further, the entire circumference of the lower part is projected laterally, and the entire circumference of the lower part overlaps with the third metallization layer 33 to close the third through hole 13. That is, the lower portion of the second penetrating conductor 22 is exposed on the lower surface of the substrate 2.

  The second penetrating conductor 22 has, for example, a rectangular shape in a plan view from the lower surface of the substrate 2, and has a size of 1.7 mm × 18 mm to 1.7 mm × 18 mm. The substrate 2 has, for example, a rectangular shape in a plan view from the upper surface and has a size of 1.3 mm × 17 mm to 1.3 mm × 17 mm. The thickness is 0.5 mm to 5 mm in the third through hole 13. The thickness of the lower part exposed from the lower surface of the substrate 2 is 0.5 mm to 3 mm. The second penetrating conductor 22 is made of, for example, a metal material made of iron, nickel, cobalt, chromium or the like or an alloy containing these, and is formed from a plated layer of gold or nickel provided on the surface by electric field plating or electroless plating. Become. The second penetrating conductor 22 is electrically connected to an electronic component mounted on the upper surface of the substrate 2 by wire bonding or the like. Therefore, since the second through conductor 22 is made of a metallic material, even if a large current flows and a large amount of heat is generated when the electronic component is used, the heat can be easily released to the outside.

  The second through conductor 22 is surrounded by the third through hole 13 and is provided so as to be spaced apart from the inner surface of the third through hole 13. When the second through conductor 22 thermally expands and contracts, the third through conductor 23 has a large coefficient of thermal expansion when the second through conductor 22 thermally expands and contracts because a large amount of current is generated when the electronic component is used. The stress load is reduced. Therefore, the electrical connection with the semiconductor element can be maintained. That is, a large current can be used.

The fourth through hole 14 is formed in the substrate 2, and a fourth metallization layer 34 is formed around the lower surface of the substrate 2. It has, for example, a rectangular shape in a plan view, and has a size of 1.5 mm × 18 mm to 1.5 mm × 18 mm. In the fourth through hole 14, a third through conductor 23 that is electrically connected to an electronic component mounted on the upper surface of the substrate 2 is formed. In a plan view, the third through hole 13, the fourth through hole 14, and the electronic component are arranged on a straight line.

  The third through conductor 23 is provided from the inside of the fourth through hole 14 to the lower surface of the substrate 2 so as to close the fourth through hole 14. The third through conductor 23 is surrounded by the fourth through hole 14 and is provided so as to be spaced apart from the inner surface of the fourth through hole 14. The third penetrating conductor 23 is a columnar body, and the lower portion of the columnar body is located below the lower surface of the substrate 2. Also, the entire circumference of the lower part is projected laterally, and the entire circumference of the lower part overlaps with the fourth metallization layer 34 to close the fourth through hole 14. That is, the lower portion of the third penetrating conductor 23 is exposed on the lower surface of the substrate 2.

  The third penetrating conductor 23 has, for example, a rectangular shape in a plan view from the lower surface of the substrate 2, and has a size of 1.7 mm × 18 mm to 1.7 mm × 18 mm. The substrate 2 has, for example, a rectangular shape in a plan view from the upper surface and has a size of 1.3 mm × 17 mm to 1.3 mm × 17 mm. The thickness is 0.5 mm to 5 mm in the fourth through hole 14. The thickness of the lower part exposed from the lower surface of the substrate 2 is 0.5 mm to 3 mm. The third penetrating conductor 23 is made of, for example, a metal material made of iron, nickel, cobalt, chromium, or the like, or an alloy containing these, and is formed from a plated layer of gold, nickel, or the like provided on the surface thereof by electric field plating or electroless plating. Become. The third penetrating conductor 23 is electrically connected to an electronic component mounted on the upper surface of the substrate 2 by wire bonding or the like. Therefore, since the third through conductor 23 is made of a metal material, it is possible to easily release the heat to the outside even when a large current is generated and a large amount of heat is generated when the electronic component is used, and at the same time, for mounting the semiconductor element. It is possible to suppress disconnection of the current path in the substrate 1. The third penetrating conductor 23 is electrically connected to an electronic component mounted on the upper surface of the substrate 2 by wire bonding or the like. Therefore, by forming the third penetrating conductor 23 from a metal material, even if a large current is generated and a large amount of heat is generated when the electronic component is used, the heat can be easily released to the outside.

  The third through conductor 23 is surrounded by the fourth through hole 14 and is provided so as to be spaced apart from the inner surface of the fourth through hole 14. When the third through conductor 23 thermally expands and contracts due to a large amount of heat generated when a large current flows when the electronic component is used, the fourth conductive conductor 24 has a difference in thermal expansion coefficient from the substrate 2. The stress load is reduced. Therefore, the electrical connection with the semiconductor element can be maintained. That is, a large current can be used.

  Further, also in the second through conductors 22 and the third through conductors 23, the entire circumferences of the side surfaces located inside the third through holes 13 and the fourth through holes 14 are the inner surfaces of the third through holes 13 and the fourth through holes 14, respectively. It is good that there is a gap. As a result, when the semiconductor element is used, a large current flows and a large amount of heat is generated, and when the second through conductor 22 and the third through conductor 23 thermally expand and contract, the coefficient of thermal expansion with the substrate 2 increases. The load of stress due to the difference of is further reduced. Therefore, the electrical connection with the semiconductor element can be maintained more effectively.

  Further, the second penetrating conductor 22 and the third penetrating conductor 23 each have a side surface located in each through hole having a curved portion in a plan view. As a result, it is possible to make the second through conductor 22 and the third through conductor 23 less likely to be deformed even when a large amount of heat is generated, as compared with the case where the side surfaces are angular.

  Further, the outer edges of the lower portions of the second through conductors 22 and the third through conductors 23 are also narrowed in width between the metallization layers facing each other, like the metal plate 3 and the through conductors 21. This can prevent the metallized layers from coming into contact with each other to cause a short circuit.

  Furthermore, in a conductive bonding material such as a brazing material or a solder that bonds the second through conductor 22 and the third through conductor 23 to the third metallization layer 33 and the fourth metallization layer 34, the third metallization layer 33 and the fourth metallization layer The amount of the bonding material provided on the metallization layer facing the metallization layer 34 is reduced, and the amount of the bonding material provided on the third metallization layer 33 and the fourth metallization layer 34 on the side facing the outer edge of the substrate 2 is reduced. You can do a lot. As a result, the bonding strength between the second through conductors 22 and the third through conductors 23 and the third metallization layer 33 and the fourth metallization layer 34 is determined by the third metallization layer 33 and the third metallization layer 33 on the side facing the outer edge of the substrate 2. 4 can be maintained by the bonding material provided on the metallized layer 34. Further, the substrate 2, the second through conductor 22, the third through conductor 23, the third metallized layer 33, and the fourth metallized layer locally occur at a location where the third metallized layer 33 and the fourth metallized layer 34 face each other and are close to each other. The stress caused by the difference in thermal expansion between the layer 34 and the bonding material can be reduced.

  Further, in plan view, the third metallized layer 33 and the fourth metallized layer 34 are formed up to the outer edge of the substrate 2, like the first metallized layer 31 and the second metallized layer 32. This makes it possible to efficiently apply the electric field plating when forming the metallized layer.

  Further, the second metallization layer 32, the third metallization layer 33, and the fourth metallization layer 34 are formed so that only one side overlaps with the outer edge of the substrate 2 when it is rectangular. The remaining three sides are formed to be smaller than the width from the outer edge of the lower part of each through conductor of the metallized layer formed to the outer edge in order to suppress a short circuit with another metallized layer. As a result, as compared with the case where it is formed large, not only the short circuit is suppressed but also the bonding strength is maintained, the substrate 2 made of a ceramic material, the metallized layer made of a metal material, the through conductor 21, and the second through conductor. It is possible to suppress the load of stress due to the difference in the thermal expansion coefficient between 22, 22, the third through conductor 23, the bonding material, and the like.

  In addition, FIG. 11 is a perspective view of a structure in which a frame is provided on a semiconductor element mounting substrate according to another embodiment of the present invention. As shown in FIG. 11, the semiconductor mounting substrate 1 may be provided with a frame 5 on the upper surface of the substrate 2. The frame body 5 is provided along the outer edge of the substrate 2 so as to surround the upper surface of the substrate 2. The frame body 5 has, for example, the same size as the substrate 2 in a plan view and a height of 0.5 mm to 5 mm. The frame body 5 is, for example, a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body or a silicon nitride sintered body, or a glass ceramic material. And resin material such as epoxy resin.

<Method for manufacturing semiconductor element mounting substrate>
The substrate 2 is made of, for example, a plurality of insulating layers, and if it is made of a glass ceramic sintered body, it is manufactured as follows. First, an appropriate organic binder, a solvent and the like are added and mixed to a raw material powder made of glass powder such as borosilicate glass and ceramic powder such as aluminum oxide to prepare a slurry. Next, the slurry is formed into a sheet by a forming method such as a doctor blade method to prepare a plurality of ceramic green sheets.

  After that, the ceramic green sheets are formed into an appropriate shape by cutting or punching, and the ceramic green sheets are laminated and pressure-bonded. Finally, the laminated ceramic green sheets are fired in a reducing atmosphere at a temperature of about 900 to 1000 ° C., whereby the substrate 2 can be manufactured.

If the first metallized layer 31, the second metallized layer 32, the third metallized layer 33, and the fourth metallized layer 34 are made of a high melting point metal such as tungsten, molybdenum, or manganese, for example, Can be formed. That is, first, a metal paste prepared by kneading a high melting point metal powder together with an organic solvent and a binder is printed on a predetermined portion of the ceramic green sheet on the lower surface of the substrate 2 by a method such as screen printing. After that, these are simultaneously fired. Through the above steps, the metallization layer is deposited on the lower surface of the substrate 2.

  The through conductor 21, the second through conductor 22, and the third through conductor 23 are cut or laser processed. The metal material is cut into a convex shape. The upper part is thinner than the lower part and is processed to have a curved part.

  The plurality of through holes, the first through hole 11, the second through hole 12, the third through hole 13 and the fourth through hole 14 are, for example, mechanical punching using metal pins, processing using laser light, or the like. Can be formed by drilling. The penetrating conductor 21, the second penetrating conductor 22, and the third penetrating conductor 23 are fitted into the respective through holes, and the lower parts thereof are joined to the metallized layer by using a joining material such as Ag—Cu brazing material.

  Thereafter, by electrolytic plating, for example, plating of nickel or the like is applied to the surface of each metallized layer, metal plate and each through conductor.

<Structure of semiconductor device>
FIG. 12 is a perspective view of the semiconductor device 10 according to the embodiment of the present invention, and FIG. 13 is an exploded perspective view of the semiconductor device 10 according to the embodiment of the present invention. In these figures, a semiconductor device 10 includes the above-described semiconductor element mounting substrate 1, semiconductor element 4, frame 5 and lid 6. Further, the electronic component 7 may be further provided.

  The semiconductor element 4 is, for example, a silicon semiconductor, a GaN semiconductor, or a SiC semiconductor. Further, when the third through hole 13 and the fourth through hole 14 are formed, the electronic component 7 is mounted on the upper surface of the substrate 2. The electronic component 7 is, for example, a capacitor, a resistance element, or a semiconductor element such as a silicon semiconductor, a GaN semiconductor, or a SiC semiconductor like the semiconductor element 4.

  The lid body 6 is joined to the upper end of the frame body 5 while covering the inside surrounded by the frame body 5. At this time, the size of the lid body 6 is the same size as the substrate 2 and the frame body 5 in a plan view. The lid 6 is made of, for example, a metal material made of iron, nickel, cobalt, chromium or the like, or an alloy containing these, and is provided with a plated layer of gold or nickel provided on the surface by electric field plating or electroless plating. Become.

  Since the semiconductor device 10 includes the above-described semiconductor element mounting substrate 1, the semiconductor device 10 can be used even with a large current. Therefore, the semiconductor device 10 using various elements can be obtained.

  The present invention described above is not limited to the above-described embodiment, and various modifications and the like can be made without departing from the scope of the present invention.

1 Semiconductor Element Mounting Substrate 2 Substrate 3 Metal Plate 3a Mounting Area 3b Peripheral Area 4 Semiconductor Element 5 Frame 6 Lid 7 Electronic Component 10 Semiconductor Device 11 First Through Hole 12 Second Through Hole 13 Third Through Hole 14 Fourth Through hole 21 Through conductor 21a Lower part 22 Second through conductor 23 Third through conductor 31 First metallized layer 32 Second metallized layer 33 Third metallized layer 34 Fourth metallized layer

Claims (7)

A substrate having a first through hole and a second through hole formed at a distance from the first through hole; a first metallization layer that is a lower surface of the substrate and surrounds an outer edge of the first through hole;
A second metallization layer surrounding the outer edge of the second through hole on the lower surface of the substrate;
A metal plate having a mounting region for mounting a semiconductor element in a central portion of an upper surface and a peripheral region surrounding the mounting region, and the peripheral region overlapping the first metallization layer and blocking the first through hole. When,
A columnar body surrounded by the second through hole and spaced apart from an inner surface of the second through hole, wherein a lower portion of the columnar body is located below a lower surface of the substrate, and the entire circumference of the lower portion is formed. And a through conductor that is electrically connected to the semiconductor element, that is, the entire circumference of the lower portion overlaps with the second metallization layer and closes the second through hole. A substrate for mounting a semiconductor element, comprising:   2. The semiconductor element mounting substrate according to claim 1, wherein the entire surface of the side surface of the through conductor, which is located inside the second through hole, is spaced apart from the inner surface of the second through hole.   The semiconductor element mounting substrate according to claim 1 or 2, wherein the substrate is made of a ceramic material, and the through conductor is made of a metal material.   The semiconductor element mounting substrate according to claim 1, wherein a side surface of the through conductor located in the second through hole has a curved portion in a plan view. .   In plan view, the outer edge of the first metallization layer is formed larger than the outer edge of the metal plate, and the outer edge of the second metallization layer is formed larger than the outer edge of the lower portion of the through conductor. The semiconductor element mounting substrate according to any one of claims 1 to 4, wherein:   The substrate for mounting a semiconductor element according to claim 1, wherein the first metallization layer and the second metallization layer are formed to an outer edge of the substrate in a plan view. A semiconductor element mounting substrate according to any one of claims 1 to 6,
A semiconductor element mounted on the upper surface of the metal plate and electrically connected to the through conductor,
A frame body formed so as to surround the upper surface of the semiconductor element mounting substrate,
A semiconductor device comprising: a lid joined to an upper end of the frame.

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