JP6516029B2 - Field effect transistor and wireless communication device - Google Patents

Description

The present disclosure relates to a field effect transistor (FET) suitable for a switch element or the like of a high frequency device, and a wireless communication apparatus including the field effect transistor .

  At the front end of a mobile communication terminal such as a mobile phone, a high frequency switch (RF-SW) for turning on and off a high frequency (RF) is used. An important characteristic of such a high frequency switch is the reduction of the passing high frequency. To that end, it is important to reduce the resistance (on resistance) of the FET in the on state or the capacitance (off capacitance) of the FET in the off state, that is, to reduce the product of the on resistance and the off capacitance (Ron * Coff). .

  The off capacitance includes a component (intrinsic component) generated in the diffusion layer and the substrate, and a component (extrinsic component) generated in the gate electrode, the contact plug, and the wiring on the gate electrode, the contact plug, and the like. For example, in the field of fine MOSFETs, it has been proposed to reduce the parasitic capacitance between the gate electrode and the contact plug and reduce external components by creating an air gap around the gate electrode (see, for example, Patent Document 1). .

Japanese Patent Application Laid-Open No. 2002-359369

  However, in the configuration of Patent Document 1, it is difficult to sufficiently reduce the parasitic capacitance between the gate electrode and the wiring on the contact plug or the capacitance (inter-wiring capacitance) generated between the wirings on the contact plug. There is still room for improvement.

An object of the present disclosure is to provide a field effect transistor capable of reducing an external component of an off capacitance and a wireless communication device provided with the field effect transistor .

A first field effect transistor according to the present disclosure is provided with the following components (A) to (F).
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with a gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region One layer provided in a region between at least a plurality of contact plugs in an in-plane direction of a plurality of first metal (E) semiconductor layers respectively stacked on a plurality of contact plugs (D) and a plurality of contact plugs including a plug In a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the insulating film (F) semiconductor layer described above, only one above at least a part of the upper surface of the gate electrode And a low dielectric constant region provided in a first region below the lower surfaces of at least the plurality of first metals in the stacking direction. At least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side of the first contact plug and the second contact plug, and It occupies at least a part of a region between the side surface of the second contact plug and the side surface of the gate electrode.
The second field effect transistor according to the present disclosure includes the following components (A) to (G).
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with a gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region A plurality of contact plugs (D) including plugs provided in a region between at least the plurality of contact plugs in the in-plane direction of the plurality of first metal (E) semiconductor layers respectively stacked on the plurality of contact plugs; Provided in a region between at least a plurality of contact plugs in an in-plane direction of a first group of one or more insulating film (F) semiconductor layers provided below the lower surfaces of the plurality of first metals in the stacking direction; In-plane direction of at least one insulating film (G) semiconductor layer of the second group provided above part of the upper surface of the gate electrode in the stacking direction In the first contact plug and the specific section in which the gate electrode located between the second contact plugs in, together with the provided one only at least a portion of the upper surface of the gate electrode, of at least the plurality in the stacking direction first Low-permittivity region provided in the first region below the lower surface of the metal At least one of the insulating films of one or more layers of the first group is located outside the side of the low-permittivity region And covers the side surface of the first contact plug and the second contact plug, and occupies at least a part of the region between the side surface of the first contact plug and the second contact plug and the side surface of the gate electrode.
The third field effect transistor according to the present disclosure is provided with the following components (A) to (F).
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with a gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region One layer provided in a region between at least a plurality of contact plugs in an in-plane direction of a plurality of first metal (E) semiconductor layers respectively stacked on a plurality of contact plugs (D) and a plurality of contact plugs including a plug In a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the insulating film (F) semiconductor layer described above, only one above at least a part of the upper surface of the gate electrode And extends from above the at least part of the upper surface of the gate electrode in the stacking direction to the upper surfaces of at least the plurality of first metals. To provided in the region, at least one insulating film of a low dielectric constant region wherein any one or more insulating films lower end of the region located below the lower surface of the plurality of first metal is of low dielectric region side of It is located outside, covers the side surfaces of the first contact plug and the second contact plug, and occupies at least a part of the region between the side surfaces of the first contact plug and the second contact plug and the side surface of the gate electrode There is.

In the first field effect transistor of the present disclosure, a specific cross section where the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer, above at least a part of the upper surface of the gate electrode The low dielectric constant region is provided in only one of the first regions below the lower surface of at least the plurality of first metals in the stacking direction. Further, at least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, and the first contact It occupies at least a part of a region between the side surface of the plug and the second contact plug and the side surface of the gate electrode. Therefore, the parasitic capacitance between the gate electrode and the contact plug or the parasitic capacitance between the gate electrode and the first metal is reduced, and the external component of the off capacitance is reduced.
In the second field effect transistor of the present disclosure, a specific cross section where the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer, above at least a part of the upper surface of the gate electrode. The low dielectric constant region is provided in only one of the first regions below the lower surface of at least the plurality of first metals in the stacking direction. In addition, at least one of the first group of one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug. , And at least a part of a region between the side surfaces of the first contact plug and the second contact plug and the side surface of the gate electrode. Therefore, the parasitic capacitance between the gate electrode and the contact plug or the parasitic capacitance between the gate electrode and the first metal is reduced, and the external component of the off capacitance is reduced.
In the third field effect transistor of the present disclosure, a specific cross section where the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer , above at least a part of the upper surface of the gate electrode. A low dielectric constant region is provided in a region extending from above the at least part of the top surface of the gate electrode to the top surfaces of at least the plurality of first metals in the stacking direction. The lower end of the region provided with the low dielectric constant region is located below the lower surface of the plurality of first metals. Further, at least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, and the first contact It occupies at least a part of a region between the side surface of the plug and the second contact plug and the side surface of the gate electrode. Therefore, the parasitic capacitance between the gate electrode and the contact plug or the parasitic capacitance between the gate electrode and the first metal is reduced, and the external component of the off capacitance is reduced.

A high frequency device according to the present disclosure includes a high frequency switch having a field effect transistor, and a high frequency integrated circuit connected to the high frequency switch, and the field effect transistor has the following components (A) to (F). is there.
(A) Gate electrode (B) Semiconductor layer having a source region and a drain region with a gate electrode in between (C) First contact plug provided on the source region and second contact provided on the drain region One layer provided in a region between at least a plurality of contact plugs in an in-plane direction of a plurality of first metal (E) semiconductor layers respectively stacked on a plurality of contact plugs (D) and a plurality of contact plugs including a plug In the specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the insulating film (F) semiconductor layer described above, only one above the at least part of the upper surface of the gate electrode And a low dielectric provided in a first region below the lower surfaces of at least the plurality of first metals in the stacking direction. At least one insulating film of the region wherein any one or more insulating films, with located outside of the side of the low dielectric region covers a side surface of the first contact plug and a second contact plug, the first contact plug And at least a part of a region between the side surface of the second contact plug and the side surface of the gate electrode.

According to the first field effect transistor of the present disclosure or the wireless communication device of the present disclosure, in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer The low dielectric constant region is provided only at least above at least a portion of the upper surface of the gate electrode, and in the first region below the lower surface of at least the plurality of first metals in the stacking direction. In addition, at least one insulating film is located outside the side of the low dielectric constant region and covers the side of the first contact plug and the second contact plug, and the side of the first contact plug and the second contact plug And at least a part of the region between the gate electrode and the side surface of the gate electrode. Therefore, it becomes possible to reduce the external component of off capacity.
According to the second field effect transistor of the present disclosure, at least a portion of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer. The low dielectric constant region is provided only in the upper region of the first region, and in the first region below the lower surface of at least the plurality of first metals in the stacking direction. In addition, at least one of the first group of one or more insulating films is located outside the side of the low dielectric constant region, and covers the side surfaces of the first contact plug and the second contact plug. And at least a part of a region between the side surface of the first contact plug and the second contact plug and the side surface of the gate electrode. Therefore, it becomes possible to reduce the external component of off capacity.
According to the third field effect transistor of the present disclosure, at least a portion of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer. The low dielectric constant region is provided only in a region extending above at least a part of the top surface of the gate electrode in the stacking direction to the top surfaces of at least the plurality of first metals in the stacking direction. The lower end of the region provided with the low dielectric constant region is located below the lower surface of the plurality of first metals. Further, at least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, and the first contact It occupies at least a part of the region between the side surfaces of the plug and the second contact plug and the side surface of the gate electrode. Therefore, it becomes possible to reduce the external component of off capacity.

  In addition, the effect described here is not necessarily limited, and may be any effect described in the present disclosure.

It is a figure showing an example of the high frequency switch which has a field effect transistor concerning a 1st embodiment of this indication. It is a figure showing the SPST switch which is the basic composition of the high frequency switch shown in FIG. It is an equivalent circuit schematic of the SPST switch shown in FIG. FIG. 6 is an equivalent circuit diagram when the SPST switch shown in FIG. 3 is on. FIG. 6 is an equivalent circuit diagram when the SPST switch shown in FIG. 3 is off. FIG. 1 is a plan view illustrating an entire configuration of a field effect transistor according to a first embodiment of the present disclosure. It is sectional drawing in the VII-VII line of FIG. It is a figure which decomposes | disassembles and represents the off capacity | capacitance of a general field effect transistor for every component. It is sectional drawing showing the modification 1 of the low-dielectric area | region shown in FIG. FIG. 8 is a cross-sectional view showing a modification 2 of the low dielectric constant region shown in FIG. 7. FIG. 6 is a cross-sectional view illustrating a configuration of a field effect transistor according to Reference Example 1. A simulation in which the relationship between the width of the low dielectric constant region and the external component of the capacitance was examined for the present embodiment shown in FIG. 7, the second modification shown in FIG. 10, and the reference example 1 shown in FIG. It is a figure showing a result. It is sectional drawing showing the positional relationship of the field effect transistor and low dielectric constant area | region which were shown in FIG. 7, and a multilayer interconnection part. FIG. 8 is a plan view showing a positional relationship between the field effect transistor and the low dielectric constant region shown in FIG. 7 and a gate contact. It is sectional drawing in the XV-XV line of FIG. It is sectional drawing in the XVIA-XVIB line of FIG. It is sectional drawing in the XVIIB-XVIIC line of FIG. It is sectional drawing in the XVIIIC-XVIIID line of FIG. FIG. 8 is a cross-sectional view showing a method of manufacturing the field effect transistor shown in FIG. 7 in the order of steps. FIG. 20 is a cross-sectional view illustrating a process following FIG. FIG. 21 is a cross-sectional view illustrating a process following FIG. 20. FIG. 22 is a cross-sectional view illustrating a process following FIG. 21. FIG. 23 is a cross-sectional view illustrating a process following FIG. FIG. 24 is a cross-sectional view illustrating a process following FIG. FIG. 25 is a cross-sectional view illustrating a process following FIG. 24. FIG. 26 is a cross-sectional view illustrating a process following FIG. 25. FIG. 27 is a cross-sectional view illustrating a process following FIG. 26. FIG. 28 is a cross-sectional view illustrating a process following FIG. 27. FIG. 29 is a cross-sectional view illustrating a process following FIG. 28. FIG. 30 is a cross-sectional view illustrating a process following FIG. 29. FIG. 31 is a cross-sectional view illustrating a process following FIG. 30. FIG. 6 is a cross-sectional view illustrating a configuration of a field effect transistor according to a second embodiment of the present disclosure. It is sectional drawing showing the structure of the field effect transistor which concerns on 3rd Embodiment of this indication. It is sectional drawing showing the structure of the field effect transistor which concerns on 4th Embodiment of this indication. It is a top view showing the composition of the field effect transistor concerning a 5th embodiment of this indication. It is sectional drawing in the XXXVI-XXXVI line of FIG. It is sectional drawing in the XXXVII-XXXVII line of FIG. FIG. 36 is a plan view showing a method of manufacturing the field effect transistor shown in FIG. 35 in the order of steps. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX of FIG. 38. FIG. 39 is a plan view illustrating a process following FIG. 38. FIG. 41 is a cross-sectional view taken along line XXXXI-XXXXI of FIG. 40. FIG. 41 is a cross-sectional view taken along line XXXXII-XXXXII of FIG. 40. It is a top view showing the composition of the field effect transistor concerning a 6th embodiment of this indication. It is a block diagram showing an example of a radio communication apparatus.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order.
1. First embodiment (high frequency switch, field effect transistor; first region below the lower surface of the first metal in the stacking direction; second region between the lower surface and the upper surface of the first metal; Example of providing a low dielectric constant region in the third region above the top surface of the metal)
2. Second embodiment (field effect transistor; an example in which the second metal is laminated on the first metal and the low dielectric constant region is extended to the second metal)
3. Third embodiment (field effect transistor; an example in which a low dielectric constant region is provided with a width larger than a portion covering the surface of the gate electrode in the first insulating film and the second insulating film)
4. Fourth embodiment (field effect transistor; an example in which the first region and the second region of the low dielectric constant region are embedded with the fifth insulating film, and the third region is an air gap)
5. Fifth embodiment (field effect transistor; an example in which a low dielectric constant region is provided in a direction intersecting with the gate electrode)
6. Sixth embodiment (field effect transistor; an example in which a low dielectric constant region is provided in a finger portion of a gate electrode and at least a part of a connection portion)
7. Application example (wireless communication device)

First Embodiment
FIG. 1 shows the configuration of a high frequency switch having a field effect transistor according to the first embodiment of the present disclosure. The high frequency switch 1 is used for the front end of a portable information terminal such as a cellular phone, and the SPS shown in FIG.
It is used properly in various configurations such as T (Single Pole Single Throw ; single pole single throw), SPDT (Single Pole Double Throw ), SP3 T... SPNT (N is a real number). FIG. 1 shows an example of the SP10T switch. The SP10T switch has, for example, one pole connected to the antenna ANT and ten contacts. The high frequency switch 1 can have various configurations, but the high frequency switch 1 of any configuration is a combination of the basic circuit configuration of the SPST switch shown in FIG.

  FIG. 3 shows an equivalent circuit of the SPST switch 1A shown in FIG. The SPST switch 1A includes, for example, a first port Port1 connected to the antenna ANT, a second port Port2, a first switching element FET1, and a second switching element FET2. The first switching element FET1 is connected between the first port Port1 and the ground. The second switching element FET2 is connected between the first port Port1 and the second port Port2.

In the SPST switch 1A, on / off control is performed by applying control voltages Vc1 and Vc2 to the gates of the first switching element FET1 and the second switching element FET2 via resistors. When it is on, as shown in FIG. 4, the second switching element FET2 becomes conductive, and the first switching element FET1 becomes nonconductive. When it is off, as shown in FIG. 5, the first switching element FET1 becomes conductive, and the second switching element FET2 becomes nonconductive.

  The on-resistance and off-capacitance of the first switching element FET1 and the second switching element FET2 are determined using the values Ron [Ωmm], Coff [fF / mm], and gate widths Wg1 and Wg2 [mm] of FET per unit length. Are respectively represented as Ron / Wg1, Ron / Wg2, Coff * Wg1, and Coff * Wg2. The on resistance is inversely proportional to the gate widths Wg1 and Wg2, and the off capacitance is proportional to the gate widths Wg1 and Wg2.

  Another feature of the on-resistance and the off-capacitance is that the loss due to the on-resistance is not dependent on the frequency, but the off-capacitance loss increases with the frequency. If it is attempted to increase the gate width Wg in order to reduce the loss, high frequency loss may occur due to the input capacitance. Therefore, it is important to reduce both Ron and Coff per unit length, that is, to minimize Ron * Coff (product) as much as possible, in order to reduce loss using the gate width Wg as large as possible.

  FIG. 6 is a plan view showing the entire configuration of a field effect transistor according to the first embodiment of the present disclosure. The field effect transistor 10 is a high frequency device field effect transistor which constitutes the first switching element FET1 or the second switching element FET2 in the SPST switch 1A shown in FIG. 3, and comprises the gate electrode 20, the source electrode 30S, and the drain. And an electrode 30D.

  The gate electrode 20 has a multi-finger structure having a plurality of finger portions 21 extended in the same direction (for example, Y direction) and a connection portion (gate lead wiring) 22 connecting the plurality of finger portions 21. . The gate width Wg of the field effect transistor 10 used for the high frequency switch 1 is considerably larger than that of a field effect transistor used for logic etc. in order to reduce loss, and is several hundreds of um to several mm. The length (finger length) L21 of the finger portion 21 is, for example, several tens of um. The connecting portion 22 is connected to a gate contact (not shown in FIG. 6, see FIG. 14). In FIG. 6, the gate electrode 20 is shown with an oblique line.

  In the following description and drawings, the longitudinal direction of the finger portion 21 of the gate electrode 20 is Y direction, the longitudinal direction of the connecting portion 22 is X direction, and the direction (stacking direction) orthogonal to both is Y direction.

  Similar to the gate electrode 20, the source electrode 30S has finger portions 31S extended in the same direction (for example, Y direction), and a connecting portion (source lead wiring) 32S connecting the plurality of finger portions 31S. The coupling portion 32S is connected to a source contact (not shown).

  Similar to the gate electrode 20, the drain electrode 30D has finger portions 31D extended in the same direction (for example, Y direction), and a connection portion (drain lead-out wiring) 32D that connects the plurality of finger portions 31D. The coupling portion 32D is connected to a drain contact (not shown).

  The finger portions 31S of the source electrode 30S and the finger portions 31D of the drain electrode 30D are alternately disposed in the gaps of the finger portions 21 of the gate electrode 20. The finger portion 21 of the gate electrode 20, the finger portion 31S of the source electrode 30S, and the finger portion 31D of the drain electrode 30D are disposed inside the active region (active region) AA. The connection portion 22 of the gate electrode 20, the connection portion 32S of the source electrode 30S, and the connection portion 32D of the drain electrode 30D are element isolation regions AB outside the active region AA (not shown in FIG. 6, see FIG. Is placed.).

  FIG. 7 shows a cross-sectional configuration along the line VII-VII in FIG. 6, and shows one finger portion 21 of the gate electrode 20 and one finger portion 31S of the source electrode 30S and drain electrode disposed on both sides thereof. It shows one finger portion 31D of 30D. The field effect transistor 10 includes the gate electrode 20 described above, the semiconductor layer 50, the contact plugs 60S and 60D, the first metal M1, and the low dielectric constant region 70.

  The gate electrode 20 is provided on the semiconductor layer 50 with the gate oxide film 23 interposed therebetween. The gate electrode 20 has a thickness of, for example, 150 nm to 200 nm, and is made of polysilicon. The gate oxide film 23 has a thickness of, for example, about 5 nm to 10 nm, and is made of silicon oxide (SiO 2).

  The semiconductor layer 50 is made of, for example, silicon (Si). The semiconductor layer 50 has a source region 50S and a drain region 50D made of n-type (n +) silicon with the gate electrode 20 in between. Low resistance regions 51S and 51D made of high concentration n-type (n ++) silicon or silicide are provided on the surfaces of the source region 50S and the drain region 50D for connection with the contact plugs 60S and 60D. Between the source region 50S and the gate electrode 20 and between the drain region 50D and the gate electrode 20, extension regions 52S and 52D made of low concentration n-type (n−) silicon are provided.

  The semiconductor layer 50 is provided, for example, on the support substrate 53 with the buried oxide film 54 interposed therebetween. That is, the support substrate 53, the buried oxide film 54 and the semiconductor layer 50 constitute an SOI (Silicon on Insulator) substrate 55. The support substrate 53 is made of, for example, a high resistance silicon substrate. The buried oxide film 54 is made of, eg, SiO 2.

  The contact plugs 60S, 60D are connected to the low resistance regions 51S, 51D of the source region 50S. The contact plugs 60S and 60D have, for example, a laminated structure (not shown) of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. The titanium layer is a film that reduces the contact resistance with the lower layer of the contact plugs 60S and 60D. The titanium nitride layer is a barrier metal that suppresses the diffusion of the tungsten layer provided on the inner side into silicon.

  The first metal M1 includes, for example, a source electrode 30S stacked on the contact plug 60S, and a drain electrode 30D stacked on the contact plug 60D. The first metal M1 has, for example, a thickness of 500 nm to 1000 nm, and is made of aluminum (Al).

  The low dielectric constant region 70 is provided in a region between the first metal M1 in the XY in-plane direction of the semiconductor layer 50, that is, in a region between the source electrode 30S and the drain electrode 30D (above the finger portion 21 of the gate electrode 20). It is done. The low dielectric constant region 70 is provided in the first region A1 below the lower surface of at least the first metal M1 in the stacking direction Z. Thereby, in the field effect transistor 10, it is possible to reduce the external component of the off capacitance.

  That is, as shown in FIG. 8, the off capacitance includes the component (intrinsic component) Cin generated in the diffusion layer and the substrate, the gate electrode 20, the contact plugs 60S and 60D, and the first metal M1 thereon. There is a component (extrinsic component) Cex which occurs in the like.

  The internal component Cin includes, for example, the following. Capacitances Cssub and Cdsub generated between the source region 50S or the drain region 50D and the support substrate 53. Capacitances Csg and Cdg generated between the source region 50S or the drain region 50D and the gate electrode 20. A capacitance Cds generated between the source region 50S and the drain region 50D. Capacitances Csb and Cdb generated between the source region 50S or the drain region 50D and the lower portion (body) of the semiconductor layer 50.

  The external component Cex includes, for example, the following. A capacitance between the gate electrode 20 and the contact plugs 60S and 60D or a capacitance CgM between the gate electrode 20 and the first metal M1. Capacitance (inter-wire capacitance) CMM1 generated between the first metals M1.

  FIG. 8 shows the off capacitance divided into component elements in a general field effect transistor. In FIG. 8, components corresponding to the field effect transistor 10 of the present embodiment shown in FIG. 7 are denoted by the same reference numerals.

  In order to reduce the off capacity, it is particularly effective to reduce the external component Cex. In the present embodiment, the external component Cex is reduced by providing the low dielectric constant region 70 in the region described above in the XY in-plane direction and the stacking direction Z. As a result, it is possible to reduce the product of the on resistance and the off capacitance (Ron * Coff) and to reduce the loss of the high frequency switch 1.

  Specifically, as shown in FIG. 7, the low dielectric constant region 70 includes the first region A1 described above and the second region A2 between the lower surface and the upper surface of the first metal M1 in the stacking direction Z. It is preferable to be provided in the third region A3 above the upper surface of the first metal M1. Thereby, a capacitance between gate electrode 20 and contact plugs 60S and 60D, a capacitance CgM between gate electrode 20 and first metal M1, or a capacitance generated between first metals M1 (inter-wiring capacitance) CMM1 etc. are suppressed and the off-component external component Cex is reduced.

(Modification 1)
Alternatively, as shown in FIG. 9, the low dielectric constant region 70 may be provided in the first region A1 and the second region A2 in the stacking direction Z. Also in this case, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D, or the capacitance CgM between the gate electrode 20 and the first metal M1, or the capacitance generated between the first metals M1. (Capacitance between wires) CMM1 or the like is suppressed, and the external component Cex of the off capacitance is reduced.

(Modification 2)
Furthermore, the low dielectric constant region 70 may be provided in the first region A1 in the stacking direction Z as shown in FIG. Also in this case, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D or the capacitance CgM between the gate electrode 20 and the first metal M1 is suppressed, and the external component Cex of the off capacitance is reduced.

(Reference example 1)
FIG. 11 shows a cross-sectional configuration of the field effect transistor 10R according to the first reference example. Reference Example 1 has the same configuration as that of the field effect transistor 10 of the present embodiment shown in FIG. 7 except that the low dielectric constant region 70 is provided in the second region A2 in the stacking direction Z. doing.

(simulation result)
FIG. 12 shows the width of the low dielectric constant region 70 of the external component Cex of the capacitance for the present embodiment shown in FIG. 7, the modified example 1 shown in FIG. 9 , and the reference example 1 shown in FIG. It represents the simulation result which investigated the dependency to W70.

As can be seen from FIG. 12, the external component Cex of the capacitance tends to decrease as the width W70 of the low dielectric constant region 70 increases. Further, in the modified example 1 in which the low dielectric constant area 70 is provided in the first area A1 and the second area A2 in the stacking direction Z, compared to the reference example 1 in which the low dielectric constant area 70 is provided only in the second area A2 in the stacking direction Z Thus, the external component Cex of the volume is reduced. Furthermore, in the present embodiment where the low dielectric constant region 70 is provided in the first region A1, the second region A2 and the third region A3 in the stacking direction Z, it also depends on the extension length of the low dielectric constant region 70 in the stacking direction Z. However, it can be seen that the external component Cex reduction effect of the capacity equal to or larger than that of the first modification can be obtained.

Furthermore, in the field effect transistor 10 shown in FIG. 7 , at least one insulating film 80 and an opening provided from the upper surface of the at least one insulating film 80 toward the upper surface of the gate electrode 20 on the semiconductor layer 50. And (concave portion) P. It is preferable that the low dielectric constant region 70 be provided in the opening P. This makes it possible to increase the width WP of the opening P. Therefore, in the case where the air gap is provided by wet etching in the vicinity of the gate electrode 20, the problem that the etching solution does not easily enter the narrow air gap is eliminated. This makes it possible to improve the etching uniformity in the wafer surface of the SOI substrate 55 and the uniformity of the characteristics of the field effect transistor 10. The width WP of the opening P is preferably 100 nm to 1000 nm, for example, because the opening P is provided between the source electrode 30S and the drain electrode 30D.

  Preferably, at least one insulating film 80 includes a plurality of insulating films having different etching rates. In the manufacturing process to be described later, it is possible to control the etching stop position of the opening P with high accuracy by utilizing the difference in the etching rates of the plurality of insulating films. Therefore, the dose loss of the Si surface which occurs when the surface of the gate electrode 20 is scraped or the side surface of the gate electrode 20 is scraped and the etching reaches the Si surface, the variation of the gate length by side etching of the gate oxide film 23, It is possible to suppress an increase in variation in threshold voltage caused thereby, stably manufacture the field effect transistor 10, and improve the reliability of the field effect transistor 10.

  Specifically, it is preferable that at least one insulating film 80 includes, for example, a first insulating film 81, a second insulating film 82, and a third insulating film 83. The first insulating film 81 covers the surface (upper surface and side surface) of the gate electrode 20 and the upper surface of the semiconductor layer 50. The second insulating film 82 covers the surface of the first insulating film 81. The third insulating film 83 is provided between the surface of the second insulating film 82 and the lower surface of the first metal M1. The second insulating film 82 is preferably made of a material different in etching rate from the first insulating film 81 and the third insulating film 83. For example, the first insulating film 81 and the third insulating film 83 are preferably made of a silicon oxide (SiO 2) film, and the second insulating film 82 is preferably made of a silicon nitride (SiN) film. As a result, the second insulating film 82 can have a function as an etching stopper layer. The opening P preferably penetrates at least the third insulating film 83 and reaches the upper surface of the second insulating film 82.

  Preferably, at least one insulating film 80 further includes a fourth insulating film 84. The fourth insulating film 84 covers the upper surface of the third insulating film 83 and the surface (upper surface and side surface) of the first metal M1. The opening P preferably penetrates the fourth insulating film 84 and the third insulating film 83 from the upper surface of the fourth insulating film 84 to reach the upper surface of the second insulating film 82. The fourth insulating film 84 is preferably made of, for example, a silicon oxide (SiO 2) film.

  Furthermore, it is preferable that the at least one insulating film 80 further include a fifth insulating film 85 on the fourth insulating film 84. An air gap AG (Air Gap) is preferably provided as a low dielectric constant region 70 in at least a part of the opening P. The configuration of the low dielectric constant region 70 or the air gap AG is not particularly limited as long as it has a dielectric constant lower than that of the silicon oxide (SiO 2, dielectric constant 3.9) film constituting the third insulating film 83 and the fourth insulating film 84. For example, air (dielectric constant 1.0) may exist in the air gap AG or may be vacuum. The upper portion of the air gap AG is preferably closed by the fifth insulating film 85. Thus, the air gap AG is hermetically sealed by the fifth insulating film 85. The fifth insulating film 85 may cover the side and bottom of the opening P. The fifth insulating film 85 is made of, for example, a silicon oxide (SiO 2) film. In addition, a sixth insulating film 86 made of, for example, silicon oxide (SiO 2) may be provided in the upper layer of the fifth insulating film 85, if necessary.

  The low dielectric constant region 70 is preferably provided, for example, with a width W 70 equal to or less than the width W 82 of a portion of the first insulating film 81 and the second insulating film 82 covering the surface of the gate electrode 20.

  FIG. 13 shows the positional relationship between the field effect transistor 10 and the low dielectric constant region 70 shown in FIG. 7 and the multilayer wiring portion 90 in the stacking direction Z. Field effect transistor 10 and low dielectric constant region 70 are provided in element region AA1 of active region AA. The multilayer wiring portion 90 is provided in the wiring area AA2 outside the element area AA1 in the active area AA. The element area AA1 and the wiring area AA2 are separated by an element isolation layer 100 by STI (Shallow Trench Isolation) method.

  The multilayer wiring section 90 includes, for example, a first wiring layer 91 and a second wiring layer 92. The first wiring layer 91 is, for example, the same layer as the source electrode 30S and the drain electrode 30D, that is, the first metal M1. The second wiring layer 92 is, for example, a second metal M2 that is an upper layer than the first metal M1. The first wiring layer 91 and the second wiring layer 92 are connected by, for example, a contact plug 93.

  The low dielectric constant region 70 is not provided between the first wiring layers 91 of the multilayer wiring portion 90 or between the second wiring layers 92. That is, the low dielectric constant region 70 is provided inside the field effect transistor 10 in the element region AA1 in the active region AA.

  FIG. 14 shows the positional relationship between the field effect transistor 10 and the low dielectric constant region 70 shown in FIG. 7 and the gate contact GC in the in-X-Y direction. Field effect transistor 10 and low dielectric constant region 70 are provided in active region AA. The gate contact GC is provided in the element isolation region AB outside the active region AA. In the element isolation region AB, instead of the semiconductor layer 50, an element isolation layer 100 is provided by the STI method over the entire surface.

  In the active area AA, the finger portion 21 of the gate electrode 20, the finger portion 31S of the source electrode 30S, and the finger portion 31D of the drain electrode 30D are provided. The finger portion 21 of the gate electrode 20 is extended in one direction (for example, the Y direction). The finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D are extended on both sides of the finger portion 21 of the gate electrode 20 in parallel with the finger portion 21 of the gate electrode 20. The contact plugs 60S and 60D are provided below the finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D, and extend in parallel to the finger portion 21 of the gate electrode 20. The low dielectric constant region 70 is provided on the finger portion 21 of the gate electrode 20 and is extended parallel to the finger portion 21 of the gate electrode 20. In other words, the low dielectric constant region 70 is provided at a position overlapping the finger portion 21 of the gate electrode 20 in the in-XY-plane direction.

  In the element isolation region AB, the connection portion 22 of the gate electrode 20, the connection portion 32S of the source electrode 30S, and the connection portion 32D of the drain electrode 30D are provided. The connection portion 22 of the gate electrode 20 is connected to the gate contact GC. The connection portion 32S of the source electrode 30S is connected to a source contact (not shown). The connection portion 32D of the drain electrode 30D is connected to a drain contact (not shown).

  FIG. 15 shows a cross-sectional configuration of the gate contact GC shown in FIG. The gate contact GC has the connection portion 22 of the gate electrode 20, the gate contact plug 24, and the gate contact layer 25 in this order on the element isolation layer 100 by the STI method. The gate contact plug 24 is provided in the same layer as the contact plugs 60S and 60D. The gate contact layer 25 is provided in the same layer as the source electrode 30S and the drain electrode 30D, that is, the first metal M1.

  FIG. 16 shows a cross-sectional configuration taken along line XVIA-XVIB in FIG. FIG. 17 shows a cross-sectional configuration taken along line XVIIB-XVIIC in FIG. FIG. 18 shows a cross-sectional configuration along the line XVIIIC-XVIIID in FIG.

  As shown in FIGS. 14 to 18, the low dielectric constant region 70 is preferably provided so as to avoid the gate contact GC. When the low dielectric constant region 70 is provided on the connecting portion 22 of the gate contact GC, it is difficult to provide the gate contact plug 24 on the connecting portion 22.

  Further, the gate contact GC is preferably covered with at least one insulating film 80, that is, the first insulating film 81 to the sixth insulating film 86, similarly to the gate electrode 20 in the field effect transistor 10. By covering the gate contact GC with at least one insulating film 80, the reliability of the gate contact GC is maintained.

  The field effect transistor 10 can be manufactured, for example, as follows.

  19 to 31 show a method of manufacturing the field effect transistor 10 in the order of steps. First, as shown in FIG. 19, an SOI substrate 55 having a buried oxide film 54 and a semiconductor layer 50 is prepared on a support substrate 53, and the semiconductor layer 50 of the SOI substrate 55 is separated by, for example, STI. 100 is formed to separate the element area AA1 in the active area AA.

  Next, a silicon oxide film is formed as an implanter film (not shown) by, eg, thermal oxidation, and well implantation and channel implantation are performed on the active area AA, and then the implanter film is removed. Subsequently, as shown in FIG. 20, a gate oxide film 23 made of, for example, silicon oxide is formed to a thickness of, for example, about 5 nm to 10 nm by thermal oxidation. After that, a gate electrode material film (not shown) made of polysilicon is formed to a thickness of, for example, 150 nm to 200 nm by, for example, a CVD (Chemical Vapor Deposition) method. By processing this gate electrode material film, for example, by photolithography and etching, gate electrode 20 is formed on the upper surface side of semiconductor layer 50 with gate oxide film 23 in between, as also shown in FIG. .

  After gate electrode 20 is formed, as shown in FIG. 21, gate electrode 20 is formed by implantation IMPL of arsenic (As) or phosphorus (P) using gate electrode 20 and offset spacer (not shown) as a mask. Extension regions 52S and 52D are formed on both sides. Furthermore, sidewalls (not shown) are formed on the side surfaces of the gate electrode 20, and implantation of arsenic (As) or phosphorus (P) is performed. Thus, the source region 50S and the drain region 50D are formed in the semiconductor layer 50 with the gate electrode 20 interposed therebetween. After that, remove the sidewall.

  After forming the source region 50S and the drain region 50D, as shown in FIG. 22, a first insulating film 81 made of, for example, silicon oxide is formed on the surface of the gate electrode 20 and the upper surface of the semiconductor layer 50 by, eg, CVD. It is formed with a thickness of several tens of nm, for example, 10 nm to 30 nm.

  After forming the first insulating film 81, as shown in FIG. 23, the surface of the first insulating film 81 is made of, for example, silicon nitride having a different etching rate than the first insulating film 81 by, eg, CVD method. The second insulating film 82 is formed with a thickness of several nm to several tens of nm, for example, 5 nm to 30 nm.

  After forming the second insulating film 82, as shown in FIG. 24, a third insulating film 83 made of silicon oxide is formed with a thickness of, for example, 500 nm to 1000 nm on the second insulating film 82 by, eg, CVD. Do.

  After the third insulating film 83 is formed, as shown in FIG. 25, a part of the third insulating film 83, the second insulating film 82 and the first insulating film 81 is removed by photolithography and etching, and the source region 50S is formed. A contact hole H1 is formed in the drain region 50D. The contact hole H1 is provided in parallel with the finger portion 21 of the gate electrode 20, as shown in the plan view of FIG.

  After the contact holes H1 are formed, as shown in FIG. 26, low resistance regions 51S and 51D are formed by implantation IMPL of high concentration arsenic (As) or phosphorus (P).

  After the low resistance regions 51S and 51D are formed, as shown in FIG. 27, contact plugs 60S and 60D having a laminated structure of a titanium layer, a titanium nitride layer, and a tungsten layer are formed in the contact holes H1. The contact plugs 60S and 60D are provided on the source region 50S and the drain region 50D. The contact plugs 60S and 60D are provided in parallel with the finger portions 21 of the gate electrode 20, as shown in the plan view of FIG.

  After the contact plugs 60S and 60D are formed, as shown in FIG. 28, the source electrode 30S and the drain electrode 30D made of aluminum (Al) are formed as the first metal M1 on the contact plugs 60S and 60D. The finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D are provided in parallel with the finger portion 21 of the gate electrode 20, as shown in the plan view of FIG.

  After the source electrode 30S and the drain electrode 30D are formed, as shown in FIG. 29, a fourth insulating film 84 made of silicon oxide is formed on the upper surface of the third insulating film 83 and the surface of the first metal M1 by CVD, for example. Form

  After the fourth insulating film 84 is formed, as shown in FIG. 30, the opening P is formed by photolithography and dry etching. The opening P is formed in a region between the first metal M1 in the XY in-plane direction of the semiconductor layer 50, specifically, in a region between the source electrode 30S and the drain electrode 30D (above the finger portion 21 of the gate electrode 20). Form. The width WP of the opening P is, for example, 100 nm to 1000 nm. At this time, the second insulating film 82 functions as an etching stopper, and the etching of the opening P proceeds through the fourth insulating film 84 and the third insulating film 83 made of silicon oxide, and the upper surface of the second insulating film 82 Stop.

After forming the opening P, as shown in FIG. 31, a fifth insulating film 85 made of silicon oxide is formed on the fourth insulating film 84 by, eg, CVD. The fifth insulating film 85 is deposited while overhanging the upper portion of the opening P. Therefore, before the fifth insulating film 85 is buried in the opening P, the upper portion of the opening P is closed with the fifth insulating film 85, and the air gap AG hermetically sealed in the opening P is formed. The side surface and the bottom surface of the opening P may be covered with the fifth insulating film 85. The air gap AG has a dielectric constant lower than that of the third insulating film 83 , the fourth insulating film 84, and the fifth insulating film 85 (silicon oxide, dielectric constant 3.9), and has a function as a low dielectric constant region 70. In the air gap AG, air (dielectric constant 1.0) may be present or vacuum may be used, and it is not particularly limited. The air gap AG, that is, the low dielectric constant region 70 is formed by a first region A1 below the lower surface of the first metal M1, a second region A2 between the lower surface and the upper surface of the first metal M1, and an upper surface of the first metal. It is integrally and continuously provided over the upper third region A3.

  After that, as shown in FIG. 7, a sixth insulating film 86 is formed on the fifth insulating film 85 as necessary. Although not shown, the second metal M2, the third metal M3, etc. are formed on the fifth insulating film 85 by sequentially forming the insulating film and forming the metal layer in the same manner as the first metal M1. It is also good. Thus, the field effect transistor 10 shown in FIG. 7 is completed.

  In the field effect transistor 10, the first region A1 below the lower surface of the first metal M1 and the first metal in a region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50 in the stacking direction Z A low dielectric constant region 70 is provided in a second region A2 between the lower surface and the upper surface of M1 and a third region A3 above the upper surface of the first metal M1. Therefore, the capacitance between gate electrode 20 and contact plugs 60S and 60D, the capacitance CgM between gate electrode 20 and first metal M1, or the capacitance (inter-wiring capacitance) CMM1 generated between first metals M1. Etc., and the off-component external component Cex is reduced.

  As described above, in the present embodiment, the dielectric constant is low in the region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50, and in the first region A1 below the lower surface of at least the first metal M1 in the stacking direction Z. A rate area 70 is provided. Therefore, it becomes possible to reduce the external component Cex of the off capacitance, reduce the product of the on resistance and the off capacitance (RonCoff), and promote the reduction of loss which is an important characteristic of the high frequency switch 1. Become.

  Further, the low dielectric constant region 70 is provided over the first region A1, the second region A2, and the third region A3 described above in the stacking direction Z. Therefore, the capacitance between the gate electrode 20 and the contact plugs 60S, 60D, the capacitance CgM between the gate electrode 20 and the first metal M1, the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1, etc. It is possible to suppress and further reduce the off-component external component Cex.

  Furthermore, at least one insulating film 80 including a plurality of insulating films having different etching rates is provided on the semiconductor layer 50. Therefore, it becomes possible to control the etching stop position of the opening P with high accuracy by utilizing the difference in the etching rates of the plurality of insulating films. Therefore, the dose loss of the Si surface which occurs when the surface of the gate electrode 20 is scraped or the side surface of the gate electrode 20 is scraped and the etching reaches the Si surface, the variation of the gate length by side etching of the gate oxide film 23, It is possible to suppress an increase in variation in threshold voltage caused thereby, stably manufacture the field effect transistor 10, and improve the reliability of the field effect transistor 10.

  In addition, an opening P is provided from the upper surface of at least one insulating film 80 to the upper surface of the gate electrode 20, and a low dielectric constant region 70 is provided in the opening P. Therefore, the width WP of the opening P can be increased. Therefore, in the case where the air gap is provided by wet etching in the vicinity of the gate electrode 20, the problem that the etching solution does not easily enter the narrow air gap is eliminated. This makes it possible to improve the etching uniformity in the wafer surface of the SOI substrate 55 and the uniformity of the characteristics of the field effect transistor 10.

Second Embodiment
In the first embodiment, only the first metal M1 is stacked on the contact plugs 60S and 60D. However, the present disclosure is also applicable to the case where the second metal M2 is stacked on the first metal M1, as in the field effect transistor 10A shown in FIG. Further, in this case, the low dielectric constant region 70 is extended to the second metal M2 to reduce the capacitance (inter-wiring capacitance) CMM2 between the second metals M2, and the off capacitance It is possible to further suppress the external component Cex.

The second metal M 2 is provided between the fourth insulating film 84 and the fifth insulating film 85. The first metal M1 and the second metal M2 are connected by a contact plug 94. Further, at least one insulating film 80 further includes a seventh insulating film 87 covering the upper surface of the fourth insulating film 84 and the surface of the second metal M2. The opening P penetrates the seventh insulating film 87, the fourth insulating film 84, and the third insulating film 83 from the upper surface of the seventh insulating film 87 to reach the upper surface of the second insulating film 82. In the opening P, an air gap AG similar to that of the first embodiment is provided as the low dielectric constant region 70.

  The air gap AG is from the first area A1 below the lower surface of the first metal M1, the second area A2 between the lower surface and the upper surface of the first metal M1, and the upper surface of the first metal M1 in the stacking direction Z. Is also provided in the upper third region A3. In the third region A3, the air gaps AG are provided between the first metal M1 and the second metal M2. Therefore, in the present embodiment, as in the first embodiment, the capacitance between the gate electrode 20 and the contact plugs 60S and 60D or the capacitance CgM between the gate electrode 20 and the first metal M1, or In addition to the fact that the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1 is suppressed, the capacitance (inter-wiring capacitance) CMM2 generated between the second metals M2 is also suppressed, and the external component of the off capacitance Cex is reduced.

Third Embodiment
In the first embodiment, the low dielectric constant region 70 is provided with a width W 70 which is equal to or less than the width W 82 of the portion of the first insulating film 81 and the second insulating film 82 which covers the surface of the gate electrode 20. Case was explained. However, when the width of the finger portion 21 of the gate electrode 20 is reduced, the low dielectric constant region 70 is formed of the first insulating film 81 and the second insulating film 82 as in the field effect transistor 10B shown in FIG. Among them, the width W 70 may be larger than the width W 82 of the portion covering the surface of the gate electrode 20.

Fourth Embodiment
Furthermore, in the first embodiment, the case where the air gap AG hermetically sealed in the opening P is provided as the low dielectric constant region 70 has been described. However, the low dielectric constant region 70 is not limited to the air gap AG, and may be made of a material having a dielectric constant lower than that of the third insulating film 83 and the fourth insulating film 84 (the insulating film through which the opening P penetrates). Specifically, for example, in the case where the third insulating film 83 and the fourth insulating film 84 are silicon oxide (SiO 2, dielectric constant: 3.9) films, the fifth insulating film 85 is oxidized by adding SiOC (carbon). It is also possible to use silicon, a dielectric constant of 2.9), and to bury at least a part of the opening P with the fifth insulating film 85. For example, as in the field effect transistor 10C shown in FIG. 34, the first area A1 and the second area A2 of the low dielectric constant area 70 have a lower dielectric constant than the third insulating film 83 and the fourth insulating film 84. 5 may be buried by the insulating film 85. In addition, the air gap AG may be provided in the third region A3 of the low dielectric constant region 70.

Fifth Embodiment
In addition, in the first embodiment, the case where the low dielectric constant region 70 is extended in parallel with the finger portion 21 of the gate electrode 20 has been described. However, as in the field effect transistor 10D shown in FIGS. 35 to 37, the low dielectric constant region 70 crosses the finger portion 21 of the gate electrode 20, for example, with respect to the finger portion 21 of the gate electrode 20. It may be extended in the vertical direction (X direction). Thus, the influence of misalignment between the gate electrode 20 and the opening P and the low dielectric constant region 70 can be reduced. Further, in this case, a plurality of low dielectric constant regions 70 may be arranged along the extension direction (Y direction) of the finger portion 21 of the gate electrode 20.

Figure 38 to Figure 42 is to the method of manufacturing the field effect transistor 10 D according to the embodiment shown in process order. The steps overlapping with the first embodiment will be described with reference to FIGS. 19 to 31.

  First, as shown in FIGS. 38 and 39, in the same manner as in the first embodiment, the gate electrode 20 is formed on the upper surface side of the semiconductor layer 50 by the steps shown in FIGS. After the source region 50S and the drain region 50D are formed in the layer 50, first to third insulating films 81 to 83, contact plugs 60S and 60D, a first metal M1 and a fourth insulating film 84 are formed.

  Next, as shown in FIGS. 40 to 42, a resist film R1 is formed on the fourth insulating film 84, and an opening P is formed by dry etching using the resist film R1 as a mask.

  Subsequently, the resist film R1 is removed, and as shown in FIGS. 35 to 37, the fifth insulating film 85 is formed on the fourth insulating film 84, and the upper portion of the opening P is closed with the fifth insulating film 85. To form a hermetically sealed air gap AG in the opening P. Thus, field effect transistor 10D shown in FIGS. 35 to 37 is completed.

Sixth Embodiment
Furthermore, in the first embodiment, as shown in FIG. 14, the low dielectric constant region 70 (air gap AG etc.) is provided above the finger portion 21 of the gate electrode 20 in the active area AA. Case was explained. However, as in the field effect transistor 10E shown in FIG. 43, the low dielectric constant region 70 can be provided above the finger portion 21 or above at least a part of the connection portion 22. Specifically, it is preferable that the low dielectric constant region 70 is provided above the region of the coupling portion 22 where the finger portion 31D of the drain electrode 30D and the coupling portion 32D are avoided. In FIG. 43, the low dielectric constant region 70 above the finger portion 21 of the gate electrode 20 is omitted.

(Example of application)
FIG. 44 illustrates an example of a wireless communication apparatus. The wireless communication device 3 is, for example, a mobile phone system having multiple functions such as voice, data communication, and LAN connection. The wireless communication device 3 includes, for example, an antenna ANT, the high frequency switch 1, a high power amplifier HPA, a high frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, and a data output unit. It has a DT and an interface unit I / F (for example, a wireless LAN (W-LAN; Wireless Local Area Network), Bluetooth (registered trademark), etc.). The high frequency switch 1 is configured by the high frequency switch 1 described with reference to FIGS. 1 to 5 in the first embodiment. The high frequency integrated circuit RFIC and the baseband unit BB are connected by an interface unit I / F.

  In the wireless communication device 3, at the time of transmission, that is, when the transmission system of the wireless communication device 3 outputs a transmission signal to the antenna ANT, the transmission signal output from the baseband unit BB is a high frequency integrated circuit RFIC, The signal is output to the antenna ANT via the high power amplifier HPA and the high frequency switch 1.

  At the time of reception, that is, when the signal received by the antenna ANT is input to the reception system of the wireless communication device 3, the reception signal is input to the baseband unit BB via the high frequency switch 1 and the high frequency integrated circuit RFIC. The signal processed by the baseband unit BB is output from an output unit such as an audio output unit MIC, a data output unit DT, and an interface unit I / F.

  Although the present disclosure has been described above by the embodiment, the present disclosure is not limited to the above embodiment, and various modifications are possible.

  Furthermore, for example, in the above embodiment, the configurations of the high frequency switch 1, the field effect transistor 10, and the wireless communication device 3 have been specifically mentioned and described, but these are limited to those including all the illustrated components. It is not a thing. In addition, it is also possible to replace some components with other components.

  In addition, although the case where the field effect transistor 10 is applied to the high frequency switch 1 of the wireless communication device 3 has been described in the above embodiment, the field effect transistor 10 is not limited to the high frequency switch (RF-SW), and PA (Power Amplifier) And other high frequency devices.

  Furthermore, the shape, material and thickness of each layer described in the above embodiment are not limited, and other shapes, materials and thicknesses may be used, or other film formation methods may be used. Good.

  Furthermore, for example, in the above embodiment, the case where the support substrate 53 of the SOI substrate 55 is a high resistance silicon substrate has been described. However, the SOI substrate 55 may be a so-called SOS (Silicon on Sapphire) substrate having a support substrate 53 made of sapphire. Since the support substrate 53 made of sapphire is insulating, the field effect transistor 10 formed on the SOS substrate exhibits characteristics closer to that of a compound FET such as GaAs. The present disclosure is applicable not only to the SOI substrate or the SOS substrate, but also to the case where the field effect transistor 10 is formed on a bulk substrate.

  In addition, the effect described in this specification is an illustration to the last, is not limited, and may have other effects.

The present technology can also be configured as follows.
(1)
A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A contact plug provided on the source region and the drain region;
A first metal stacked on the contact plug;
And a low dielectric constant region provided in a region between the first metals in the in-plane direction of the semiconductor layer and provided in a first region below the lower surface of the first metal at least in the stacking direction. Field effect transistor.
(2)
The electric field according to (1), wherein the low dielectric constant region is provided in the stacking direction in the first region and a second region between the lower surface of the first metal and the upper surface of the first metal. Effect transistor.
(3)
The field effect transistor according to (2), wherein the low dielectric constant region is provided in the first region, the second region, and a third region above the upper surface of the first metal in the stacking direction. .
(4)
At least one insulating film provided on the semiconductor layer;
And an opening provided from the upper surface of the at least one layer of insulating film to the upper surface of the gate electrode;
The field effect transistor according to (3), wherein the low dielectric constant region is provided in the opening.
(5)
The field effect transistor according to (4), wherein the at least one insulating film includes a plurality of insulating films having different etching rates.
(6)
The at least one insulating film is
A first insulating film covering a surface of the gate electrode and an upper surface of the semiconductor layer;
A second insulating film covering a surface of the first insulating film;
A third insulating film provided between the surface of the second insulating film and the lower surface of the first metal;
Including
The second insulating film is made of a material having an etching rate different from that of the first insulating film and the third insulating film.
The field effect transistor according to (4) or (5), wherein the opening penetrates at least the third insulating film and reaches an upper surface of the second insulating film.
(7)
The at least one insulating film further includes a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal,
The field effect transistor according to (6), wherein the opening extends from the upper surface of the fourth insulating film to the upper surface of the second insulating film.
(8)
The at least one insulating film further includes a fifth insulating film on the fourth insulating film,
An air gap is provided in at least a part of the opening as the low dielectric constant region,
The field effect transistor according to (7), wherein an upper portion of the air gap is closed by the fifth insulating film.
(9)
The field effect transistor according to (8), wherein the fifth insulating film covers the side surface and the bottom surface of the opening.
(10)
The low dielectric constant region is provided with a width equal to or less than the width of a portion of the first insulating film and the second insulating film covering the surface of the gate electrode. In any one of (6) to (9) Field effect transistor as described.
(11)
The gate electrode is extended in one direction,
The field effect transistor according to any one of (1) to (10), wherein the contact plug, the first metal, and the low dielectric constant region are extended in parallel to the gate electrode.
(12)
An element region in which the source region and the drain region are provided in the semiconductor layer;
A wiring area having a multilayer wiring portion,
And a device isolation layer for partitioning the device region and the wiring region.
The field effect transistor according to any one of (1) to (11), wherein the low dielectric constant region is provided in the element region.
(13)
An active area including the element area and the wiring area;
An element isolation region provided outside the active region and provided with the element isolation layer;
The element isolation region has a gate contact connected to the gate electrode on the element isolation layer,
The field effect transistor according to (12), wherein the low dielectric constant region is provided avoiding the gate contact.
(14)
A second metal is further provided between the fourth insulating film and the fifth insulating film,
The at least one insulating film further includes a seventh insulating film covering an upper surface of the fourth insulating film and a surface of the second metal,
The field effect transistor according to (8), wherein the opening extends from the upper surface of the seventh insulating film to the upper surface of the second insulating film.
(15)
The low dielectric constant region is provided with a width larger than the width of the portion covering the surface of the gate electrode among the first insulating film and the second insulating film. Any one of (6) to (9) The field effect transistor described in.
(16)
In at least a part of the opening, a fifth insulating film made of a material having a lower dielectric constant than the third insulating film and the fourth insulating film is embedded as the low dielectric constant region. Field effect transistor.
(17)
The gate electrode is extended in one direction,
The contact plug and the first metal are extended parallel to the gate electrode,
The field effect transistor according to any one of (1) to (16), wherein the low dielectric constant region is extended in a direction intersecting with the gate electrode.
(18)
The gate electrode has a plurality of finger portions extended in the same direction, and a connection portion connecting the plurality of finger portions.
The field effect transistor according to any one of (1) to (17), wherein the low dielectric constant region is provided above the finger portion or above at least a part of the connection portion.
(19)
The field effect transistor according to any one of (1) to (18), which is a field effect transistor for high frequency devices.
(20)
Forming a gate electrode on the upper surface side of the semiconductor layer;
Forming a source region and a drain region in the semiconductor layer with the gate electrode interposed therebetween;
Providing a contact plug over the source region and the drain region;
Laminating a first metal on the contact plug;
Providing a low dielectric constant region in a region between the first metals in the in-plane direction of the semiconductor layer, and in a first region lower than the lower surface of the first metal in the stacking direction. Production method.

DESCRIPTION OF SYMBOLS 1 ... High frequency switch, 3 ... Wireless communication apparatus, 10, 10A-10E ... Field effect transistor, 20 ... Gate electrode, 21 ... Finger part, 22 ... Connection part, 23 ... Gate oxide film, 24 ... Gate contact plug, 25 ... Gate contact layer 30S: source electrode 31S: finger portion 32S: connecting portion 30D: drain electrode 31D: finger portion 32D: connecting portion 50: semiconductor layer 50S: source region 50D: drain region 51S 51D: low resistance region 52S 52D: extension region 53: supporting substrate 54: buried oxide film 55: SOI substrate 60S, 60D: contact plug 70: low dielectric constant region 80: insulation of at least one layer Film 81: first insulating film 82: second insulating film 83: third insulating film 84: fourth insulating film 85 Fifth insulating film 86: sixth insulating film 87: seventh insulating film 90: multilayer wiring portion 91: first wiring layer 92: second wiring layer 93: contact plug 100: element isolation layer A1 ... first area, A2 ... second area, A3 ... third area, AA ... active area, AA1 ... element area, AA2 ... wiring area, AB ... element isolation area, AG ... air gap, M1 ... first metal, M2 ... 2nd metal, P ... opening.

Claims (35)

A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region;
A plurality of first metals respectively stacked on the plurality of contact plugs;
One or more insulating films provided in a region between at least the plurality of contact plugs in the in-plane direction of the semiconductor layer;
Only one is provided above at least a part of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer And a low dielectric constant region provided in a first region below the lower surface of at least the plurality of first metals in the stacking direction,
At least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, A field effect transistor which occupies at least a part of a region between a first contact plug and a side surface of the second contact plug and a side surface of the gate electrode. The field effect transistor according to claim 1, wherein the low dielectric constant region is constituted by an air gap. The field effect transistor according to claim 2, wherein an upper end of the air gap is formed of one of the one or more insulating films. The upper end of the air gap is formed of one insulating film out of the one or more insulating films, and is provided at a position below the lower surface of the plurality of first metals in the stacking direction. Field effect transistor. One of the one or more insulating films is provided between the lower surface of the plurality of first metals and the upper surface of the gate electrode in the stacking direction, and forms the upper end of the air gap. The field effect transistor according to claim 2. The one or more insulating films include a first insulating film, a second insulating film, and a third insulating film.
The first insulating film extends along at least a side surface of the gate electrode,
At least a portion of the first insulating film is provided between the second insulating film and the gate electrode.
The third insulating film is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer, and is provided below the lower surface of the plurality of first metals in the stacking direction.
The third insulating film is located outside the side of the air gap and covers the side of the first contact plug and the second contact plug, and the side of the first contact plug and the second contact plug The field effect transistor according to any one of claims 2 to 5, wherein the field effect transistor occupies at least a part of a region between the second insulating film and the second insulating film . At least the first insulating film and the second insulating film of the first insulating film, the second insulating film, and the third insulating film are one of the contact plugs of the plurality of contact plugs and the gate. The field effect transistor according to claim 6, which occupies a region between the side surfaces of the electrode. The field effect transistor according to claim 6, wherein the plurality of contact plugs are provided to penetrate the first insulating film, the second insulating film, and the third insulating film. The field effect transistor according to any one of claims 6 to 8, wherein the second insulating film is made of a material having an etching rate different from that of the first insulating film and the third insulating film. The one or more insulating films further include a fourth insulating film,
The upper end of the air gap is formed of the fourth insulating film, and is provided at a position below the lower surface of the plurality of first metals in the stacking direction. Field effect transistor. The one or more insulating films further include a fourth insulating film,
The field effect transistor according to any one of claims 6 to 9, wherein the fourth insulating film is provided between the side portion of the air gap and the third insulating film. The field effect transistor according to any one of claims 2 to 11, wherein a lower end of the air gap is located in the vicinity of the upper surface of the gate electrode in the stacking direction. The low dielectric constant region is provided in the stacking direction in the first region and a second region between the lower surfaces of the plurality of first metals and the upper surfaces of the plurality of first metals. The field effect transistor according to any one of 1 to 12. The electric field according to claim 13, wherein the low dielectric constant region is provided in the stacking direction, in the first region, the second region, and a third region above the upper surfaces of the plurality of first metals. Effect transistor. The one or more insulating films have an opening, and the opening is provided from the upper surface of the one or more insulating films toward the upper surface of the gate electrode.
The field effect transistor according to any one of claims 1 to 14, wherein the low dielectric constant region is provided in the opening. The gate electrode is extended in one direction,
The field effect transistor according to any one of claims 1 to 15, wherein the plurality of contact plugs, the plurality of first metals, and the low dielectric constant region are extended in parallel to the gate electrode. An element region in which the source region and the drain region are provided in the semiconductor layer;
A wiring area having a multilayer wiring portion,
And a device isolation layer for partitioning the device region and the wiring region.
The field effect transistor according to any one of claims 1 to 16, wherein the low dielectric constant region is provided in the element region. An active area including the element area and the wiring area;
An element isolation region provided outside the active region and provided with the element isolation layer;
The element isolation region has a gate contact connected to the gate electrode on the element isolation layer,
The field effect transistor according to claim 17, wherein the low dielectric constant region is provided avoiding the gate contact. And a plurality of second metals provided above each of the plurality of first metals,
The field effect transistor according to any one of claims 1 to 18, wherein the low dielectric constant region extends to at least upper surfaces of the plurality of second metals. 10. The device according to any one of claims 6 to 9, wherein the low dielectric constant region is provided with a width larger than a width of a portion of the first insulating film and the second insulating film covering the surface of the gate electrode. Field effect transistor as described. The gate electrode is extended in one direction,
The plurality of contact plugs and the plurality of first metals are extended in parallel to the gate electrode,
The field effect transistor according to any one of claims 1 to 15, 17 to 20, wherein the low dielectric constant region is extended in a direction intersecting with the gate electrode. The gate electrode has a plurality of finger portions extended in the same direction, and a connection portion connecting the plurality of finger portions.
The field effect transistor according to any one of claims 1 to 21, wherein the low dielectric constant region is provided above the finger portion or above at least a part of the connection portion. The field effect transistor according to any one of claims 1 to 22, which is a field effect transistor for high frequency devices. A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region;
A plurality of first metals respectively stacked on the plurality of contact plugs;
A first group of one or more insulating films provided in a region between at least the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided below the lower surfaces of the plurality of first metals in the stacking direction When,
A second group of one or more insulating films provided in a region between at least the plurality of contact plugs in the in-plane direction of the semiconductor layer and provided above a portion of the upper surface of the gate electrode in the stacking direction When,
Only one is provided above at least a part of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer And a low dielectric constant region provided in a first region below the lower surface of at least the plurality of first metals in the stacking direction,
At least one insulating film of the first group of one or more insulating films is located outside the side of the low dielectric constant region, and the side surfaces of the first contact plug and the second contact plug And covering at least a part of a region between the side surface of the first contact plug and the second contact plug and the side surface of the gate electrode. 25. The field effect transistor according to claim 24, wherein the low dielectric constant region is constituted by an air gap. The one or more insulating films of the first group have a first insulating film, a second insulating film, and a third insulating film.
The first insulating film extends along at least a side surface of the gate electrode,
At least a portion of the first insulating film is provided between the second insulating film and the gate electrode.
The third insulating film is provided in a region between the plurality of contact plugs in the in-plane direction of the semiconductor layer, and is provided below the lower surface of the plurality of first metals in the stacking direction.
The third insulating film is located outside the side of the air gap and covers the side of the first contact plug and the second contact plug, and the side of the first contact plug and the second contact plug 26. The field effect transistor according to claim 25 , wherein the field effect transistor occupies at least a part of a region between the first and second insulating films . The one or more insulating films of the second group have a fourth insulating film,
The field effect transistor according to claim 25 or 26 , wherein the upper end of the air gap is formed by the fourth insulating film, and is provided below the lower surface of the plurality of first metals in the stacking direction. The one or more insulating films of the second group have a fourth insulating film,
The field effect transistor according to claim 26, wherein the fourth insulating film is provided between the side of the air gap and the third insulating film. A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region;
A plurality of first metals respectively stacked on the plurality of contact plugs;
One or more insulating films provided in a region between at least the plurality of contact plugs in the in-plane direction of the semiconductor layer;
Only one is provided above at least a part of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer And at least a portion of the upper surface of the gate electrode in the stacking direction is provided in a region extending from at least a portion of the upper surface to the upper surface of the plurality of first metals. And a low dielectric constant region located below,
At least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, A field effect transistor which occupies at least a part of a region between a first contact plug and a side surface of the second contact plug and a side surface of the gate electrode. The field effect transistor according to claim 29, wherein the low dielectric constant region is constituted by an air gap. The region provided with the low dielectric constant region includes a first region, a second region, and a third region,
The first region is a region below the lower surfaces of the plurality of first metals in the stacking direction,
The second region is a region between the lower surface of the plurality of first metals and the upper surface of the plurality of first metals in the stacking direction,
The field effect transistor according to claim 29, wherein the third region is a region above the upper surface of the plurality of first metals in the stacking direction. And a plurality of second metals provided above each of the plurality of first metals,
The field effect transistor according to any one of claims 29 to 31, wherein the region provided with the low dielectric constant region extends to at least upper surfaces of the plurality of second metals. A high frequency switch having a field effect transistor;
A high frequency integrated circuit connected to the high frequency switch;
The field effect transistor is
A gate electrode,
A semiconductor layer having a source region and a drain region with the gate electrode interposed therebetween;
A plurality of contact plugs including a first contact plug provided on the source region and a second contact plug provided on the drain region;
A plurality of first metals respectively stacked on the plurality of contact plugs;
One or more insulating films provided in a region between at least the plurality of contact plugs in the in-plane direction of the semiconductor layer;
Only one is provided above at least a part of the upper surface of the gate electrode in a specific cross section in which the gate electrode is located between the first contact plug and the second contact plug in the in-plane direction of the semiconductor layer And a low dielectric constant region provided in a first region below the lower surface of at least the plurality of first metals in the stacking direction,
At least one of the one or more insulating films is located outside the side of the low dielectric constant region and covers the side surfaces of the first contact plug and the second contact plug, A wireless communication device occupying at least a part of a region between a first contact plug and a side surface of the second contact plug and a side surface of the gate electrode. 34. The wireless communication apparatus according to claim 33, further comprising a baseband unit connected to the high frequency integrated circuit. The wireless communication apparatus according to claim 34, further comprising an antenna connected to the high frequency switch.

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