JP6541862B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device provided with an IGBT (Insulated Gate Bipolar Transistor).

Conventionally, a trench IGBT having a high collector-emitter saturation voltage V _CE (sat) and a high short-circuit resistance has a p-type floating region. The p-type floating region is generally diffused into the drift layer to be in contact with the trench gate. This drift layer is either an epitaxial wafer or a pull-up wafer having a comparable resistance value.

Satoru Machida, Takahide Sugiyama, Masayasu Ishiko, Satoshi Yasuda, Jun Saito, Kimori Shibata, "Relationship Analysis of Switching Loss and Device Capacity of IGBT", Material of the Electronic Materials Research Institute of the Institute of Electrical Engineers of Japan 29), p. 55-59 Watanabe, Hiroshi Mori, Taisuke Arai, Keisuke Ishibashi, Kei Toyoda, Tetsuo Oda, Takuo Harada, Katsuaki Saito, "Low loss, low noise, high reliability 1.7kV trench IGBT with floating p layer separated from gate" Materials for Electronic Devices Research Institute of the Institute of Electrical Engineers of Japan (EDD-11, 66-83), p. 67-71 Patent No. 4785334

However, in the IGBT having a structure in which the p-type floating region and the trench gate are electrically connected, there is a problem that the switching loss increases because of the high floating capacitance in the junction region between the trench gate and the p-type floating region. There is also a problem that switching noise is generated at the time of switching on operation.
A technique for improving such problems of switching loss and switching noise without sacrificing various characteristics such as on voltage and short circuit withstand voltage of a semiconductor device has not been established yet.

  One embodiment of the present invention provides a semiconductor device comprising an IGBT capable of reducing the occurrence of switching loss and switching noise and achieving excellent on voltage and short circuit withstand capability.

  In one embodiment of the present invention, a semiconductor layer of a first conductivity type having a front surface and a back surface, a collector region of a second conductivity type formed in a surface layer portion of the back surface of the semiconductor layer, an outer peripheral surface, and an inner peripheral surface And a plurality of annular trenches formed on the surface of the semiconductor layer at intervals including each other in a mode in which the outer peripheral surfaces face each other, each including a bottom surface connecting the outer peripheral surface and the inner peripheral surface. An insulating film formed on the inner surface of each of the trenches, a gate junction embedded in the outer circumferential surface of each of the trenches with the insulating film interposed therebetween, and the gate junction on the inner circumferential surface of each of the trenches An emitter junction portion spaced apart from the bottom portion and sandwiching the insulating film, a central insulating film interposed between the gate junction portion and the emitter junction portion in each of the trenches, and the surface of the semiconductor layer The surface layer is formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other in the surface layer portion, and the surface of the semiconductor layer with respect to the central portion of the trench or the central portion of the trench in the thickness direction of the semiconductor layer A base region of the second conductivity type having a bottom located on the side, an emitter region of the first conductivity type formed in the surface layer portion of the base region, and the surface region of the surface of the semiconductor layer A second electrically conductive state is formed in a region surrounded by the inner circumferential surface, and a bottom portion located on the back surface side of the semiconductor layer with respect to the bottom surface of the trench in the thickness direction of the semiconductor layer A floating region of a conductive type, an interlayer insulating film selectively covering the surface of the semiconductor layer, and an insulating film formed on the interlayer insulating film and electrically connected to the gate junction And a surface gate electrode, wherein formed on the interlayer insulating film, the emitter junction and including, and electrically connected to the surface emitter electrode on the emitter region, to provide a semiconductor device.

According to this configuration, an FET structure including the semiconductor layer, the base region, and the emitter region is formed in the region between the first side surfaces of the plurality of trenches adjacent to each other in the surface layer portion of the surface of the semiconductor layer. Further, in the surface layer portion of the surface of the semiconductor layer, the floating region is formed in the region between the second side surfaces of the plurality of trenches adjacent to each other.
According to this configuration, the capacitive component due to the contact between the trench and the floating region can be made the capacitive component (capacitance between the collector and the emitter junction) in the junction region between the emitter junction and the floating region. Thus, the gate junction is not affected by the junction with the floating region. Therefore, switching loss can be reduced as compared with the conventional semiconductor device in which the floating region and the trench gate are joined. On the other hand, if the semiconductor layer opposed to the gate junction is grounded together with the collector region, the capacitance change between the gate junction and the semiconductor layer can be stably maintained during the switching operation. As a result, the occurrence of switching noise can be suppressed.

  On the other hand, the inventors of the present application form a semiconductor device including an IGBT having a structure in which a plurality of trench emitters are formed between adjacent trench gates and the trench emitter and the floating region are electrically connected (hereinafter referred to as “reference example Semiconductor device)) was examined. In this structure, since there is no junction region between the trench gate and the floating region, the above-mentioned problems of switching loss and switching noise can be improved. However, in the case of the semiconductor device according to the reference example, an FET structure is formed in each region between the trench gate and the trench emitter. Thus, the trench gate and the trench emitter face each other through the FET structure. Therefore, the carrier accumulation effect by sandwiching the FET structure with the trench gate is reduced, and the carrier density in the semiconductor layer is also reduced accordingly. As a result, the drift resistance in the semiconductor layer is increased, and the on voltage is likely to be increased.

  On the other hand, according to the configuration of the present invention, since the gate junctions can be made to face each other through the insulating film and the FET structure, the carrier accumulation effect by the gate junction can be enhanced. Thereby, the carrier density in the semiconductor layer is increased, so that the drift resistance in the semiconductor layer can be reduced. Thus, the on voltage of the semiconductor device can be reduced.

  Furthermore, according to the configuration of the present invention, unlike the semiconductor device according to the reference example, since the gate junction and the emitter junction are formed in the same trench, it is necessary to form the trench gate and the trench emitter. Absent. Thus, the number of FET structures to be formed can be reduced. That is, the number of contact openings for connecting the FET structure can be reduced. As a result, the contact opening ratio can be reduced, so that it is possible to effectively suppress the reduction in the short circuit withstand voltage of the semiconductor device.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of the semiconductor device shown in FIG. FIG. 2B is a schematic cross-sectional view showing one end of the trench of the semiconductor device shown in FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a reference example. FIG. 4 is a graph for comparing each steady-state loss of the semiconductor device shown in FIG. 1 and the semiconductor device according to the reference example. FIG. 5 is a graph for comparing carrier densities of the semiconductor device shown in FIG. 1 and the semiconductor device according to the reference example. FIG. 6A is a cross-sectional view for illustrating an example of a manufacturing process of the semiconductor device of FIG. FIG. 6B is a view showing the next manufacturing step of FIG. 6A. FIG. 6C is a view showing the next manufacturing step of FIG. 6B. FIG. 6D is a view showing the next manufacturing step of FIG. 6C. FIG. 6E is a view showing the next manufacturing step of FIG. 6D. FIG. 6F is a view showing the next manufacturing step of FIG. 6E. FIG. 6G is a view showing the next manufacturing step of FIG. 6F. FIG. 6H is a view showing the next manufacturing step of FIG. 6G. FIG. 6I is a view showing the next manufacturing step of FIG. 6H. FIG. 6J is a view showing the next manufacturing step of FIG. 6I. FIG. 6K is a view showing the next manufacturing step of FIG. 6J. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 10 is a schematic plan view of the semiconductor device according to the first reference example. FIG. 11 is a schematic plan view for explaining lead wiring of the semiconductor device according to the first reference example. FIG. 12 is an enlarged plan view of the lead wiring of the semiconductor device shown in FIG. 13A is a cross-sectional view as seen from the section line XIIIA-XIIIA shown in FIG. FIG. 13B is an electric circuit diagram for describing an electrical structure of the semiconductor device shown in FIG. FIG. 14A is a graph showing switching characteristics of the semiconductor device shown in FIG. FIG. 14B is a graph showing the switching characteristics of the semiconductor device shown in FIG. FIG. 14C is a graph showing the switching characteristics of the semiconductor device shown in FIG. FIG. 15 is a schematic plan view of the semiconductor device according to the second reference example. FIG. 16 is a schematic plan view for explaining lead wiring of the semiconductor device according to the second reference example. FIG. 17 is a schematic cross-sectional view showing a modification of the semiconductor device according to the first embodiment. FIG. 18 is a circuit diagram for explaining an inverter circuit to which the semiconductor device according to the first to fourth embodiments is applied. FIG. 19 is a schematic cross-sectional view showing a modification of the semiconductor device according to the first and second reference examples. FIG. 20 is a circuit diagram for explaining an inverter circuit to which the semiconductor device according to the first and second reference examples is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present invention.
The semiconductor device 1 is formed in a square shape in plan view viewed from the normal direction of the surface (hereinafter, simply referred to as “planar view”), and the gate finger 2 and the gate pad are formed on the surface peripheral portion. And 3 are formed. The gate finger 2 is formed in a substantially square ring shape along the peripheral portion of the semiconductor device 1 in a plan view. An active region 4 is formed in a region surrounded by the gate finger 2.

  At a central portion in the longitudinal direction of a region along one side of the gate finger 2, a gate pad 3 having a substantially square shape in plan view is provided. The gate pad 3 is formed integrally with the gate finger 2. A bonding wire (not shown) is connected to the gate pad 3 to supply power to the semiconductor device 1. The gate finger 2 and the gate pad 3 are made of, for example, a metal material containing Al as a main component. In this embodiment, an example in which the gate pad 3 is provided at the center in the longitudinal direction of the region along one side of the semiconductor device 1 will be described. However, the gate pad 3 is formed at one corner of the gate finger 2 May be

  In a region surrounded by the gate finger 2 and the gate pad 3, a removal region 5 for preventing the gate finger 2 and the gate pad 3 from coming into contact with the emitter electrode 6 is formed. The removal area 5 is formed in a concave annular shape in plan view along the gate finger 2 and the gate pad 3. Emitter electrode 6 is formed in a concave shape in which a part thereof is selectively recessed in plan view so as to cover the area surrounded by removal area 5. The gate pad 3 is disposed in the recessed area of the emitter electrode 6. Emitter electrode 6 is made of, for example, the same metal material as gate finger 2 and gate pad 3.

  A plurality of FET structures 8 forming a unit cell 7 of an IGBT (Insulated Gate Bipolar Transistor) are formed in a stripe shape in the active region 4. A region of constant width is provided between the plurality of FET structures 8, and one annular trench 10 is formed in this region. Thus, FET structures 8 and annular trenches 10 are alternately formed in the active region 4.

The annular trench 10 is formed in a closed curve structure formed in a rectangular annular shape which is elongated along the stripe direction. A p-type floating region 9 (a region indicated by a broken line in FIG. 1) is formed in the inner region of the annular trench 10.
The shape of the annular trench 10 is not limited to a rectangular annular shape in plan view, and may be any shape as long as it is annularly formed. For example, an annular trench 10 having an oval annular shape in plan view may be formed.

At both longitudinal ends of the annular trench 10, a gate contact trench 11 and an emitter contact trench 12 are formed. The gate contact trench 11 and the emitter contact trench 12 are drawn outward and inward from the respective ends of the annular trench 10 in opposite directions.
Each of the gate contact trench 11 and the emitter contact trench 12 is formed in an arch shape integrally connected to the annular trench 10 in a plan view. More specifically, each of the gate contact trench 11 and the emitter contact trench 12 has an arch shape (in this embodiment, a pair of pillars facing each other, and the pair of pillars facing each other over the short side of the annular trench 10). It is formed in the shape of a square arch including the beam part which connects the pillar part in a row. The gate finger 2 is disposed to cross the gate contact trench 11 formed in each annular trench 10 (specifically, covering the beam portion of the gate contact trench 11).

  Next, with reference to FIGS. 2A and 2B, a cross-sectional view of the semiconductor device 1 will be described. FIG. 2A is a schematic cross-sectional view of the semiconductor device 1 shown in FIG. FIG. 2B is a schematic cross-sectional view showing one end of the annular trench 10 of the semiconductor device 1 shown in FIG. FIG. 2A is a cross-sectional view when the semiconductor device 1 is cut in the direction perpendicular to the stripe direction of the annular trench 10. FIG. 2B is a cross-sectional view when the semiconductor device 1 is cut in the direction across the short side of the annular trench 10, the gate contact trench 11 and the emitter contact trench 12.

As shown to FIG. 2A and FIG. 2B, the semiconductor device 1 contains the semiconductor substrate 15 as an example of the semiconductor layer of this invention. The semiconductor substrate 15 is, for example, an n ⁻ -type silicon substrate, and has a structure in which a p ⁺ -type collector region 16 and an n ⁻ -type drain region 17 are formed in order from the back surface side. The p ⁺ -type collector region 16 is exposed on the entire back surface of the semiconductor substrate 15, and the n ⁻ -type drain region 17 is exposed on the surface of the semiconductor substrate 15.

The dopant concentration of the p ⁺ -type collector region 16 is, for example, 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . As the p-type dopant, for example, B (boron), Al (aluminum) or the like can be used (hereinafter the same). On the other hand, the dopant concentration of the n ⁻ -type drain region 17 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ . In addition, as the n-type dopant, for example, N (nitrogen), P (phosphorus), As (arsenic) or the like can be used (hereinafter the same).

  An annular trench 10 is formed in the semiconductor substrate 15 by digging the surface of the semiconductor substrate 15 in the thickness direction. The annular trench 10 is formed with a constant width. The side surface of the annular trench 10 is formed substantially perpendicular to the surface of the semiconductor substrate 15. The bottom of the annular trench 10 is formed to be rounded from the side surface of the annular trench 10. A p-type floating region 9 is formed in the inner region partitioned into the annular trench 10.

The p-type floating region 9 is a semiconductor region in which an electrically floating state is maintained. The p-type floating region 9 is, in this embodiment, formed so as to extend outward below the annular trench 10, and the bottom of the p-type floating region 9 is located deeper than the bottom of the annular trench 10. Specifically, the outer peripheral edge at the bottom of the p-type floating region 9 is located below the central insulating film 21 described later. Thus, the p-type floating region 9 is formed under the emitter junction 20 described later, but not under the gate junction 19. The dopant concentration of the p-type floating region 9 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

In the region between the annular trenches 10 adjacent to each other (the outer region of the annular trench 10), n ⁺ -type emitter regions 31 and n ⁻ -types facing each other across the p-type base region 28 in the depth direction of the annular trench 10 An FET structure 8 (unit cell 7) including the drain region 17 is formed.
The p-type base region 28 is shared by one annular trench 10 and the other annular trench 10 adjacent to each other. Further, in this embodiment, the interface between the p-type base region 28 and the n ⁻ -type drain region 17 is set at the central portion in the depth direction of the annular trench 10 or above the central portion. Are diffused and formed relatively shallowly in the semiconductor substrate 15. The dopant concentration of the p-type base region 28 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

In the p-type base region 28, a contact trench 29 dug down from the surface of the semiconductor substrate 15 is formed. The contact trench 29 is formed with a constant width along the longitudinal direction of the annular trench 10. At the bottom of the contact trench 29, ap ⁺ -type base contact region 30 is formed. The dopant concentration of the p ⁺ -type base contact region 30 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

An n ⁺ -type emitter region 31 is formed on the surface of the p-type base region 28 between the contact trench 29 and each annular trench 10. The n ⁺ -type emitter regions 31 are provided one by one on both sides of the contact trench 29, and each is exposed to the side surface of the contact trench 29. The dopant concentration of the n ⁺ -type emitter region 31 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .

  As shown in FIGS. 2A and 2B, an insulating film 18 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 15 and the inner surface (side and bottom) of each annular trench 10. A gate junction 19 and an emitter junction 20 are formed inside the insulating film 18 in the annular trench 10. Gate junction 19 and emitter junction 20 are spaced apart in annular trench 10 and are isolated from one another. More specifically, gate junction 19 and emitter junction 20 are formed in a film shape along the inner side and the outer side of annular trench 10 in the cross sections shown in FIGS. 2A and 2B, respectively. Thus, at the center in the width direction of the annular trench 10, a space defined by the back surfaces of the gate junction 19 and the emitter junction 20 (opposite to the contact surface with the annular trench 10) is formed. Then, by completely backfilling this space with the central insulating film 21 up to the opening end of the annular trench 10, the gate junction 19 and the emitter junction 20 are insulated and separated from each other.

The gate junction 19 is formed in a substantially square ring shape in plan view so as to surround the emitter junction 20. That is, the gate junction 19 is formed on the outer region side of the annular trench 10 and is joined to the FET structure 8 through the insulating film 18. Gate junction 19 is formed of, for example, an electrode material such as polysilicon.
The emitter junction portion 20 is formed on the inner region side of the annular trench 10 in a substantially square ring shape in plan view. That is, the emitter junction 20 is joined to the p-type floating region 9 through the insulating film 18. The emitter junction 20 is formed of the same material as the gate junction 19.

As shown in FIG. 2B, the gate contact trench 11 and the emitter contact trench 12 are formed at one end in the longitudinal direction of the annular trench 10 with a width W ₂ narrower than the width W ₁ of the annular trench 10. . The width W ₁ of the annular trench 10 is, for example, 1.5 μm to 3.0 μm, while the width W ₂ of the gate contact trench 11 and the emitter contact trench 12 is, for example, 0.7 μm to 1.2 μm. is there. The gate contact trench 11 and the emitter contact trench 12 may be formed to have different widths within the range of these numerical values.

  An insulating film 18 is formed on the inner surfaces of the contact trenches 11 and 12 in the same manner as the above-described annular trench 10. A buried gate electrode 24 is formed in the gate contact trench 11 via the insulating film 18. The buried gate electrode 24 is formed integrally with the gate junction 19 formed in the annular trench 10. On the other hand, a buried emitter electrode 25 is formed in the emitter contact trench 12 via the insulating film 18. The buried emitter electrode 25 is formed integrally with the emitter junction 20 formed in the annular trench 10.

  Since each contact trench 11, 12 is completely back-filled by each embedded electrode 24, 25, the area of polysilicon (electrode material) when each contact trench 11, 12 is viewed from the upper side in the depth direction Is at least equal to the diameter (width) of each contact trench 11, 12. As a result, it is possible to easily contact each of the embedded electrodes 24 and 25.

An interlayer film 34 is stacked on the surface of the semiconductor substrate 15 as shown in FIGS. 2A and 2B. In the interlayer film 34, a contact hole 35 integrally formed with the contact trench 29 is formed. Further, as shown in FIG. 2B, in the interlayer film 34, a contact hole 36 for emitter for selectively exposing the buried emitter electrode 25 and a contact hole 37 for gate for selectively exposing the buried gate electrode 24 are formed. It is done. The interlayer film 34 is made of, for example, an insulating material such as tetraethyl orthosilicate (TEOS), borophosphorous silicate glass (BPSG), silicon oxide (SiO ₂ ) or the like.

On the interlayer film 34, an emitter electrode 6, a gate finger 2, and a gate pad 3 (see FIG. 1) are formed.
Emitter electrode 6 enters contact trench 29 via contact hole 35, and is connected to n ⁺ -type emitter region 31 on the side surface of contact trench 29. Further, the emitter electrode 6 is connected to the p-type base region 28 via the p ⁺ -type base contact region 30 at the bottom of the contact trench 29.

Furthermore, the emitter electrode 6 enters the emitter contact hole 36 and is connected to the buried emitter electrode 25. Thereby, the power from the emitter electrode 6 is supplied to the emitter junction 20 through the buried emitter electrode 25.
On the other hand, gate finger 2 enters gate contact hole 37 and is connected to buried gate electrode 24. Thus, the power from the gate finger 2 (gate pad 3) is supplied to the gate junction 19 via the buried gate electrode 24.

  As described above, according to the semiconductor device 1, as shown in FIG. 2A, the p-type floating region 9 is disposed in the inward region of the annular trench 10. Emitter junctions 20 formed on the inner region side of trench 10 are opposed to each other. Conversely speaking, the gate junction 19 formed on the outer region side of the annular trench 10 is separated from the p-type floating region 9 via the emitter junction 20 and the central insulating film 21. Therefore, the capacitance component due to the contact between the annular trench 10 and the p-type floating region 9 can be made the capacitance between the collector and the emitter junction. On the other hand, since the gate junction 19 is not in contact with the p-type floating region 9, the gate junction 19 can be prevented from being affected by the capacitance due to the contact with the p-type floating region 9. As a result, switching loss can be effectively reduced.

In addition, the n ⁻ -type drain region 17 opposed to the gate junction 19 via the insulating film 18 is grounded together with the p ⁺ -type collector region 16. Therefore, since the change in capacitance between the gate junction 19 and the n ⁻ -type drain region 17 is stable during the switching operation, noise is less likely to occur. As a result, the generation of noise at the time of switching operation can be reduced.
Further, when the characteristics of the semiconductor device 1 and the characteristics of the semiconductor device 41 according to the reference example shown in FIG. 3 were examined by simulation, the graph shown in FIG. 4 and the graph shown in FIG. 5 were obtained. Hereinafter, after describing the configuration of the semiconductor device 41 according to the reference example of FIG. 3, the characteristics of the semiconductor device 1 will be described with reference to FIGS. 3 to 5.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 41 according to a reference example. In FIG. 3, parts corresponding to the parts shown in FIG. 2A described above are given the same reference numerals, and descriptions thereof will be omitted.
The semiconductor device 41 according to the reference example is a semiconductor device including an IGBT having a structure in which a plurality of trench emitters 43 are formed between adjacent trench gates 42 and the trench emitter 43 and the p-type floating region 9 are joined. is there. FIG. 3 shows an example in which two trench emitters 43 are formed between the trench gates 42 adjacent to each other.

  The trench gate 42 includes a gate electrode 45 embedded in the trench 44 via the insulating film 18, and the trench emitter 43 includes an emitter electrode 46 embedded in the trench 44 via the insulating film 18. The FET structure 8 is formed in each region between the trench gate 42 and the trench emitter 43. That is, in the semiconductor device 41 according to the reference example, there is no junction region between the trench gate 42 and the p-type floating region 9, and the contact trench 29 and the contact hole 35 correspond to the region where each FET structure 8 is formed. And are formed.

FIG. 4 is a graph for comparing each steady loss of the semiconductor device 1 shown in FIG. 1 and the semiconductor device 41 according to the reference example. FIG. 5 is a graph for comparing carrier densities of the semiconductor device 1 shown in FIG. 1 and the semiconductor device 41 according to the reference example.
The graph of FIG. 4 shows the relationship between the collector current I _C (A) and the voltage V _CE (V) between the collector and the emitter, and the graph of FIG. 5 shows the carrier density (1 / cm ⁻³ ) and the semiconductor substrate 15 Shows the relationship with the position (μm) from the surface of. In each graph of FIG. 4 and FIG. 5, the characteristic of the semiconductor device 1 is indicated by a solid line, and the characteristic of the semiconductor device 41 according to the reference example is indicated by a broken line.

Referring to FIG. 4, the collector current I _C of the semiconductor device 41 according to the reference example has a smooth region from its rise to a saturation region, and has a relatively high collector-emitter voltage V _CE . It can be confirmed that the saturation region has been reached.
On the other hand, the collector current I _C of the semiconductor device 1 is steep in the region from its rise to the saturation region, and reaches the saturation region in the state of a relatively low collector-emitter voltage V _CE. It can be confirmed that

Further, it can be confirmed that the on voltage of the semiconductor device 1 is lower than the on voltage of the semiconductor device 41 according to the reference example. Therefore, it can be said that the steady state loss of the semiconductor device 1 is lower than the steady state loss of the semiconductor device 41 according to the reference example. The on-state voltage is defined by the voltage V _CE between the collector and the emitter required to flow the rated current in the state where the voltage required for the on-state is applied between the gate and the emitter (the state where _V.sub.GE is applied). Be done.

Next, referring to FIG. 5, comparing the carrier density of the semiconductor device 1 with the carrier density of the semiconductor device 41 according to the reference example, the semiconductor device 1 covers the entire surface of the semiconductor substrate 15 from the entire back surface. It can be seen that the carrier density is higher than the carrier density of the semiconductor device 41 according to the reference example.
According to the configuration of the semiconductor device 41 according to the reference example, as shown in FIG. 3, there is no junction region between the trench gate 42 and the p-type floating region 9, so that the gate junction 19 has a capacitance between the collector and the gate junction. Can be expected to improve the problems of switching loss and switching noise. However, in the case of such a structure, the FET structure 8 is sandwiched between the trench gate 42 and the trench emitter 43 and not sandwiched between the adjacent trench gates 42. Therefore, the carrier accumulation effect by the trench gate 42 is reduced, and as the carrier density in the semiconductor substrate 15 is reduced as shown in FIG. 5, the drift resistance in the n ⁻ -type drain region 17 is increased. As a result, as shown in FIG. 4, the on-voltage of the IGBT becomes relatively high.

On the other hand, according to the configuration of the semiconductor device 1, as shown in FIG. 2A, since the FET structure 8 is sandwiched by the adjacent gate junctions 19, the carrier accumulation effect by the gate junction 19 can be enhanced. it can. As a result, as shown in FIG. 5, the carrier density in the semiconductor substrate 15 is increased, so that the drift resistance in the n ⁻ -type drain region 17 can be reduced. As a result, as shown in FIG. 4, the on-voltage of the IGBT can be reduced.

In addition, although not shown in the drawings, simulation of how much switching noise occurs for each of the structures of the semiconductor device 1 and the semiconductor device 41 according to the reference example shows that the noise of the structure of the semiconductor device 1 is a semiconductor device according to the reference example. It was confirmed to be significantly smaller than the 41 structure.
Furthermore, according to the configuration of the semiconductor device 1, unlike the semiconductor device 41 according to the reference example, the gate junction 19 and the emitter junction 20 are provided in the same annular trench 10, so the trench gate 42 and the trench There is no need to form the emitter 43. Therefore, the number of FET structures 8 to be formed can be reduced. That is, the number of contact trenches 29 (contact holes 35) for connecting the FET structure 8 can be reduced. As a result, the contact opening ratio can be reduced, so that the short circuit withstand capability of the IGBT can be effectively suppressed.

Next, manufacturing steps of the semiconductor device 1 will be described with reference to FIGS. 6A to 6K. 6A to 6K are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1 of FIG. 6A to 6K correspond to FIG. 2A, respectively.
In order to manufacture the semiconductor device 1, first, as shown in FIG. 6A, the semiconductor substrate 15 in a state in which the p ⁺ -type collector region 16 is not formed on the back surface side is prepared. Next, an ion implantation mask 50 having an opening selectively in the region where the p-type floating region 9 is to be formed is formed on the semiconductor substrate 15. Then, p-type dopant is implanted into the semiconductor substrate 15 through the ion implantation mask 50. Thereby, the ion implantation region 56 is formed. After the formation of the ion implantation region 56, the ion implantation mask 50 is removed.

  Next, as shown in FIG. 6B, the hard mask 51 having an opening selectively in the region where the annular trench 10, the gate contact trench 11 and the emitter contact trench 12 (see FIG. 2B) are to be formed is a semiconductor It is formed on a substrate 15. Then, the semiconductor substrate 15 is etched through the hard mask 51 to simultaneously form the trenches 10, 11 and 12. After forming the trenches 10, 11, 12, the hard mask 51 is removed.

Next, as shown in FIG. 6C, the surface of the semiconductor substrate 15 is thermally oxidized. As a result, a sacrificial oxide film 57 made of a silicon oxide film is formed on the surface of the semiconductor substrate 15 including the inner surfaces (bottom and side surfaces) of the trenches 10, 11 and 12.
Next, as shown in FIG. 6D, the semiconductor substrate 15 covered with the sacrificial oxide film 57 is annealed to diffuse the p-type dopant in the ion implantation region 56 (drive in). This annealing process is performed under the condition that the p-type dopant wraps around below the annular trench 10. At this time, since the sacrificial oxide film 57 is formed on the inner surface of the annular trench 10 prior to the drive-in process, it is possible to prevent ions from being lost from the inner surface. As a result, the p-type dopant can be diffused efficiently, and as a result, the p-type floating region 9 which wraps under the annular trench 10 is formed.

Next, as shown in FIG. 6E, after the sacrificial oxide film 57 is peeled off, the surface of the semiconductor substrate 15 is thermally oxidized to form the insulating film 18. Next, polysilicon is deposited on the surface of the semiconductor substrate 15 by, eg, CVD (Chemical Vapor Deposition) to form a polysilicon deposition layer 52. In this case, the width _{W 2} of the gate contact trench 11 and the emitter contact trench 12 is narrower than the width _{W 1} of the annular trench 10 _(see W 2 _{<W 1} Figure 2). Therefore, as shown in FIG. 6E, a polysilicon deposition layer 52 is formed in the annular trench 10 of width W ₁ following the shape of the inner surface, while each contact trench 11 12 of width W ₂ is The polysilicon deposition layers 52 deposited on the one and the other side surfaces are integrated inside the contact trenches 11 and 12. As a result, as shown in FIG. 2B, each contact trench 11, 12 can be completely backfilled by the polysilicon deposition layer 52, and the buried gate electrode 24 and the buried emitter electrode 25 buried in each contact trench 11, 12 can be used. You can get Next, the surface of the polysilicon deposition layer 52 is oxidized to form a thin polysilicon oxide film 53.

  Next, as shown in FIG. 6F, the surface of semiconductor substrate 15 is left to leave polysilicon deposited layer 52 formed on the side surface of annular trench 10 by anisotropic etching such as RIE (Reactive Ion Etching), for example. And the polysilicon deposition layer 52 formed on the bottom of the annular trench 10 is selectively removed. Thereby, the gate junction 19 and the emitter junction 20 are simultaneously formed.

Next, as shown in FIG. 6G, SiO ₂ is formed into an annular trench 10 (more specifically, the gate junction 19 and the emitter junction) by, for example, HDP-CVD (High Density Plasma CVD: High Density Plasma CVD) method or the like. 20) is deposited on the surface of the semiconductor substrate 15 so as to backfill the region between 20 and 20). Thereby, the SiO ₂ film 54 is formed.
Next, as shown in FIG. 6H, etch back is performed, for example, by dry etching or the like so that the surface of the SiO ₂ film 54 is substantially flush with the surface of the semiconductor substrate 15. Thereby, the central insulating film 21 interposed between the gate junction 19 and the emitter junction 20 is formed.

Next, as shown in FIG. 6I, an ion implantation mask 55 having an opening selectively is formed in the region where the p-type base region 28 and the n ⁺ -type emitter region 31 are to be formed. Then, the p-type dopant and the n-type dopant are selectively implanted into the semiconductor substrate 15 through the ion implantation mask 55. Thereby, the FET structure 8 including the p-type base region 28 and the n ⁺ -type emitter region 31 is formed. After the p-type base region 28 and the n ⁺ -type emitter region 31 are formed, the ion implantation mask 55 is removed.

Next, as shown in FIG. 6J, TEOS is deposited on the semiconductor substrate 15 by, eg, LP-CVD (Low Pressure CVD: low pressure CVD) method or the like to form an interlayer film 34. Next, a hard mask (not shown) having an opening selectively in the region where contact hole 35, emitter contact hole 36 and gate contact hole 37 (see FIG. 2B) are to be formed is formed on interlayer film 34. It is formed. Then, the interlayer film 34 is etched through the hard mask to form the contact holes 35, 36 and 37. At the same time as the contact holes 35, 36 and 37 are formed, a contact trench 29 dug down from the surface of the semiconductor substrate 15 is formed in the p-type base region 28. After the contact trench 29 is formed, the hard mask is removed. Next, p-type dopant is implanted into p-type base region 28 through contact trench 29 to form p ⁺ -type base contact region 30.

Next, as shown in FIG. 6K, materials of the emitter electrode 6 and the gate finger 2 (gate pad 3) are deposited on the interlayer film 34. Next, the material is patterned to simultaneously form the emitter electrode 6 and the gate finger 2 (gate pad 3). Next, p-type dopant is selectively implanted into the back surface of semiconductor substrate 15 to form p ⁺ -type collector region 16. Thus, the semiconductor substrate 15 has a structure in which the p ⁺ -type collector region 16 and the n ⁻ -type drain region 17 are formed in order from the back surface side. The semiconductor device 1 is manufactured through the above steps.

  FIG. 7 is a schematic cross-sectional view of a semiconductor device 61 according to a second embodiment of the present invention. The semiconductor device 61 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment described above in that instead of the p-type floating region 9, a relatively shallow p-type floating region 62 is formed. And a plurality of emitter trenches 63 are formed in the area surrounded by the annular trench 10. The other configuration is the same as that of the semiconductor device 1 according to the first embodiment described above. In FIG. 7, parts corresponding to the parts shown in FIG. 2A described above are given the same reference numerals, and descriptions thereof will be omitted.

  The p-type floating region 62 is formed at the same depth as the p-type base region 28 in this embodiment. In the region surrounded by the annular trench 10, a plurality of emitter trenches 63 as a second trench of the present invention is formed to penetrate the p-type floating region 62. In this embodiment, an example in which two emitter trenches 63 are formed in a region surrounded by the annular trench 10 is shown, but two or more emitter trenches 63 are formed. It is also good. In addition, one emitter trench 63 may be formed in a region surrounded by the annular trench 10.

The emitter trench 63 is formed integrally with the annular trench 10. More specifically, the emitter trench 63 is formed in a stripe shape in plan view in the longitudinal direction of the annular trench 10 in a region surrounded by the annular trench 10, and continues to the annular trench 10 at each short side of the annular trench 10 There is. Emitter trench 63 is formed to have the same cross-sectional shape as annular trench 10. That is, the width W ₃ of the emitter trench 63 is the same as the width W ₁ of the annular trench 10. Also, the emitter trench 63 is formed to the same depth as the annular trench 10.

  In the emitter trench 63, a pair of second emitter junctions 64 are formed in a stripe shape in plan view with the insulating film 18 interposed therebetween. The pair of second emitter junctions 64 is formed in the same configuration as the gate junction 19 and the second emitter junction 20 in the first embodiment described above. That is, the pair of second emitter junctions 64 are formed in the emitter trench 63 at an interval, and are insulated and separated from each other. More specifically, the pair of second emitter junctions 64 are separated from each other in the form of a film along the one and the other side surfaces of the emitter trench 63 in the cross section shown in FIG. Thus, at the center in the width direction of the emitter trench 63, a space defined by the back surfaces of the pair of second emitter junctions 64 (opposite to the contact surface with the emitter trench 63) is formed. Then, the space is completely filled with the central insulating film 21 back to the opening end of the emitter trench 63, whereby the pair of second emitter junctions are insulated and separated from each other.

  The pair of second emitter junctions 64 are each connected to the p-type floating region 62 via the insulating film 18. In addition, the pair of second emitter junctions 64 is formed to be integrally connected to the emitter junction 20 at each short side of the annular trench 10. Thus, power is supplied from the emitter electrode 6 to the second emitter junction 64 via the emitter junction 20. The pair of second emitter junctions 64 is formed of the same material as the gate junction 19 and the emitter junction 20.

  In order to form such a semiconductor device 61, for example, in the process of forming the annular trench 10 in FIG. 6B described above, the layout of the hard mask 51 may be changed to form the emitter trench 63. Thereafter, the second emitter junction 64 can be formed through the same steps (see FIGS. 6E to 6H) as the steps of forming the gate junction 19 and the emitter junction 20.

As described above, even with the configuration of the semiconductor device 61 according to the second embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained.
FIG. 8 is a schematic cross-sectional view of a semiconductor device 81 according to a third embodiment of the present invention. The semiconductor device 81 according to the third embodiment is different from the semiconductor device 61 according to the second embodiment described above in that an emitter trench 83 having a narrow width relative to the annular trench 10 is formed. . The other configuration is the same as that of the semiconductor device 61 according to the second embodiment described above. In FIG. 8, parts corresponding to the parts shown in FIG. 7 described above are given the same reference numerals, and descriptions thereof will be omitted.

A plurality of emitter trenches 83 are formed narrower than the width W ₁ of the annular trench 10 in a region surrounded by the annular trench 10. Width _{W 4} of the emitter trench 83 is, for example, be formed of the same width as the width _{W 2} of the gate contact trench 11 and the emitter contact trench 12 (see FIG. 2B), in 0.7μm~1.2μm is there. In this embodiment, an example in which three emitter trenches 83 are formed is shown, but one or two emitter trenches 83 may be formed. In addition, three or more emitter trenches 83 may be formed.

Unlike the above-described second embodiment, a pair of second emitter junctions 64 is not formed in the emitter trench 83, and a second emitter junction 84 embedded as an integral body is formed.
As described above, the semiconductor device 81 can also provide the same effects as the effects described in the second embodiment. Further, the width W ₄ of the emitter trench 83 is formed smaller than the width W ₁ of the annular trench 10. Therefore, in the process of FIG. 6E described above, the width W ₄ is narrower than the annular trench 10 by the same principle as the relatively narrow contact trenches 11 and 12 are completely back-filled with the polysilicon deposition layer 52. The emitter trench 83 can be completely backfilled with the polysilicon deposition layer 52, and a second emitter junction 84 buried in the emitter trench 83 can be obtained.

FIG. 9 is a schematic cross-sectional view of a semiconductor device 91 according to a fourth embodiment of the present invention. The semiconductor device 91 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment described above in that the semiconductor substrate 15 includes an n ⁻ -type buffer region 92, and a contact trench 29 is formed. And the point that a part of the p ⁺ -type base contact region 30 and the n ⁺ -type emitter region 31 is exposed from the surface of the semiconductor substrate 15. The other configuration is the same as that of the semiconductor device 1 according to the first embodiment described above. In FIG. 9, the parts corresponding to the parts shown in FIG. 2A described above are denoted by the same reference numerals, and the description thereof is omitted.

The semiconductor substrate 15 according to the semiconductor device 91 includes an n ⁻ -type buffer region 92 interposed between the p ⁺ -type collector region 16 and the n ⁻ -type drain region 17. The dopant concentration of the n ⁻ -type buffer region 92 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ .
Such an n ⁻ -type buffer region 92 selectively injects an n-type dopant on the back surface side of the semiconductor substrate 15 prior to the step of forming the p ⁺ -type collector region 16 in the step shown in FIG. It can be formed by

In each contact hole 35 related to the semiconductor device 91, a tungsten contact 93 containing tungsten is formed. The tungsten contact 93 is connected to the p ⁺ -type base contact region 30 and a part of the n ⁺ -type emitter region 31 on the surface of the semiconductor substrate 15. In addition, the emitter electrode 6 is connected to the p ⁺ -type base contact region 30 and the embedded emitter electrode 25 through the tungsten contact 93. On the other hand, the gate finger 2 is connected to the buried gate electrode 24 through the tungsten contact 93.

  As described above, according to the semiconductor device 91, since the tungsten contact 93 is formed in each contact hole 35, a good contact can be obtained. Therefore, in the process shown in FIG. 6J, the contact trench 29 may not be separately formed. Further, in the process shown in FIG. 6K, since tungsten may be embedded in each contact hole 35 when forming the emitter electrode 6 and the gate finger 2, the manufacturing process is not complicated. As described above, also by the configuration of the semiconductor device 91, the same effects as the effects described in the first embodiment can be obtained.

FIG. 10 is a schematic plan view of the semiconductor device 101 according to the first reference example.
As shown in FIG. 10, the semiconductor device 101 is formed in, for example, a square chip shape in a plan view (hereinafter simply referred to as a "plan view") when the surface of the semiconductor device 101 is viewed from the normal direction. There is. In the semiconductor device 101, an active area 102 and an end area 113 surrounding the active area 102 are set. The active region 102 is formed in a substantially rectangular shape in plan view in the inner region of the semiconductor device 101. Further, in the active region 102, a plurality of gate trenches 137 are formed in stripes.

  A gate metal 103 as an example of a surface gate metal selectively surrounding the active region 102 and an emitter electrode 104 selectively covering the active region 102 are formed on the surface of the semiconductor device 101. In FIG. 10, the gate metal 103 and the emitter electrode 104 are cross-hatched for the sake of clarity. The gate metal 103 further includes a gate pad 105 as an example of a pad portion, and a wiring portion 167 formed of a gate finger 106 and a pad peripheral portion 107.

The gate pad 105 is formed in a substantially rectangular shape in plan view at a central portion in the longitudinal direction of a region along one side 101 a of the semiconductor device 101. Power is externally supplied to the gate pad 105 by connecting a bonding wire 108. The gate pad 105 is made of, for example, a metal material containing Al (aluminum) as a main component.
The gate finger 106 is formed in a line shape so as to surround the active region 102 of the semiconductor device 101. More specifically, the gate finger 106 extends from the side of the gate pad 105 in the stripe direction of the gate trench 137 (that is, the direction along the side 101 a of the semiconductor device 101) in plan view, and further to the side 101 a. It is formed extending in a direction perpendicular to the stripe direction intersecting at right angles (that is, a direction along the other side 101 b and the side 101 c opposite to the other side 101 b). A pad peripheral portion 107 is formed around the gate pad 105 with the first removal region 110 interposed therebetween.

  In the first reference example, an example in which the gate pad 105 is provided at the longitudinal center of the region along one side 101 a of the semiconductor device 101 will be described. However, the gate pad 105 is formed at one corner of the semiconductor device 101. It may be done. In the first reference example, the gate finger 106 is not formed on the side 101 d opposite to the side 101 a of the semiconductor device 101, but the gate finger 106 is provided over the entire periphery of the semiconductor device 101. It may be formed.

  The first removal region 110 is formed in a substantially square ring shape in plan view so as to surround the periphery of the gate pad 105. The first removal area 110 is an area from which the metal material is removed, such that the gate pad 105 and the pad peripheral portion 107 are not in contact with each other. In the first reference example, an example in which the first removal region 110 is formed in an annular shape surrounding the entire circumference of the gate pad 105 will be described. It may be configured to selectively surround part of the periphery.

  The pad peripheral portion 107 is formed in a substantially square ring shape so as to surround the entire periphery of the gate pad 105 in plan view. The pad peripheral portion 107 is formed integrally with the gate finger 106 in an area lateral to the gate pad 105. In the pad peripheral portion 107, a second removal region 111 which selectively surrounds the periphery of the first removal region 110 is formed, whereby the pad peripheral portion 107 is formed of the first removal region 110 and the second removal region 111. And an outer region 107b surrounding the inner region 107a.

  In the inward region of the semiconductor device 101 partitioned into the gate metal 103, an emitter electrode 104 is formed with the third removal region 112 interposed therebetween. The third removal region 112 is formed in a line along the gate metal 103. Emitter electrode 104 is formed to cover active region 102. In the region under the gate metal 103 and the emitter electrode 104, the first lead wiring 115, the gate finger lead wiring 116 and the second lead wiring 117 are formed via the interlayer insulating film 145 (see FIG. 13A).

FIG. 11 is a schematic plan view for explaining the first lead-out wiring 115, the gate finger lead-out wiring 116, and the second lead-out wiring 117 of the semiconductor device 101 according to the first reference example. FIG. 12 is an enlarged plan view of the first routing wiring 115, the gate finger routing wiring 116, and the second routing wiring 117 of the semiconductor device 101 shown in FIG.
As shown in FIG. 11, the first lead wiring 115 is formed to have a closed curved structure in a plan view so as to straddle the gate pad 105 and the pad peripheral portion 107 in the lower region of the gate pad 105. More specifically, the first lead wiring 115 is formed in a square ring shape so as to cross the first removal area 110 from the gate pad 105 to the inward area 107 a of the pad peripheral portion 107. The first lead wiring 115 is made of a material having a resistance value higher than that of the gate metal 103, and is preferably made of, for example, an electrode material such as polysilicon.

  As shown in FIG. 12, the first lead wiring 115 is electrically connected to the gate pad 105 through the contact 118 for gate pad and to the pad peripheral portion 107 through the contact 119 for the first pad peripheral portion. It is done. The gate pad contact 118 is formed in the gate pad 105 in a square ring shape in plan view surrounding the gate pad 105. On the other hand, the first pad peripheral portion contact 119 is formed in a quadrangular ring in plan view surrounding the first removal region 110 in the inward region 107 a of the pad peripheral portion 107. As described above, the gate pad 105 is electrically connected to the pad peripheral portion 107 and the gate finger 106 through the first lead wiring 115.

  The gate finger lead wiring 116 is formed in the lower region of the gate finger 106. The gate finger lead wiring 116 is formed narrower than the gate finger 106 and is completely covered by the gate finger 106. The gate finger lead wiring 116 is formed of the same electrode material as the first lead wiring 115. The gate finger lead wiring line 116 is electrically connected to the gate finger 106 through the gate finger contact 120 as shown in FIG.

  The second lead wiring 117 is formed at a predetermined distance from the first lead wiring 115 so as to selectively surround the periphery of the first lead wiring 115. The second lead wiring 117 is formed to straddle the pad peripheral portion 107 and the active region 102. More specifically, the second lead wiring 117 is formed so as to cross the second removal region 111, the outer region 107 b of the pad periphery 107, and the third removal region 112 from the inward region 107 a of the pad periphery 107. It is done. The second lead wiring 117 is integrally connected to the gate finger lead wiring 116 on the side of the region where the gate pad 105 is formed. The second lead wiring 117 is formed of the same electrode material as the first lead wiring 115.

  As shown in FIG. 12, the second lead-out wiring 117 is connected to the inward region 107a of the pad peripheral portion 107 via the second pad peripheral portion contact 121, and via the third pad peripheral portion contact 122. It is electrically connected to the outer side area | region 107b of the part 107, respectively. The second pad peripheral portion contact 121 is formed in a line shape selectively surrounding the first pad peripheral portion contact 119 in the inward region 107 a of the pad peripheral portion 107. On the other hand, the third pad peripheral portion contact 122 is formed in a line shape surrounding the second removal region 111 in the outer region 107b of the pad peripheral portion 107, and in the side of the region where the gate pad 105 is formed. , And the gate finger contacts 120 are integrally connected. As described above, the pad peripheral portion 107 is electrically connected to the gate finger 106 also via the second lead wiring 117.

Next, the configuration of a partial cross section of the semiconductor device 101 will be described with reference to FIG. 13A. 13A is a cross-sectional view as seen from the section line XIIIA-XIIIA shown in FIG.
As shown in FIG. 13A, the semiconductor device 101 includes a semiconductor substrate 125 as an example of a semiconductor layer. The semiconductor substrate 125 is, for example, an n ⁻ -type silicon substrate, and has a structure in which a p ⁺ -type collector region 126 and an n ⁻ -type drain region 127 are stacked in order from the back surface side. The p ⁺ -type collector region 126 is exposed on the entire back surface of the semiconductor substrate 125, and the n ⁻ -type drain region 127 is exposed on the surface of the semiconductor substrate 125. The dopant concentration of the p ⁺ -type collector region 126 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . As the p-type dopant, for example, B (boron), Al (aluminum) or the like can be used (hereinafter the same). On the other hand, the dopant concentration of the n ⁻ -type drain region 127 is, for example, 5 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁵ cm ⁻³ . In addition, as the n-type dopant, for example, N (nitrogen), P (phosphorus), As (arsenic) or the like can be used (hereinafter the same).

In the active region 102 of the semiconductor substrate 125, a plurality of gate trenches 137 are formed in stripes. A region of a fixed width is provided between the plurality of gate trenches 137, and one unit cell 136 of the IGBT is formed in this region.
The gate trench 137 is formed to dig down the surface of the semiconductor substrate 125. More specifically, the gate trench 137 is formed to have a constant width and is flush with the side surface of the semiconductor substrate 125 substantially perpendicular to the surface of the semiconductor substrate 125. And a bottom portion formed.

Unit cell 136 is formed along the stripe direction of gate trench 137 and is formed of p-type base region 140 and p ⁺ -type base contact region 141 and n ⁺ formed in the inner region of p-type base region 140. And an emitter region 142.
The p-type base region 140 is shared by one gate trench 137 and the other gate trench 137 adjacent to each other. The bottom of the p-type base region 140 is located closer to the surface of the semiconductor substrate 125 than the bottom of the gate trench 137. The dopant concentration of the p-type base region 140 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

The n ⁺ -type emitter region 142 is formed on the surface of the semiconductor substrate 125. One n ⁺ -type emitter region 142 is provided on both sides of the side surface of the gate trench 137, and each of the n ⁺ -type emitter regions 142 is exposed on the side surface of the gate trench 137. The dopant concentration of the n ⁺ -type emitter region 142 is 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . On the other hand, the p ⁺ -type base contact regions 141 are formed to be sandwiched between the n ⁺ -type emitter regions 142. The dopant concentration of the p ⁺ -type base contact region 141 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

An insulating film 134 is formed on the surface of the semiconductor substrate 125 and the inner surface (side and bottom) of the gate trench 137. The insulating film 134 is made of, for example, an insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ) or the like. Then, the gate electrode 138 is embedded in the gate trench 137 via the insulating film 134.

  The gate electrode 138 is buried in the gate trench 137 so that the surface of the gate electrode 138 exposed from the gate trench 137 is flush with the surface of the semiconductor substrate 125. The electrode material of the gate electrode 138 is preferably made of, for example, the same electrode material as the first and second lead wirings 115 and 117 described above. In this case, since the first and second lead wirings 115 and 117 can be formed in the same process as the gate electrode 138, the manufacturing process can be simplified.

On the surface of the semiconductor substrate 125, the aforementioned first and second lead wirings 115 and 117 and a gate finger lead wiring 116 (see FIG. 11) are formed via the insulating film 134. The second lead-out line 117 includes a lead-out portion 117 a drawn to the active region 102 along the direction crossing the stripe.
The gate electrodes 138 are electrically connected to gate finger lead wirings 116 formed across the gate trenches 137 at both longitudinal ends of the gate trenches 137. Thus, the gate electrode 138 is electrically connected to the gate finger 106 through the gate finger lead wire 116. Also, as shown in FIG. 13A, the gate electrode 138 is electrically connected to the lead-out portion 117a. Thus, the gate electrode 138 is electrically connected to the pad peripheral portion 107 via the lead-out portion 117a. The second lead wiring 117 may have a lead portion 117a (see FIGS. 11 and 12) drawn to the active region 102 along the stripe direction, thereby electrically connecting to the pad peripheral portion 107. It may be done.

An interlayer insulating film 145 is formed on the surface of the semiconductor substrate 125. In interlayer insulating film 145 in active region 102, an emitter contact hole 147 is formed to selectively expose p ⁺ -type base contact region 141 and a part of n ⁺ -type emitter region 142. The interlayer insulating film 145 in the termination region 113 includes the contact 118 for the gate pad, the contact 119 for the first pad peripheral portion, the contact 120 for the gate finger (see FIG. 12), and the contact 121 for the second pad peripheral portion. And third pad peripheral contacts 122 are formed. The interlayer insulating film 145 is made of, for example, an insulating material such as tetraethyl orthosilicate (TEOS), borophosphorous silicate glass (BPSG), silicon oxide (SiO ₂ ) or the like.

A gate metal 103 and an emitter electrode 104 are formed on the interlayer insulating film 145. Emitter electrode 104 is electrically connected to p ⁺ -type base contact region 141 and a part of n ⁺ -type emitter region 142 via emitter contact hole 147.
On the other hand, as described above, the gate metal 103 is electrically connected to the first and second lead wirings 115 and 117 via the contacts 118, 119, 121 and 122. Thus, the gate metal 103 is electrically connected to the gate electrode 138 via the first and second lead wirings 115 and 117 and the lead-out portion 117 a of the second lead wiring 117, and the surface current is transferred from the gate pad 105 to the gate electrode. A current path leading to 138 is formed.

A surface protection film 146 is formed on the interlayer insulating film 145 so as to selectively cover the region between the gate pad 105 and the emitter electrode 104. The surface protective film 146 is made of, for example, a resin.
The semiconductor device 101 is represented by an electric circuit diagram shown in FIG. 13B. FIG. 13B is an electric circuit diagram for describing an electrical structure of semiconductor device 101 shown in FIG.

  As shown in FIG. 13B, the semiconductor device 101 includes a current limiting portion 139 interposed between the gate pad 105 and the gate electrode 138. The current limiting unit 139 includes a resistance component of the first lead wiring 115 connected in series to the gate pad 105, a resistance component of the lead wiring for the gate finger 116, and a resistance component of the second lead wiring 117. When a voltage is applied to the gate pad 105, a current flows in the gate electrode 138 via the current limiting portion 139.

  As described above, according to the configuration of the semiconductor device 101, as shown in FIGS. 12, 13A and 13B, when current flows from the gate pad 105 to the pad peripheral portion 107 and the gate finger 106, the first and second Since the current flows through the lead wirings 115 and 117 (current limiting portion 139), the inflow of current to the pad peripheral portion 107 and the gate finger 106 due to surface current can be limited at a position close to the gate pad 105. Thereby, rush current is locally applied locally to the gate electrode 138 of the MIS gate structure 132 at a position close to the gate pad 105 (in particular, the peripheral portion of the gate pad 105 electrically connected via the pad peripheral portion 107). (Di / dt) flows, and the local turning on of the MIS gate structure 132 can be suppressed. As a result, regardless of the distance from the gate pad 105, the variation in applied current among the plurality of MIS gate structures 132 can be suppressed.

  Further, even if rush current flows from gate pad 105 to inward region 107a of pad peripheral portion 107, pad peripheral portion 107 passes through second lead-out wiring 117 or bypasses third removal region 112 thereafter. Flow to the outer region 107b of the That is, the flow of current into the gate electrode 138 at the periphery of the gate pad 105 can be double limited. Therefore, the rush current flowing into the gate electrode 138 of the MIS gate structure 132 disposed in the vicinity of the gate pad 105 can be effectively limited. On the other hand, since the gate finger 106 is in contact with the gate electrode 138 of the MIS gate structure 132 at a position relatively far from the gate pad 105, this can limit the rush current.

In addition, when the switching characteristics of the semiconductor device 101 were examined, the graphs shown in FIGS. 14A to 14C were obtained.
14A to 14C are graphs showing switching characteristics of the semiconductor device 101 shown in FIG.
14A shows the relationship between the gate-emitter voltage V _GE (V) of the semiconductor device 101 and the time (nsec), and FIG. 14B shows the collector-emitter voltage V _CE (V) of the semiconductor device 101. FIG. 14C shows the relationship between time (nsec) and the collector current I _c (A) of the semiconductor device 101 and the relationship between time (nsec). 14A to 14C, the characteristics of the semiconductor device 101 are indicated by solid lines, and the switching characteristics of the semiconductor device 148 according to the reference example are indicated by broken lines. The semiconductor device 148 according to the reference example is a semiconductor device in which the first and second lead wirings 115 and 117 are not formed.

Referring to FIG. 14A, in the semiconductor device 148 according to the reference example, it can be confirmed that noise is generated in the voltage V _GE between the gate and the emitter at the turn-on time t _on . On the other hand, in the semiconductor device 101, noise like the semiconductor device 148 according to the reference example can not be confirmed. Note that the turn-on time t _on, IGBT gate at turn - is defined as the time required until the voltage V _CE between the emitter is lowered to 10% of the maximum value - from the rising of the voltage V _GE between the emitter collector.

Further, referring to FIG. 14B, in the semiconductor device 148 according to the reference example, the rise time t _r, the collector - noise voltage V _CE between the emitter can be confirmed that has occurred. On the other hand, in the semiconductor device 101, noise like the semiconductor device 148 according to the reference example can not be confirmed. Note that the rise time t _r, from the time when the collector current I _C during turn of the IGBT is increased to 10% of the maximum value collector - the time required until the voltage V _CE between the emitter is lowered to 10% of the maximum value It is defined.

14C, in the semiconductor device 148 according to the reference example, it can be confirmed that noise is generated in the collector current I _C at the reverse recovery time t _rr . On the other hand, in the semiconductor device 101, noise like the semiconductor device 148 according to the reference example can not be confirmed. The reverse recovery time _trr is defined by the time required for the reverse recovery current of the built-in diode to disappear. Further, in the semiconductor device 101, it can be confirmed that the value of the effective current is hardly changed while the value of the peak current is lower than the value of the peak current of the semiconductor device 148 according to the reference example in the reverse recovery time _trr . . This is because a current other than the current detected as an effective current, that is, a surface current (rush current) flowing to the gate metal 103 flows to the gate electrode 138 through the first and second lead wirings 115 and 117. .

  In FIGS. 14A to 14C, the generation of noise in the semiconductor device 148 according to the reference example is described as follows. That is, in the gate pad 105 formed around the MIS gate structure 132, and the pad peripheral portion 107 and the gate finger 106, an LC resonant circuit is usually formed by parasitic inductance and parasitic capacitance. Therefore, when the surface current flows, the switching of the MIS gate structure 132 is triggered to generate resonance noise. In the semiconductor device 148 according to the reference example, since the first and second lead wirings 115 and 117 are not formed, such surface current can not be limited. Therefore, in the semiconductor device 148 according to the reference example, as shown in the graphs of FIGS. 14A to 14C, the waveform of resonance noise is detected.

  On the other hand, according to the configuration of the semiconductor device 101, since the flow of current to the pad peripheral portion 107 and the gate finger 106 due to surface current can be limited, local turning on of the MIS gate structure 132 can be suppressed. Therefore, it is possible to suppress the occurrence of resonance noise caused by the switching of the MIS gate structure 132 as a trigger. Thus, switching loss caused by resonance noise can be reduced during switching on operation.

As described above, it is possible to provide the semiconductor device 101 capable of effectively limiting the inrush current and reducing the occurrence of the switching loss and the resonance noise.
FIG. 15 is a schematic plan view of a semiconductor device 151 according to the second reference example. FIG. 16 is a schematic plan view for explaining the first and second lead wirings 160 and 161 of the semiconductor device 151 according to the second reference example. The semiconductor device 151 according to the second reference example is different from the semiconductor device 101 according to the first reference example in that a gate metal 152 is formed instead of the gate metal 103. The other configuration is the same as that of the semiconductor device 101 according to the first reference example. In FIG. 15 and FIG. 16, the same referential mark is attached | subjected to the part corresponding to each part shown by above-mentioned FIGS. 10-13A, and description is abbreviate | omitted. The semiconductor device 151 is formed in the shape of a square chip in plan view as in the first reference example described above, and a plurality of gate trenches 137 are formed in the shape of stripes in the active region 102.

  As shown in FIG. 15, in the termination region 113 of the semiconductor device 151, a gate metal 152 as an example of a surface gate metal is formed so as to selectively surround the active region 102. The gate metal 152 further includes a gate pad 153 as an example of a pad portion, and a wiring portion 168 including a first gate finger 154, a second gate finger 155, and a pad peripheral portion 156.

The gate pad 153 is formed at one corner of the semiconductor device 151 in the second reference example. The gate pad 153 is externally supplied with power by the bonding wire 108 being connected.
The first gate finger 154, the second gate finger 155, and the pad peripheral portion 156 are formed in a line so as to surround the active region 102 of the semiconductor device 151.

  The first gate finger 154 is formed integrally with the gate pad 153. More specifically, the first gate finger 154 extends from the gate pad 153 in the stripe direction of the gate trench 137 (that is, the direction along the side 151a of the semiconductor device 151) and further intersects the side 151a at a right angle. It is formed extending in the direction orthogonal to the direction (that is, the direction along the other side 151b). The first gate finger 154 is formed to cross one end in the longitudinal direction of the gate trench 137 in a region along the side 151 b of the semiconductor device 151.

  The pad peripheral portion 156 is formed to selectively surround the inner periphery of the gate pad 153 with the removal region 157 interposed therebetween. The removal region 157 is formed in a line along the periphery of the gate pad 153. That is, the pad peripheral portion 156 is formed separately from both the gate pad 153 and the first gate finger 154 by the removal region 157.

  The second gate finger 155 is formed along the side 151 c opposite to the other side 151 b of the semiconductor device 151. More specifically, it is formed so as to cross the other end in the longitudinal direction of gate trench 137 from gate pad 153, and is formed integrally integrally with one end portion 156a of pad peripheral portion 156. That is, the second gate finger 155 is also formed separately from any of the gate pad 153 and the first gate finger 154.

In the region under the gate metal 152, as shown in FIG. 16, a first lead wiring 160 and a second lead wiring 161 are formed.
The first lead wiring 160 is formed to straddle the first gate finger 154 and the second gate finger 155. More specifically, the first lead wiring 160 is formed along the area where the first gate finger 154, the gate pad 153, and the second gate finger 155 are formed, across the area where the removal area 157 is formed. It is done. The first lead wiring 160 is formed wider than the first gate finger 154 and the second gate finger 155. The first lead wiring 160 is made of a material having a resistance value higher than that of the gate metal 152, and is preferably made of, for example, an electrode material such as polysilicon.

  The second routing wiring 161 is formed along the region where the pad peripheral portion 156 is formed. The second lead wiring 161 is formed wider than the pad peripheral portion 156. The second lead-out interconnection 161 is formed integrally with the first lead-out interconnection 160 on the side where the second gate finger 155 is formed. An end 161 a of the second lead-out interconnection 161 on the gate pad 153 side is formed to cross the removal region 157 and reach the gate pad 153.

As shown in FIGS. 15 and 16, the gate pad 153 and the first gate finger 154 are connected to the first lead wiring 160 through the first contact 162 formed along the gate pad 153 and the first gate finger 154. It is electrically connected.
On the other hand, the pad peripheral portion 156 and the second gate finger 155 are electrically connected to the first lead wiring 160 through the second contact 163 formed along the second gate finger 155. That is, the gate pad 153 is electrically connected to the pad peripheral portion 156 and the second gate finger 155 via the first lead wiring 160.

  The first and second lead wirings 160 and 161 are electrically connected to the gate electrode 138 embedded in the gate trench 137, as in the first reference example described above. Thus, the gate metal 152 is electrically connected to the gate electrode 138 via the first and second lead wirings 160 and 161, and a current path for guiding surface current from the gate pad 153 to the gate electrode 138 is formed. There is.

  As described above, in the semiconductor device 151, the first gate finger 154 is not in contact with the gate electrode 138 in the portion extending along the MIS gate structure 132 from the gate pad 153 at the corner to the adjacent corner, and the gate pad The side opposite to 153 is in contact with the gate electrode 138. That is, since the contact is made with the gate electrode 138 of the MIS gate structure 132 at a position relatively far from the gate pad 153, the rush current can be thereby limited. On the other hand, the second gate finger 155 and the pad peripheral portion 156 are in contact with the gate electrode 138 of the MIS gate structure 132 at a position relatively close to the gate pad 153, but the second gate finger 155 It is arranged separately. In addition, since the second gate finger 155 and the pad peripheral portion 156 are electrically connected to the gate pad 153 via the first and second lead wirings 160 and 161, it is assumed that rush current flows in the gate pad 153. Also, the inrush current can be limited. Therefore, the same effects as the effects described in the first embodiment can be obtained.

As mentioned above, although the form concerning the embodiment of the present invention, and the 1st and 2nd reference examples was explained, the present invention can also be carried out with other form.
For example, in the second and third embodiments described above, although the example in which the emitter trenches 63 and 83 are formed in stripes in the longitudinal direction of the annular trench 10 has been described, the emitter trenches 63 and 83 have a plan view. Alternatively, it may be formed in a stripe shape in the short direction of the annular trench 10. Further, the emitter trenches 63 and 83 may be formed in a mesh shape in the inner region of the annular trench 10.

In each of the embodiments described above, although the gate contact trench 11 and the emitter contact trench 12 are formed in an arch shape in a plan view angle, other closed curves such as a circular arch shape and a triangular arch shape are described. It may be a structure.
Moreover, although the above-mentioned each embodiment demonstrated the example in which the bottom part of each trench 10, 11, 12, 63, 83 was formed so that roundness may be taken from the side, each trench 10, 11, 12, The bottom portions 63 and 83 may be formed parallel to the surface of the semiconductor substrate 15.

In each of the above-described embodiments, the example in which the IGBT is formed in the active region 4 has been described. However, in addition to the IGBT, a CMOS (Complementary MOS) may be formed. For example, the configuration shown in FIG. 17 may be employed as the configuration including the MOS structure.
FIG. 17 is a schematic cross-sectional view showing a modification of the semiconductor device 1 according to the first embodiment. In FIG. 17, the main components common to those of the semiconductor device 1 are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 17, in this modification, a semiconductor device 94 employing an n ⁺ -type drain region 95 instead of the p ⁺ -type collector region 16 is formed. That is, in the semiconductor device 94, a MOSFET is formed instead of the IGBT. In this case, the emitter electrode 6 (n ⁺ -type emitter region 31) of the IGBT corresponds to the source electrode 96 (n ⁺ -type source region 97) of the semiconductor device 94. Of course, in each of the semiconductor devices 61, 81, and 91 according to the second to fourth embodiments, an n ⁺ -type drain region 95 may be employed instead of the p ⁺ -type collector region 16 to form a MOSFET structure. .

  In each of the above-described embodiments, the example in which the IGBT is formed in the active region 4 has been described. However, in addition to the IGBT, various semiconductors such as BJT (Bipolar Junction Transistor), JFET (Junction Field Effect Transistor), capacitor, resistor, etc. Elements and circuit elements may be formed. Furthermore, by combination of these semiconductor elements and circuit elements, large scale integration (LSI), small scale integration (SSI), medium scale integration (MSI), very large scale integration (VLSI), ultra-very large scale (ULSI) Integrated circuit, etc. may be configured.

In each of the embodiments described above, the conductivity type of each semiconductor region such as the p-type floating region 9, the p ⁺ -type collector region 16, and the n ⁻ -type drain region 17 may be reversed. Therefore, in this case, the p-type floating region 9 is an n-type floating region, the p ⁺ -type collector region 16 is an n ⁺ -type collector region, and the n ⁻ -type drain region 17 is a p-type drain region. Of course, the conductivity types of the other semiconductor regions are also reversed.

The semiconductor devices 1, 61, 81, and 91 according to the first to fourth embodiments can be applied to an inverter circuit as shown in FIG.
FIG. 18 is a circuit diagram for describing an inverter circuit 201 to which the semiconductor devices 1, 61, 81, and 91 according to the first to fourth embodiments are applied.
The inverter circuit 201 is a three-phase inverter circuit connected to the three-phase motor 202 as a load. The inverter circuit 201 includes a DC power supply 203 and a switch unit 204.

DC power supply 203 is, for example, 700V. In the DC power supply 203, the high voltage side wiring 205 is connected to the high voltage side, and the low voltage side wiring 206 is connected to the low voltage side. The switch unit 204 includes three arms 207 to 209 corresponding to the U-phase 202U, the V-phase 202V, and the W-phase 202W of the three-phase motor 202, respectively.
The arms 207 to 209 are connected in parallel between the high voltage side wire 205 and the low voltage side wire 206. The arms 207 to 209 respectively include high-side high-side transistors 210H to 212H (semiconductor devices 1, 61, 81, 91) and low-pressure side low side transistors 210L to 212L (semiconductor devices 1, 61, 81, 91). Have. Regeneration diodes 213H to 215H and 213L to 215L are connected in parallel to the transistors 210H to 212H and 210L to 212L, respectively, in such a direction that a forward current flows from the low voltage side to the high voltage side.

  In the inverter circuit 201, by alternately switching on / off control of the high side transistors 210H to 212H and low side transistors 210L to 212L of the arms 207 to 209, that is, one transistor is switched on and the other is switched off. An alternating current can be supplied to the three-phase motor 202 by alternately switching the states. On the other hand, by turning off both of the transistors, power to the three-phase motor 202 can be stopped. Thus, the switching operation of the three-phase motor 202 is performed.

  Also, in the first reference example described above, an example is described in which one first removal region 110 is formed in an annular shape so as to surround the periphery of the gate pad 105 (see FIG. 10). Region 110 may be annularly formed to selectively surround the periphery of gate pad 105. For example, in FIG. 10, the first removal region 110 may not be formed on the side opposite to the protruding direction of the gate pad 105 with respect to the gate pad 105. In this case, both the pad peripheral portion 107 and the gate finger 106 are electrically connected to the gate pad 105 through the metal constituting the gate metal 103. Even in this case, since the first removal region 110 surrounding three sides of the gate pad 105 must be bypassed in order for the current supplied to the gate pad 105 to flow to the pad peripheral portion 107, rush current to the pad peripheral portion 107 Can be reduced.

Further, in the first reference example described above, an example has been described in which the second removal region 111 selectively surrounds a part of the periphery of the gate pad 105 (see FIG. 11), the second removal region 111 is It may be configured to surround the entire periphery of the gate pad 105.
In the first reference example described above, the first lead wiring 115 is formed in a closed curved ring shape in plan view in the area below the gate pad 105. However, the first lead wiring 115 is a gate pad. As long as 105 is electrically connected to the pad peripheral portion 107, it may not be formed in a ring shape. Therefore, the first lead wiring 115 may be formed in a line shape in the lower region of the gate pad 105.

Further, in the first reference example described above, an example is described in which the gate finger lead wiring 116 is formed narrower than the gate finger 106 (see FIG. 11), but the gate finger lead wiring 116 is a gate finger. It may be configured to be wider than 106.
Further, in the first reference example described above, although the example in which the second lead wiring 117 is formed so as to selectively surround the periphery of the first lead wiring 115 has been described (see FIG. 11), the second lead wiring is described. The portion 117 may be formed to surround the entire periphery of the first lead wiring 115. In this case, the second pad peripheral contact 121 (see FIG. 12) may be formed in a square ring in plan view so as to surround the entire periphery of the first pad peripheral contact 119 all around. .

  Also, in the second reference example described above, an example is described in which the removal region 157 is formed in a line along the periphery of the gate pad 153 (see FIG. 15). It may be formed over the entire circumference. In this case, the first gate finger 154 is also formed separately from the gate pad 153. Even in such a configuration, since the first lead wiring 160 is formed to bridge the gate pad 153 and the first gate finger 154, the gate pad 153 and the first gate finger 154 are electrically connected. be able to. Therefore, the surface current flowing on the surface of the gate pad 153 can be limited also between the gate pad 153 and the first gate finger 154.

  Also, in the first and second reference examples described above, although the example in which the gate trench 137 in a stripe shape in plan view is formed in the active region 102 has been described, the gate trench 137 is formed in a mesh shape in plan view. May be In this case, the unit cell 136 of the IGBT is formed in a region surrounded by the mesh-like gate trench 137.

Further, in the first and second reference examples described above, the example in which the IGBT is formed in the active region 102 has been described, but the example shown in FIG. 19 may be adopted.
FIG. 19 is a schematic cross-sectional view showing a modification of the semiconductor devices 101 and 151 according to the first and second reference examples. In FIG. 19, the main components common to those of the semiconductor devices 101 and 151 are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 19, in this modification, a semiconductor device 191 is formed in which an n ⁺ -type drain region 192 is employed instead of the p ⁺ -type collector region 126. That is, in the semiconductor device 191, a MOSFET is formed instead of the IGBT. In this case, the emitter electrode 104 (n ⁺ -type emitter region 142) of the IGBT corresponds to the source electrode 193 (n ⁺ -type source region 194) of the MOSFET.

Even with such a configuration, the gate electrode 138 of the MIS gate structure 132 in the MOSFET can be prevented from being turned on locally, so that the same effect as that of the IGBT can be obtained. In addition, SiC (silicon carbide) may be adopted for the semiconductor substrate 125 to constitute a SiC-IGBT, or a SiC-MOSFET may be constituted.
In the first and second reference examples, the trench gate type IGBT is formed in the active region 102, but the gate electrode is formed on the surface of the semiconductor substrate 125 via the insulating film 134. A planar gate type IGBT may be employed. Of course, a planar gate MOSFET may be employed instead of the planar gate IGBT.

  In the first and second reference examples described above, the bottom of the gate trench 137 is formed parallel to the surface of the semiconductor substrate 125. However, the bottom of the gate trench 137 is rounded from the side thereof. You may form so that it may take. In the first and second reference examples described above, the side surface of the gate trench 137 is formed at right angles to the surface of the semiconductor substrate 125. However, the side surface of the gate trench 137 is an opening thereof. , And the width may be gradually narrowed toward the bottom.

  Also, in the first and second reference examples described above, the example in which the IGBT is formed in the active region 102 has been described, but in addition to the IGBT, CMOS (Complementary MOS), BJT (Bipolar Junction Transistor), JFET (Junction Field Effect) Various semiconductor elements and circuit elements such as a transistor, a capacitor, and a resistor may be formed. Furthermore, by combination of these semiconductor elements and circuit elements, large scale integration (LSI), small scale integration (SSI), medium scale integration (MSI), very large scale integration (VLSI), ultra-very large scale (ULSI) Integrated circuit, etc. may be configured.

In the first and second reference examples described above, the conductivity types of the semiconductor regions of the p ⁺ -type collector region 126, the n ⁻ -type drain region 127, the p-type base region 140, and the n ⁺ -type emitter region 142 are reversed. It may be a configuration.
The semiconductor devices 101 and 151 according to the first and second reference examples can be applied to an inverter circuit 221 as shown in FIG.

FIG. 20 is a circuit diagram for describing an inverter circuit 221 to which the semiconductor devices 101 and 151 according to the first and second reference examples are applied.
The inverter circuit 221 differs from the inverter circuit 201 shown in FIG. 18 in that high side transistors 222H to 224H (semiconductor devices 101 and 151) and low side transistors 222L instead of the high side transistors 210H to 212H and low side transistors 210L to 212L. .About.224 L (semiconductor devices 101 and 151) are connected. The other configuration is the same as that of the inverter circuit 201 shown in FIG.

  As shown in FIG. 20, each of the high side transistors 222H to 224H and the low side transistors 222L to 224L has a current limiting portion 139 interposed between the gate pad 105 and the gate electrode 138 (FIG. 13B). See also)). The current limiting unit 139 can reduce switching loss caused by resonance noise during switching on operation.

In addition, various design changes can be made within the scope of matters described in the claims. The features extracted from the description of this specification and the drawings are shown below.
[A1] A semiconductor layer having an active region in which a plurality of MIS gate structures are arranged, a surface gate metal disposed on the semiconductor layer, and a pad portion for receiving an external power supply, and the active A wiring portion extending along the periphery of the region and electrically connected to the gates of the plurality of MIS gate structures is provided, and a removal region is formed to at least partially separate the pad portion and the wiring portion. A semiconductor device comprising: a front surface gate metal; and a lead-out wiring which is drawn from the pad portion to the adjacent wiring portion across the removal region and which is made of a material having a resistance value higher than that of the front surface gate metal.

  In a semiconductor device provided with a gate pad, there is known a problem that an inrush current (di / dt) is generated when a voltage is applied to the gate pad. This inrush current is likely to flow on the gate pad and the surface of the gate metal interconnection connected to the gate pad. Therefore, rush current flows into the gate structure near the gate pad as a surface current, and as a result, the gate structure may be turned on locally. The generation of such surface current not only causes variations in applied current among a plurality of gate structures, but is one of the causes of switching loss at the time of switching on operation.

In addition, since a gate pad and a gate metal wiring formed around the gate structure usually constitute an LC resonant circuit with parasitic inductance and parasitic capacitance, switching of the gate structure is a trigger when surface current flows. Resonance noise is generated. As a result, the switching loss at the time of switching on increases.
Therefore, a semiconductor device capable of effectively limiting inrush current and reducing the occurrence of switching loss and resonance noise is desired.

  According to the semiconductor device described in A1, when the current flows from the pad portion to the wiring portion, the current flows to the wiring portion due to the surface current can be limited because it passes through the lead wiring. As a result, an inrush current (di / dt) flows locally to the gate of the MIS gate structure near the pad portion, and it is possible to suppress the local turning on of the MIS gate structure. As a result, it is possible to suppress the variation in applied current among the plurality of MIS gate structures regardless of the distance from the pad portion. In addition, since it is possible to suppress the local turning on of the MIS gate structure, it is possible to suppress the occurrence of resonance noise caused by the switching of the MIS gate structure. Thus, switching loss caused by resonance noise can be reduced during switching on operation.

[A2] The semiconductor device according to A1, wherein the removal region is formed to surround the pad portion.
According to this semiconductor device, since the surface current can be limited at a position close to the pad portion, the local current flow into the MIS gate structure in the vicinity of the pad portion can be effectively suppressed.
[A3] The semiconductor device according to A2, wherein the wiring portion includes a linear gate finger extending to surround the active region.

According to this semiconductor device, since the current whose surface current is limited flows through the gate finger, it is possible to suppress the variation of the current along the longitudinal direction of the gate finger.
[A4] The semiconductor device according to A3, wherein the wiring portion further encloses the removal area surrounding the pad portion, and includes a pad peripheral portion integrally formed with the gate finger.
According to this semiconductor device, it is possible to suppress the variation in the current flowing into the gate of the MIS gate structure without the gate finger.

  [A5] The plurality of MIS gate structures are formed in a stripe shape in a plan view seen from the normal direction of the surface of the semiconductor layer, and the gate finger crosses the stripe MIS gate structure. The semiconductor device according to A3 or A4, disposed and in contact with the gate of the MIS gate structure at both longitudinal ends of each of the MIS gate structures.

[A6] The pad portion is formed in the middle of a region along the stripe direction of the MIS gate structure, and the gate finger extends from the pad portion to both sides along the stripe direction, and further the stripe shape The semiconductor device according to A5, wherein the semiconductor device is formed to cross the MIS gate structure.
According to this semiconductor device, since the gate finger is in contact with the gate of the MIS gate structure at a position relatively far from the pad portion, the rush current can be thereby limited.

  [A7] The semiconductor layer is formed in a square shape in plan view, the pad portion is formed at a corner of the square semiconductor layer, and the gate finger is integrally connected with the pad portion. The first gate finger is formed and arranged to extend along the stripe direction of the MIS gate structure, and is separated via the pad portion and the removal region so as to cross the MIS gate structure from the pad portion The semiconductor device according to A5, including a second gate finger disposed.

  According to this semiconductor device, since the first gate finger is in contact with the gate of the MIS gate structure at a position relatively far from the pad portion, the rush current can be thereby limited. On the other hand, the second gate finger is in contact with the gate of the MIS gate structure at a position relatively close to the pad portion, but the second gate finger is disposed separately from the pad portion. Moreover, since the second gate finger is connected to the pad portion via the lead wiring, even if the rush current flows in the pad portion, the rush current can be limited.

[A8] The semiconductor device according to any one of A2 to A7, wherein the removal region selectively surrounds a part of the periphery of the pad portion.
[A9] The semiconductor device according to any one of A2 to A7, wherein the removal region surrounds the entire periphery of the pad portion.
According to this semiconductor device, the surface current can be limited over the entire circumference of the pad portion. Thus, local current flow into the MIS gate structure in the vicinity of the pad portion can be effectively suppressed.

[A10] The semiconductor device according to any one of A1 to A9, wherein the lead-out wiring connects the pad portion and the wiring portion via a lower portion of the removal region.
According to this semiconductor device, the lead wiring can be formed in the same process as the gate of the MIS gate structure. Therefore, the manufacturing process can be simplified. Therefore, in this case, the lead wiring is preferably formed of the same material as the gate of the MIS gate structure.

[A11] The semiconductor device according to A10, wherein the wiring portion is made of a metal material containing Al as a main component, and the lead-out wiring and the gate of the MIS gate structure are made of polysilicon.
[A12] The semiconductor device according to any one of A1 to A11, wherein an IGBT partially including the MIS gate structure is formed in the semiconductor layer.

[A13] The semiconductor device according to A12, wherein the IGBT includes a trench gate type IGBT.
[B1] A semiconductor layer in which a trench is formed, an FET structure formed on the side of the trench and having an emitter region and a drain region facing each other across the base region in the depth direction of the trench, and the trench A gate junction which is provided in the same trench as a floating region formed on the opposite side of the FET structure and electrically isolated from each other in the trench and an emitter junction which is electrically connected to the emitter region And the gate junction and the emitter junction are each connected to the FET via an insulating film.
A semiconductor device facing a structure and the floating region.

  According to this configuration, the capacitive component due to the contact between the trench and the floating region can be made the capacitive component (capacitance between the collector and the emitter junction) in the junction region between the emitter junction and the floating region. Thus, the gate junction is not affected by the junction with the floating region. Therefore, switching loss can be reduced as compared with the conventional semiconductor device in which the floating region and the trench gate are joined. On the other hand, if the drain region of the FET structure opposed to the gate junction is grounded together with the collector region, the capacitance change between the gate junction and the drain region can be stably maintained during the switching operation. As a result, the occurrence of switching noise can be suppressed.

On the other hand, the inventors of the present application form a semiconductor device including an IGBT having a structure in which a plurality of trench emitters are formed between adjacent trench gates and the trench emitter and the floating region are electrically connected (hereinafter referred to as “reference example Semiconductor device)) was examined. In this structure, since there is no junction region between the trench gate and the floating region, the above-mentioned problems of switching loss and switching noise can be improved. However, in the case of the semiconductor device according to the reference example, an FET structure is formed in each region between the trench gate and the trench emitter. Thus, the trench gate and the trench emitter face each other through the FET structure. Therefore, the carrier accumulation effect by sandwiching the FET structure with the trench gate is reduced, and the carrier density in the semiconductor layer is also reduced accordingly. As a result, the drift resistance in the drain region is increased and the on voltage is likely to be increased.
On the other hand, according to the configuration of the present invention, since the gate junctions can be made to face each other through the insulating film and the FET structure, the carrier accumulation effect by the gate junction can be enhanced. As a result, the carrier density in the semiconductor layer is increased, so that the drift resistance in the drain region can be reduced. Thus, the on voltage of the semiconductor device can be reduced.

Furthermore, according to the configuration of the present invention, unlike the semiconductor device according to the reference example, since the gate junction and the emitter junction are formed in the same trench, it is necessary to form the trench gate and the trench emitter. Absent. Thus, the number of FET structures to be formed can be reduced. That is, the number of contact openings for connecting the FET structure can be reduced. As a result, the contact opening ratio can be reduced, so that it is possible to effectively suppress the reduction in the short circuit withstand voltage of the semiconductor device.
[B2] The gate junction and the emitter junction are respectively formed in proximity to one side and the other side of the trench in a cross section perpendicular to the longitudinal direction of the trench, and the semiconductor device is The semiconductor device according to B1, comprising a central insulating film interposed between the gate junction and the emitter junction.

[B3] The semiconductor device according to B2, wherein the gate junction portion and the emitter junction portion are each formed in a film shape along the side surface of the trench which is relatively close in relation to the other junction portion.
[B4] The semiconductor device is respectively formed in the semiconductor layer, and a contact trench for the gate connected to the side surface of the trench adjacent to the gate junction and an emitter for the semiconductor connected to the side surface of the trench adjacent to the emitter junction. The semiconductor device according to B2 or B3, including a contact trench, wherein the gate contact trench and the emitter contact trench are formed with a smaller width than the trench.
According to this configuration, in order to obtain a configuration in which each junction is close to one side and the other side of the trench, when the electrode material of the gate junction and the emitter junction is deposited along the inner surface of the trench, In the narrower gate contact trench and the emitter contact trench, the electrode materials deposited on one side and the other side can be integrated inside the trench. As a result, each of the gate contact trench and the emitter contact trench can be completely backfilled with the electrode material. As a result, the area of the electrode material when viewed from above in the depth direction of each contact trench is at least equal to the diameter (width) of each contact trench, so that contact can be made easily.
[B5] The trench is annularly formed to define an inward region in which the floating region is disposed and an outward region in which the FET structure is disposed, and the gate contact trench is formed from the annular trench The semiconductor device according to B4, wherein the emitter trench is formed by being drawn out from the annular trench to the inward region.

  [B6] A plurality of the FET structures are formed in a stripe shape in a plan view seen from the normal direction of the surface of the semiconductor layer, and the annular trench is disposed in a region between the adjacent FET structures And the gate contact trench and the emitter contact trench of the annular trench disposed in the region are outward and opposite to each other from one end of the annular trench in the longitudinal direction of the stripe, respectively. The semiconductor device is formed so as to cross the gate contact trench around the active region in which the stripe-shaped FET structure is formed, and is electrically connected to the gate junction. Gate finger and the gate finger spaced above the active area Wherein is formed so as to cover the emitter contact trench, it said and an emitter junction and electrically connected to the emitter electrode, the semiconductor device according to B5 in.

[B7] The semiconductor device according to any one of B1 to B6, wherein the floating region is formed to wrap around below the trench.
According to this configuration, the floating region is formed to go under the trench, so that the collector-emitter voltage applied to the trench can be relaxed at the switching off operation. Therefore, the device breakdown can be suppressed against a steep voltage change (dv / dt). Thereby, the short circuit tolerance of the semiconductor device can be maintained. Moreover, while the short circuit tolerance can be improved by the floating region deeper than the base region, since the base region may be shallow, the channel length is shortened by appropriately designing the depth of the base region to suppress the rise of the on voltage. You can also
[B8] The semiconductor device is provided with a second trench formed to reach at least the floating region in the semiconductor layer, and the second trench via an insulating film, and electrically connected to the emitter region. The semiconductor device according to any one of B1 to B6, further including a second emitter junction.

[B9] The semiconductor device according to B8, wherein the floating region is formed at the same depth as the base region, and the second trench is formed to penetrate the floating region.
[B10] The second trench is formed to have the same width as the trench, and the second emitter junction includes a pair of junctions isolated from each other in the second trench, B8 or B9 The semiconductor device of description.
According to this configuration, the second trench can be formed in the same step as the step of forming the trench only by changing the layout of the mask. Moreover, since the second trench is formed to have the same width as the trench, the second emitter junction can be formed in the same step as the step of forming the gate junction and the emitter junction. As a result, the second trench and the second emitter junction can be formed without complication of the manufacturing process.
[B11] The semiconductor device according to B8 or B9, wherein the second trench is formed to have a width smaller than that of the trench, and the second emitter junction is integrally embedded in the second trench. .

  Also with such a configuration, the second emitter junction can be formed in the same step as the step of forming the gate junction and the emitter junction.

1 semiconductor device 2 gate fingers 4 active region 6 emitter electrode 8 FET structure 9 p-type floating region 10 annular trench 11 gate contact trench 12 emitter contact trench 15 semiconductor substrate 17 n ^- -type drain region 18 insulating film 19 gate junction 20 Emitter junction 21 Central insulating film 28 p-type base region 31 n ⁺ -type emitter region 41 Semiconductor device according to the reference example 61 Semiconductor device 62 p-type floating region 63 Emitter trench 64 Second emitter junction 81 Semiconductor device 83 Emitter trench 84 second emitter junction portion 91 semiconductor device 101 semiconductor device 102 active region 103 gate metal 105 gate pad 106 gate finger 107 pad peripheral portion 110 first removal region 11 second removal region 115 first lead wiring 116 lead finger for lead finger 117 second lead wiring 125 semiconductor substrate 132 MIS gate structure 148 semiconductor device according to a reference example 151 semiconductor device 152 gate metal 153 gate pad 154 first gate finger 155 Second gate finger 156 Pad peripheral portion 157 Removal region 160 First lead wiring 161 Second lead wiring 167 Wiring portion 168 Wiring portion W _{1 to} W ₄ width

Claims (20)

A semiconductor layer of a first conductivity type having a front surface and a back surface;
A buffer region of a first conductivity type formed in a surface layer portion of the back surface of the semiconductor layer;
A collector region of a second conductivity type formed in the surface layer portion on the back surface side of the semiconductor layer in the buffer region ;
An outer peripheral surface, an inner peripheral surface, and a bottom surface connecting the outer peripheral surface and the inner peripheral surface, and the outer peripheral surfaces are formed on the surface of the semiconductor layer at an interval in such a manner as to face each other ; A plurality of annular trenches each having a width of 1.5 μm to 3.0 μm ,
An insulating film formed on the inner surface of each of the trenches;
A gate junction buried on the outer peripheral surface side of each of the trenches with the insulating film interposed therebetween;
An emitter junction which is buried on the inner circumferential surface side of each of the trenches at a distance from the gate junction and sandwiching the insulating film;
A central insulating film interposed between the gate junction and the emitter junction in each of the trenches;
It is formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other in the surface layer portion of the surface of the semiconductor layer, with respect to the central portion of the trench or the central portion of the trench in the thickness direction of the semiconductor layer. A base region of a second conductivity type having a bottom portion located on the surface side of the semiconductor layer;
An emitter region of a first conductivity type formed in a surface layer portion of the base region;
The surface layer portion of the surface of the semiconductor layer is electrically floated in a region surrounded by the inner circumferential surface of each of the trenches, with respect to the bottom surface of the trench in the thickness direction of the semiconductor layer. A floating region of a second conductivity type having a bottom portion located on the back surface side of the semiconductor layer;
An interlayer insulating film selectively covering the surface of the semiconductor layer;
A surface gate electrode formed on the interlayer insulating film and electrically connected to the gate junction;
A semiconductor device comprising: a surface emitter electrode formed on the interlayer insulating film and electrically connected to the emitter junction and the emitter region.   The semiconductor device according to claim 1, wherein the floating region covers the bottom surface of the trench.   The semiconductor device according to claim 2, wherein the floating region is formed below the emitter junction and covers the bottom surface of the trench so as not to be formed below the gate junction.   The semiconductor device according to claim 1, wherein the gate junction is separated from the floating region via the emitter junction and a central insulating film.   The plurality of trenches are respectively formed in a rectangular ring extending in a first direction in a plan view, and are formed at intervals along a second direction intersecting the first direction. The semiconductor device according to any one of the above. The plurality of trenches each have one end on one side and the other end on the other side in the first direction,
The semiconductor device according to claim 5, wherein the surface gate electrode is electrically connected to the gate junction in a region on the one end portion side and a region on the other end portion side of each of the trenches.   The surface gate electrode includes a gate pad formed on the interlayer insulating film, and a gate finger drawn from the gate pad onto the interlayer insulating film and electrically connected to the gate junction. The semiconductor device according to any one of claims 1 to 6.   The semiconductor device according to claim 7, wherein the plurality of trenches include the trenches formed in a region overlapping with the gate pad in plan view. The gate finger is formed along the periphery of the semiconductor layer so as to define an inward region of the semiconductor layer in a plan view.
The semiconductor device according to claim 7, wherein the plurality of trenches are respectively formed in regions partitioned by the gate fingers in a plan view. The interlayer insulating film has a contact hole that exposes the emitter region.
The semiconductor device according to any one of claims 1 to 9, wherein the surface emitter electrode is electrically connected to the emitter region through the contact hole. The semiconductor device further includes a contact trench formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other to expose the emitter region on the surface of the semiconductor layer,
The contact hole communicates with the contact trench.
11. The semiconductor device according to claim 10, wherein the surface emitter electrode is electrically connected to the emitter region through the contact hole and the contact trench.   The semiconductor device according to claim 11, wherein the contact trench is located on the surface side of the semiconductor layer with respect to the bottom of the base region.   The semiconductor device according to claim 11, further comprising a base contact region of a second conductivity type formed in a region along the contact trench in the surface layer portion of the base region. A contact emitter electrode embedded in the contact hole and electrically connected to the emitter region;
The semiconductor device according to any one of claims 11 to 13, wherein the surface emitter electrode is electrically connected to the emitter region through the contact emitter electrode. The surface emitter electrode enters the contact hole from above the interlayer insulating film,
The semiconductor device according to claim 14, wherein the contact emitter electrode is formed by a portion located in the contact hole in the surface emitter electrode.   The semiconductor device according to claim 15, wherein the surface emitter electrode comprises aluminum.   The semiconductor device according to claim 14, wherein the contact emitter electrode includes a conductive material different from the surface emitter electrode. The surface emitter electrode comprises aluminum,
The semiconductor device according to claim 17, wherein the contact emitter electrode comprises tungsten.   A semiconductor layer of a first conductivity type having a front surface and a back surface;
  A collector region of a second conductivity type formed in a surface layer portion of the back surface of the semiconductor layer;
  An outer peripheral surface, an inner peripheral surface, and a bottom surface connecting the outer peripheral surface and the inner peripheral surface are formed on the surface of the semiconductor layer with a space therebetween in a mode in which the outer peripheral surfaces face each other. With multiple annular trenches,
  An insulating film formed on the inner surface of each of the trenches;
  A gate junction buried on the outer peripheral surface side of each of the trenches with the insulating film interposed therebetween;
  An emitter junction which is buried on the inner circumferential surface side of each of the trenches at a distance from the gate junction and sandwiching the insulating film;
  A central insulating film interposed between the gate junction and the emitter junction in each of the trenches;
  It is formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other in the surface layer portion of the surface of the semiconductor layer, with respect to the central portion of the trench or the central portion of the trench in the thickness direction of the semiconductor layer. A base region of a second conductivity type having a bottom portion located on the surface side of the semiconductor layer;
  An emitter region of a first conductivity type formed in a surface layer portion of the base region;
  The surface layer portion of the surface of the semiconductor layer is electrically floated in a region surrounded by the inner circumferential surface of each of the trenches, with respect to the bottom surface of the trench in the thickness direction of the semiconductor layer. A floating region of a second conductivity type having a bottom portion located on the back surface side of the semiconductor layer;
  An interlayer insulating film selectively covering the surface of the semiconductor layer;
  A surface gate electrode formed on the interlayer insulating film and electrically connected to the gate junction;
  A surface emitter electrode formed on the interlayer insulating film and electrically connected to the emitter junction and the emitter region;
  The surface gate electrode includes a gate pad formed on the interlayer insulating film, and a gate finger drawn from the gate pad onto the interlayer insulating film and electrically connected to the gate junction. ,
  A semiconductor device, wherein the plurality of trenches include the trenches formed in a region overlapping with the gate pad in plan view.   The interlayer insulating film has a contact hole that exposes the emitter region.
  The semiconductor device according to claim 19, wherein the surface emitter electrode is electrically connected to the emitter region through the contact hole.

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