JP6288627B2 - Semiconductor device provided with voltage generation circuit - Google Patents

Description

  The present invention relates to a semiconductor device, and can be suitably used particularly for a semiconductor device having a built-in voltage generation circuit.

  A reference voltage generation circuit that generates a reference voltage in a semiconductor device such as an LSI (Large Scale Integration) is known. The reference voltage generation circuit is required to have low dependency on the semiconductor manufacturing process and low temperature dependency from the viewpoint of accuracy. Moreover, the operation | movement with a low power supply voltage is also requested | required from a viewpoint of power saving. A bandgap reference (hereinafter referred to as “BGR (Bandgap Reference)”) circuit is known as a reference voltage generation circuit that satisfies such requirements.

  Examples of the BGR circuit are disclosed in Patent Document 1 and Non-Patent Document 1. A BGR circuit corresponding to a low power supply voltage is disclosed in Patent Document 2.

On the other hand, the BGR circuit includes a bipolar transistor (hereinafter also referred to as “BJT (Bipolar Junction Transistor)”) as a basic component. It is known that the temperature dependence of the base-emitter voltage of a bipolar transistor is non-linear (example: Non-Patent Document 2). Non-Patent Document 3 discloses a BGR circuit that improves the nonlinear temperature dependence of the output voltage. Non-Patent Documents 4 to 6 disclose correction circuits that correct non-linear temperature dependence in the BGR circuit of Patent Document 1. Furthermore, Non-Patent Document 7 discloses a method for correcting temperature characteristics by a current (I _PTAT ² ) proportional to the square of absolute temperature.

U.S. Pat. No. 3,888,863 JP 11-45125 A (corresponding US Pat. No. 6,160,391)

Kuijk, K .; E, “A precision reference voltage source”, IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL. sc-8, no. 3, JUNE 1973. Tsividis, Y.M. P. , “Accurate analysis of temperature effects in Ic—VBE charac- teristics with application to bandgap reference sources, CIE. sc-15, No. 6, DECEMBER 1980. P. Malcovati, “Curvature-Compensated BiCMOS Bandgap With 1-V Supply Voltage”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-36, no. 7, JULY 2001. Pease, R.M. A. "A new Fahrenheit temperature sensor", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-19, no. 6, DECEMBER 1984. Paul, R.A. Patra, A.M. , “A temperature-compensated bandgap voltage Reference reference circuit for high precision applications”, Indian Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First Publication Date: 20-22 Dec. 2004. Paul, R.A. Patra, A.M. Baranwal, S.M. Dash, K .; , “Design of second-order sub-bandgap mixed-mode voltage reference circuit for low voltage applications”, VLSI Design, 2005. 18th International Contest 7 2005. Sundar, Siddharth, “A low power high power supply rejection ratio bandgap reference for portable applications, Massachusetts Institute of Technology 8”.

In recent years, a BGR circuit operates with a power supply voltage of 1 V or less and has a high output voltage accuracy (example: variation is 1% or less) over a wide temperature range (example: −50 ° C. to 150 ° C.). It is getting demanded. As such a BGR circuit, in a typical prior art, a base-emitter voltage difference V _PTAT (proportional to absolute temperature) of two bipolar transistors having different emitter areas and a base-emitter voltage V _{BE of the} bipolar transistor are used. (Monotonically decreasing with temperature) is added to generate the reference voltage V _BGR .

The graph of the reference voltage V _BGR has a mountain shape that is convex upward with respect to temperature. Then, the temperature T ₁ of the vicinity of the top of the mountain is set to be a central operating temperature of the semiconductor device mounting a BGR circuit. In this case, the temperature coefficient of the reference voltage V _BGR becomes substantially zero in a certain temperature range centered on the temperature T ₁ near the top of the mountain. As a result, the BGR circuit of the prior art can generate the reference voltage V _BGR with little temperature dependency in the temperature range.

However, BGR circuit of the prior art, leaves significantly to the high temperature side and low temperature side from the temperature T _1, the slope of the graph of the reference voltage V _BGR increases. That is, when out of the range of temperatures around the temperature T _1, the temperature coefficient increases, the reference voltage V _BGR of less accurate considerably. In addition, it is considered that the temperature range is difficult to cover the temperature range that has recently been increasing in demand. A BGR circuit with high output voltage accuracy over a wide temperature range is desired.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, the semiconductor device corrects the reference voltage (V _BGR ) generated by the reference voltage generation circuit with a plurality of correction currents (Icomp1, Icomp2,...) Output from the plurality of correction circuits. To do. The plurality of correction currents (Icomp1, Icomp2,...) Generated by the plurality of correction circuits are currents that monotonously increase from a predetermined temperature that is different for each correction circuit toward the low temperature side or the high temperature side.

According to the embodiment, the semiconductor device can further improve the accuracy of the reference voltage (V _BGR ) in a desired temperature range.

FIG. 1 is a block diagram illustrating an example of a voltage generation circuit built in a semiconductor device according to an embodiment. FIG. 2A is a graph showing the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 2B is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 2C is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 2D is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 2E is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 2F is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 3 is a block diagram showing another example of the voltage generation circuit built in the semiconductor device according to the embodiment. FIG. 4A is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 4B is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 4C is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 4D is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 4E is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 5A is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 5B is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 5C is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 5D is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 5E is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 6A is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 6B is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 6C is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 6D is a graph illustrating the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. FIG. 7 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the first embodiment. FIG. 8 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the first embodiment. FIG. 9 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the second embodiment. FIG. 10 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the second embodiment. FIG. 11 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the second embodiment. FIG. 12 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the third embodiment. FIG. 13 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the third embodiment. FIG. 14 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the fourth embodiment. FIG. 15A is a graph showing the principle of the temperature characteristic correction method in the voltage generation circuit in the case of FIG. FIG. 15B is a graph showing the principle of the temperature characteristic correction method in the voltage generation circuit in the case of FIG. FIG. 15C is a graph showing the principle of the temperature characteristic correction method in the voltage generation circuit in the case of FIG. FIG. 16 is a circuit diagram showing an example of a specific circuit configuration of the BGR core circuit. FIG. 17A is a circuit diagram illustrating an example of a specific circuit configuration of the second current generation unit of the BGR core circuit. FIG. 17B is a circuit diagram illustrating another example of the specific circuit configuration of the second current generation unit of the BGR core circuit. FIG. 18 is a partial circuit diagram illustrating an example of a specific circuit configuration of the voltage generation circuit according to the fourth embodiment. FIG. 19 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the fourth embodiment. FIG. 20A is a graph showing the principle of a method for correcting nonlinear temperature characteristics in the voltage generation circuit in the case of FIG. FIG. 20B is a graph showing the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit in the case of FIG. FIG. 20C is a graph showing the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit in the case of FIG. FIG. 21 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the fifth embodiment. FIG. 22 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit according to the fifth embodiment. FIG. 23 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the sixth embodiment. FIG. 24 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generating circuit according to the sixth embodiment. FIG. 25 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit according to the seventh embodiment. FIG. 26 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generating circuit according to the seventh embodiment. FIG. 27 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the eighth embodiment. FIG. 28 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the eighth embodiment. FIG. 29 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the ninth embodiment. FIG. 30 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the ninth embodiment. FIG. 31 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit. FIG. 32 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit. FIG. 33 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit. FIG. 34 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit. FIG. 35A is a circuit diagram illustrating an example of a differential amplifier in the voltage generation circuit. FIG. 35B is a circuit diagram illustrating an example of a differential amplifier in the voltage generation circuit. FIG. 36 is a circuit diagram illustrating an example of a voltage generation circuit including a startup circuit. FIG. 37 is a block diagram showing an example of a circuit configuration including a voltage generation circuit in which a low-pass filter is inserted in the power supply line. FIG. 38A is an explanatory diagram illustrating an example of a system to which the voltage generation circuit is applied. FIG. 38B is an explanatory diagram illustrating an example of a system to which the voltage generation circuit is applied. FIG. 38C is an explanatory diagram illustrating an example of a system to which the voltage generation circuit is applied. FIG. 38D is an explanatory diagram illustrating an example of a system to which the voltage generation circuit is applied. FIG. 39 is an explanatory diagram showing an example of a system to which the voltage generation circuit is applied. FIG. 40 is an explanatory diagram showing an example of a system to which the voltage generation circuit is applied. FIG. 41 is a block diagram showing an example of a chip layout of a semiconductor integrated circuit device to which the voltage generation circuit is applied. FIG. 42 is a cross-sectional view showing a part of a voltage generating circuit manufactured on a semiconductor substrate.

  Hereinafter, embodiments of a semiconductor device including a voltage generation circuit will be described with reference to the accompanying drawings.

1. Outline of Embodiment Hereinafter, an outline of a semiconductor device according to an embodiment will be described.

FIG. 1 is a block diagram illustrating an example of a voltage generation circuit built in a semiconductor device according to an embodiment. The voltage generation circuit 1 includes a reference voltage generation circuit 10 and a correction circuit 20. In this figure, there is one correction circuit 20. The reference voltage generation circuit 10 generates and outputs a reference voltage V _BGR (hereinafter also referred to as “BGR core circuit”). The correction circuit 20 generates a correction current Icomp based on the reference voltage V _BGRC and _feeds it back to the BGR core circuit 10. The correction current Icomp is a current for correcting the temperature characteristic of the reference voltage V _BGR .

  2A to 2F are graphs showing the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. These figures show the principle of the temperature characteristic correction method in the voltage generation circuit 1 of FIG. In each graph, the vertical axis represents voltage and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept.

2A to 2B show the principle of a conventionally known method for generating the reference voltage V _BGR . The reference voltage V _BGR is a difference voltage V _PTAT (proportional to absolute temperature) between the base-emitter voltages of two bipolar transistors having different emitter areas and a forward voltage V _BE (temperature) of the PN junction between the base and emitter of the bipolar transistor. And monotonously decreasing). At this time, the graph of the reference voltage V _BGR has an upwardly convex mountain shape. Then, the temperature T ₁ corresponding to the vicinity of the peak of the mountain is set to be the central use temperature of the voltage generation circuit 1. As a result, at a certain temperature range around the temperature T _1, it becomes the temperature coefficient is almost zero, the temperature dependency less reference voltage V _BGR is generated. However, leaves significantly to the high temperature side and low temperature side from the temperature T _1, the slope of the graph of the reference voltage V _BGR increases, that is, the temperature coefficient increases, the reference voltage V _BGR of less accurate.

In the voltage generation circuit 1 according to the present embodiment shown in FIG. 1, a correction circuit 20 is provided so as not to reduce the accuracy of the reference voltage V _BGR even at temperatures away from the central use temperature toward the high temperature side and the low temperature side. Yes. 2C to 2F show the principle of the method for generating the reference voltage V _BGR of the present embodiment. First, as shown in FIG. 2C, BGR core circuit 10, a temperature corresponding to the vicinity of the top of the graph peaks in the reference voltage V _BGR generates a reference voltage V _BGR to shift to the low temperature side. In this figure, the temperature T ₁ is shifted to the low temperature side as the temperature T ₁ ′. The reason for shifting to the low temperature side is to correct the high temperature side. The temperatures T ₁ improves the low temperature side of the accuracy by shifting to the low temperature side, thereby improving the high-temperature side of the accuracy by correcting the high-temperature side. As a result, the accuracy can be increased over a wide temperature range. Conversely, in the case of correcting the low temperature side, it is considered by shifting the temperature T ₁ of the high temperature side.

Next, as shown in FIGS. 2D to 2E, the correction circuit 20 subtracts the reference voltage V _BGR or a voltage V _BGRC proportional to the reference voltage V _BGR and the forward voltage V _BE of the PN junction between the base and the emitter of the bipolar transistor. Thus, the correction current Icomp is generated in the range where the subtraction result is positive. At this time, the voltage V _BGRC or the voltage V _BE is generated so that the temperature T _{2 at} the intersection of the voltage V _BGRC and the voltage V _{BE satisfies} T ₂ > T ₁ ′. As a result, the correction circuit 20 as the correction current Icomp (Figure 2E), and generates a current which increases monotonically toward the high temperature side from the predetermined temperature _{T 2.} The predetermined temperature T ₂ is also referred to as a threshold temperature.

2F, the correction current Icomp (FIG. 2E) of the correction circuit 20 is fed back to the BGR core circuit 10 and added to the reference voltage V _BGR (FIG. 2C), so that the final reference voltage V _BGR (FIG. 2F) is generated. The graph of this final reference voltage V _BGR (FIG. 2F) has a shape in which the peak of the mountain is at two locations of temperature T ₁ ′ and temperature T ₃ (> T ₂ ), and there is a valley near temperature T _2. . However, T ₁ ′ <T ₂ <T ₃ . At this time, the fluctuation range of the reference voltage V _BGR with respect to the temperature becomes small in the range from the temperature slightly lower side of the temperature T ₁ ′ to the temperature slightly higher side of the temperature T ₃ . That is, the temperature coefficient is kept small in the temperature range. In other words, as compared to the reference voltage V _BGR of Figure 2B, the reference voltage V _BGR of Figure 2F is a wide range, it is possible to reduce the voltage variation with respect to temperature. That is, the accuracy of the reference voltage V _BGR can be further increased. A specific circuit configuration of the voltage generation circuit 1 of FIG. 1 will be described later.

In FIG. 1, only one correction circuit 20 is provided. However, the accuracy of the reference voltage V _BGR can be further increased by providing a plurality of correction circuits. Hereinafter, a case where a plurality of correction circuits are provided will be described.

FIG. 3 is a block diagram showing another example of the voltage generation circuit built in the semiconductor device according to the present embodiment. The voltage generation circuit 1 includes a BGR core circuit 10 and a plurality of correction circuits 20-1 to 20-n (n is a natural number; the number of correction circuits). The BGR core circuit 10 generates and outputs a reference voltage V _BGR . The plurality of correction circuits 20-1 to 20-n generate a correction current Icomp and feed it back to the BGR core circuit 10. Each of the correction circuits 20-i (i = 1 to n; natural number) has a correction current Icompi (“secondary”) that monotonously increases from a predetermined temperature (threshold temperature) that is different for each correction circuit 20-i toward the low temperature side or the high temperature side. Also referred to as “correction current”. The correction current Icomp is a current for correcting the temperature characteristic of the reference voltage V _BGR and is the sum of a plurality of correction currents Icomp1 to Icompn generated by the plurality of correction circuits 20-1 to 20-n. The correction circuit 20-i generates the correction current Icompi based on the reference voltage V _BGR or the corresponding voltage V _BGRC .

However, the correction circuit 20-i may generate the correction current Icompi based on at least one of the voltage V _PTAT or the current I _PTAT corresponding thereto and the voltage V _BE or the current I _VBE corresponding thereto. However, the voltage V _PTAT is a difference voltage between the base-emitter voltages of two bipolar transistors having different emitter areas. The voltage V _BE is a forward voltage V _BE at the PN junction between the base and the emitter of the bipolar transistor.

In the present embodiment shown in FIG. 3, a plurality of correction circuits 20-1 to 20-n are provided so as not to _deteriorate the accuracy of the reference voltage V _BGR even at temperatures away from the central use temperature toward the high temperature side and the low temperature side. Is provided. Each correction circuit 20-i generates a correction current Icompi. Each correction current Icompi is monotonically increased from the threshold temperature T ₂ toward the high temperature side or the low temperature side. However, the predetermined temperature T ₂ is different from the predetermined temperature T ₂ of the correction current Icompi ′ of the other correction circuit 20-i ′ (i ′ ≠ i). Note that it is not necessary to use all of the plurality of correction circuits 20-1 to 20-n, and among the plurality of correction circuits 20-1 to 20-n by a method such as control of power supply to the correction circuit 20-i. Any one or a plurality of correction circuits 20 may be operated.

  In other words, the plurality of correction circuits 20-1 to 20-n are cascade-connected to the BGR core circuit 10, and can be said to be circuits that detect different threshold temperatures and generate different correction currents Icomp1 to Icompn. . The correction current Icomp (= ΣIcompi) can be arbitrarily changed by arbitrarily changing the number of cascade stages as necessary. This will be specifically described below.

First, a method for correcting the temperature characteristic on the high temperature side of the reference voltage V _BGR will be described.
4A to 4E are graphs showing the principle of the temperature characteristic correction method in the voltage generation circuit according to the embodiment. These figures show the principle of the temperature characteristic correction method in the voltage generation circuit 1 of FIG. In each graph, the vertical axis represents voltage and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept. These drawings show the case where there are three correction circuits 20 (n = 3, correction circuits 20-1 to 20-3). The basic function of each correction circuit 20-i is the same as that of the correction circuit 20 of FIG. That is, each correction circuit 20-i generates the correction current Icompi as shown in FIGS. 2D and 2E. Each correction current Icompi is monotonically increased from the threshold temperature _{T 2} toward the high temperature side. However, the least, different the threshold temperature _{T 2} is the threshold temperature _{T 2} of the other correction circuits 20-i '(i' ≠ i) of the correction current Icompi '. Further, the rate of increase / decrease of the correction current Icompi with respect to the temperature may be different.

FIG. 4A is a diagram corresponding to FIG. 2E relating to the correction circuit 20-1, and shows the correction current Icomp1. The correction current Icomp1 are monotonically increasing from the threshold temperature _{T 2a} toward the high temperature side. FIG. 4B is a diagram corresponding to FIG. 2E regarding the correction circuit 20-2, and shows the correction current Icomp2. The correction current Icomp2 are monotonically increasing from the threshold temperature _{T 2b} toward the high temperature side. FIG. 4C is a diagram corresponding to FIG. 2E regarding the correction circuit 20-3, and shows the correction current Icomp3. The correction current Icomp3 are monotonically increasing from the threshold temperature _{T 2c} toward the high temperature side. Here, T _2a <T _2b <T _2c . Changing the threshold temperature _{T 2,} for example, it can be realized by changing the voltage _{V BGRC} each correction circuit 20-i. In the example of FIGS. 4A to 4C, this can be realized by decreasing the voltage V _{BGRC in} the order of the correction circuits 20-1, 20-2 and _20-3 . However, the method of generating the correction current Icompi is not limited to the example (V _BGRC + V _BE ) in FIG. 2D.

As shown in FIG. 4D, the final correction current Icomp is the sum of correction currents Icomp1, Icomp2, and Icomp3. The correction current Icomp is the threshold temperature _T 2a _{through T} in _2b Icomp1, the threshold temperature _T 2b _{through T 2c} in Icomp1 + Icomp2, the Icomp1 + Icomp2 + Icomp3 the threshold temperature _{T 2c} above. That is, the correction current Icomp gradually increases as the temperature rises. This corresponds to that the reference voltage V _BGR (FIG. 2C) before adding the correction current Icomp gradually decreases toward the high temperature side. By adding the correction current Icomp to the voltage V _BGR in FIG. 2C, the reference voltage V _{BGR in} FIG. 4E is generated. Reference voltage V _BGR of Figure 4E, as compared to the reference voltage V _BGR of Figure 2F, the high temperature side, in a wider range, it is possible to reduce the voltage variation with respect to temperature. That is, the accuracy of the reference voltage V _BGR can be further increased. A specific circuit configuration of the voltage generation circuit 1 of FIG. 3 in this case will be described later.

Next, a method for correcting the temperature characteristic on the low temperature side of the reference voltage V _BGR will be described.
5A to 5E are graphs showing the principle of the temperature characteristic correction method in the voltage generation circuit according to the present embodiment. These figures show the principle of the temperature characteristic correction method in the voltage generation circuit 1 of FIG. In each graph, the vertical axis represents voltage and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept. These drawings also show the case where there are three correction circuits 20 (n = 3, correction circuits 20-1 to 20-3). The basic function of each correction circuit 20-i is opposite to that of the correction circuit 20 of FIG. That is, each correction circuit 20-i _subtracts a voltage V _BGRC (which may be a reference voltage V _BGR) proportional to the reference voltage V _BGR and a forward voltage V _{BE at the} base-emitter PN junction, and the subtraction result The correction current Icompi is generated in a range in which becomes positive. That is, the positive voltage in FIG. 2D is reversed. Each correction current Icompi increases monotonically toward the low temperature side from the threshold temperature _{T 2.} However, at least, the threshold temperature _{T 2} is different from the other correction circuits 20-i correction current Icompi of '(i' ≠ i) ' . Further, the rate of increase / decrease of the correction current Icompi with respect to the temperature may be different.

FIG. 5A is a diagram corresponding to FIG. 2E relating to the correction circuit 20-1, and shows the correction current Icomp1. The correction current Icomp1 is increased monotonically toward the low temperature side from the threshold temperature _{T 2c.} FIG. 5B is a diagram corresponding to FIG. 2E related to the correction circuit 20-2, and shows the correction current Icomp2. The correction current Icomp2 is increased monotonically toward the low temperature side from the threshold temperature _{T 2b.} FIG. 5C is a diagram corresponding to FIG. 2E relating to the correction circuit 20-3, and shows the correction current Icomp3. The correction current Icomp3 is increased monotonically toward the low temperature side from the threshold temperature _{T 2a. However,} a _{T 2a <T 2b <T 2c} . Changing the threshold temperature _{T 2,} for example, it can be realized by changing the voltage _{V BGRC} each correction circuit 20-i. 5A to 5C can be realized by increasing the voltage V _{BGRC in} the order of the correction circuits 20-1, 20-2, and _20-3 . However, the method of generating the correction current Icompi is not limited to the case where the positive voltage is reversed in the example of FIG. 2D (V _BGRC + V _BE ).

As shown in FIG. 5D, the final correction current Icomp is the sum of correction currents Icomp1, Icomp2, and Icomp3. The correction current Icomp is the threshold temperature _T 2c _{through T} in _2b Icomp3, the threshold temperature _T 2b _{through T 2a} in Icomp2 + Icomp3, the Icomp1 + Icomp2 + Icomp3 at below the threshold temperature _{T 2a.} That is, the correction current Icomp gradually increases as the temperature decreases. This corresponds to that the reference voltage V _BGR (FIG. 2C) before adding the correction current Icomp gradually decreases toward the low temperature side. By adding the correction current Icomp to the voltage V _BGR in FIG. 2C, the reference voltage V _{BGR in} FIG. 5E is generated. However, in this case, as the voltage V _{BGR in} FIG. 2C, it is preferable to use a curve in which the temperature T ₁ at the peak of the mountain shape is shifted to the high temperature side (not the low temperature side) to be the temperature T ₁ ′. Reference voltage V _BGR of Figure 5E, as compared with the reference voltage V _BGR of Figure 2F, the low temperature side, in a wider range, it is possible to reduce the voltage variation with respect to temperature. That is, the accuracy of the reference voltage V _BGR can be further increased. A specific circuit configuration of the voltage generation circuit 1 of FIG. 3 in this case will be described later. Note that one correction circuit 20-i may be provided as shown in FIG.

Next, a method for correcting the temperature characteristics of both the high temperature side and the low temperature side of the reference voltage V _BGR will be described.
6A to 6D are graphs showing the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit according to the present embodiment. These figures show the principle of the temperature characteristic correction method in the voltage generation circuit 1 of FIG. In each graph, the vertical axis represents voltage and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept. These drawings show the case where there are two correction circuits 20 (n = 2, correction circuits 20-1 to 20-2). The basic function of the correction circuit 20-1 (low temperature side) is opposite to that of the correction circuit 20 of FIG. 1 as in the case of FIGS. 5A to 5E. The basic function of the correction circuit 20-2 (high temperature side) is the same as that of the correction circuit 20 of FIG. 1 as in the case of FIGS. 4A to 4E. Correction current Icomp1 increases monotonically toward the low temperature side from the threshold temperature _{T 2a.} Correction current Icomp2 is monotonically increased from the threshold temperature _{T 2b} toward the high temperature side. Then, the predetermined temperature _{T 2a} is different from the other predetermined temperature _{T 2b.} This will be specifically described below. Further, the rate of increase / decrease of the correction current Icompi with respect to the temperature may be different.

FIG. 6A is a diagram corresponding to FIG. 5C relating to the correction circuit 20-1, and shows the correction current Icomp1. The correction current Icomp1 is increased monotonically toward the low temperature side from the threshold temperature _{T 2a.} FIG. 6B is a diagram corresponding to FIG. 4C relating to the correction circuit 20-2, and shows the correction current Icomp2. The correction current Icomp2 are monotonically increasing from the threshold temperature _{T 2b} toward the high temperature side. However, T _2a <T _2b . Changing the threshold temperature _{T 2,} for example, it can be realized by changing the voltage _{V BGRC} each correction circuit 20-i. However, the method of generating the correction current Icompi is not limited to the example (V _BGRC + V _BE ) in FIG. 2D.

As shown in FIG. 6C, the final correction current Icomp is the sum of the correction currents Icomp1 and Icomp2. The correction current Icomp is below the threshold temperature _{T 2a} is Icomp1, the Icomp2 the threshold temperature _{T 2b} above. That is, the correction current Icomp increases as the temperature decreases on the low temperature side, and the correction current Icomp increases as the temperature increases on the high temperature side. This corresponds to the fact that the reference voltage V _BGR (FIG. 2B) before adding the correction current Icomp decreases toward the low temperature side and decreases toward the high temperature side. By adding the correction current Icomp to the voltage V _BGR in FIG. 2B, the reference voltage V _{BGR in} FIG. 6D is generated. However, in this case, as the voltage V _BGR of FIG. 2B, shifting the temperature T ₁ of the vertex of the mound, especially on the low temperature side and high temperature side is not always necessary. Reference voltage V _BGR of Figure 6D, as compared to the reference voltage V _BGR of Figure 2B, both sides of the low temperature side and high temperature side, in a wider range, it is possible to reduce the voltage variation with respect to temperature. That is, the accuracy of the reference voltage V _BGR can be further increased. A specific circuit configuration of the voltage generation circuit 1 of FIG. 3 in this case will be described later. Note that a plurality of correction circuits 20-i may be provided on each of the high temperature side and the low temperature side depending on the accuracy to be obtained. Further, the number of correction circuits 20-i may be different between the low temperature side and the high temperature side.

2. Details of Embodiments Details of specific embodiments for realizing the configuration and operational effects described in the outline of the above embodiments will be described below.

(First embodiment)
A semiconductor device according to the first embodiment will be described. In the first embodiment, the correction circuit 20 generates a correction current Icomp based on the reference voltage V _BGR (or voltage V _BGRC ) and the base-emitter voltage V _{BE of the} bipolar transistor, and the correction current Icomp is A case where the high temperature side of the reference voltage V _BGR is corrected will be described. In the present embodiment, there is one correction circuit 20.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 1, and performs correction on the high temperature side as shown in FIGS. 2C to 2F.

  FIG. 7 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the first embodiment. The voltage generation circuit 1 is not particularly limited, but is formed on a semiconductor substrate such as a single silicon substrate by a known CMOS integrated circuit manufacturing technique. Hereinafter, the same applies to each embodiment.

The BGR core circuit 10 includes a current generation unit 101 and a voltage output unit 102. The current generator 101 generates a current corresponding to the voltage difference (ΔV _BE ) between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas and the base-emitter voltage V _BE2 of the bipolar transistor Q _2. A current I is generated by adding the corresponding current and the correction current Icomp generated by the correction circuit 20. The voltage output unit 102 converts the generated current into a reference voltage V _BGR and outputs it.

The current generator 101 includes, for example, NPN bipolar transistors Q ₁ and Q ₂ , resistors R ₁ , R ₂ , R ₃ , R ₅ , R ₇ , R ₈ , Rz, a capacitor Cc, and a differential amplifier A ₁ and P-channel type MOS transistors MP1 and MP2. The output unit 102 includes, for example, a resistor _{R 4.}

The bipolar transistors Q ₁ and Q ₂ have emitter terminals connected in common. The base terminal of the bipolar transistor Q ₁ is connected to the collector terminal of the bipolar transistor Q _2. Emitter area of the bipolar transistor Q ₁ is, the n bipolar transistor Q ₂ (n is an integer of 2 or more) is significantly doubled. That is, when the same current is supplied to bipolar transistors Q ₁ and Q ₂ , the emitter current density of bipolar transistor Q ₂ is set to be n times the emitter current density of transistor Q ₁ . In the example of this figure, n = 20. The resistor R ₁ has one end connected to the base terminal of the bipolar transistor Q ₂ and the other end connected to the collector terminal of the bipolar transistor Q ₁ . Resistor R ₂ is connected at one end to one end of the resistor R _1, and is connected at the other end to the collector terminal of the bipolar transistor Q _2. Resistor R ₅ is provided between the bipolar transistor Q _1, commonly connected emitter terminals and the ground node of Q _2. Resistor R ₃ are provided between the base terminal of the bipolar transistor Q ₂ and the ground node. Differential amplifier _{A 1} is input bipolar transistors _Q 1, _{Q 2} of the collector-side potential, respectively. PMOS transistors MP1, MP2 are both inputted to the output voltage of the differential amplifier _{A 1} to a gate terminal is connected to power supply node Vcc through a respective source terminal resistor _R 7, _{R 8.} The drain terminal of the PMOS transistor MP1 is connected to a connection node of the resistors _{R 1} and _{R 2.} Thereby, a feedback loop is formed. The resistor R ₄ is connected at one end to the drain terminal of the PMOS transistor MP2, and is connected at the other end to the ground node. Thereby, current I is supplied to the resistor _{R 4} from the drain terminal of the PMOS transistor MP2. Voltage at the node between the drain terminal and the resistor _{R 4} of the PMOS transistor MP2 becomes the reference voltage _{V BGR.} The operation principle of the BGR core circuit 10 will be described later.

The resistor Rz and the capacitor Cc are connected in series in this order, and are connected to the output side of the differential amplifier A1 and the drain terminal of the PMOS transistor MP1. These are elements for phase compensation for preventing circuit oscillation, and are not directly related to the generation of current / voltage. The resistors R ₇ and R ₈ are source resistors for reducing the effect of mismatch between the PMOS transistors MP1 and MP2, and may be omitted if the effect of mismatch can be ignored.

Correction circuit 20 generates a correction current Icomp corresponding to the output voltage _{V BGR} or voltage obtained by subtracting the base-emitter voltage _{V BE3} of the bipolar transistor _{Q 3} from the voltage _{V BGRC} corresponding thereto. Then, the generated correction current Icomp is fed back to the current generation unit 101.

Correction circuit 20 includes, for example, a differential amplifier _{A 2,} includes a bipolar transistor _{Q 3,} a resistor _{R 6,} and a MOS transistor MP3, MP4 of P-channel type. Further, it is preferable to include a P-channel type MOS transistor MP6.

The differential amplifier A ₂ receives the output voltage V _BGR of the BGR core circuit 10 or a voltage V _BGRC corresponding to the output voltage V _BGR and constitutes a voltage follower. Bipolar transistor Q ₃ are connected to the output terminal of the differential amplifier A ₂ to the base terminal. Resistor R ₆ is provided between the emitter terminal of the bipolar transistor Q ₃ and the ground node. PMOS transistor MP3 is connected to power supply node Vcc to the source terminal is connected to the collector terminal of the gate terminal and the bipolar transistor Q ₃ to the drain terminal. The PMOS transistor MP4 has a source terminal connected to the power supply node Vcc and a gate terminal connected to the gate terminal of the PMOS transistor PM3. PMOS transistor MP3, MP4 form a current mirror circuit for outputting a correction current Icomp from PMOS transistor MP4 depending on the current flowing to the collector of the bipolar transistor _{Q 3.} Although not particularly limited, the correction current Icomp is fed back between the resistor R ₅ of the current generator 101 and the emitter terminal connected in common to the bipolar transistors Q ₁ and Q ₂ . By adopting the feedback method in this way, high accuracy is not required for element circuits such as a differential amplifier and a current mirror used in the correction circuit 20, and accuracy can be improved without adding a large area or current.

Incidentally, the differential amplifier A ₂ is provided in order to supply the base current of the bipolar transistor Q _3. However, when the influence on the reference voltage V _BGR by supplying the base current directly from the PMOS transistor MP2 can be ignored, it may be omitted. The detailed operation principle of the correction circuit 20 will be described later.

  Next, the operation principle of the voltage generation circuit 1 will be described separately for the BGR core circuit 10 and the correction circuit 20.

(I) BGR core circuit 10
In FIG. 7, the current flowing through the resistor R ₁ is I ₁ , the current flowing through the resistor R ₂ is I ₂ , the current flowing through the PMOS transistors MP 1 and MP 2 is I, and the voltage at the connection point between the resistors R ₁ and R ₂ is V _3. And R ₁ = R ₂ = R ₁₂ is assumed. In the following description, the mirror ratio of the current mirror circuit or the like will be described as 1: 1, but it is not particularly limited, and the mirror ratio can be changed. In the following description, the base current of the bipolar transistor is ignored for easy understanding. However, in the simulation or the like in actual design, the calculation including the base current is performed.

The saturation current density of the bipolar transistor is Js, the unit area is A, the thermal voltage V _T = kT / q, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. At this time, the base-emitter voltage _{V BE2} of the bipolar transistor to _{Q 1} base-emitter voltage _{V BE1} and the bipolar transistor _{Q 2,} the formula (1) is satisfied. Also, feedback by the differential amplifier A ₁ is operating normally, the following equation (2) is satisfied.

  When Expression (1) is substituted into Expression (2), the following Expression (3) is established.

Further, the following equation (4) from Kirchhoff's voltage law from node potential V ₃ to the input of the differential amplifier A ₁ is satisfied. To summarize it, the following formula (5) is established as the relationship between the currents I ₁ and I ₂ . When the current I ₂ is eliminated from the equations (3) and (5), it can be approximated as the following equation (6). Here, V _OS is an input offset voltage of the differential amplifier A ₁ . However, in Equation (6), V _OS / I ₁ · R ₁₂ << 1 is assumed.

Here, when the quadratic equation for I ₁ in equation (6) is solved, I ₁ becomes the following equation (7A). However, D in Formula (7A) is the following Formula (7B).

Therefore, the output voltage V _BGR can be expressed by the following equation (8). Further, as apparent from the equation, by setting the resistance R ₄ <R ₃ , the output voltage V _BGR can be lowered (about 1.0 V or less).

When ΔV _BGR indicating an error from V _OS = 0 of the output voltage V _BGR is obtained based on the equation (8), the BGR core circuit 10 of the present embodiment is described in Non-Patent Document 1 and Patent Document 1. As compared with the BGR core circuit of FIG.

It is understood that the BGR core circuit 10 according to the present embodiment can operate from an output voltage V _BGR of 1.0 V or less and a power supply voltage Vcc of about 1.0 V. This can be easily understood from equation (8). That is, the BGR core circuit 10 according to the present embodiment has a PTAT (Proportional) proportional to the current (I _R3 = V _BE2 / R ₃ ) corresponding to V _BE of the bipolar transistor Q ₂ flowing through the resistor R ₃ and the absolute temperature. To Absolute Temperature) Current (I = I ₁ + I ₂ ) is added to cancel the coefficient proportional to temperature. Then, a structure for converting the summed current by resistor R ₄ to the voltage. Therefore, by adjusting the ratio of the resistor R ₃ and the resistor R ₄ , a low voltage output with the output voltage V _BGR of 1.0 V or less is possible.

As described above, according to the BGR core circuit 10 according to the present embodiment, the lower output voltage V _BGR can be generated by adjusting the ratio of the resistor R ₃ and the resistor R ₄ , and the low power supply voltage Vcc Operation becomes possible. Further, as shown in FIG. 7, the resistor R ₅ is inserted between the emitter terminals of the bipolar transistors Q ₁ and Q ₂ and the ground node, whereby the common input voltage of the differential amplifier A ₁ can be shifted high. Can be designed easily.

(II) Correction circuit 20
First, the temperature dependence of the base-emitter voltage V _BE of the bipolar transistor will be described. Temperature dependence of the base-emitter voltage, as shown in Non-Patent Document 2 described above, when the equation (9) below the temperature dependence of the collector current I _C, as shown in the following expression (10) expressed.

Where T _R is a reference temperature. Also, η is a constant depending on the device structure of the bipolar transistor, and the value is about 3.6 to 4.0. V _G0 is an extrapolated value to the absolute temperature 0K of the band gap voltage. As described above, m is if the collector current I _C is proportional to the absolute temperature becomes "1". When Expression (10) is transformed, the following Expression (11) is obtained.

In the above formula (Formula 11), the first item is a constant independent of temperature, and the second item is a term proportional to the absolute temperature. In addition, the third item is not proportional to the absolute temperature but is a term indicating nonlinear dependence. That is, the base-emitter voltage V _BE has a nonlinear dependence on the temperature.

The general formula (formula (8)) of the BGR core circuit shown in the above (I) BGR core circuit 10 can be expressed as the following formula (12), where K and L are constants determined by the resistance ratio. it can. Here, ΔV _BE is a difference voltage between the base-emitter voltage V _BE of the two bipolar transistors Q1 and Q2.

As can be seen from the above equation (12), the temperature dependence of the base-emitter voltage V _BE of the first item has nonlinearity. Therefore, the nonlinear temperature dependence is corrected only by the second item proportional to the absolute temperature. It turns out that it is theoretically impossible to do. Therefore, in the voltage generation circuit 1 according to the present embodiment, the nonlinear temperature dependence correction of the output voltage V _BGR is performed by the following method.

7, the potential of the resistor _{R 5} and the connection point of the bipolar transistors _Q 1, _{Q 2} of the emitter terminal and _{V 2,} the correction current and Icomp. For easy understanding, it is assumed that R ₁ = R ₂ = R ₁₂ and I ₁ = I ₂ = I _PTAT . At this time, I _PTAT can be expressed by the following formula (13) from V _BE2 = V _BE1 + R ₁₂ · I _PTAT .

Next, the current I is expressed by the following equation (14) from the Kirchhoff current law, and the current I _R3 flowing through the resistor R ₃ is expressed by the following equation (15). Therefore, the current I is expressed by the following equation (16): It becomes.

Therefore, the output voltage V _BGR is expressed by the following equation (17).

The output voltage V _BGR can be lowered by adjusting the resistor R ₃ and the resistor R ₄ as in the BGR core circuit 10 of FIG. 3 described above.

  The correction current Icomp can be expressed by the following equation (18) when the mirror ratio of the PMOS transistors MP3 and MP4 is 1: 1.

As shown in equation (18) above, correction current Icomp is generated based on the difference voltage between the base-emitter voltage _{V BE3} of the output voltage _{V BGRC} the bipolar transistor _{Q 3.} Correction current Icomp does not flow because it is _V BGRC _{<V BE3} is the low temperature side, the correction current Icomp from temperature at which _V BGRC _{= V BE3} is added at the high temperature side. Thus, the correction current Icomp is expressed as in the following formula (19).

Therefore, in the voltage generation circuit 1, the nonlinearity of the base-emitter voltage V _BE (corresponding to V _BE in FIG. 2A) of the first term of the above equation (17) is represented by I _PTAT (corresponding to V _BE of FIG. 2A). _The linear correction is performed using the correction current Icomp (corresponding to Icomp in FIG. 2E) in the third term. The temperature dependence is two voltages: to generate a correction current Icomp according to a difference (output voltage _{V BGRC} the base-emitter voltage _{V BE3} corresponds to Figure 2D of the _{V BGRC} and _{V BE),} V _BGRC = _{V BE3} become temperature correction current Icomp (corresponding to _{T 2} of the FIG. 2E) can be configured to be summed. The slope of the correction current Icomp can be controlled by the value of the resistor _{R 6.} As a result, the non-linear temperature characteristic can be corrected by adjusting the characteristic of V _BGR so that V _BGR ≧ V _BE3 in a desired temperature range in which the temperature characteristic is desired to be corrected.

Note that the above calculation is an approximate calculation, and in reality, a loop is formed between the BGR core circuit 10 and the correction circuit 20 and feedback is applied. Therefore, the values of the resistance, the correction current Icomp, etc. Deviation occurs. The exact value can be obtained by simulation. The power supply voltage Vcc in this example is about 1.0 V, since it is assumed to set the output voltage _{V BGR} of about 0.63V, while the bipolar transistor _{Q 3} of the correction circuit 20 is one stage configuration , if the output voltage is about 1.2V, it is desirable that the bipolar transistor Q ₃ of the correction circuit 20 and the two-stage configuration.

Whether or not the correction circuit 20 is used can be controlled by a control signal (power down signal). As an example, the following method can be considered. The PMOS transistor MP6 has a source terminal connected to the power supply node Vcc and a drain terminal connected to the gate terminal of the PMOS transistor PM3. Then, to the gate terminal of the differential power supply switch of the amplifier _{A 2} (not shown) and a PMOS transistor MP6, power-down signal PD and the inverted signal PD_N each is supplied. The power down signal PD is a control signal for powering down the correction circuit 20 at a high level. That is, when the correction circuit 20 is not used, the power down signal PD is set to a high level. In that case, the power supply to the differential amplifier _{A 2} is stopped power supply switch of the differential amplifier _{A 2} is turned off, PMOS transistor PM6 is turned on, PMOS transistors MP3, MP4 is turned off. As a result, the operation of the correction circuit 20 can be stopped. This method can also be used in the following other embodiments.

In the voltage generation circuit 1, the reference voltage V _BGR can be adjusted after the voltage generation circuit 1 is manufactured by making the resistances R _{1 to} R ₅ of the BGR core circuit 10 and the resistance R ₆ of the correction circuit 20 variable. (trimming). That is, the resistors R _{1 to} R ₆ have a function of adjusting the resistance value after manufacturing in order to correct the influence of element variation during manufacturing. For example, it is possible to adjust the resistance after manufacturing by providing a tap on the resistance and switching with a semiconductor switch or a fuse. The location where the tap switching information is held may be inside or outside the semiconductor chip. However, like a fuse or a non-volatile memory, it can be rewritten after manufacture and held in a non-volatile manner. The characteristics that are affected by the variation in the manufacturing elements include the absolute value of the output (reference voltage V _BGR ) and the temperature characteristics. For example, in the circuit of FIG. 7, the temperature characteristic of the output (reference voltage V _BGR ) can be improved by adjusting the resistor R ₃ , that is, by changing the size of the resistor R ₃ after the BGR core circuit 10 is manufactured. Is possible. Alternatively, resistor _R 1 _{= R} 2 ₌ even change the size of the _{R 12} can be improved as well. In addition, the absolute value of the output (reference voltage V _BGR ) can be improved by adjusting the resistor R ₄ . Further, by adjusting the resistors R ₅ and R ₆ , the nonlinear effect of the output (reference voltage V _BGR ) can be improved. These are also apparent from the equations (17) and (19). The resistors R _{1 to} R ₆ are preferably resistors of the same element type (eg, resistors using polysilicon). This method can also be used in the following other embodiments.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit 1 according to the first embodiment will be described.
FIG. 8 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the first embodiment. Voltage generating circuit 1 in FIG. 8, differs from the voltage generating circuit 1 in FIG. 7 in that it is not using the differential amplifier A ₂ in the correction circuit 20a. Hereinafter, differences from the voltage generation circuit 1 of FIG. 7 will be mainly described.

In this case, the BGR core circuit 10 supplies the current I instead of the reference voltage V _BGR to the correction circuit 20a. However, as in the case of FIG. 7, the current I is the sum of I ₁ (I _PTAT ) + I ₂ (I _PTAT ) and I _R3 and is a current flowing through the PMOS transistor MP2.

Correction circuit 20a subtracts the base-emitter voltage _{V BE3} of the bipolar transistor _{Q 3} from the voltage _{V BGRC} corresponding to the reference voltage _{V BGR} generated from current I to generate a correction current Icomp. Then, the correction current Icomp is fed back to the current generator 101.

Correction circuit 20 includes, for example, a bipolar transistor _{Q 3,} a resistor _{R 6, R 10, R 40} , and a MOS transistor MP3, MP4 of P-channel type. Here, the description of the P-channel type MOS transistor MP6 shown in FIG. 7 is omitted.

PMOS transistor MP5 is connected to the gate terminal of the PMOS transistor MP2 of the BGR core circuit 10 to the gate terminals are connected to power supply node Vcc through a resistor _{R 10} to the source terminal. Resistor _{R 40} is connected at one end to the drain of the PMOS transistor MP5, and is ground node connected to the other end. A connection node between the PMOS transistor MP5 and the resistor _{R 40} is connected to the base terminal of the bipolar transistor _{Q 3.} The other bipolar transistor Q ₃ , resistor R ₆ , and PMOS transistors MP3 and MP4 are the same as those in FIG. When the resistors R ₇ and R ₈ in the BGR core circuit are omitted, the resistor R ₁₀ is also omitted.

The PMOS transistor MP5 forms a current mirror circuit with the PMOS transistor MP2 of the BGR core circuit 10. Accordingly, the current I flowing through the PMOS transistor MP2 also flows through the PMOS transistor MP5. As a result, the connection node between the PMOS transistor MP5 and the resistor _{R 40,} the voltage _{V BGRC} corresponding to the output voltage _{V BGR} generated. Its voltage _{V BGRC} is supplied to the base terminal of the bipolar transistor _{Q 3.} As a result, the correction circuit 20a in FIG. 8 can perform the same operation as the correction circuit 20 in FIG.

In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 7 can be obtained in the case of the voltage generation circuit 1 of FIG. In addition, the correction circuit 20a of such 8 is different from the correction circuit 20 of FIG. 7 does not use the differential amplifier A _2. Therefore, the circuit area can be reduced as compared with the correction circuit 20 of FIG.

(Second Embodiment)
A semiconductor device according to the second embodiment will be described. In the second embodiment, the correction circuit 20 generates a correction current Icomp based on the reference voltage V _BGR (or voltage V _BGRC ) and the base-emitter voltage V _{BE of the} bipolar transistor, and the correction current Icomp is A case where the high temperature side of the reference voltage V _BGR is corrected will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, this embodiment is different from the first embodiment in which there is a single correction circuit 20 in that there are a plurality of correction circuits 20. Hereinafter, differences from the first embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on the high temperature side as shown in FIGS. 4A to 4E.

  FIG. 9 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the second embodiment. This voltage generation circuit 1 is different from the voltage generation circuit 1 of FIG. 7 in that a plurality of, for example, three correction circuits 20 are provided. In the example of this figure, there is shown a case where three correction circuits 20 can be regarded as three because of the substantial function of the circuit, instead of three independent correction circuits 20. However, three correction circuits 20 may exist independently. Hereinafter, differences from the voltage generation circuit 1 of FIG. 7 will be mainly described.

The output unit 102 of the BGR core circuit 10 includes four resistors R _4a , R _4b , R _4c , and R _4d . The resistors R _4a , R _4b , R _4c and R _4d are connected in series in this order between the drain terminal of the PMOS transistor MP2 and the ground node. The voltage at the connection node between the drain terminal of the PMOS transistor MP2 and the resistor _R4a becomes the reference voltage _VBGR . The reference voltage V _BGR is _divided by resistors R _4a , R _4b , R _4c , and R _4d . As a result, the voltage at the connection node between the resistor R _4a and the resistor R _4b is output to the correction circuit 20 as the voltage V _BGRCa . Similarly, the voltage at the connection node between the resistor R _4b and the resistor R _4c is output to the correction circuit 20 as the voltage V _BGRCb . Further, the voltage at the connection node between the resistor R _4c and the resistor R _4d is output to the correction circuit 20 as the voltage V _BGRCc . However, reference voltage V _BGR > voltage V _BGRCa > voltage V _BGRCb > voltage V _BGRCc . The voltage V _BGRCa , the voltage V _BGRCb , and the voltage V _BGRCc can be _referred to as a voltage V _BGRC corresponding to the output voltage V _BGR .

The correction circuit 20 includes, for example, differential amplifiers A _2a , A _2b , A _2c , bipolar transistors Q _3a , Q _3b , Q _3c , resistors R _6a , R _6b , R _6c , and P-channel type MOS transistor MP3. , MP4. In the correction circuit 20, the differential amplifier A _2a , the bipolar transistor Q _3a , the resistor R _6a, and the PMOS transistors MP3 and MP4 constitute one correction circuit 20-1. Similarly, the differential amplifier A _2bc , the bipolar transistor Q _3b , the resistor R _6b, and the PMOS transistors MP3 and MP4 constitute another correction circuit 20-2. Further, the differential amplifier A _2c , the bipolar transistor Q _3c , the resistor R _6c, and the PMOS transistors MP3 and MP4 constitute another correction circuit 20-3. Accordingly, the PMOS transistors MP3 and MP4 constituting the current mirror circuit are shared by the three correction circuits 20-1 to 20-3. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted.

In the correction circuit 20-1, the differential amplifier A _{2a receives} the voltage V _BGRCa of the BGR core circuit 10 and constitutes a voltage follower. Bipolar transistor _{Q 3a} is connected to the output terminal of the differential amplifier _{A 2a} to the base terminal is connected to the drain terminal of the PMOS transistor MP3 to the collector terminal. The resistor _R6a is provided between the emitter terminal of the bipolar transistor _Q3a and the ground node. At this time, the correction circuit 20-1 generates a correction current Icomp1 corresponding to a voltage _obtained by subtracting the base-emitter voltage V _BE3a of the bipolar transistor Q _3a from the voltage V _BGRCa . The threshold temperature at that time is T _2a in FIG. 4A.

Similarly, in the correction circuit 20-2, the differential amplifier A _{2b receives} the voltage V _BGRCb of the BGR core circuit 10 and constitutes a voltage follower. The bipolar transistor _Q3b has a base terminal connected to the output terminal of the differential amplifier _A2b and a collector terminal connected to the drain terminal of the PMOS transistor MP3. The resistor _R6b is provided between the emitter terminal of the bipolar transistor _Q3b and the ground node. At this time, the correction circuit 20-2 generates a correction current Icomp2 corresponding to the voltage obtained by subtracting the base-emitter voltage _{V BE3B} of the bipolar transistor _{Q 3b} from the voltage _{V BGRCb.} The threshold temperature at that time is T _2b in FIG. 4B.

Further, in the correction circuit 20-3, the differential amplifier A _{2c receives} the voltage V _BGRCc of the BGR core circuit 10 and constitutes a voltage follower. The bipolar transistor _Q3c has a base terminal connected to the output terminal of the differential amplifier _A2c , and a collector terminal connected to the drain terminal of the PMOS transistor MP3. Resistor R _6c is provided between the emitter terminal of bipolar transistor Q _3c and the ground node. At this time, the correction circuit 20-3 generates a correction current Icomp3 corresponding to the voltage obtained by subtracting the base-emitter voltage _{V BE3c} of the bipolar transistor _{Q 3c} from the voltage _{V BGRCc.} The threshold temperature at that time is T _2c in FIG. 4C.

The PMOS transistors MP3 and MP4 are the same as in the case of FIG. The PMOS transistors MP3 and MP4 constitute a current mirror circuit that outputs a current flowing to the collector side of the bipolar transistor Q ₃ (Q _3a , Q _3b , Q _3c ) as a correction current Icomp from the PMOS transistor MP4. Here, the PMOS transistors MP3 and MP4 are shared by the three correction circuits 20-1 to 20-3. Therefore, the correction current Icomp output from the PMOS transistor MP4 is the sum of the correction currents Icomp1, Icomp2, and Icomp3.

In this case, as a method of changing the threshold temperature T ₂ (T _2a , T _2b , T _2c ) in each correction circuit 20, for example, a method of changing the values of the resistors R _4a , R _4b , R _4c , R _4d Can be considered. Thereby, the voltage _{V BGRCa, V BGRCb,} since _{V BGRCc} changes, the intersection of the voltage _{V BE3} vary (see Figure 2D). As a result, the threshold temperatures T _2a , T _2b , T _2c are changed. On the other hand, as a method of changing the temperature dependency of the increase / decrease of the correction current Icomp (the slopes of the graphs of FIGS. 4A, 4B, and 4C), a method of changing the magnitudes of the resistors R _6a , R _6b , and R _6c can be considered. . The greater the resistance, the smaller the slope.

  Other configurations, operations, and principles of the BGR core circuit 10 and the correction circuit 20 are the same as those in the case of FIG.

  Also in this embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 7 can be obtained. In addition, in this case, the effects described in FIGS. 4A to 4E can be obtained by increasing the number of correction circuits 20.

(Modification 1)
Next, a modification of the specific circuit configuration of the voltage generation circuit 1 according to the second embodiment will be described.
FIG. 10 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the second embodiment. The voltage generation circuit 1 of FIG. 10 is different from the voltage generation circuit 1 of FIG. 9 in that the differential amplifiers A _{2a to} A _2c are not used in the correction circuit 20b (20b-1 to 20b-3). Hereinafter, differences from the voltage generation circuit 1 of FIG. 9 will be mainly described.

The differential amplifiers A _{2a to} A _2c are provided to supply base currents of the bipolar transistors Q _{3a to} Q _3c . However, when the influence on the reference voltage V _BGR by supplying the base current directly from the PMOS transistor MP2 can be ignored, it may be omitted.

In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 9 can be obtained in the case of the voltage generation circuit 1 of FIG. In addition, unlike the correction circuit 20 of FIG. 9, the correction circuit 20b of FIG. 10 does not use the differential amplifiers A _{2a to} A _2c . Therefore, the circuit area can be reduced as compared with the correction circuit 20 of FIG.

(Modification 2)
Furthermore, a modification of the specific circuit configuration of the voltage generation circuit 1 according to the second embodiment will be described.
FIG. 11 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the second embodiment. In the voltage generation circuit 1 of FIG. 11, the BGR core circuit 10 does not include resistors R _{4a to} R _4d that _{divide the} reference voltage V _BGR , and the correction circuit 20a includes resistors R _{40a to} R _40d having the same function. This is different from the voltage generation circuit 1 of FIG. Hereinafter, differences from the voltage generation circuit 1 of FIG.

In this case, the BGR core circuit 10 supplies the current I instead of the reference voltage V _BGR to the correction circuit 20a. However, as in the case of FIG. 9, the current I is the sum of I ₁ (I _PTAT ) + I ₂ (I _PTAT ) and I _R3 and is a current that flows through the PMOS transistor MP2. Further, the resistors R _4a , R _4b , R _4c , and R _4d for _dividing the reference voltage V _BGR are not provided.

Correction circuit 20a subtracts the base-emitter voltage _{V BE3} of the bipolar transistor _{Q 3} from the voltage _{V BGRC} corresponding to the reference voltage _{V BGR} generated from current I to generate a correction current Icomp. Then, the correction current Icomp is fed back to the current generator 101.

Correction circuit 20a, for example, a bipolar transistor _{Q 3a,} Q _3b, and _{Q 3c,} resistor _{R 6a, R 6b, R 6c} , R 10, R 40a, R 40b, R 40c, and _{R 40d,} MOS P-channel type Transistors MP3, MP4, and MP5 are provided. Of this correction circuit 20a, constituting the bipolar transistor _{Q 3a} and the resistor _{R 6a, R 10, R 40a} , R 40b, R 40c, and _{R 40d,} PMOS transistor MP3, MP4, MP5 and is the one of the correction circuit 20a-1 doing. Similarly, the bipolar transistor Q _3b , the resistors R _6b , R ₁₀ , R _40a , R _40b , R _40c , R _40d and the PMOS transistors MP3, MP4, MP5 constitute another correction circuit 20a-2. . Furthermore, the bipolar transistor Q _3c , the resistors R _6c , R ₁₀ , R _40a , R _40b , R _40c , R _40d and the PMOS transistors MP3, MP4, MP5 constitute another correction circuit 20a-3. . Accordingly, the resistors R ₁₀ , R _40a , R _40b , R _40c , R _40d and the PMOS transistor MP5 constituting the current mirror circuit and the PMOS transistors MP3 and MP4 constituting the other current mirror circuit are composed of the three correction circuits 20a. -1 to 20a-3. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. The resistor R _40a may be omitted.

PMOS transistor MP5 is connected to the gate terminal of the PMOS transistor MP2 of the BGR core circuit 10 to the gate terminal, connected to power supply node Vcc through a resistor _{R 10} to the source terminal. The resistors R _40a , R _40b , R _40c and R _40d are connected in series in this order between the drain terminal of the PMOS transistor MP5 and the ground node. The voltage at the connection node between the drain terminal of the PMOS transistor MP5 and the resistor R _40a becomes the reference voltage V _BGRC (in this case, equal to V _BGR ). The voltage V _BGRC is _divided by resistors R _40a , R _40b , R _40c , and R _40d . As a result, the voltage at the connection node between the resistor R _40a and the resistor R _40b is output as the voltage V _BGRCa to the base terminal of the bipolar transistor Q _3a . Similarly, the voltage of the connection node between the resistor R _40b and the resistor R _40c is output as the voltage V _BGRCb to the base terminal of the bipolar transistor Q _3c . Further, the voltage at the connection node between the resistor R _40c and the resistor R _40d is output as the voltage V _BGRCc to the base terminal of the bipolar transistor Q _3c . However, reference voltage V _BGR > voltage V _BGRCa > voltage V _BGRCb > voltage V _BGRCc . The voltage V _BGRCa , the voltage V _BGRCb , and the voltage V _BGRCc can be _referred to as a voltage V _BGRC corresponding to the output voltage V _BGR . The relationship among the bipolar transistors Q _3a , Q _3b , Q _3c , the resistors R _6a , R _6b , R _6c and the PMOS transistors MP3, MP4 is the same as in FIG.

The PMOS transistor MP5 forms a current mirror circuit with the PMOS transistor MP2 of the BGR core circuit 10. Accordingly, the current I flowing through the PMOS transistor MP2 also flows through the PMOS transistor MP5. As a result, an output voltage V _BGRC (= voltage V _BGR ) is generated at a connection node between the PMOS transistor MP5 and the resistor R _40a . The voltage V _BGRC is _divided by resistors R _40a , R _40b , R _40c , and R _40d , and is applied to the base terminals of the bipolar transistors Q _3a , Q _3b , and Q _3c as the voltage V _BGRCa , the voltage V _BGRCb , and the voltage V _BGRCc , respectively. Supplied. As a result, the correction circuits 20a-1 to 20a-3 in FIG. 11 can perform the same operation as the correction circuits 20-1 to 20-3 in FIG.

In this case, as a method of changing the threshold temperature T ₂ (T _2a , T _2b , T _2c ) in each correction circuit 20, for example, a method of changing the values of the resistors R _40a , R _40b , R _40c , R _40d. Can be considered. Thereby, the voltage _{V BGRCa, V BGRCb,} since _{V BGRCc} changes, the intersection of the voltage _{V BE3} vary (see Figure 2D). As a result, the threshold temperatures T _2a , T _2b , T _2c are changed. On the other hand, as a method of changing the temperature dependency of the increase / decrease of the correction current Icomp (the slopes of the graphs of FIGS. 4A, 4B, and 4C), a method of changing the magnitudes of the resistors R _6a , R _6b , and R _6c can be considered. . The greater the resistance, the smaller the slope.

  Other configurations, operations, and principles of the BGR core circuit 10 and the correction circuit 20a are the same as those in FIG.

In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 10 can be obtained in the case of the voltage generation circuit 1 of FIG. In addition, BGR core circuit 10 of such 11 is different from the BGR core circuit 10 of FIG. 10, does not use a resistor _{R 4} to the voltage dividing. Therefore, the wiring on the BGR core circuit 10 side can be simplified.

In the present embodiment, whether or not these correction circuits 20 are used can be controlled by the control signal (power down signal) described in the first embodiment. As an example, the power down signal PD can be supplied to the gate terminal of the PMOS transistor MP6. That is, the voltage generation circuit 1 in each embodiment can selectively turn on / off a desired correction circuit 20 from among the plurality of correction circuits 20 by a power-down signal. For example, in the case of a surrounding environment where it is not necessary to worry about temperature dependence or when the accuracy of the output voltage V _BGR required for the system is not high, all or some of the plurality of correction circuits 20 are turned off. Can do. On the contrary, in the case of the surrounding environment where the temperature dependence needs to be taken care of, or when the accuracy of the output voltage V _BGR required for the system is extremely high, all of the plurality of correction circuits 20 may be turned on. it can. In other words, the voltage generation circuit 1 according to the present embodiment can make a graph of the temperature dependence of the output voltage V _BGR into a desired curve in advance or afterwards depending on the situation. As a result, the power consumed by the unnecessary correction circuit 20 can be suppressed to save power. The same applies to the following other embodiments having a plurality of correction circuits 20.

(Third embodiment)
A semiconductor device according to a third embodiment will be described. In the third embodiment, the correction circuit 20 generates a correction current Icomp based on the reference voltage V _BGR (or voltage V _BGRC ) and the base-emitter voltage V _{BE of the} bipolar transistor, and the correction current Icomp is A case where the low temperature side of the reference voltage V _BGR is corrected will be described. In the present embodiment, there is one correction circuit 20. In other words, this embodiment is different from the first embodiment in which the high temperature side is corrected in that the low temperature side of the reference voltage V _BGR is corrected. Hereinafter, differences from the first embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 1, and performs correction on the low temperature side as shown in FIGS. 5A to 5E (however, one correction circuit 20 is provided).

FIG. 12 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the third embodiment. The voltage generating circuit 1, the correction circuit 20c, without using the resistor R _40, differs from the voltage generating circuit 1 in FIG. 8 in that it uses a diode D1, D2. Hereinafter, differences from the voltage generation circuit 1 of FIG. 8 will be mainly described.

Correction circuit 20c subtracts the base-emitter voltage _{V BE3} of the bipolar transistor _{Q 3} from 2 times the voltage 2V _D of the forward voltage of the diode generated from current I to generate a correction current Icomp. Then, the correction current Icomp is fed back to the current generator 101.

Correction circuit 20c includes, for example, a bipolar transistor _{Q 3,} a resistor _{R 6, R 10,} and diodes D1, D2, and a P-channel MOS transistor MP3, MP4, MP5. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted.

PMOS transistor MP5 is connected to the gate terminal of the PMOS transistor MP2 of the BGR core circuit 10 to the gate terminals are connected to power supply node Vcc through a resistor _{R 10} to the source terminal. The diodes D1 and D2 have one end connected to the drain of the PMOS transistor MP5 and the other end connected to the ground node. A connection node between the PMOS transistor MP5 and diodes D1, D2 is connected to the base terminal of the bipolar transistor _{Q 3.} The other bipolar transistor Q ₃ , resistors R ₆ and R ₁₀ , and PMOS transistors MP 3 and MP 4 are the same as in FIG.

The PMOS transistor MP5 forms a current mirror circuit with the PMOS transistor MP2 of the BGR core circuit 10. Accordingly, the current I flowing through the PMOS transistor MP2 also flows through the PMOS transistor MP5. At that time, the connection node between the PMOS transistor MP5 and the diode D1 can be said to be a voltage 2V _D that is twice the forward voltage of the diode. The voltage 2V _D is supplied to the base terminal of the bipolar transistor _{Q 3.} Thereby, the correction current Icomp is generated as in the case of FIG. Here, as the ambient temperature increases, the forward voltage of the diodes D1 and D2 decreases. Along with this, the current I is constant, since the voltage 2V _D decreases, the base voltage of the bipolar transistor Q ₃ is gradually reduced. Along with this, the correction current Icomp also decreases. As a result, when the temperature exceeds a predetermined temperature T ₂ (threshold temperature), the base voltage of the bipolar transistor Q ₃ becomes extremely small (below the threshold voltage), and no current flows through the bipolar transistor Q ₃ . Therefore, no current flows through the current mirror circuit composed of the PMOS transistors MP3 and MP4. As a result, the correction current Icomp becomes zero. That is, the correction current Icomp decreases with increasing temperature, not flow at a temperature above the threshold temperature T _2. In other words, the correction current Icomp increases monotonically toward the low temperature side from the threshold temperature _{T 2.} Thus, the correction circuit 20c is a circuit capable of realizing the low-temperature side correction shown in FIGS. 5A to 5E.

Although this embodiment is a case where there is one correction circuit 20c, more precise correction is possible by using a plurality of correction circuits having different threshold temperatures as in the second embodiment. . In that case, the plurality of correction circuits 20c, as a method for each of the threshold temperature T ₂ to be different from each other, for example, when the diodes D1 = D2, a method of changing the number of diodes can be considered. The more is increased, the threshold temperature T ₂ is higher. Further, as a method for changing the temperature dependence of the increase or decrease of the correction current Icomp (inclination of the graph, such as FIG. 5A), a method of changing the size of the resistor R ₆ is considered. The greater the resistance, the smaller the slope. In this case, as in the case of FIG. 11 and the like, in the plurality of correction circuits 20c, for example, a plurality of diodes and the PMOS transistors MP3, MP4, and MP5 can be shared.

  Other configurations, operations, and principles of the BGR core circuit 10 are the same as those in FIG.

In the present embodiment, the reference voltage V _BGR can reduce the voltage change with respect to the temperature in a wide range on the low temperature side as compared with the reference voltage V _{BGR in} FIG. 2B. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the third embodiment will be described.
FIG. 13 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the third embodiment. Voltage generating circuit 1 in FIG. 13, the correction circuit 20d, without using the bipolar transistor _{Q 3,} in that it uses an MOS transistor MN1 of the N-channel type is different from the voltage generating circuit 1 in FIG. 12. In the following, differences from FIG. 12 will be mainly described.

Correction circuit 20d includes, for example, a MOS transistor MN1, MN2, MN3 of N-channel type, a resistor _{R 6, R 10,} and a MOS transistor MP3, MP4, MP5 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted.

PMOS transistor MP5 is connected to the gate terminal of the PMOS transistor MP2 of the BGR core circuit 10 to the gate terminals are connected to power supply node Vcc through a resistor _{R 10} to the source terminal. The NMOS transistor MN2 has a drain terminal connected to the gate terminal and the drain of the PMOS transistor MP5. The NMOS transistor MN3 has a drain terminal connected to the gate terminal and the source terminal of the NMOS transistor MN2, and a source terminal connected to the ground node. NMOS transistor NM1 is connected to the gate terminal to the gate of the NMOS transistor MN2, is connected to the source terminal to one end of resistor _{R 6,} are connected to the drain terminal to the drain terminal of the PMOS transistor MP3. The NMOS transistors MN2 and MN3 are both diode-connected, that is, can be viewed as the diodes D1 and D2 in FIG. Other resistors R ₆ and R ₁₀ and PMOS transistors MP3 and MP4 are the same as those in FIG.

The PMOS transistor MP5 forms a current mirror circuit with the PMOS transistor MP2 of the BGR core circuit 10. Accordingly, the current I flowing through the PMOS transistor MP2 also flows through the PMOS transistor MP5. The connection node between the PMOS transistor MP5 and the NMOS transistor MN2 can be said to be a voltage 2V _TH that is twice the threshold voltage of the NMOS transistor. This voltage 2V _TH is supplied to the gate terminal of the NMOS transistor MN1. As a result, the NMOS transistor MN1 is turned on, a current flows through the current mirror circuit composed of the PMOS transistors MP3 and MP4, and the correction current Icomp is generated. However, as the ambient temperature increases, the threshold voltages of the diode-connected NMOS transistors MN2 and MN3 decrease. Accordingly, if the current I is constant, the voltage 2V _TH decreases, so the gate voltage of the NMOS transistor MN1 decreases. Along with this, the correction current Icomp also decreases. As a result, when the temperature exceeds a predetermined temperature T ₂ (threshold temperature), the gate voltage of the NMOS transistor MN1 becomes extremely small (below the threshold voltage), and no current flows through the NMOS transistor MN1. Therefore, no current flows through the current mirror circuit composed of the PMOS transistors MP3 and MP4. As a result, the correction current Icomp becomes zero. That is, the correction current Icomp decreases with increasing temperature, not flow at a temperature above the threshold temperature T _2. In other words, the correction current Icomp increases monotonically toward the low temperature side from the threshold temperature _{T 2.} Thus, the correction circuit 20d is a circuit capable of realizing the low-temperature side correction shown in FIGS. 5A to 5E.

In this case as well, there is only one correction circuit 20d, but more precise correction is possible by using a plurality of correction circuits having different threshold temperatures as described above. In this case, by increasing or decreasing the NMOS transistor of diode connection, to change the threshold temperature T _2.

  Other configurations, operations, and principles of the BGR core circuit 10 are the same as those in FIG.

  In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 12 can be obtained in the case of the voltage generation circuit 1 of FIG.

Although the second embodiment is correction on the high temperature side and the third embodiment is correction on the low temperature side, it is possible to combine both. For example, the correction circuit 20a may be used as the high-temperature correction circuit 20, and the correction circuit 20c may be used as the low-temperature correction circuit 20. Accordingly, it is possible to realize a method for correcting both the high temperature side and low temperature side temperature characteristics of the reference voltage V _BGR as shown in FIGS. 6A to 6D.

(Fourth embodiment)
A semiconductor device according to a fourth embodiment will be described. In the fourth embodiment, the correction circuit 20 corresponds to the current corresponding to the difference voltage ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas and the base-emitter voltage V _BE of the bipolar transistor. The case where the correction current Icomp is generated based on the current and the high temperature side of the reference voltage V _BGR is corrected with the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, the present embodiment is different from the second embodiment in the type of current used for generating the correction current Icomp. Hereinafter, differences from the second embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on the high temperature side as shown in FIGS. 4A to 4E. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 14 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the fourth embodiment.
The BGR core circuit 10 corresponds to the current corresponding to the voltage difference (ΔV _BE ) between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas and the base-emitter voltage V _BE of the bipolar transistor Q. The current generator 101 generates a current obtained by adding the corrected current and the correction current Icomp generated by the correction circuit 20. Then, the generated current is converted into a reference voltage V _BGR by the voltage output unit 102 and output. Further, the BGR core circuit 10 generates I _PTAT1 and I _PTAT2 as currents corresponding to the difference voltage (ΔV _BE ) between the base-emitter voltages of two bipolar transistors having different emitter areas. Further, a current I _VBE corresponding to the base-emitter voltage V _BE of the bipolar transistor is generated. Then, the generated current is output to the correction circuit 20. A specific configuration of the BGR core circuit 10 will be described later.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I PTAT1} and the current _{I VBE.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT2} and the current _{I VBE.} Then, the correction current Icomp2 is fed back to the current generator 101.

The correction circuit 20-1 includes, for example, a constant current source I _VBE , a constant current source I _PTAT1 , and P channel type MOS transistors MP31 and MP32. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source I _VBE has one end connected to power supply node Vcc so that constant current I _VBE flows from power supply node Vcc to the ground node based on current I _VBE from BGR core circuit 10. Constant current source I _PTAT1 has one end connected to the other end of constant current source I _VBE so that constant current I _PTAT1 flows from power supply node Vcc to the ground node based on current I _PTAT1 from BGR core circuit 10. The other end is connected to the ground node. The PMOS transistor MP31 has a source terminal connected to the power supply node Vcc, and a drain terminal connected to a gate terminal and a connection node between the constant current source I _VBE and the constant current source _IPTAT1 . The PMOS transistor MP32 has a source terminal connected to the power supply node Vcc and a gate terminal connected to the gate terminal of the PMOS transistor PM31. The PMOS transistors MP31 and MP32 constitute a current mirror circuit. Its current mirror circuit outputs a correction current Icomp1 from the drain terminal of the PMOS transistor MP32 in accordance with the difference current flowing into the connection node between the constant current source _{I VBE} and the constant current source _{I PTAT1 (ΔI1 = I PTAT1 -I} VBE) . In this case, if ΔI1 ≧ 0, that is, I _PTAT1 ≧ I _VBE , ΔI1 = Icomp1 flows.

The correction circuit 20-2 includes, for example, a constant current source I _VBE , a constant current source I _PTAT2, and P-channel type MOS transistors MP33 and MP34. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source I _VBE has one end connected to power supply node Vcc so that constant current I _VBE flows from power supply node Vcc to the ground node based on current I _VBE from BGR core circuit 10. The constant current source _{I PTAT2,} based on the current _{I PTAT2} from BGR core circuit 10, to flow a constant current _{I PTAT2} in the direction of the ground node from the power supply node Vcc, one end connected to the other end of the constant current source _{I VBE} The other end is connected to the ground node. The PMOS transistor MP33 has a source terminal connected to the power supply node Vcc, and a drain terminal connected to a gate terminal and a connection node between the constant current source I _VBE and the constant current source _IPTAT2 . The PMOS transistor MP34 has a source terminal connected to the power supply node Vcc and a gate terminal connected to the gate terminal of the PMOS transistor PM33. The PMOS transistors MP33 and MP34 constitute a current mirror circuit. Its current mirror circuit outputs a correction current Icomp2 from the drain terminal of the PMOS transistor MP34 in accordance with the difference current flowing into the connection node between the constant current source _{I VBE} and the constant current source _{I PTAT2 (ΔI2 = I PTAT2 -I} VBE) . In this case, if ΔI2 ≧ 0, that is, I _PTAT2 ≧ I _VBE , ΔI2 = Icomp2 flows.

  15A to 15C are graphs showing the principle of the temperature characteristic correction method in the voltage generation circuit in the case of FIG. In each graph, the vertical axis represents current or voltage, and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept.

As shown in FIG. 15A, currents I _PTAT1 and I _PTAT2 and a current I _VBE are supplied from the BGR core circuit 10. The currents I _PTAT1 and I _PTAT2 are currents according to the difference voltage (ΔV _BE ) between the base-emitter voltages of two bipolar transistors having different emitter areas, and are proportional to the absolute temperature. The current I _VBE is a current corresponding to the base-emitter voltage V _BE of the bipolar transistor and is non-linear.

Next, as shown in FIG. 15B, the correction circuit 20-1, based on a constant current _{I VBE} and the constant current _{I PTAT1,} generate their difference current (ΔI1 _{= I} PTAT1 _{-I VBE)} as a correction current Icomp1 To do. In this case, .DELTA.I1 ≧ 0, that is, _{I PTAT1} ≧ _{I VBE,} the threshold temperature above _{T 1,} ΔI1 = Icomp1 is generated. Similarly, the correction circuit 20-2, based on a constant current _{I VBE} and the constant current _{I PTAT2,} produces their difference current (ΔI2 _{= I} PTAT2 _{-I VBE)} as a correction current Icomp2. In this case, [Delta] I2 ≧ 0, that is, _{I PTAT2} ≧ _{I VBE,} the threshold temperature _{T 2} above, ΔI2 = Icomp2 is generated. As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I PTAT1} and the current _{I PTAT2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

Next, as shown in FIG. 15C, BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C. That is, the reference voltage V _BGR before addition is the current corresponding to the difference voltage (ΔV _BE ) between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas and the base of the bipolar transistor Q ₄ . A current obtained by adding a current corresponding to the emitter-to-emitter voltage V _BE4 is converted into a voltage.

The graph of this final reference voltage V _BGR (FIG. 15C) has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ , and there are peak peaks at three locations across each valley. However, T ₁ <T ₂ . That is, as compared with the reference voltage _{V BGR} of FIG. 2B and FIG. 2C, the in (higher temperature side than the apex of the particular original reference voltage _{V BGR} mountain) relatively wide range of the reference voltage _{V BGR} of Figure 15C, the temperature The voltage change with respect to can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

Next, the BGR core circuit 10 according to the present embodiment will be described.
FIG. 16 is a circuit diagram showing an example of a specific circuit configuration of the BGR core circuit 10. The BGR core circuit 10 includes a current generation unit 101, an output unit 102, and a first current generation unit 103.

The current generator 101 includes, for example, NPN bipolar transistors Q ₁ , Q ₂ , Q ₄ , resistors R ₁ , R ₂ , R ₄ , R ₇ , R ₈ , Rz, a capacitor Cc, and a differential amplifier A ₁ and P-channel type MOS transistors MP1 and MP2. The output unit 102 includes, for example, a resistor _{R 3.} The first current generator 103 includes, for example, resistors R ₁₇ and R ₁₈ and P-channel type MOS transistors MP13 and MP14.

In the current generator 101, the bipolar transistors Q ₁ and Q ₂ have their emitter terminals connected in common to the ground node. The base terminal of the bipolar transistor Q ₁ is connected to the collector terminal of the bipolar transistor Q _2. Emitter area of the bipolar transistor Q ₁ is, the n bipolar transistor Q ₂ (n is an integer of 2 or more) is significantly doubled. That is, when allowed to flow the same current to the bipolar transistor Q _1, Q _2, the emitter current density of the bipolar transistor Q ₂ is set to be n times the emitter current density of the transistor Q _1. In the example of this figure, n = 20. The resistor R ₁ has one end connected to the base terminal of the bipolar transistor Q ₂ and the other end connected to the collector terminal of the bipolar transistor Q ₁ . Resistor R ₂ is connected at one end to one end of the resistor R _1, and is connected at the other end to the collector terminal of the bipolar transistor Q _2. Differential amplifier _{A 1} is input bipolar transistors _Q 1, _{Q 2} of the collector-side potential, respectively. PMOS transistors MP1, MP2 are both inputted to the output voltage of the differential amplifier _{A 1} to a gate terminal is connected to power supply node Vcc through a respective source terminal resistor _R 7, _{R 8.} The drain terminal of the PMOS transistor MP1 is connected to a connection node of the resistors _{R 1} and _{R 2.} Thereby, a feedback loop is formed. Further, the bipolar transistor _{Q 4} are, is connected to the collector terminal and the base terminal to the drain terminal of the PMOS transistor MP2. Resistor R ₄ is at one end to the emitter terminal of the bipolar transistor Q _4, and is connected at the other end to the ground node.

  The resistor Rz and the capacitor Cc are connected in series in this order, and are connected to the output side of the differential amplifier A1 and the drain terminal of the PMOS transistor MP1. These are elements for phase compensation for preventing circuit oscillation, and are not directly related to the generation of current / voltage.

At the output 102, the resistor _{R 3} is connected at one end to the drain terminal of the PMOS transistor MP2, and is connected at the other end to the ground node. The connection node between the drain terminal of the resistor _{R 3} and the PMOS transistor MP2, the correction current Icomp from the correction circuit 20 is supplied. The voltage of the connection node is output as the reference voltage V _BGR . Here, in the connection node, the following expression (20) is established. When it is arranged, it is expressed as the following formula (21).

_{However, V BE} is the base-emitter voltage _{V BE4} of the bipolar transistor _{Q 4.} 2I _PTAT is a current (I = I ₁ + I ₂ ) corresponding to the voltage difference between the base-emitter voltages of _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas. Icomp is a correction current from the correction circuit 20. Therefore, three currents are supplied to the connection node. That is, a current according to the base-emitter voltage V _BE4 of the bipolar transistor Q ₄ , a current according to the difference voltage between the base-emitter voltages of _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas, and a correction circuit The correction current Icomp from 20. By adding these three currents (the same _applies to the voltages), the reference voltage V _BGR can be made highly accurate within a relatively wide range, as shown in FIG. 15C.

In the first current generator 103, the PMOS transistor MP13 is connected to the gate terminal of the PMOS transistor MP2 to the gate terminals are connected to power supply node Vcc through a resistor _{R 17} to the source terminal. Further, the PMOS transistor MP14 is connected to the gate terminal of the PMOS transistor MP2 to the gate terminals are connected to power supply node Vcc through a resistor _{R 18} to the source terminal.

The PMOS transistors MP13 and MP14 constitute a current mirror circuit with the PMOS transistor MP2. Here, a current I (= I ₁ + I ₂ = 2I _PTAT ) corresponding to the voltage difference between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas flows through the PMOS transistor MP2. . Therefore, a current (∝I _PTAT ) corresponding to the voltage difference between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas can be passed to the PMOS transistors MP13 and MP14. Here, different currents I _PTAT1 and I _PTAT2 can be generated by making the current mirror ratios of the PMOS transistors MP13 and MP14 different. However, when the current _{I PTAT} may be one can omit the PMOS transistor MP14. When the voltage V _PTAT is required, the current I _PTAT may be converted into a voltage using a resistor or the like.

FIG. 17A is a circuit diagram illustrating an example of a specific circuit configuration of the second current generation unit 104 of the BGR core circuit 10. The second current generator 104 includes a bipolar transistor Q11, a resistor R ₁₄ , P-channel MOS transistors MP21, MP22, MP23, MP24, and a differential amplifier A10. Second current generation unit 104 generates a current corresponding to base-emitter voltage _VBE11 of bipolar transistor Q11.

The PMOS transistors MP21 and MP22 have their source terminals connected to the power supply node and their gate terminals connected in common. The differential amplifier A10 has two input terminals connected to the drain terminals of the PMOS transistors MP21 and MP22, and an output terminal connected to the gate terminals of the PMOS transistors MP21 and MP22. The bipolar transistor Q11 has a collector terminal and a base terminal connected to the drain terminal of the PMOS transistor MP21, and an emitter terminal connected to the ground node. Resistor _{R 14} is connected at one end to the drain terminal of the PMOS transistor MP22, and is connected at the other end to the ground node. Here, the PMOS transistors MP21 and MP22 constitute a current mirror circuit. Accordingly, a current corresponding to the base-emitter voltage _VBE11 of the bipolar transistor Q11 flowing in the PMOS transistor MP21 also flows in the PMOS transistor _MP22 .

  Further, the PMOS transistor MP23 has a gate terminal connected to the gate terminal of the PMOS transistor MP22 and a source terminal connected to the power supply node. The PMOS transistor MP24 has a gate terminal connected to the gate terminal of the PMOS transistor MP22 and a source terminal connected to the power supply node.

The PMOS transistors MP23 and MP24 form a current mirror circuit with the PMOS transistor MP22. Accordingly, a current corresponding to the base-emitter voltage _VBE11 of the bipolar transistor Q11 flows through the PMOS transistor _MP22, and currents corresponding to the current also flow through the PMOS transistors MP23 and MP24. Here, by varying the current mirror ratio of the PMOS transistors MP23, MP24, it is possible to produce different currents _{I VBE1, I VBE2.} However, if only one current I _VBE is required, the PMOS transistor MP24 can be omitted. When the voltage V _VBE is necessary, the current I _VBE may be converted into a voltage using a resistor or the like.

FIG. 17B is a circuit diagram illustrating another example of the specific circuit configuration of the second current generation unit 104 of the BGR core circuit 10. This example is different from the case of FIG. 17A in that a differential amplifier is not used. Differences will be described below. The second current generation unit 104 includes a bipolar transistor Q11, a resistor R ₁₄ , P-channel MOS transistors MP21, MP22, MP23, MP24, and N-channel MOS transistors MN11, MN12. Second current generation unit 104 generates a current corresponding to base-emitter voltage _VBE11 of bipolar transistor Q11.

The PMOS transistors MP21 and MP22 have their source terminals connected to the power supply node and their gate terminals connected in common. Further, the PMOS transistor MP22 has a gate terminal connected to the drain terminal. The NMOS transistor MN11 has a drain terminal and a gate terminal connected to the drain terminal of the PMOS transistor MP21, and a source terminal connected to the collector terminal of the bipolar transistor Q11. NMOS transistor MN12 is connected to the drain terminal to the drain terminal of the PMOS transistor MP22 is connected to the gate terminal to the gate terminal of the NMOS transistor MN11, and is connected to the source terminal to one end of a resistor _{R 14.} Also in this case, the PMOS transistors MP21 and MP22 constitute a current mirror circuit. Further, the PMOS transistors MP23 and MP24 constitute a current mirror circuit with the PMOS transistor MP22. Accordingly, as in FIG. 17A in this case, it is possible to generate a current _{I VBE1, I VBE2.}

FIG. 18 is a partial circuit diagram illustrating an example of a specific circuit configuration of the voltage generation circuit 1 according to the fourth embodiment. In the example of this figure, as a specific circuit configuration of the voltage generation circuit 1 of FIG. 14, a case where a circuit combining FIG. 16 and FIG. However, as the BGR core circuit 10, only the PMOS transistors MP13 and MP23 and the NMOS transistor MN15 related to the output of the circuit combining FIG. 16 and FIG. 17A are shown. Further, the correction circuit 20 shows only the correction circuit 20-1. Resistor _{R 17} being inserted into the source terminal of the PMOS transistor MP13 is omitted.

In the correction circuit 20-1, a constant current source _{I VBE} is implemented as a PMOS transistor MP33. Here, the PMOS transistor MP33 has a source terminal connected to the power supply node and a drain terminal connected to the constant current source _IPTAT1 . Further, the PMOS transistor MP33 has a gate terminal connected to the gate terminal and drain terminal of the PMOS transistor MP23 of the second current generator 104. Thus, the PMOS transistor MP33 and the PMOS transistor MP23 constitute a current mirror circuit. As a result, the current I _VBE generated in the PMOS transistor MP23 is reflected in the PMOS transistor MP33. That is, it can be seen that the constant current source I _VBE (PMOS transistor MP33) is substantially supplied with the current I _VBE from the BGR core circuit 10 (the second current generation unit 104 thereof).

In the correction circuit 20-1, the constant current source _IPTAT1 is realized as an NMOS transistor MN31. Here, the NMOS transistor MN31 has a source terminal connected to the ground node and a drain terminal connected to the constant current source _IVBE . Further, the NMOS transistor MN31 has a gate terminal connected to the gate terminal and drain terminal of the NMOS transistor MN15 of the first current generator 103. However, the NMOS transistor MN15 has a source terminal connected to the ground node, and a gate terminal and a drain terminal connected to the drain of the PMOS transistor MP13. Then, the current _IPTAT1 flowing through the PMOS transistor MP13 also flows through the NMOS transistor MN15. Here, the NMOS transistor MN31 and the NMOS transistor MN15 constitute a current mirror circuit. As a result, the current _IPTAT1 that occurs in the PMOS transistor MP13 and also flows in the NMOS transistor MN15 is reflected in the NMOS transistor MN31. That is, it can be considered that the constant current source I _PTAT1 (NMOS transistor MN31) is substantially supplied with the current I _PTAT1 from the BGR core circuit 10 (the first current generation unit 103 _thereof ).

  As described above, the voltage generation circuit 1 shown in FIG. 14 is realized.

  Each circuit configuration illustrated in FIGS. 16 to 18 is an exemplification, and other circuit configurations having similar functions may be used.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the fourth embodiment will be described.
FIG. 19 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the fourth embodiment. In the voltage generation circuit 1 of FIG. 14 described above, the same current is used as the current I _{VBE and} different currents are used as the current I _PTAT in the correction circuits 20-1 and 20-2. However, in the voltage generation circuit 1 of FIG. 19, in the correction circuits 20-1 and 20-2, different currents are used as the current I _{VBE and the} same current is used as the current I _PTAT . Hereinafter, differences from the case of FIG. 14 will be mainly described.

The BGR core circuit 10 generates I _PTAT as a current corresponding to the difference voltage (ΔV _BE ) between the base-emitter voltages of two bipolar transistors having different emitter areas. Furthermore, to generate a current _{I VBE1, I VBE2} corresponding to the base-emitter voltage _{V BE} of the bipolar transistor. Then, the generated current is output to the correction circuit 20. Other functions and configurations of the BGR core circuit 10 are the same as those in FIG. The specific configuration of the BGR core circuit 10 is exemplified in the cases illustrated in FIGS. 16 to 18.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I PTAT} current _{I VBE1.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT} current _{I VBE2.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1 and 20-2, the case of FIG. 14 Conversely, unlike the constant current source _{I VBE1, I VBE2,} the constant current source _{I PTAT} is the same. Others are the same as in the case of FIG. As a result, the correction circuit 20-1, PMOS transistors MP31, a current mirror circuit composed of MP32, the difference current flowing into the connection node between the constant current source _{I VBE1} and the constant current source _{I PTAT (ΔI1 = I PTAT} -I _In response to VBE1), the correction current Icomp1 is output from the drain terminal of the PMOS transistor MP32. In this case, .DELTA.I1 ≧ 0, that is, when the _{I PTAT} ≧ _{I VBE1,} flows ΔI1 = Icomp1. On the other hand, in the correction circuit 20-2, PMOS transistors MP33, a current mirror circuit composed of MP34, the difference current flowing into the connection node between the constant current source _{I VBE2} and the constant current source _{I PTAT (ΔI2 = I PTAT -I} VBE2 ), The correction current Icomp2 is output from the drain terminal of the PMOS transistor MP34. In this case, if ΔI2 ≧ 0, that is, I _PTAT ≧ I _VBE2 , ΔI2 = Icomp2 flows.

  20A to 20C are graphs showing the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit in the case of FIG. In each graph, the vertical axis represents current or voltage, and the horizontal axis represents temperature. However, each figure is not necessarily a numerically accurate graph to show the concept.

As shown in FIG. 20A, the current _{I PTAT} and current _I VBE1 from BGR core circuit _{10, I VBE2} is supplied. The current I _PTAT is a current according to the difference voltage (ΔV _BE ) between the base-emitter voltages of two bipolar transistors having different emitter areas, and is proportional to the absolute temperature. The current _{I VBE1, I VBE2} is a current corresponding to the base-emitter voltage _{V BE} of the bipolar transistor is a non-linear.

Next, as shown in FIG. 20B, the correction circuit 20-1 based on the constant current _{I VBE1} and the constant current _{I PTAT,} generating their difference current (ΔI1 ₌ I _{PTAT -I VBE1)} as a correction current Icomp1 To do. In this case, .DELTA.I1 ≧ 0, that is, _{I PTAT} ≧ _{I VBE1,} at the threshold temperature above _{T 1,} ΔI1 = Icomp1 is generated. Similarly, the correction circuit 20-2 based on the constant current _{I VBE2} and the constant current _{I PTAT,} produces their difference current (ΔI2 ₌ I _{PTAT -I VBE2)} as a correction current Icomp2. In this case, [Delta] I2 ≧ 0, that is, _{I PTAT} ≧ _{I VBE2,} the threshold temperature _{T 2} above, ΔI2 = Icomp2 is generated. As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I VBE1} and the current _{I VBE2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

Next, as shown in FIG. 20C, BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C. That is, the reference voltage V _BGR before addition is the current corresponding to the difference voltage (ΔV _BE ) between the base-emitter voltages of the _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas and the base of the bipolar transistor Q ₄ . A current obtained by adding a current corresponding to the emitter-to-emitter voltage V _BE4 is converted into a voltage.

The graph of this final reference voltage V _BGR (FIG. 20C) has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ , and there are peak peaks at three locations across each valley. However, T ₁ <T ₂ . That is, as compared with the reference voltage _{V BGR} of FIG. 2B and FIG. 2C, in (the high temperature side from the apex of the particular original reference voltage _{V BGR} mountain) reference voltage _{V BGR} is relatively wide range of FIG. 15C, with respect to the temperature Voltage change can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Fifth embodiment)
A semiconductor device according to a fifth embodiment will be described. In the fifth embodiment, the correction circuit 20 generates the correction current Icomp based on a current corresponding to the voltage difference ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas and a predetermined constant current. A case where the high temperature side of the reference voltage V _BGR is corrected with the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, the present embodiment is different from the fourth embodiment in the type of current used to generate the correction current Icomp. Hereinafter, differences from the fourth embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on the high temperature side as shown in FIGS. 4A to 4E. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 21 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the fourth embodiment.
The BGR core circuit 10 generates a current corresponding to a difference voltage (ΔV _BE ) between the base-emitter voltages of _two bipolar transistors Q ₁ and Q _{2 having} different emitter areas and a base-emitter voltage V _BE4 of the bipolar transistor Q _4. The current generation unit 101 generates a current obtained by adding the corresponding current and the correction current Icomp generated by the correction circuit 20. Then, the generated current is converted into a reference voltage V _BGR by the voltage output unit 102 and output. Further, the BGR core circuit 10 generates I _PTAT as a current corresponding to the difference voltage (ΔV _BE ) between the base and emitter voltages of two bipolar transistors having different emitter areas. Then, the generated current is output to the correction circuit 20. The specific configuration of the BGR core circuit 10 is exemplified in the cases illustrated in FIGS. 16 to 18.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I PTAT} resistor _{R 31.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT} resistor _{R 32.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1 comprises, for example, a resistor _{R 31,} a constant current source _{I PTAT,} and a MOS transistor MP31 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Resistor _{R 31} is connected at one end to the power supply node Vcc, is connected at the other end to the constant current source _{I PTAT.} A current corresponding to the applied voltage is supplied. The constant current source I _PTAT has one end connected to the other end of the resistor R ₃₁ so that the constant current I _PTAT flows from the power node Vcc toward the ground node based on the current I _PTAT from the BGR core circuit 10. The other end is connected to the ground node. PMOS transistor MP31 is connected to power supply node Vcc to the source terminal, the gate terminal and the resistor _{R 31} is connected to a connection node between the constant current source _{I PTAT.} PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the resistor _{R 31} and the constant current source _{I PTAT1,} and outputs a correction current Icomp1 from the drain terminal. In this case, if I _PTAT · R ₃₁ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 flows.

Correction circuit 20-2 comprises, for example, a resistor _{R 32,} a constant current source _{I PTAT,} and a MOS transistor MP32 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. The resistor _R32 has one end connected to the power supply node Vcc and the other end connected to the constant current source _IPTAT . A current corresponding to the applied voltage is supplied. The constant current source I _PTAT has one end connected to the other end of the resistor R ₃₂ so that the constant current I _PTAT flows in the direction from the power supply node Vcc to the ground node based on the current I _PTAT from the BGR core circuit 10. The other end is connected to the ground node. PMOS transistor MP32 is connected to power supply node Vcc to the source terminal, the gate terminal and the resistor _{R 32} is connected to a connection node between the constant current source _{I PTAT.} PMOS transistor MP32 is controlled gate voltage at a voltage corresponding with the resistor _{R 32} to a constant current source _{I PTAT,} and outputs a correction current Icomp2 from the drain terminal. In this case, if I _PTAT · R ₃₂ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP32), Icomp2 flows.

In the correction circuit _20-1, the _{I PTAT} · _{R 31} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), the threshold temperature above _{T 1,} Icomp1 is generated. Similarly, in the correction circuit _20-2, the _{I PTAT} · _{R 32} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP32), the threshold temperature _{T 2} above, Icomp2 is generated. As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. This final correction current Icomp is the same as in FIGS. 15B and 20B. Here, in order to set the threshold temperature T ₁ and the threshold temperature T ₂ to different values, different R ₃₁ and R ₃₂ are used in the correction circuit 20-1 and the correction circuit 20-2.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

The graph of this final reference voltage V _BGR is the same as in the case of FIGS. 15C and 20C. That is, there are valleys at two locations near the temperatures T ₁ and T ₂ , and there are peaks with peaks at three locations across each valley. In other words, as compared to the reference voltage _{V BGR} of FIG. 2B and FIG. 2C, than apex the same manner as in the case the reference voltage _{V BGR} a relatively wide range (especially of the original reference voltage _{V BGR} mountain FIG. 15C and FIG. 20C On the high temperature side, the voltage change with respect to the temperature can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased. Further, the circuit configuration can be simplified as compared with the case of the fourth embodiment.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the fifth embodiment will be described.
FIG. 22 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the fifth embodiment. In the voltage generating circuit 1 of FIG. 21 described above, the correction circuit 20-1 and 20-2, with the same current as the current _{I PTAT,} use different resistor as the resistor _{R 3.} However, in the voltage generating circuit 1 in FIG. 22, the correction circuit 20-1 and 20-2, using different current as the current _{I PTAT,} using the same resistance as the resistor _{R 3.} Hereinafter, differences from the case of FIG. 21 will be mainly described.

The BGR core circuit 10 generates I _PTAT1 and I _PTAT2 as currents corresponding to the difference voltage (ΔV _BE ) between the base-emitter voltages of two bipolar transistors having different emitter areas. Then, the generated current is output to the correction circuit 20. Other functions and configurations of the BGR core circuit 10 are the same as those in FIG. The specific configuration of the BGR core circuit 10 is as described in FIGS. 16 to 18.

Correction circuit 20-1 generates a correction current Icomp1 based on the resistor R and current _{I PTAT1.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the resistor R and current _{I PTAT2.} Then, the correction current Icomp2 is fed back to the current generator 101.

In the correction circuits 20-1 and 20-2, contrary to the case of FIG. 21, the constant current sources I _PTAT1 and I _PTAT2 are different, and the resistance R ₃₁ is the same. Others are the same as those in FIG. As a result, the correction circuit 20-1, PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the resistor _{R 31} and the constant current source _{I PTAT1,} and outputs a correction current Icomp1 from the drain terminal. In this case, if I _PTAT1 · R ₃₁ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 flows. Further, in the correction circuit 20-2, PMOS transistors MP32, the resistance _{R 31} and is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT2,} and outputs a correction current Icomp2 from the drain terminal. In this case, if I _PTAT2 · R ₃₁ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP32), Icomp2 flows.

In the correction circuit _20-1, the _{I PTAT1} · _{R 31} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), the threshold temperature above _{T 1,} Icomp1 is generated. Similarly, in the correction circuit _20-2, the _{I PTAT2} · _{R 31} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP32) with a threshold temperature _{T 2} above comprising, Icomp2 is generated. As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. This final correction current Icomp is the same as in FIGS. 15B and 20B. Here, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, it is used and different _{I PTAT1} and _{I PTAT2} in the correction circuit 20-1 and the correction circuit 20-2.

BGR core circuit 10, as in the case of FIG. 21, by adding the current corresponding to the final correction current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} The graph of this final reference voltage V _BGR is the same as in the case of FIGS. 15C and 20C.

  In the present embodiment, the same effect as in the case of FIG. 21 can be obtained in the case of the voltage generation circuit 1 of FIG.

(Sixth embodiment)
A semiconductor device according to a sixth embodiment will be described. In the sixth embodiment, the correction circuit 20 corresponds to the current corresponding to the difference voltage ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas and the base-emitter voltage V _BE of the bipolar transistor. The case where the correction current Icomp is generated based on the current and the low temperature side of the reference voltage V _BGR is corrected with the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, this embodiment is different from the fourth embodiment in that the low temperature side is corrected. Hereinafter, differences from the fourth embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on the low temperature side as shown in FIGS. 5A to 5E. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 23 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the sixth embodiment.
The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I PTAT1} and the current _{I VBE.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT2} and the current _{I VBE.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1, for example, includes a constant current source _{I PTAT1,} a constant current source _{I VBE,} and a MOS transistor MP31, MP32 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source _IPTAT1 has one end connected to power supply node Vcc so that constant current _IPTAT1 flows from power supply node Vcc to the ground node based on current _IPTAT1 from BGR core circuit 10. Constant current source I _VBE has one end connected to the other end of constant current source I _PTAT1 so that constant current I _VBE flows from power supply node Vcc to the ground node based on current I _VBE from BGR core circuit 10. The other end is connected to the ground node. PMOS transistor MP31 is connected to power supply node Vcc to the source terminal is connected to a connection node between the gate terminal and the constant current source _{I PTAT1} a constant current source _{I VBE} to the drain terminal. The PMOS transistor MP32 has a source terminal connected to the power supply node Vcc and a gate terminal connected to the gate terminal of the PMOS transistor PM31. The PMOS transistors MP31 and MP32 constitute a current mirror circuit. Its current mirror circuit outputs a correction current Icomp1 from the drain terminal of the PMOS transistor MP32 in accordance with the difference current flowing into the connection node between the constant current source _{I PTAT1} and the constant current source _{I VBE (ΔI1 = I VBE -I} PTAT1) . In this case, if ΔI1 ≧ 0, that is, I _VBE ≧ _IPTAT1 , ΔI1 = Icomp1 flows.

Correction circuit 20-2, for example, includes a constant current source _{I PTAT2,} a constant current source _{I VBE,} and a MOS transistor MP33, MP34 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source _IPTAT2 has one end connected to power supply node Vcc so that constant current _IPTAT2 flows from power supply node Vcc to the ground node based on current _IPTAT2 from BGR core circuit 10. Constant current source I _VBE has one end connected to the other end of constant current source _IPTAT so that constant current I _VBE flows from power supply node Vcc to the ground node based on current I _VBE from BGR core circuit 10. The other end is connected to the ground node. PMOS transistor MP33 is connected to power supply node Vcc to the source terminal is connected to a connection node between the gate terminal and the constant current source _{I PTAT2} a constant current source _{I VBE} to the drain terminal. The PMOS transistor MP34 has a source terminal connected to the power supply node Vcc and a gate terminal connected to the gate terminal of the PMOS transistor PM33. The PMOS transistors MP33 and MP34 constitute a current mirror circuit. Its current mirror circuit outputs a correction current Icomp2 from the drain terminal of the PMOS transistor MP34 in accordance with the difference current flowing into the connection node between the constant current source _{I PTAT2} and the constant current source _{I VBE (ΔI2 = I VBE -I} PTAT2) . In this case, if ΔI2 ≧ 0, that is, I _VBE ≧ _IPTAT2 , ΔI2 = Icomp2 flows.

Next, the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit 1 in the case of FIG. 23 will be described. The relationship between the currents I _PTAT2 , I _PTAT2 and I _VBE input to the correction circuits 20-1 and 20-2 is as shown in FIG. 15A. Here, in the voltage generation circuit 1 in the case of FIG. 23, the positional relationship between the constant current source I _PTAT2 / I _PTAT1 and the constant current source I _VBE is reversed as compared with the voltage generation circuit 1 in the case of FIG. It has become. Therefore, as described above, in the correction circuit 20-1, .DELTA.I1 ≧ 0, that is, _{I VBE} ≧ _{I PTAT1,} it flows ΔI1 = Icomp1 at a lower temperature range than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases toward the low temperature side from the threshold temperature _{T 1.} Similarly, in the correction circuit 20-2, [Delta] I2 ≧ 0, that is, _{I VBE} ≧ _{I PTAT2,} flows ΔI2 = Icomp2 at a lower temperature range than the threshold temperature _{T 2.} Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I PTAT1} and the current _{I PTAT2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

The graph of this final reference voltage V _BGR has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ and peaks at three locations across each valley. However, T ₁ <T ₂ . That is, as compared with the reference voltage V _{BGR in} FIG. 2B or 2C, the reference voltage V _BGR is a relatively wide range (especially at a lower temperature than the peak of the original reference voltage V _BGR ). Can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the sixth embodiment will be described.
FIG. 24 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the sixth embodiment. In the voltage generation circuit 1 of FIG. 23 described above, the same current is used as the current I _{VBE and} different currents are used as the current I _PTAT in the correction circuits 20-1 and 20-2. However, in the voltage generation circuit 1 of FIG. 24, different currents are used as the current I _{VBE and the} same current is used as the current I _PTAT in the correction circuits 20-1 and 20-2. Hereinafter, differences from the case of FIG. 23 will be mainly described.

  The BGR core circuit 10 is the same as that in FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I PTAT} current _{I VBE1.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT} current _{I VBE2.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1 and 20-2, the case of FIG. 23 Conversely, unlike the constant current source _{I VBE1, I VBE2,} the constant current source _{I PTAT} is the same. Others are the same as in FIG. As a result, the correction circuit 20-1, PMOS transistors MP31, a current mirror circuit composed of MP32 a constant current source _{I PTAT} and differential current flowing to the connection node between the constant current source _{I VBE1 (ΔI1 = I VBE1} -I _In response to _PTAT ), the correction current Icomp1 is output from the drain terminal of the PMOS transistor MP32. In this case, .DELTA.I1 ≧ 0, that is, when the _{I VBE1} ≧ _{I PTAT,} flows ΔI1 = Icomp1. On the other hand, in the correction circuit 20-2, the current mirror circuit composed of the PMOS transistors MP33 and MP34 has a difference current (ΔI2 = I _VBE2 −I _PTAT) flowing in a connection node between the constant current source I _PTAT and the constant current source I _VBE2. ), The correction current Icomp2 is output from the drain terminal of the PMOS transistor MP34. In this case, if ΔI2 ≧ 0, that is, I _VBE2 ≧ I _PTAT , ΔI2 = Icomp2 flows.

Next, the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit 1 in the case of FIG. 24 will be described. Current _I PTAT is input to the correction circuit 20-1 and _20-2, the relationship of I _{VBE1, I VBE2} is shown in FIG. 20A. Here, the voltage generating circuit 1 in the case of FIG. 24 is different from the voltage generating circuit 1 in the case of FIG. 19, the positional relationship opposite to the constant-current source _{I PTAT} and a constant current source _I VBE1 _{/ I VBE2} It has become. Therefore, as described above, in the correction circuit 20-1, .DELTA.I1 ≧ 0, that is, _{I VBE1} ≧ _{I PTAT,} flows ΔI1 = Icomp1 at a lower temperature range than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases toward the low temperature side from the threshold temperature _{T 1.} Similarly, in the correction circuit 20-2, [Delta] I2 ≧ 0, that is, _{I VBE2} ≧ _{I PTAT,} flows ΔI2 = Icomp2 at a lower temperature range than the threshold temperature _{T 2.} Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I VBE1} and the current _{I VBE2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

  In the voltage generation circuit 1 of FIG. 24 in the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 23 can be obtained.

(Seventh embodiment)
A semiconductor device according to a seventh embodiment will be described. In the seventh embodiment, the correction circuit 20 generates the correction current Icomp based on the current and resistance corresponding to the voltage difference ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas. A case where the low temperature side of the reference voltage V _BGR is corrected with the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, this embodiment is different from the fifth embodiment in that the low temperature side is corrected. Hereinafter, differences from the fifth embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on the low temperature side as shown in FIGS. 5A to 5E. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 25 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the seventh embodiment.
The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the resistor R and the current _{I PTAT.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the resistor R and the current _{I PTAT.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1, for example, comprises a constant current source _{I PTAT,} a resistor _{R 31,} and a MOS transistor MP31 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source I _PTAT has one end connected to power supply node Vcc and the other end connected to supply a constant current I _PTAT from power node Vcc to the ground node based on current I _PTAT from BGR core circuit 10. It is connected to the resistor _{R 31.} The resistor R ₃₁ has one end connected to the other end of the constant current source I _{PTAT and} the other end connected to the ground node. A current corresponding to the applied voltage is supplied. PMOS transistor MP31 is connected to power supply node Vcc to the source terminal, a gate terminal connected to a connection node between the constant current source _{I PTAT} and a resistor _{R 31.} PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT1} a resistor _{R 31,} and outputs a correction current Icomp1 from the drain terminal. In this case, if (absolute value of threshold voltage of PMOS transistor MP31) ≧ Vcc−I _PTAT · R ₃₁ , Icomp1 flows.

Correction circuit 20-2, for example, comprises a constant current source _{I PTAT,} a resistor _{R 32,} and a MOS transistor MP32 of P-channel type. Here, the P-channel MOS transistor MP6 shown in FIG. 7 is omitted. Constant current source I _PTAT has one end connected to power supply node Vcc and the other end connected to supply a constant current I _PTAT from power supply node Vcc to the ground node based on current I _PTAT from BGR core circuit 10. The resistor R ₃₂ is connected to one end. The resistor R ₃₂ has one end connected to the constant current source I _PTAT and the other end connected to the ground node. A current corresponding to the applied voltage is supplied. PMOS transistor MP32 is connected to power supply node Vcc to the source terminal, a gate terminal connected to a connection node between the constant current source _{I PTAT} and a resistor _{R 32.} PMOS transistor MP32 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT} resistor _{R 32,} and outputs a correction current Icomp2 from the drain terminal. In this case, if (absolute value of threshold voltage of PMOS transistor MP32) ≧ Vcc−I _PTAT · R ₃₂ , Icomp2 flows.

In the correction circuit 20-1, a _{≧ Vcc-I PTAT · R 31} ( absolute value of the threshold voltage of the PMOS transistor MP31), the threshold temperature _{T 1} of less, Icomp1 is generated. Then, Icomp1 monotonically increases toward the low temperature side from the threshold temperature _{T 1.} Similarly, in the correction circuit 20-2, the (PMOS transistor absolute value of the threshold voltage of _{MP32) ≧ Vcc-I PTAT ·} R 32, at the threshold temperature _{T 2} less, Icomp2 is generated. Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. In this way, in order to set the threshold temperature T ₁ and the threshold temperature T ₂ to different values, here, the resistors R ₃₁ and R ₃₂ that are different in the correction circuit 20-1 and the correction circuit 20-2 are used. Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before being adding the correction current Icomp is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

The graph of this final reference voltage V _BGR has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ and peaks at three locations across each valley. However, T ₁ <T ₂ . That is, as compared with the reference voltage V _{BGR in} FIG. 2B or 2C, the reference voltage V _BGR is a relatively wide range (especially at a lower temperature than the peak of the original reference voltage V _BGR ). Can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the seventh embodiment will be described.
FIG. 26 is a circuit diagram showing a modification of the specific circuit configuration of the voltage generation circuit 1 according to the seventh embodiment. In the voltage generating circuit 1 of the aforementioned FIG. 25, the correction circuit 20-1 and 20-2, with the same current as the current _{I PTAT,} they use different resistor as the resistor _{R 3.} However, in the voltage generating circuit 1 in FIG. 26, the correction circuit 20-1 and 20-2, using different current as the current _{I PTAT,} using the same resistance as the resistor _{R 3.} Hereinafter, differences from the case of FIG. 24 will be mainly described.

  The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

The correction circuit 20-1 generates a correction current Icomp1 based on the resistor R and the current _IPTAT1 . Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the resistor R and the current _IPTAT2 . Then, the correction current Icomp2 is fed back to the current generator 101.

In the correction circuits 20-1 and 20-2, contrary to the case of FIG. 25, the constant current sources I _PTAT1 and I _PTAT2 are different and the resistance R ₃₁ is the same. Others are the same as those in FIG. As a result, the correction circuit 20-1, PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT1} a resistor _{R 31,} and outputs a correction current Icomp1 from the drain terminal. In this case, (the absolute value of the threshold voltage of the PMOS transistor MP31) For _{≧ Vcc-I PTAT1 · R 31} , flows Icomp1. Further, in the correction circuit 20-2, PMOS transistor MP32 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT2} a resistor _{R 31,} and outputs a correction current Icomp2 from the drain terminal. In this case, (the absolute value of the threshold voltage of the PMOS transistor MP32) For _{≧ Vcc-I PTAT2 · R 31} , flows Icomp2.

In the correction circuit 20-1, the (threshold absolute value of the voltage of the PMOS transistor _{MP31) ≧ Vcc-I PTAT1 ·} R 31, at threshold temperatures _{T 1} or less, Icomp1 is generated. Then, Icomp1 monotonically increases toward the low temperature side from the threshold temperature _{T 1.} Similarly, in the correction circuit 20-2, the (absolute value of the threshold voltage of the PMOS transistor _{MP32) ≧ Vcc-I PTAT2 ·} R 31, at the threshold temperature _{T 2} less, Icomp2 is generated. Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 and Icomp2. Thus, in order to set the threshold temperature T ₁ and the threshold temperature T ₂ to different values, the constant current source I _PTAT1 and the constant current source I _PTAT2 that are different in the correction circuit 20-1 and the correction circuit 20-2 are used _here. And are used.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

  In the present embodiment, the voltage generating circuit 1 of FIG. 26 can obtain the same effect as that of the voltage generating circuit of FIG.

(Eighth embodiment)
A semiconductor device according to the eighth embodiment will be described. In the eighth embodiment, the correction circuit 20 corresponds to the current corresponding to the difference voltage ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas and the base-emitter voltage V _BE of the bipolar transistor. A case where the correction current Icomp is generated based on the current and the high temperature side and the low temperature side of the reference voltage V _BGR are corrected by the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, this embodiment is different from the fourth embodiment and the sixth embodiment in that correction is performed on both the high temperature side and the low temperature side. Hereinafter, differences from the fourth embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on both the high temperature side and the low temperature side as shown in FIGS. 6A to 6D. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 27 is a circuit diagram showing an example of a specific circuit configuration of the voltage generation circuit 1 according to the eighth embodiment.
The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I VBE} and the current _{I PTAT1.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT2} and the current _{I VBE.} Then, the correction current Icomp2 is fed back to the current generator 101.

The correction circuit 20-1 is the same as that in FIG. A current mirror circuit composed of PMOS transistors MP31, MP32, the drain of the PMOS transistor MP32 in accordance with the difference current flowing into the connection node between the constant current source _{I VBE} and the constant current source _{I PTAT1 (ΔI1 = I PTAT1 -I} VBE) The correction current Icomp1 is output from the terminal. In this case, if ΔI1 ≧ 0, that is, I _PTAT1 ≧ I _VBE , ΔI1 = Icomp1 flows. On the other hand, the correction circuit 20-2 is the same as that in FIG. A current mirror circuit composed of PMOS transistors MP33, MP34, the drain of the PMOS transistor MP34 in accordance with the difference current flowing into the connection node between the constant current source _{I PTAT2} and the constant current source _{I VBE (ΔI2 = I VBE -I} PTAT2) The correction current Icomp2 is output from the terminal. In this case, if ΔI2 ≧ 0, that is, I _VBE ≧ _IPTAT2 , ΔI2 = Icomp2 flows.

Next, the principle of the nonlinear temperature characteristic correction method in the voltage generation circuit 1 in the case of FIG. 27 will be described. The relationship between the currents I _PTAT1 , I _PTAT2 and I _VBE input to the correction circuits 20-1 and 20-2 is as shown in FIG. 15A. However, for convenience of explanation, a current _{I PTAT2} and threshold temperature _{T 2} shown in FIG. 15A, the current _{I PTAT1} and threshold temperatures _{T 1} in the case of FIG. 27, the current _{I PTAT1} and threshold temperatures _{T 1} shown in FIG. 15A, the current _{I PTAT2} and threshold temperature _{T 2} in the case of FIG. 27 (subscript shall replace the "1" and "2" of the character).

Here, in FIG. 27, the correction circuit 20-1 in _{I PTAT1 ≧ I VBE, ΔI1 =} Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases from the threshold temperature _{T 1} of toward the high temperature side. On the other hand, in FIG. 27, the correction circuit 20-2 in _{I VBE} ≧ _{I PTAT2,} flows ΔI2 = Icomp2 at a lower temperature range than the threshold temperature _{T 2.} Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 on the high temperature side and Icomp2 on the low temperature side. That, Icomp2 flows through a temperature range lower than the threshold temperature _{T 2,} the correction current does not flow in the temperature range of the threshold temperature _T 2 ~T _1, Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I PTAT1} and the current _{I PTAT2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before being added to the correction current Icomp is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

The graph of this final reference voltage V _BGR has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ and peaks at three locations across each valley. However, T ₂ <T ₁ . That is, compared with the reference voltage V _{BGR of} FIG. 2B and FIG. 2C, the reference voltage V _BGR has a relatively wide range (especially on the high temperature side and the low temperature side of the peak of the original reference voltage V _BGR ). The voltage change with respect to can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the eighth embodiment will be described.
FIG. 28 is a circuit diagram showing another example of the specific circuit configuration of the voltage generation circuit 1 according to the eighth embodiment. In the voltage generation circuit 1 of FIG. 27 described above, the same current is used as the current I _{VBE and} different currents are used as the current I _PTAT in the correction circuits 20-1 and 20-2. However, in the voltage generation circuit 1 of FIG. 28, different currents are used as the current I _{VBE and the} same current is used as the current I _PTAT in the correction circuits 20-1 and 20-2. Hereinafter, differences from the case of FIG. 27 will be mainly described.

  The BGR core circuit 10 is the same as that in FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the current _{I VBE1} and the current _{I PTAT.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the current _{I PTAT} current _{I VBE2.} Then, the correction current Icomp2 is fed back to the current generator 101.

Correction circuit 20-1 and 20-2, the case of FIG. 27 Conversely, unlike the constant current source _{I VBE1, I VBE2,} the constant current source _{I PTAT} is the same. Others are the same as those in FIG. That is, the correction circuits 20-1 and 20-2 are the same as those in FIGS. 19 and 24, respectively. As a result, the correction circuit 20-1, PMOS transistors MP31, a current mirror circuit composed of MP32, the difference current flowing into the connection node between the constant current source _{I VBE1} and the constant current source _{I PTAT (ΔI1 = I PTAT} -I _In response to VBE1), the correction current Icomp1 is output from the drain terminal of the PMOS transistor MP32. In this case, .DELTA.I1 ≧ 0, that is, when the _{I PTAT} ≧ _{I VBE1,} flows ΔI1 = Icomp1. On the other hand, in the correction circuit 20-2, the current mirror circuit composed of the PMOS transistors MP33 and MP34 has a difference current (ΔI2 = I _VBE2 −I _PTAT) flowing in a connection node between the constant current source I _PTAT and the constant current source I _VBE2. ), The correction current Icomp2 is output from the drain terminal of the PMOS transistor MP34. In this case, if ΔI2 ≧ 0, that is, I _VBE2 ≧ I _PTAT , ΔI2 = Icomp2 flows.

Next, the principle of the nonlinear temperature characteristic correction method in the voltage generation circuit 1 in the case of FIG. 28 will be described. Current _I PTAT is input to the correction circuit 20-1 and _20-2, the relationship of I _{VBE1, I VBE2} is shown in FIG. 20A. However, for convenience of explanation, a current _{I VBE2} and threshold temperature _{T 2} shown in FIG. 20A, the current _{I VBE1} and threshold temperatures _{T 1} in the case of FIG. 28, the current _{I VBE1} and threshold temperatures _{T 1} shown in FIG. 20A, 28, the current I _VBE2 and the threshold temperature T _{2 are} assumed (subscripts “1” and “2” are interchanged).

Here, in FIG. 28, the correction circuit 20-1 in _{I PTAT ≧ I VBE1, ΔI1 =} Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases from the threshold temperature _{T 1} of toward the high temperature side. On the other hand, in FIG. 28, the correction circuit in 20-2 _{I VBE2} ≧ _{I PTAT,} flows ΔI2 = Icomp2 at a lower temperature range than the threshold temperature _{T 2.} Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 on the high temperature side and Icomp2 on the low temperature side. That, Icomp2 flows through a temperature range lower than the threshold temperature _{T 2,} the correction current does not flow in the temperature range of the threshold temperature _T 2 ~T _1, Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} Thus, in order to make the threshold temperature _{T 1} of the threshold temperature _{T 2} to different values, here, by using the different currents _{I VBE1} and the current _{I VBE2} in the correction circuit 20-1 and the correction circuit 20-2 Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

  In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 27 can be obtained with the voltage generation circuit 1 of FIG.

(Ninth embodiment)
A semiconductor device according to a ninth embodiment will be described. In the ninth embodiment, the correction circuit 20 generates the correction current Icomp based on the current and resistance corresponding to the voltage difference ΔV _BE between the base-emitter voltages of two bipolar transistors having different emitter areas. A case where the high temperature side and the low temperature side of the reference voltage V _BGR are corrected with the correction current Icomp will be described. In the present embodiment, there are a plurality of correction circuits 20. In other words, this embodiment is different from the eighth embodiment in the type of current for generating the correction current Icomp. In the following, differences from the eighth embodiment will be mainly described.

  The voltage generation circuit according to the present embodiment is a voltage generation circuit as shown in FIG. 3, and performs correction on both the high temperature side and the low temperature side as shown in FIGS. 6A to 6D. Needless to say, the present invention can be applied to the case where there is only one correction circuit 20 as long as no technical contradiction occurs.

FIG. 29 is a circuit diagram showing another example of the specific circuit configuration of the voltage generation circuit 1.
The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

Correction circuit 20-1 generates a correction current Icomp1 based on the resistor R and the current _{I PTAT.} Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the resistor R and the current _{I PTAT.} Then, the correction current Icomp2 is fed back to the current generator 101.

The correction circuit 20-1 is the same as that in FIG. PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT} resistor _{R 31,} and outputs a correction current Icomp1 from the drain terminal. In this case, if I _PTAT · R ₃₁ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 flows. On the other hand, the correction circuit 20-2 is the same as that in FIG. PMOS transistor MP32 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT} resistor _{R 32,} and outputs a correction current Icomp2 from the drain terminal. In this case, if (absolute value of threshold voltage of PMOS transistor MP32) ≧ Vcc−I _PTAT · R ₃₂ , Icomp2 flows.

Next, the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit 1 in the case of FIG. 29 will be described. 29, the correction circuit _20-1, the _{I PTAT} · _{R 31} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 is produced in a temperature range higher than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases from the threshold temperature _{T 1} of toward the high temperature side. On the other hand, in FIG. 29, the correction circuit 20-2, the (absolute value of the threshold voltage of the PMOS transistor _{MP32) ≧ Vcc-I PTAT ·} R 32, Icomp2 is produced in a temperature range lower than the threshold temperature _{T 2} . Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 on the high temperature side and Icomp2 on the low temperature side. That, Icomp2 flows through a temperature range lower than the threshold temperature _{T 2,} the correction current does not flow in the temperature range of the threshold temperature _T 2 ~T _1, Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} In this way, in order to set the threshold temperature T ₁ and the threshold temperature T ₂ to different values, here, the resistors R ₃₁ and R ₃₂ that are different in the correction circuit 20-1 and the correction circuit 20-2 are used. Yes.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

The graph of this final reference voltage V _BGR has a shape in which there are valleys at two locations near the temperatures T ₁ and T ₂ and peaks at three locations across each valley. However, T ₂ <T ₁ . That is, compared with the reference voltage V _{BGR of} FIG. 2B and FIG. 2C, the reference voltage V _BGR has a relatively wide range (especially on the high temperature side and the low temperature side of the peak of the original reference voltage V _BGR ). The voltage change with respect to can be reduced. That is, the accuracy of the reference voltage V _BGR can be further increased.

(Modification)
Next, a modification of the specific circuit configuration of the voltage generation circuit according to the ninth embodiment will be described.
FIG. 30 is a circuit diagram showing another example of the specific circuit configuration of the voltage generation circuit 1 according to the ninth embodiment. In the voltage generating circuit 1 of FIG. 29 described above, the correction circuit 20-1 and 20-2, with the same current as the current _{I PTAT,} use different resistor as the resistor _{R 3.} However, in the voltage generating circuit 1 in FIG. 30, the correction circuit 20-1 and 20-2, using different current as the current _{I PTAT,} using the same resistance as the resistor _{R 3.} Hereinafter, differences from the case of FIG. 29 will be mainly described.

  The BGR core circuit 10 is the same as in the case of FIG. For the BGR core circuit 10, for example, the circuits of FIGS. 16 to 18 can be used.

The correction circuit 20-1 generates a correction current Icomp1 based on the resistor R and the current _IPTAT1 . Then, the correction current Icomp1 is fed back to the current generator 101. Similarly, the correction circuit 20-2 generates a correction current Icomp2 based on the resistor R and current _{I PTAT2.} Then, the correction current Icomp2 is fed back to the current generator 101.

In the correction circuits 20-1 and 20-2, contrary to the case of FIG. 29, the constant current sources I _PTAT1 and I _PTAT2 are different, and the resistance R ₃₁ is the same. Others are the same as those in FIG. That is, the correction circuits 20-1 and 20-2 are the same as those in FIGS. As a result, the correction circuit 20-1, PMOS transistor MP31 is controlled gate voltage at a voltage corresponding to the resistor _{R 31} and the constant current source _{I PTAT1,} and outputs a correction current Icomp1 from the drain terminal. In this case, if I _PTAT1 · R ₃₁ ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 flows. On the other hand, in the correction circuit 20-2, PMOS transistor MP32 is controlled gate voltage at a voltage corresponding to the constant current source _{I PTAT2} a resistor _{R 31,} and outputs a correction current Icomp2 from the drain terminal. In this case, (the absolute value of the threshold voltage of the PMOS transistor MP32) For _{≧ Vcc-I PTAT2 · R 31} , flows Icomp2.

Next, the principle of the method for correcting the nonlinear temperature characteristic in the voltage generation circuit 1 in the case of FIG. In Figure 30, the correction circuit _20-1, the _{I PTAT1} · _{R 31} ≧ (the absolute value of the threshold voltage of the PMOS transistor MP31), Icomp1 is produced in a temperature range higher than the threshold temperature _{T 1.} Then, Icomp1 monotonically increases from the threshold temperature _{T 1} of toward the high temperature side. On the other hand, in the correction circuit 20-2, the (absolute value of the threshold voltage of the PMOS transistor _{MP32) ≧ Vcc-I PTAT2 ·} R 31, Icomp2 is generated at a lower temperature range than the threshold temperature _{T 2.} Then, Icomp2 monotonically increases toward the low temperature side from the threshold temperature _{T 2.} As a result, the final correction current Icomp is the sum of Icomp1 on the high temperature side and Icomp2 on the low temperature side. That, Icomp2 flows through a temperature range lower than the threshold temperature _{T 2,} the correction current does not flow in the temperature range of the threshold temperature _T 2 ~T _1, Icomp1 flows at a temperature range higher than the threshold temperature _{T 1.} Thus, in order to set the threshold temperature T ₁ and the threshold temperature T ₂ to different values, the constant current source I _PTAT1 and the constant current source I _PTAT2 that are different in the correction circuit 20-1 and the correction circuit 20-2 are used _here. And are used.

BGR core circuit 10 adds a current corresponding to the final compensation current Icomp and the reference voltage _{V BGR,} to produce a final reference voltage _{V BGR.} However, the reference voltage _{V BGR} before correction current Icomp is added is the reference voltage _{V BGR} in the state of FIG. 2B and FIG. 2C.

  In the present embodiment, the same effect as that of the voltage generation circuit 1 of FIG. 29 can be obtained with the voltage generation circuit 1 of FIG.

(I _PTAT generation circuit)
In each of the above embodiments, the first current generation unit 103 of the BGR core circuit 10 illustrated in FIG. 16 is illustrated as a circuit that generates the current _IPTAT applied to each current generation circuit 1. However, the circuit for generating the current _IPTAT is not limited to that example. As another example, the following BGR core circuit 10 can be considered. FIG. 31 is a circuit diagram showing another example of a specific circuit configuration of the BGR core circuit 10. The BGR core circuit 10 includes a current generation unit 101, an output unit 102, and a first current generation unit 103.

The current generation unit 101 and the output unit 102 omit the description of the output voltage V _BGRC and the feedback correction current Icomp. However, the current generation unit 101 and the output unit 102 are the same as those in FIG.

The first current generator 103 includes, for example, a bipolar transistor _{Q 3} of the NPN type, a resistor Rx, and a MOS transistor MP7, MP8 of P-channel type. Bipolar transistor Q ₃ are connected to the emitter terminal to a ground node, the base terminal is connected to the collector terminal of the bipolar transistor Q _1. Emitter area of the bipolar transistor Q ₃ are the same as the bipolar transistor Q _1. Resistor Rx is connected at one end to the collector terminal of the bipolar transistor Q _3. The PMOS transistor MP8 has a source terminal connected to the power supply node, and a gate terminal and a drain terminal connected to the other end of the resistor Rx. The PMOS transistor MP7 has a source terminal connected to the power supply node and a gate terminal connected to the gate terminal of the PMOS transistor MP7. The PMOS transistors MP7 and MP8 constitute a current mirror circuit.

In this case, PMOS transistor MP8, in the path of the resistor Rx and the bipolar transistors Q3, current _I 1 _{(I PTAT)} current _{I PTAT} corresponding to flow through the path of the resistor _{R 1} and the bipolar transistor _{Q 1.} As a result, a current _IPTAT is generated in the PMOS transistor MP7 that forms a current mirror circuit together with the PMOS transistor MP8, and is output from the drain terminal.

(BGR core circuit)
In each of the above embodiments, the BGR core circuit 10 (particularly, the current generation unit 101 and the output unit 102) applied to the voltage generation circuit 1 is not limited to the above examples. As another example, the following BGR core circuit 10 can be considered.

(A-1) BGR core circuit (1)
FIG. 32 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit 10. In the figure, the same components as those in the BGR core circuit 10 in FIG.

BGR core circuit 10 shown in the figure, that no resistor _{R 5,} and the correction current Icomp is different from that BGR core circuit 10 of FIG. 7 in that the feedback to the resistor _{R 3.} Below, a difference is mainly demonstrated. The output voltage V _BGRC , resistors R ₇ , R ₈ , Rz, and capacitor Cc are not shown, but they are the same as in FIG.

In BGR core circuit 10, a feedback target correction current Icomp is a resistor _{R 3.} Is not particularly limited, in the example of this figure, a resistor R ₃ divided into a resistor R ₃₁ and resistor R _32, a configuration for feeding back to a connection node between the resistor R ₃₁ and the resistor R _32.

In this case, the output voltage V _BGR by the BGR core circuit 10 is expressed by the following equation (22).

In the above equation (22), the first term is the term of the base-emitter voltage V _BE , and the second term is the term of the difference voltage V _PTAT between the base-emitter voltages of two bipolar transistors having different emitter areas. Yes, the third term is the term of the correction current Icomp.

(A-2) BGR core circuit (2)
FIG. 33 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit 10. In the figure, the same components as those in the BGR core circuit 10 in FIG.

BGR core circuit 10 shown in the figure, that no resistor _{R 5,} and the correction current Icomp resistor _{R 2} and in that feedback to between the collector terminal of the bipolar transistor Q2 of FIG. 7 BGR core circuit 10 Is different. Below, a difference is mainly demonstrated. The output voltage V _BGRC , resistors R ₇ , R ₈ , Rz, and capacitor Cc are not shown, but they are the same as in FIG.

In BGR core circuit 10, a feedback target correction current Icomp is a connection node between the collector terminal of the resistor _{R 2} and a bipolar transistor _{Q 2.}

   The output voltage VBGR of the reference voltage generation circuit 4 is as follows. Although not particularly limited, for simplicity, the mirror ratio of the correction current ICOMP is 1: 1.

In this case, the output voltage V _BGR by the BGR core circuit 10 is expressed by the following equation (23).

In the above equation (23), the first term is the term of the base-emitter voltage V _BE , and the second term is the term of the difference voltage V _PTAT between the base-emitter voltages of two bipolar transistors having different emitter areas. Yes, the third term is the term of the correction current Icomp.

(A-3) BGR core circuit (3)
FIG. 34 is a circuit diagram showing another example of the specific circuit configuration of the BGR core circuit 10. In the figure, the same components as those in the BGR core circuit 10 in FIG.

BGR core circuit 10 shown in the figure, that no resistor _{R 5,} and the correction current Icomp is different from that BGR core circuit 10 of FIG. 7 in that the feedback to the resistor _{R 4.} Below, a difference is mainly demonstrated. The output voltage V _BGRC , resistors R ₇ , R ₈ , Rz, and capacitor Cc are not shown, but they are the same as in FIG.

In BGR core circuit 10, a feedback target correction current Icomp is a resistor _{R 4.} It is not particularly limited, in the example of this figure, a resistor R ₄ is divided into a resistor R ₄₁ and resistor R _42, a configuration for feeding back to a connection node between the resistor R ₄₁ and the resistor R _42.

In this case, the output voltage V _BGR by the BGR core circuit 10 is expressed by the following equation (24).

In the above equation (24), the first term is the term of the base-emitter voltage V _BE , and the second term is the term of the difference voltage V _PTAT between the base-emitter voltages of two bipolar transistors having different emitter areas. Yes, the third term is the term of the correction current Icomp.

(Differential amplifier)
In the above embodiments, a specific example of the differential amplifier A ₁ in BGR core circuit 10 applied to the voltage generating circuit 1.

(B-1) Differential amplifier A ₁ (Part 1)
FIG. 35A is a circuit diagram illustrating an example of the differential amplifier A ₁ in the voltage generation circuit 1.
Figure 35A is an example of the differential amplifier _{A 1} to the input stage of N-channel type MOS transistor. This amplifier includes a first stage 31 and an output stage 32. The first stage unit 31 includes N-channel MOS transistors M1 and M2, a current source i1, and P-channel MOS transistors M4 and M5. The NMOS transistors M1 and M2 constitute a differential input stage. Current source i1 is provided between the source terminal and the ground node. The PMOS transistors M4 and M5 are provided between the drain terminals of the NMOS transistors M1 and M2 and the power supply voltage Vcc, and constitute an active load by a current mirror circuit. The output stage unit 32 is an inverting amplifier circuit having a P-channel MOS transistor M3. In the PMOS transistor M3, the output signal of the first stage unit 31 is input to the gate terminal, and the source is connected to the node of the power supply voltage Vcc. The inverting amplifier circuit uses a current source i3 provided between the drain terminal and the ground node as a load. A capacitor Cf and a resistor Rf as a phase compensation circuit are provided between the gate terminal and the drain terminal of the PMOS transistor M3.

(B-2) Amplifier A ₁ (Part 2)
FIG. 35B is a circuit diagram illustrating an example of the differential amplifier A ₁ in the voltage generation circuit 1.
Figure 35B is another example of a differential amplifier A ₁ to the input stage of N-channel type MOS transistor. The amplifier includes a first stage unit 31, an output stage unit 32, and a current source unit 33. When the reference voltage generating circuit 1 is configured, it is necessary to reduce the power consumption. However, as an adverse effect, the gain of the amplifier becomes higher than necessary, and phase compensation may be difficult. The amplifier shown in the figure has a circuit configuration for the purpose of reducing power consumption, a first-stage amplifier unit for differential input using an N-channel MOS transistor, and a source-grounded inverting amplifier circuit including a P-channel MOS transistor. The output stage is composed of an output stage and a current source for driving them. The current source unit converts the voltage difference between the gate-source voltages of the N-channel MOS transistors M12 and M13 with a resistor Rref in order to stably supply a minute current, and generates a converted current Iref. The current Iref determines the bias currents i1 and i3 of the first stage and the output stage as a current mirror form by the MOS transistors M14 and M15. When the current value of the current i1 is set to be small, in order to prevent the gain of the first-stage amplifier from becoming high and making phase compensation difficult, each of the MOS transistors M4 and M5 constituting the current mirror that becomes a factor for determining the gain is used. The current sources M6 and M7 for supplying a constant current i2 are connected in parallel. The constant current Iref flows through the MOS transistors M13 and M11 and the diode-connected M9, and the MOS transistors M6 to M9 are formed in a current mirror form, whereby the constant current i2 can be formed. This facilitates phase compensation. That is, in addition to the conventionally used mirror compensation, it is possible to perform pole-zero compensation (a series connection of Rf and Cf connected to the output stage) that is easy to design.

(Other configuration of voltage generation circuit 1)
In each of the above-described embodiments, a circuit configuration excluding the startup circuit (startup circuit) is shown in order to facilitate understanding of the operation principle of the voltage generation circuit 1. However, the voltage generation circuit 1 may further include a startup circuit.

FIG. 36 is a circuit diagram showing an example of the voltage generation circuit 1 having a startup circuit.
The voltage generation circuit 1 includes a reference voltage generation circuit (BGR core circuit) 10, a correction circuit 20, and a startup circuit 30. The voltage generation circuit 1 may become stable when the output voltage V _BGR is 0 V at the start-up such as when the power supply voltage is turned on. As a countermeasure against this, a startup circuit 30 is provided in the voltage generation circuit 1 to start up by forcibly flowing a current.

The start-up circuit 30 includes, for example, a PMOS transistor MP7 and NMOS transistors MN1 and MN2. The PMOS transistor MP7 has a source terminal connected to the power supply node Vcc. The NMOS transistor MN1 has a source terminal connected to the ground node, a drain terminal connected to the drain terminal of the PMOS transistor MP7, and a gate terminal connected to the drain terminal (V _BGR output terminal) of the PMOS transistor MP2. The NMOS transistor MN2 has a source terminal connected to the ground node, a drain terminal connected to the gate terminal of the PMOS transistor MP2, and a gate terminal connected to the drain terminal of the NMOS transistor MN1.

Hereinafter, the operation of the startup circuit 30 will be described. For example, when the gate potential V1 of the PMOS transistor MP1 is Vcc, the PMOS transistor MP1 is off and no current flows. At this time, since the PMOS transistor MP2 is also turned off, the output voltage V _BGR becomes the ground potential, and the NMOS transistor MN1 is turned off. Potential V4 of the node where the drain terminal is connected to the NMOS transistor MN1, when the threshold voltage of the PMOS transistor MP7 and _{V THP,} Vcc- _{| V THP |} next, NMOS transistor MN2 is turned on. As a result, the gate potential V1 of the PMOS transistor MP1 drops from Vcc, and the BGR core circuit 10 can operate with a normal bias.

The startup circuit 30 makes it possible to generate the output voltage V _BGR without error when the power is turned on or when the sleep is released. Further, even if there is a disturbance or the like during normal operation, the output voltage V _BGR is stably generated by recovering immediately. Furthermore, according to the circuit configuration of the start-up circuit 30, by appropriately selecting the transistor sizes of the PMOS transistor MP7 and the NMOS transistors MN1 and MN2, the gate potential V4 of the NMOS transistor MN2 is made lower than the threshold voltage V _THN of the NMOS transistor MN2. It can be. Thereby, the current of the NMOS transistor MN2 can be ignored and the operation of the BGR core circuit 10 can be prevented from being affected. The startup circuit 30 is an example, and the voltage generation circuit 1 may be provided with a startup circuit having another circuit configuration.

(Other configuration 2 of the voltage generation circuit)
FIG. 37 is a block diagram showing an example of a circuit configuration including the voltage generation circuit 1 in which a low pass filter (LPF) is inserted in the power supply Vcc line.

  The BGR core circuit 10 and the correction circuit 20 according to the above embodiments have a small circuit scale and power consumption. Therefore, as shown in the figure, a low-pass filter 60 is inserted in the power supply Vcc line, and the output voltage Vcc_LPF of the low-pass filter 60 is supplied to the BGR core circuit 10, the correction circuit 20, the regulator circuit (reference current source) 70, and the like. It can be. Thereby, PSRR (power supply rejection ratio) can be reduced and the tolerance with respect to a power supply voltage fluctuation | variation can be improved. The low-pass filter 60 is realized by, for example, a resistance element and a capacitance element, but may have other circuit configurations as long as low-pass transmission characteristics are obtained.

(System using voltage generation circuit)
Next, a system to which the voltage generation circuit 1 of each of the above embodiments is applied will be described.

(C-1) AD Converter FIG. 38A shows an example in which the voltage generation circuit 1 is applied to the AD converter 51. AD converter 51 based on the voltage generated on the basis of the V _BGR voltage and V _BGR voltage generated by the voltage generating circuit 1, converts the analog input signal into a digital signal.

(C-2) DA Converter FIG. 38B shows an example in which the voltage generation circuit 1 is applied to the DA converter 52. DA converter 52 based on the voltage generated on the basis of the V _BGR voltage and V _BGR voltage generated by the voltage generating circuit 1, converts the digital input signal into an analog signal.

(C-3) Reference Current Source FIG. 38C shows an example in which the voltage generation circuit 1 is applied to the reference current source 53. Reference current source 53 is based on a voltage generated based on the generated V _BGR voltage and V _BGR voltage by the voltage generating circuit 1 generates and outputs a reference current I _REF.

(C-4) Temperature Sensor FIG. 38D shows an example in which the voltage generation circuit 1 (V _PTAT can be output) is applied to the temperature sensor 54. The temperature sensor 54 measures the temperature based on the V _PTAT voltage proportional to the temperature and the V _BGR voltage having low temperature dependence, and outputs the measurement result.

(C-5) Semiconductor integrated circuit device (1)
FIG. 39 is a block diagram showing an example of a semiconductor integrated circuit device to which the voltage generation circuit 1 is applied. Although not particularly limited, the semiconductor integrated circuit device 100 is, for example, a system LSI having a built-in power supply circuit.

The semiconductor integrated circuit device 100 includes, for example, a power supply circuit 50, a CPU (central processing unit) 45, a register 46, a nonvolatile memory element 47, other peripheral circuits 48, and an input / output circuit 49. The power supply circuit 50 includes, for example, a power supply control unit 41, a voltage generation circuit 1, a reference voltage buffer circuit 42, a main regulator 43 as a main power supply, and a sub-regulator 44 as a standby power supply. These circuits operate by receiving the power supply voltage _VCC supplied from the external terminal. The power supply control unit 41 outputs control signals cnt1, cnt2, and cnt3 through the input / output circuit 49 or based on a control signal input from the CPU 45. The voltage generation circuit 1 outputs a reference voltage V _BGR based on the control signal cnt1. The reference voltage buffer circuit 42 outputs the reference voltage Vbuf based on the reference voltage V _BGR . One of the main regulator 43 and the sub-regulator 44 outputs the internal voltage Vint based on the control signals cnt2 and cnt3 and the reference voltage Vbuf. The CPU 45, the register 46, the nonvolatile memory element 47, and the other peripheral circuits 48 constituting the system LSI operate by being supplied with the internal voltage Vint as an operating voltage.

For example, when the semiconductor integrated circuit device (system LSI) 100 is driven by a battery, low power supply voltage and low power consumption are required. However, each circuit cannot secure a sufficient margin due to the lower power supply voltage, so that a demand for more accurate characteristics is expected. Therefore, when the voltage generation circuit 1 according to the present embodiment is applied to the system LSI, low power supply voltage operation and low output voltage are possible and effective. In order to achieve higher accuracy, it is preferable that the voltage generation circuit 1 is configured by a CMOS process. In particular (mismatch equivalent current) small influence of the offset of the differential amplifier _{A 1} it is advantageous when mounting SOC (System on a chip) memory, a microprocessor. Furthermore, it may be employed or employed chopper to reduce the device mismatch of the differential amplifier _{A 1,} a DEM (DynamicElement Matching) in order to improve the matching of the MOS transistor.

(C-6) Semiconductor integrated circuit device (2)
FIG. 40 is a block diagram showing another example of the semiconductor integrated circuit device to which the voltage generation circuit 1 is applied. Although not particularly limited, the semiconductor integrated circuit device 100a is, for example, a system LSI having a built-in power supply circuit.

The semiconductor integrated circuit device 100a has a configuration in which a temperature sensor 54 is added to the semiconductor integrated circuit device (system LSI) 100 of FIG. 39 described above. The temperature sensor 54 includes a voltage generation circuit 1 and an AD converter 56. The voltage generation circuit 1 is shared with the main regulator 43 and the sub-regulator 44. The voltage generation circuit 1 includes, for example, a BGR core circuit 10 (V _PTAT can be output) and a correction circuit 20.

In the system to which the voltage generation circuit of each of the above embodiments is applied, low voltage output and low power supply voltage operation are possible in the voltage generation circuit, and the accuracy of the output voltage V _BGR is improved over a wide temperature range. Therefore, low power consumption and high reliability can be ensured.

(Chip layout)
FIG. 41 is a block diagram showing an example of a chip layout of a semiconductor integrated circuit device to which the voltage generation circuit 1 is applied. Although not particularly limited, the semiconductor integrated circuit device 100b is a system LSI having a built-in power supply circuit, for example.

  The semiconductor integrated circuit device 100b has a core portion as a center, and a flash ROM, a plurality of analog IPs, a PMU (power supply control circuit), a VDC (power supply circuit), a PLL-VDC (PLL dedicated power supply circuit), SRAM and BGR (voltage generation circuit 1) are provided. Then, as a wiring-related configuration for supplying power to them, a plurality of terminals 81, an I / O ring circumferential power trunk 82, a core circumferential power trunk 83, a Main_VDC wiring region 84, a Core power trunk mesh 85, a terminal-power trunk 86 and an analog power supply trunk line 87. The plurality of terminals 81 are provided at predetermined intervals along the edge of the semiconductor integrated circuit device 100b. The I / O ring circuit power supply trunk line 82 is a power supply trunk circuit that circulates along the edge of the semiconductor integrated circuit device 100b. The Main_VDC wiring area 84 is an area having wiring for supplying VDC (power supply) to the Core section. A Core power trunk mesh 85 in the Main_VDC wiring region 84 is a mesh-shaped power trunk provided in the Core section. The Core circulation power supply trunk line 83 in the Main_VDC wiring region 84 is a power supply trunk line provided so as to surround the Core part power supply trunk line mesh 85. The terminal-power supply trunk line 86 is a power supply trunk line that connects the terminal 81 and a VDC (power supply). The analog power supply trunk line 87 is a power supply trunk line that connects the analog IP and the VDC (power supply).

FIG. 42 is a cross-sectional view showing a part of the voltage generating circuit 1 when manufactured on a semiconductor substrate.
In this example, a deep n-well is provided at a deep position of the P-type semiconductor substrate. On the deep n-well (a position shallower than the deep n-well), an n-well is provided along the edge of the deep n-well, and a p-well is formed inside the n-well. Is provided. These n-well and p-well are provided at substantially the same depth. On the p-well on the deep n-well, a p + layer is provided along the edge of the p-well, and an n + layer is provided inside the p + layer with an insulating layer interposed therebetween. An n + layer is provided on the n-well on the edge of the deep n-well. At this time, the deep n well is a collector layer of the bipolar transistor, and an n + layer provided on the n well on the edge of the deep n well serves as a collector terminal. The p well on the deep n well is a base layer of the bipolar transistor, and the p + layer on the p well serves as a base terminal. The n + layer on the p well on the deep n well is an emitter layer of the bipolar transistor and also an emitter terminal. The p + layer on the p well serves as a base terminal. That is, a bipolar transistor is formed in this region.

  A p-well is further provided on the side of the n-well on the edge of the deep n-well. On the p-well, n + layers are provided facing each other at a predetermined distance. The region of a predetermined distance corresponds to the channel of the MOS transistor, and a gate electrode is provided on the upper portion through an insulating layer. The n + layers facing each other correspond to the source terminal and the drain terminal. That is, a MOS transistor is formed in this p well. This p-well and the aforementioned n-well and p-well are provided at substantially the same depth.

  Thus, the bipolar transistor and the MOS transistor are formed in the same series of manufacturing processes on the same semiconductor substrate.

According to the voltage generation circuit 1 in each embodiment, the BGR core circuit 10 has the above-described circuit configuration, thereby enabling low voltage output and low power supply voltage operation. Further, by generating the correction current Icomp by the correction circuit 20 and feeding it back to the BGR core circuit 10, the temperature dependence of the output voltage V _BGR can be further reduced. As a result, the accuracy of the output voltage V _BGR is improved over a wide temperature range.

Moreover, the voltage generation circuit 1 in each embodiment is provided with a plurality of correction circuits 20 having different operating temperatures (threshold temperatures), and is cascade-connected to the BGR core circuit. Therefore, each correction circuit can correct the output voltage V _BGR at different temperatures. Thereby, the correction of the temperature dependence of the output voltage V _BGR can be performed in a wider temperature range. As a result, the accuracy of the output voltage V _BGR is improved over a wider temperature range.

In addition, the voltage generation circuit 1 in each embodiment can selectively turn on / off a desired correction circuit 20 from among a plurality of correction circuits 20 by a control signal (power down signal). As a result, some of the plurality of correction circuits 20 can be turned off according to the surrounding environment (such as temperature and humidity) and the accuracy of the output voltage V _BGR required for the system. Thereby, the graph of the temperature dependence of the output voltage V _BGR can be made a desired curve. Further, unnecessary power consumption in the correction circuit 20 can be suppressed to save power.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Some or all of the above-described embodiments and examples can be described as in the following supplementary notes, but are not limited to the following.

(Appendix 1)
A semiconductor device comprising a voltage generation circuit,
The voltage generation circuit includes a reference voltage generation circuit that outputs a reference voltage, and a plurality of correction circuits that generate a correction current and feed back to the reference voltage generation circuit.
Each of the plurality of correction circuits generates a sub correction current that monotonously increases from a predetermined temperature that is different for each of the plurality of correction circuits toward the low temperature side or the high temperature side,
The semiconductor device, wherein the correction current is a sum of a plurality of sub correction currents generated by the plurality of correction circuits.

(Appendix 2)
The semiconductor device according to appendix 1, wherein
Each of the plurality of correction circuits generates the sub correction current based on the reference voltage or a voltage proportional to the reference voltage or a current corresponding thereto and a forward voltage of a PN junction or a current corresponding thereto. Semiconductor device.

(Appendix 3)
The semiconductor device according to attachment 2, wherein
In each of the plurality of correction circuits, the plurality of sub correction currents monotonously increase from the predetermined temperature toward the high temperature side.

(Appendix 4)
The semiconductor device according to attachment 3, wherein
Each of the plurality of correction circuits includes a first PMOS transistor having a source connected to the first power supply, a gate connected to the drain, a source connected to the first power supply, and a gate connected to the gate of the first PMOS transistor. 2 PMOS transistors, a drain connected to the PMOS transistor at the collector, a bipolar transistor connected to the voltage generated from the reference voltage at the base, an emitter of the bipolar transistor at one end, and the other end connected to the second power source Provided with resistance,
The voltage corresponding to the reference voltage is a voltage obtained by dividing the reference voltage with a resistor, and is different for each of the plurality of correction circuits.
The second PMOS transistor outputs the sub correction current from a drain.

(Appendix 5)
The semiconductor device according to appendix 4, wherein
Each of the plurality of correction circuits further includes an amplifier having a voltage corresponding to the reference voltage connected to one input and a base of the bipolar transistor connected to the other input and output.

(Appendix 6)
The semiconductor device according to attachment 2, wherein
In each of the plurality of correction circuits, the plurality of sub correction currents monotonously increase from the predetermined temperature toward a low temperature side.

(Appendix 7)
The semiconductor device according to appendix 6, wherein
Each of the plurality of correction circuits includes a first power source as a source, a third PMOS transistor having a gate connected to a gate of a transistor through which a reference current in the reference voltage generation circuit flows, and a first power source as a source. A first PMOS transistor having a drain connected to the gate, a first power supply to the source, a second PMOS transistor having the gate connected to the gate of the first PMOS transistor, a drain to the PMOS transistor to the collector, and the base to the second PMOS transistor A bipolar transistor connected to the drain of the third PMOS transistor, a base connected to the bipolar transistor at one end, a diode connected to the second power source at the other end, an emitter of the bipolar transistor at one end, and the other end at the other end 2 power supplies each And a connection to a resistor,
The transistor for passing the reference current in the reference voltage generation circuit and the third PMOS transistor constitute a current mirror circuit,
The current mirror ratio of the current mirror circuit is different for each of the plurality of correction circuits,
The second PMOS transistor (MP4) is a semiconductor device that outputs the sub correction current from a drain.

(Appendix 8)
The semiconductor device according to attachment 1, wherein each of the plurality of correction circuits includes a difference voltage between base-emitter voltages of two bipolar transistors having different emitter areas or a current corresponding thereto and a forward voltage of a PN junction, or A semiconductor device that generates the sub correction current based on at least one of currents corresponding thereto.

(Appendix 9)
The semiconductor device according to appendix 8, wherein each of the plurality of correction circuits has the plurality of sub correction currents monotonously increasing from the predetermined temperature toward a high temperature side.

(Appendix 10)
The semiconductor device according to appendix 9, wherein
Each of the plurality of correction circuits includes a first PMOS transistor having a source connected to the first power supply, a gate connected to the drain, a source connected to the first power supply, and a gate connected to the gate of the first PMOS transistor. 2 PMOS transistors, a first constant current source connected between the first power supply and the drain of the first PMOS transistor, and a second constant current connected between the drain of the first PMOS transistor and the second power supply. With a source,
The one constant current source generates a current corresponding to a forward voltage of a PN junction,
The second constant current source generates a current according to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, and is different in each of the plurality of correction circuits,
The second PMOS transistor outputs the sub correction current from a drain.

(Appendix 11)
The semiconductor device according to appendix 9, wherein
Each of the plurality of correction circuits includes a first PMOS transistor having a source connected to the first power supply, a gate connected to the drain, a source connected to the first power supply, and a gate connected to the gate of the first PMOS transistor. 2 PMOS transistors, a first constant current source connected between the first power supply and the drain of the first PMOS transistor, and a second constant current connected between the drain of the first PMOS transistor and the second power supply. With a source,
The one constant current source generates a current according to a forward voltage of a PN junction, and is different for each of the plurality of correction circuits.
The second constant current source generates a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas;
The second PMOS transistor outputs the sub correction current from a drain.

(Appendix 12)
The semiconductor device according to appendix 9, wherein
Each of the plurality of correction circuits includes a resistor having one end connected to a first power supply, a PMOS transistor having a source connected to the first power supply, a gate connected to the other end of the resistor, and the other end of the resistor. And a constant current source connected between the second power source and
The constant current source generates a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The resistance is different in each of the plurality of correction circuits,
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 13)
The semiconductor device according to appendix 9, wherein
Each of the plurality of correction circuits includes a resistor having one end connected to a first power supply, a PMOS transistor having a source connected to the first power supply, a gate connected to the other end of the resistor, and the other end of the resistor. And a constant current source connected between the second power source and
The constant current source generates a current according to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and is different for each of the plurality of correction circuits.
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 14)
The semiconductor device according to appendix 8, wherein
In each of the plurality of correction circuits, the plurality of sub correction currents monotonously increase from the predetermined temperature toward a low temperature side.

(Appendix 15)
The semiconductor device according to appendix 14, wherein
Each of the plurality of correction circuits includes a first PMOS transistor having a source connected to the first power supply, a gate connected to the drain, a source connected to the first power supply, and a gate connected to the gate of the first PMOS transistor. 2 PMOS transistors, a first constant current source connected between the first power supply and the drain of the first PMOS transistor, and a second constant current connected between the drain of the first PMOS transistor and the second power supply. With a source,
The one constant current source generates a current corresponding to a forward voltage of a PN junction,
The second constant current source generates a current according to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, and is different in each of the plurality of correction circuits,
The second PMOS transistor outputs the sub correction current from a drain.

(Appendix 16)
The semiconductor device according to appendix 14, wherein
Each of the plurality of correction circuits includes a first PMOS transistor having a source connected to the first power supply, a gate connected to the drain, a source connected to the first power supply, and a gate connected to the gate of the first PMOS transistor. 2 PMOS transistors, a first constant current source connected between the first power supply and the drain of the first PMOS transistor, and a second constant current connected between the drain of the first PMOS transistor and the second power supply. With a source,
The one constant current source generates a current according to a forward voltage of a PN junction, and is different for each of the plurality of correction circuits.
The second constant current source generates a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas;
The second PMOS transistor outputs the sub correction current from a drain.

(Appendix 17)
The semiconductor device according to appendix 14, wherein
Each of the plurality of correction circuits includes a constant current source having one end connected to a first power source, a PMOS transistor having a source connected to the first power source, and a gate connected to the other end of the constant current source, A resistor connected between the other end of the constant current source and the second power source;
The constant current source generates a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The resistance is different in each of the plurality of correction circuits,
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 18)
The semiconductor device according to appendix 14, wherein
Each of the plurality of correction circuits includes a constant current source having one end connected to a first power source, a PMOS transistor having a source connected to the first power source, and a gate connected to the other end of the constant current source, A resistor connected between the other end of the constant current source and the second power source;
The constant current source generates a current according to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and is different for each of the plurality of correction circuits.
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 19)
The semiconductor device according to appendix 8, wherein
In the first correction circuit of the plurality of correction circuits, the sub correction current monotonously increases from the first predetermined temperature toward the high temperature side,
The second correction circuit of the plurality of correction circuits is a semiconductor device in which the sub correction current monotonously increases from a second predetermined temperature lower than the first predetermined temperature toward a low temperature side.

(Appendix 20)
The semiconductor device according to appendix 19, wherein
The first correction circuit includes a first PMOS transistor having a source connected to a first power supply, a gate connected to a drain, and a first PMOS transistor having a source connected to the source and a gate connected to the gate of the first PMOS transistor. A first constant current source connected between the first power source and the drain of the first PMOS transistor; a second constant current source connected between the drain of the first PMOS transistor and the second power source; With
The first constant current source generates a first current corresponding to a forward voltage of a PN junction,
The second constant current source generates a second current according to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The second PMOS transistor outputs the sub correction current from the drain,
The second correction circuit includes a third PMOS transistor having a source connected to the first power source and a gate connected to a drain, a first PMOS connected to the source, and a fourth PMOS connected to the gate of the third PMOS transistor. A transistor, a third constant current source connected between the first power source and the drain of the third PMOS transistor, and a fourth constant current source connected between the drain of the first PMOS transistor and the second power source. And
The three constant current sources generate a third current corresponding to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and the third current is different from the two currents,
The fourth constant current source generates a fourth current according to a forward voltage of a PN junction, and the fourth current is the same as the two currents.
The fourth PMOS transistor outputs the sub correction current from a drain.

(Appendix 21)
The semiconductor device according to appendix 19, wherein
The first correction circuit includes a first PMOS transistor having a source connected to a first power supply, a gate connected to a drain, and a first PMOS transistor having a source connected to the source and a gate connected to the gate of the first PMOS transistor. A first constant current source connected between the first power source and the drain of the first PMOS transistor; a second constant current source connected between the drain of the first PMOS transistor and the second power source; With
The first constant current source generates a first current corresponding to a forward voltage of a PN junction,
The second constant current source generates a second current according to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The second PMOS transistor outputs the sub correction current from the drain,
The second correction circuit includes a third PMOS transistor having a source connected to the first power source and a gate connected to a drain, a first PMOS connected to the source, and a fourth PMOS connected to the gate of the third PMOS transistor. A transistor, a third constant current source connected between the first power source and the drain of the third PMOS transistor, and a fourth constant current source connected between the drain of the first PMOS transistor and the second power source. And
The three constant current sources generate a third current corresponding to a voltage difference between the base-emitter voltages of two bipolar transistors having different emitter areas, and the third current is the same as the two currents. The current source generates a fourth current according to a forward voltage of the PN junction, and the fourth current is different from the two currents,
The fourth PMOS transistor outputs the sub correction current from a drain.

(Appendix 22)
The semiconductor device according to appendix 19, wherein
The first correction circuit includes a first resistor having a first power source connected to one end, a first PMOS transistor having a source connected to the first power source, a gate connected to the other end of the first resistor, and the first resistor. A first constant current source connected between the other end of one resistor and a second power source;
The first constant current source generates a first current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The first PMOS transistor outputs the sub correction current from a drain;
The second correction circuit includes a second constant current source having one end connected to the first power source, a first source connected to the source, and a second PMOS having the gate connected to the other end of the second constant current source. A transistor, and a second resistor connected between the other end of the second constant current source and the second power source,
The second constant current source generates a second current according to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and the second current is different from the first current,
The second resistor is the same as the first resistor,
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 23)
The semiconductor device according to appendix 19, wherein
The first correction circuit includes a first resistor having a first power source connected to one end, a first PMOS transistor having a source connected to the first power source, a gate connected to the other end of the first resistor, and the first resistor. A first constant current source connected between the other end of one resistor and a second power source;
The first constant current source generates a first current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The first PMOS transistor outputs the sub correction current from a drain;
The second correction circuit includes a second constant current source having one end connected to the first power source, a first source connected to the source, and a second PMOS having the gate connected to the other end of the second constant current source. A transistor, and a second resistor connected between the other end of the second constant current source and the second power source,
The second constant current source generates a second current corresponding to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and the second current is the same as the first current;
The second resistor is different from the first resistor,
The PMOS transistor outputs the sub correction current from a drain.

(Appendix 24)
The semiconductor device according to appendix 1, wherein
Each of the plurality of correction circuits is selectively turned on or off by a control signal.

(Appendix 25)
The semiconductor device according to appendix 1, wherein
The reference voltage generation circuit generates a reference current obtained by adding a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, a current corresponding to a forward voltage of a PN junction, and the correction current. A semiconductor device that generates, converts to a voltage, and outputs the reference voltage.

(Appendix 26)
The semiconductor device according to appendix 5, wherein
The reference voltage generation circuit generates a reference current obtained by adding a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, a current corresponding to a forward voltage of a PN junction, and the correction current. A current generation unit for generating, and an output unit for converting the reference current into an output voltage and outputting the output voltage,
The current generation unit has a first bipolar transistor having an emitter terminal disposed on the first potential node side and an emitter area larger than that of the first bipolar transistor, and the emitter terminal is an emitter of the first bipolar transistor. A second bipolar transistor having a base terminal connected to the collector terminal of the first bipolar transistor, one end connected to the collector terminal of the first bipolar transistor, and the other end to the base of the first bipolar transistor. A first resistance element connected to the terminal; one end connected to the collector terminal of the second bipolar transistor; the other end connected to the other end of the first resistance element; and one end connected to the first resistor One bipolar transistor is connected to the base terminal, and the other end is the first potential. A third resistance element connected to the first node, a fourth resistance element having one end connected to the emitter terminal of the first bipolar transistor and the other end connected to the first potential node; An amplifier for outputting a first voltage corresponding to a voltage difference between a collector-side voltage and a collector-side voltage of the second bipolar transistor; and converting the first voltage into a second reference current; A voltage-current conversion unit (MP1, MP2, MP3, MP4) that supplies a node to which an element and the second resistance element are connected and supplies the output unit as the reference current;
The output unit includes a fifth resistance element having one end connected to the voltage-current converter and the other end connected to the first potential node.
The fifth resistance element outputs a voltage on the voltage-current conversion unit side generated by the flow of the reference current as the output voltage, and includes a plurality of sub-resistance elements connected in series,
The temperature characteristics of the output voltage can be adjusted by the third resistance element,
The absolute value of the output voltage can be adjusted by the fifth resistance element,
A semiconductor device capable of adjusting a nonlinear effect of the output voltage by the fourth resistance element.

1 Voltage generation circuit 10 Reference voltage generation circuit (BGR core circuit)
20, 20a, 20b, 20c, 20d, 20-i (i = 1 to n; natural number), 20a-1 to 20a-3, 20b-1 to 20b-3 Correction circuit 30 Start-up circuit 31 First stage part 32 Output stage part 33 Current source section 41 Power supply control section 42 Reference voltage buffer circuit 43 Main regulator 44 Sub-regulator 45 CPU (central processing unit)
46 Register 47 Nonvolatile memory element 48 Peripheral circuit 49 Input / output circuit 50, 55 Power supply circuit 51, 56 AD converter 52 DA converter 53 Reference current source 54 Temperature sensor 60 Low-pass filter 81 Terminal 82 I / O ring circulating power supply main line 83 Core circuit power supply main line 84 Main_VDC wiring region 85 Core section power supply main line mesh 86 Terminal-power supply main line 87 Analog power supply main line 100, 100a, 100b Semiconductor integrated circuit device 101 Current generation section 102: Output section 103: First current generation section 104: First 2 Current generator

Claims (5)

A semiconductor device comprising a voltage generation circuit,
The voltage generation circuit includes:
A reference voltage generation circuit for outputting a reference voltage;
A plurality of correction circuits that generate a correction current and feed back to the reference voltage generation circuit;
Each of the plurality of correction circuits generates a sub correction current that monotonously increases from a predetermined temperature that is different for each of the plurality of correction circuits toward the low temperature side or the high temperature side,
Each of the plurality of correction circuits is based on at least one of a difference voltage between base-emitter voltages of two bipolar transistors having different emitter areas or a current corresponding thereto and a forward voltage of a PN junction or a current corresponding thereto. Generate a sub-correction current,
In the first correction circuit of the plurality of correction circuits, the sub correction current monotonously increases from the first predetermined temperature toward the high temperature side,
In the second correction circuit of the plurality of correction circuits, the sub correction current monotonously increases from the second predetermined temperature lower than the first predetermined temperature toward the low temperature side,
The first correction circuit includes a first resistor having a first power source connected to one end, a first PMOS transistor having a source connected to the first power source, a gate connected to the other end of the first resistor, and the first resistor. A first constant current source connected between the other end of one resistor and a second power source;
The first constant current source generates a first current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas,
The first PMOS transistor outputs the sub correction current from a drain;
The second correction circuit includes a second constant current source having one end connected to the first power source, a first source connected to the source, and a second PMOS having the gate connected to the other end of the second constant current source. A transistor, and a second resistor connected between the other end of the second constant current source and the second power source,
The second constant current source generates a second current corresponding to a voltage difference between a base-emitter voltage of two bipolar transistors having different emitter areas, and the second current is the same as the first current. ,
The second resistor is different from the first resistor,
The second PMOS transistor outputs the sub correction current from the drain,
The correction current is a sum of a plurality of sub correction currents generated by the plurality of correction circuits. The semiconductor device according to claim 1,
Each of the plurality of correction circuits is selectively turned on or off by a control signal.
Semiconductor device. The semiconductor device according to claim 1,
The reference voltage generation circuit generates a reference current obtained by adding a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, a current corresponding to a forward voltage of a PN junction, and the correction current. Generate, convert to voltage and output as the reference voltage,
Semiconductor device. A semiconductor device comprising a voltage generation circuit,
The voltage generation circuit includes:
A reference voltage generation circuit for outputting a reference voltage;
A plurality of correction circuits that generate a correction current and feed back to the reference voltage generation circuit;
Each of the plurality of correction circuits generates a sub correction current that monotonously increases from a predetermined temperature that is different for each of the plurality of correction circuits toward the low temperature side or the high temperature side,
The correction current is a sum of the plurality of sub correction currents generated by the plurality of correction circuits,
Each of the plurality of correction circuits generates the sub correction current based on the reference voltage or a voltage proportional to the reference voltage or a current corresponding thereto, and a forward voltage of the PN junction or a current corresponding thereto,
In each of the plurality of correction circuits, the plurality of sub correction currents monotonously increase from the predetermined temperature toward the high temperature side,
Each of the plurality of correction circuits includes:
A first PMOS transistor having a source connected to the first power supply and a gate connected to the drain;
A second PMOS transistor having a source connected to the first power source and a gate connected to the gate of the first PMOS transistor;
A bipolar transistor having a collector connected to the drain of the PMOS transistor and a base connected to a voltage generated from the reference voltage;
A resistor having one end connected to the emitter of the bipolar transistor and the other end connected to a second power source,
The voltage corresponding to the reference voltage is a voltage obtained by dividing the reference voltage with a resistor, and is different for each of the plurality of correction circuits.
The second PMOS transistor outputs the sub correction current from the drain,
The reference voltage generation circuit includes:
A current generator for generating a reference current obtained by adding a current corresponding to a difference voltage between a base-emitter voltage of two bipolar transistors having different emitter areas, a current corresponding to a forward voltage of a PN junction, and the correction current;
An output unit that converts the reference current into an output voltage and outputs the output voltage,
The current generator is
A first bipolar transistor having an emitter terminal disposed on the first potential node side;
A second bipolar transistor having an emitter area larger than that of the first bipolar transistor, an emitter terminal connected to the emitter terminal of the first bipolar transistor, and a base terminal connected to the collector terminal of the first bipolar transistor; When,
A first resistance element having one end connected to the collector terminal of the first bipolar transistor and the other end connected to the base terminal of the first bipolar transistor;
A second resistance element having one end connected to the collector terminal of the second bipolar transistor and the other end connected to the other end of the first resistance element;
A third resistance element having one end connected to the base terminal of the first bipolar transistor and the other end connected to the first potential node;
A fourth resistance element having one end connected to the emitter terminal of the first bipolar transistor and the other end connected to the first potential node;
An amplifier for outputting a first voltage corresponding to a voltage difference between a voltage on a collector side of the first bipolar transistor and a voltage on a collector side of the second bipolar transistor;
A voltage-current converter that converts the first voltage into a second reference current, supplies the first voltage to a node to which the first resistance element and the second resistance element are connected, and supplies the output section as the reference current; Have
The output unit includes a fifth resistance element having one end connected to the voltage-current converter and the other end connected to the first potential node.
The fifth resistance element outputs a voltage on the voltage-current conversion unit side generated by the flow of the reference current as the output voltage, and includes a plurality of sub-resistance elements connected in series,
The temperature characteristic of the output voltage can be adjusted by the third resistance element, the absolute value of the output voltage can be adjusted by the fifth resistance element, and the nonlinear effect of the output voltage can be adjusted by the fourth resistance element Is possible,
Semiconductor device. The semiconductor device according to claim 4,
Each of the plurality of correction circuits further includes an amplifier having a voltage corresponding to the reference voltage connected to one input and a base of the bipolar transistor connected to the other input and output.

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