JP6264837B2 - Semiconductor light emitting element, light source head, and image forming apparatus - Google Patents

Description

  The present invention relates to a semiconductor light emitting element, a light source head, and an image forming apparatus.

In Patent Document 1, a first semiconductor layer of one of N-type and P-type conductivity, a second semiconductor layer opposite in conductivity type to the first semiconductor layer, and the same conductivity type as the first semiconductor layer are formed on a substrate. In the light emitting thyristor in which the third semiconductor layer and the fourth semiconductor layer having the opposite conductivity type to the first semiconductor layer are stacked in this order, the band gap of the third semiconductor layer is equal to the band gap of the second semiconductor layer. The third semiconductor layer is substantially the same and narrower than the band gap of the first and fourth semiconductor layers, and the third semiconductor layer includes a first region on the substrate side and a second region on the opposite side of the substrate. The impurity concentration of the first region is lower than the impurity concentration of the second region and less than 1 × 10 ¹⁶ (cm ⁻³ ), and the impurity concentration of the second semiconductor layer is Impurity concentration of the first region of the third semiconductor layer The impurity concentration of the fourth semiconductor layer is substantially the same as or higher than the impurity concentration of the first semiconductor layer, and the impurity concentration of the fourth semiconductor layer is substantially equal to the impurity concentration of the second region of the third semiconductor layer. Light emitting thyristors are described which are characterized by the same or higher concentration.

  Patent Document 2 discloses a multilayer film reflecting mirror formed on a substrate, a light emitting layer formed on the multilayer film reflecting mirror, and light emitted from the light emitting layer using the multilayer reflecting mirror as a lower reflecting mirror. A semiconductor light emitting device comprising a semiconductor layer, and a phase shift layer that generates a standing wave having a plurality of main modes by shifting a phase of a resonance spectrum of the resonator Has been.

JP 2010-239084 A JP 2013-161979 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor light emitting element, a light source head, and an image forming apparatus having a low threshold voltage compared to the case where the symmetry of both PNP type and NPN type transistors in a semiconductor light emitting element is different. .

In order to achieve the above object, a semiconductor light-emitting device according to claim 1 includes a first-conductivity-type multilayer reflector formed on a substrate and a second-conductivity-type reflector formed on the multilayer reflector. A first semiconductor layer, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, and a second film of the second conductivity type that is a single film formed on the second semiconductor layer. The third semiconductor layer is formed on the third semiconductor layer, has a band gap equal to that of the first semiconductor layer, is larger than that of the second semiconductor layer, and is larger than that of the third semiconductor layer. It viewed including a fourth semiconductor layer of the band gap is smaller second conductivity type, wherein the multilayer reflector anode, the first semiconductor layer is a gate, said second semiconductor layer is a gate, said third semiconductor layer and The fourth semiconductor layer is a cathode, and the multilayer reflector; In the first transistor formed by the first semiconductor layer and the second semiconductor layer, the energy of electrons of the multilayer mirror in contact with the first semiconductor layer and the second semiconductor layer in contact with the first semiconductor layer The magnitude relationship with the electron energy of the first semiconductor layer is in contact with the second semiconductor layer in the second transistor formed by the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer. The magnitude relationship between the energy of electrons in the first semiconductor layer and the energy of electrons in the third semiconductor layer in contact with the second semiconductor layer is equivalent .

In the semiconductor light emitting device according to claim 2 , a band gap of the third semiconductor layer is equal to a band gap of the multilayer reflector that is in contact with the first semiconductor layer.

A light source head according to a third aspect includes the semiconductor light emitting element of the present invention as a light source.

The image forming apparatus according to claim 4 is provided with a photosensitive member, a charging unit that charges the surface of the photosensitive member, and a light source head according to the present invention, and an electrostatic latent image is formed on the surface of the photosensitive member charged by the charging unit. An exposure unit that exposes light emitted from the light source head to form an image; a development unit that develops the electrostatic latent image formed by the exposure unit; and the electrostatic latent image developed by the development unit And fixing means for fixing.

  According to the first aspect of the present invention, the threshold voltage is low compared to the case where the PNP type and NPN type transistors in the semiconductor light emitting element are different in symmetry.

According to the invention described in claim 2, compared with a case not having the present structure, to improve carrier injection efficiency.

According to the third and fourth aspects of the present invention, the image quality of the image is improved as compared with the case where the present configuration is not provided.

1 is a schematic configuration diagram showing an outline of an example of an image forming apparatus according to the present embodiment. It is a schematic sectional drawing which shows the internal structure of an example of the light source head which concerns on this Embodiment. It is a perspective view which shows the external appearance of an example of the semiconductor light-emitting element array which concerns on this Embodiment. It is sectional drawing which shows schematic structure of an example of the semiconductor light-emitting device concerning this Embodiment, and a figure which shows the band gap of each semiconductor layer. It is explanatory drawing which showed an example of the correspondence of the electric current and voltage which flow through the inside of a semiconductor light-emitting device. It is explanatory drawing which showed typically the PNPN type light emission thyristor. It is a schematic diagram of the band structure of the semiconductor light emitting device of the present embodiment. It is sectional drawing which shows schematic structure of an example of the conventional semiconductor light-emitting device, and a figure which shows the band gap of each semiconductor layer. It is a schematic diagram of the band structure of the conventional semiconductor light emitting element.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing an outline of an example of an image forming apparatus according to the present embodiment. FIG. 2 is a schematic cross-sectional view showing the internal configuration of an example of the light source head of the present embodiment. FIG. 3 is a perspective view showing an appearance of an example of the semiconductor light emitting element array according to the present embodiment.

  As shown in FIG. 1, the image forming apparatus 10 according to the present embodiment includes a photoreceptor 12 that rotates in the direction of arrow A.

  Around the photosensitive member 12, along the rotational direction of the photosensitive member 12, a charger 14, a light source head 16 (an example of an exposure unit), a developing unit 18 (an example of a developing unit), and a transfer member 20 (of the transfer unit). An example), a cleaner 22 and an erase lamp 24 are arranged in this order. The charger 14 charges the surface of the photoconductor 12. The light source head 16 is used for exposure to form an electrostatic latent image on the surface of the photoreceptor 12 charged by the charger 14. The developing device 18 develops the electrostatic latent image with a developer to form a toner image. The transfer body 20 transfers the toner image to the paper 28 (an example of a recording medium). The cleaner 22 removes residual toner remaining on the photoconductor 12 after transfer. The erase lamp 24 neutralizes the potential by removing the charge from the photoconductor 12.

  That is, the surface of the photoconductor 12 is charged by the charger 14, and then a light beam is irradiated by the light source head 16 to form a latent image on the photoconductor 12. The light source head 16 is connected to a driving unit (not shown), and the driving unit controls lighting of the semiconductor light emitting element 100 to emit a light beam based on image data.

  To the formed latent image, toner is supplied by the developing unit 18 to form a toner image on the photoreceptor 12. The toner image on the photoconductor 12 is transferred onto the conveyed paper 28 by the transfer body 20. The toner remaining on the photoconductor 12 after the transfer is removed by the cleaner 22, neutralized by the erase lamp 24, charged by the charger 14 again, and the same processing is repeated.

  On the other hand, the paper 28 onto which the toner image has been transferred is conveyed to a fixing device 30 (an example of a fixing unit) composed of a pressure roller 30A and a heating roller 30B and subjected to a fixing process. As a result, the toner image is fixed and a desired image is formed on the paper 28. The paper 28 on which the image is formed is discharged out of the apparatus.

  Next, the configuration of the light source head 16 of the present embodiment will be described in detail. The light source head 16 of the present embodiment uses an SLED (Self-scanning LED). The SLED is obtained by integrating an LED array and a driving portion thereof, and includes a light emitting unit (semiconductor light emitting element 100, which will be described in detail later) having a plurality of thyristor structures. As shown in FIG. 2, the light source head 16 includes a semiconductor light emitting element array 50, a mounting substrate 52, and a rod lens array 54. The mounting substrate 52 is mounted with a circuit (not shown) for supporting the semiconductor light emitting element array 50 and supplying various signals for controlling the driving of the semiconductor light emitting element array 50. The rod lens array 54 is a Selfox lens array or the like (Selfock is a registered trademark of Nippon Sheet Glass Co., Ltd.).

  The mounting substrate 52 is disposed in the housing 56 with the mounting surface of the semiconductor light emitting element array 50 facing the photoreceptor 12 and is supported by a plate spring 58.

  As shown in FIG. 3, the semiconductor light emitting element array 50 includes, for example, a plurality of chips 62 in which a plurality of semiconductor light emitting elements 100 are arranged along the axial direction of the photoreceptor 12 according to the resolution in the axial direction. Are arranged in series. The semiconductor light emitting element array 50 irradiates the light beam with a predetermined resolution in the axial direction of the photosensitive member 12.

  In the present embodiment, an example in which a plurality of chips 62 are arranged in a one-dimensional manner in series is shown. However, the present invention is not limited to this, and the chips 62 may be arranged in a plurality of rows and arranged in a two-dimensional manner. For example, when arranged in a zigzag pattern, the plurality of chips 62 are arranged in a row so as to be aligned along the axial direction of the photoconductor 12 and are arranged in two rows with a certain interval in the direction intersecting the axial direction. Is done. Even when divided into a plurality of chips 62, each of the plurality of semiconductor light emitting elements 100 has an interval between the two semiconductor light emitting elements 100 adjacent to each other in the axial direction of the photosensitive member 12 so as to be substantially constant. It is arranged.

  As shown in FIG. 2, the rod lens array 54 is supported by a holder 64 and forms an image of the light beam emitted from each semiconductor light emitting element 100 on the photoreceptor 12.

  Next, the semiconductor light emitting device 100 of the present embodiment will be described in detail.

First, a schematic configuration of the semiconductor light emitting device 100 of the present embodiment will be described. FIG. 4 shows a cross-sectional view of a schematic configuration of an example of the semiconductor light emitting device 100 of the present embodiment and the band gap of each semiconductor layer. In the present embodiment, the semiconductor light emitting element 100 is an Al _x Ga _1-x As-based PNPN type light emitting thyristor from the substrate side. Hereinafter, the Al ratio (x) in Al _x Ga _1-x As is referred to as Al composition ratio. Moreover, in the semiconductor light emitting device 100 of the present embodiment, as an example, Zn is doped as an impurity in the p-type, and Si is doped as an impurity in the n-type.

  In the semiconductor light emitting device 100, a substrate 102, a buffer layer 104, a DBR (Distributed Bragg Reflector) layer 106, a gate layer 108, a light emitting layer 110, a gate layer 112, an adjustment layer 114, a cathode layer 116, and a contact layer 118 are stacked in this order. Has been.

  As shown in FIG. 4, in the semiconductor light emitting device 100 of the present embodiment, a p-type GaAs buffer layer 104 is stacked on a p-type GaAs substrate 102. The buffer layer 104 has a function for improving the crystallinity between the substrate 102 and the p-type AlGaAs DBR layer 106.

The DBR layer 106 is a multilayer film reflector in which two semiconductor layers each having a thickness of 0.25λ and different refractive indexes are alternately stacked. The reference wavelength λ is a value obtained by dividing the peak wavelength of light emitted from the light emitting layer 110 in vacuum (that is, the peak wavelength of the spontaneous emission spectrum) λ ₀ by the refractive index n of the DBR layer 106 (λ = λ ₀ / n). That is, λ is a peak wavelength when light emitted from the light emitting layer 110 propagates in the DBR layer 106.

In the DBR layer 106, a pair of a high-refractive index semiconductor film 106A and a low-refractive index semiconductor film 106B is repeatedly stacked in order from the substrate 102 side by 10.5 pairs. Specifically, in the DBR layer 106, the total number of the semiconductor films 106B made of p-type Al _0.2 Ga _0.8 As is 10, and the p-type Al _0.9 Ga _0.1 As is used. The total number of the semiconductor films 106A is 11, and the number of quantum wells is 10.

The semiconductor film 106A has an Al composition ratio of 0.90, a band gap of 2.13 eV, and a film thickness of 0.25λ. The semiconductor film 106B has an Al composition ratio of 0.20, a band gap of 1.67 ev, and a film thickness of 0.25λ. By setting the film thicknesses of the high refractive index semiconductor film 106A and the low refractive index semiconductor film 106B of the DBR layer 106 to 0.25λ, the reflectance with respect to the light having the reference wavelength λ (λ ₀ ) is maximized.

  On the DBR layer 106, an n-type AlGaAs gate layer 108 having an Al composition ratio of 0.30, a band gap of 1.8 eV, and a film thickness of 1.28 μm is laminated. On the gate layer 108, a non-doped AlGaAs light emitting layer 110 having an Al composition ratio of 0.143, a band gap of 1.60 eV, and a film thickness of 1.00 μm is stacked. Further, a p-type AlGaAs gate layer 112 having an Al composition ratio of 0.143, a band gap of 1.60 eV, and a film thickness of 0.89 μm is stacked on the light emitting layer 110.

  Carriers (electrons) injected as decimal carriers from the gate layer 108 side move to the light emitting layer 110. In addition, carriers (holes) injected as fractional carriers from the gate layer 112 side move to the light-emitting layer 110. In the light emitting layer 110, the moved electrons and holes are recombined by light emission.

  On the gate layer 112, an n-type AlGaAs adjustment layer 114 having an Al composition ratio of 0.90, a band gap of 2.13 eV, and a film thickness of 0.51 μm is laminated. The adjustment layer 114 functions as a cathode. The adjustment layer 114 of this embodiment has a higher Al ratio than the cathode layer 116. In AlGaAs, the higher the Al composition ratio, the larger the band gap. Therefore, the adjustment layer 114 has a larger band gap than the cathode layer 116.

  On the adjustment layer 114, an n-type AlGaAs cathode layer 116 having an Al composition ratio of 0.30, a band gap of 1.8 eV, and a film thickness of 0.45 μm is laminated. In the semiconductor light emitting device 100 of the present embodiment, the Al composition ratio of the cathode layer 116 is lowered in order to reduce the resistance value. Specifically, the Al composition ratio of the cathode layer 116 is lower than the Al composition ratio of the semiconductor film 106 </ b> A (detailed later) of the DBR layer 106 in contact with the gate layer 108.

  Further, as described above, the cathode layer 116 has a lower Al composition ratio and a smaller band gap than the adjustment layer 114. A contact layer 118 is laminated on the cathode layer 116. The contact layer 118 has an Al composition ratio of 0, a band gap of 1.42 eV, and a film thickness of 0.03 μm.

  For crystal growth of each of the semiconductor layers of the semiconductor light emitting device 100, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method is applied.

  On the back side of the substrate 102 of the semiconductor light emitting device 100 (the side opposite to the side in contact with the buffer layer 104), a lower electrode (not shown) that is an anode electrode is provided. Further, an upper electrode (not shown) that is a cathode electrode is provided on the front side of the contact layer 118 of the semiconductor light emitting device 100 (the side opposite to the side in contact with the cathode layer 116). Further, a gate electrode (not shown) is provided on the gate layer 112 (on the side opposite to the side in contact with the light emitting layer 110). In the semiconductor light emitting device 100, a signal (voltage) is applied to the gate electrode, and a gate current is caused to flow from the gate electrode to the upper electrode, thereby establishing conduction between the lower electrode and the upper electrode. Thereby, carriers (electrons and holes) are recombined in the light emitting layer 110, and light emitted by the recombination is emitted from the light emitting surface (the side where the contact layer 118 of the semiconductor light emitting element 100 is provided).

  FIG. 5 shows an example of the correspondence relationship between the current flowing through the semiconductor light emitting device 100 and the voltage. FIG. 5 shows a case where 3.0 V is applied to the gate electrode of the semiconductor light emitting device 100. As shown in FIG. 5, the threshold voltage in the case where 3.0 V was applied to the gate electrode of the semiconductor light emitting device 100 of the present embodiment was 4.5 V.

  Next, the operation of the semiconductor light emitting device 100 of the present embodiment will be described in detail.

  In general, a PNPN light-emitting thyristor is equivalent to a decoding circuit that combines a PNP transistor and an NPN transistor. FIG. 6 is an explanatory diagram schematically showing a PNPN type light-emitting thyristor. As shown in FIG. 6A, the light-emitting thyristor has a PNPN quadruple structure. The PNPN light-emitting thyristor is equivalent to a decoding circuit combining a PNP transistor and an NPN transistor, as shown in FIGS. 6 (2) and 6 (3).

  In the semiconductor light emitting device 100 of the present embodiment, the adjustment layer 114 and the cathode layer 116 function as a cathode, and the DBR layer 106 functions as an anode. The semiconductor light emitting device 100 of this embodiment includes an NPN transistor including a gate layer 108, a light emitting layer 110, a gate layer 112, an adjustment layer 114, and a cathode layer 116, a DBR layer 106, a gate layer 108, a light emitting layer 110, and This is equivalent to the combination with the PNP transistor by the gate layer 112.

The characteristics of the NPN transistor are affected by the band gap of the cathode and the band gap of the n-type gate. Specifically, in the semiconductor light emitting device 100 of the present embodiment, it is affected by the band gap of the adjustment layer 114 and the band gap of the gate layer 108. On the other hand, the characteristics of the PNP transistor are affected by the band gap of the anode and the band gap of the p-type gate. Specifically, in the semiconductor light emitting device 100 of the present embodiment, the band gap of the semiconductor film 106A (Al _0.9 Ga _0.1 As) of the DBR layer 106 in contact with the gate layer 108 and the band gap of the gate layer 112 are determined. to be influenced.

In the AlGaAs system, the band gap is the same if the Al composition ratio is the same regardless of whether it is p-type or n-type. In the semiconductor light emitting device 100 of the present embodiment, the Al composition ratio of the adjustment layer 114 is the same as the Al composition ratio of the semiconductor film 106A (Al _0.9 Ga _0.1 As) of the DBR layer 106 in contact with the gate layer 108. is there. Therefore, as shown in FIG. 4, the band gap of the adjustment layer 114 and the band gap of the semiconductor film 106 _</ b> A (Al _0.9 Ga _0.1 As) of the DBR layer 106 in contact with the gate layer 108 are equal.

  In FIG. 7, the schematic diagram of the band structure of the semiconductor light-emitting device 100 of this Embodiment is shown. FIG. 7 schematically shows the correspondence between the position of the PNP transistor and the NPN transistor in the layer depth direction and the energy of electrons in the semiconductor light emitting device 100 of the present embodiment. As shown in FIG. 7, the symmetry of the band gap sandwiching the gate layer 112 (and the light emitting layer 110) in the NPN transistor and the symmetry of the band gap sandwiching the gate layer 108 (and the light emitting layer 110) in the PNP transistor. Sex is the same.

  Therefore, there is no significant difference in characteristics between the PNP transistor and the NPN transistor in the semiconductor light emitting device 100 of the present embodiment. That is, the PNP transistor and the NPN transistor in the semiconductor light emitting device 100 of the present embodiment have similar characteristics.

  Here, a conventional semiconductor light emitting device will be described for comparison with the semiconductor light emitting device 100 of the present embodiment.

  FIG. 8 shows a cross-sectional view of a schematic configuration of an example of a conventional semiconductor light emitting device and band gaps of the respective semiconductor layers. In the conventional semiconductor light emitting device 1000, a substrate 1102, a buffer layer 1104, a DBR (Distributed Bragg Reflector) layer 1106, a gate layer 1108, a light emitting layer 1110, a gate layer 1112, a cathode layer 1116, and a contact layer 1118 are laminated in this order. Yes. The conventional semiconductor light emitting device 1000 shown in FIG. 8 is a PNPN type light emitting thyristor from the substrate side.

  As shown in FIG. 8, a conventional semiconductor light emitting device 1000 has a p-type DBR layer 1106 formed on a p-type GaAs substrate 1102 via a p-type GaAs buffer layer 1104. The DBR layer 1106 has a p-type AlGaAs semiconductor film 1106B having an Al composition ratio of 0.2 (band gap of 1.67 eV) and a p-type Al composition ratio of 0.9 (band gap of 2.13 eV). A pair of AlGaAs-based semiconductor film 1106A is repeatedly laminated by 10.5 pairs. On the DBR layer 1106, an n-type AlGaAs gate layer 1108 having an Al composition ratio of 0.30 (band gap of 1.8 eV) and an undoped layer having an Al composition ratio of 0.143 (band gap of 1.6 eV). An AlGaAs light emitting layer 1110 and a p-type AlGaAs gate layer 1112 having an Al composition ratio of 0.143 (band gap 1.6 eV) are stacked in this order. On the gate layer 1112, an n-type AlGaAs cathode layer 1116 and a contact layer 1118 having an Al composition ratio of 0.30 (band gap is 1.8 eV) are stacked in this order.

  That is, the conventional semiconductor light emitting device 1000 is different from the semiconductor light emitting device 100 of the present embodiment in that a semiconductor layer corresponding to the adjustment layer 114 in the semiconductor light emitting device 100 of the present embodiment is not provided.

  As shown in FIG. 5, the threshold voltage when 3.0 V was applied to the gate electrode of the conventional semiconductor light emitting device 1000 was 5.0 V or more.

  FIG. 9 is a schematic diagram schematically showing a band structure of a conventional semiconductor light emitting device 1000. As shown in FIG. FIG. 9 schematically shows the correspondence between the position in the layer depth direction and the energy of electrons in the semiconductor light emitting device 1000. In the conventional semiconductor light emitting device 1000, the cathode layer 1116 functions as a cathode, and the DBR layer 1106 functions as an anode. A conventional semiconductor light emitting device 1000 includes an NPN transistor including a gate layer 1108, a light emitting layer 1110, a gate layer 1112, and a cathode layer 1116, and a PNP transistor including a DBR layer 1106, a gate layer 1108, a light emitting layer 1110, and a gate layer 1112. Is equivalent to the combination.

In the AlGaAs system, the lower the Al composition ratio, the smaller the band gap, regardless of whether it is p-type or n-type. As shown in FIG. 8, the Al composition ratio of the cathode layer 1116 is lower than the Al composition ratio of the semiconductor film 1106 </ b> A (Al _0.9 Ga _0.1 As) of the DBR layer 1106 in contact with the gate layer 1108. Therefore, the band gap of the cathode layer 1116 is smaller than the band gap of the semiconductor film 1106A (Al _0.9 Ga _0.1 As) of the DBR layer 1106 in contact with the gate layer 1108.

  Therefore, in the conventional semiconductor light emitting device 1000, as shown in FIG. 9, the symmetry of the band gap across the gate layer 1112 (and the light emitting layer 1110) in the NPN transistor and the gate layer 1108 (and light emission in the PNP transistor). The band gap symmetry across the layer 1110) is different.

  That is, in the conventional semiconductor light emitting device 1000, the PNP type transistor and the NPN type transistor have different characteristics. When the characteristics of the two transistors are different as in the conventional semiconductor light emitting device 1000, particularly when the difference in characteristics is large, the carrier injection efficiency is low.

  On the other hand, as described above, in the semiconductor light emitting device 100 of the present embodiment, the characteristics of the PNP transistor and the NPN transistor are the same. When the characteristics of both transistors are the same, the carrier injection efficiency is higher than when the characteristics are different.

  In the semiconductor light emitting device, when the carrier injection efficiency is low, the threshold voltage may increase. The threshold voltage of the conventional semiconductor light emitting device 1000 is 5.0 V or higher, whereas the threshold voltage of the semiconductor light emitting device 100 of the present embodiment is 4.5 V (see FIG. 5 above). Thus, in the semiconductor light emitting device 100 of the present embodiment, the threshold voltage is lower than that of the conventional semiconductor light emitting device 1000 by increasing the carrier injection efficiency compared to the conventional semiconductor light emitting device 1000.

As described above, in the semiconductor light emitting device 100 of this embodiment, the adjustment layer 114 that functions as a cathode is provided between the gate layer 112 and the cathode layer 116. The adjustment layer 114 has a higher Al composition ratio and a larger band gap than the cathode layer 116. The adjustment layer 114 has the same Al composition ratio and the same band gap as the semiconductor film 106A (Al _0.9 Ga _0.1 As) of the DBR layer 106 in contact with the gate layer 108.

  In the semiconductor light emitting device 100 of the present embodiment, the symmetry of the band gap across the gate layer 112 (and the light emitting layer 110) in the NPN transistor and the gate layer 108 (and the light emitting layer 110) in the PNP transistor are sandwiched. The symmetry of the band gap is the same. Thereby, the characteristics of the NPN transistor and the PNP transistor are the same. In the semiconductor light emitting device 100 of the present embodiment, since the characteristics of the PNP transistor and the NPN transistor are the same, the carrier injection efficiency is improved.

  Therefore, in the semiconductor light emitting device 100 of the present embodiment, the threshold voltage is lower than that of the conventional semiconductor light emitting device 1000 in which the symmetry of both the PNP type and NPN type transistors is different.

  Further, in the semiconductor light emitting device 100 of the present embodiment, since the adjustment layer 114 is a layer (single layer) made of a single semiconductor film, carrier injection is performed compared to the case where the adjustment layer is formed of a plurality of semiconductor layers. Efficiency is improved. As a semiconductor light emitting device in which a plurality of semiconductor films are provided between a gate layer and a cathode layer, for example, in Patent Document 2, a semiconductor light emitting device in which a phase shift layer is provided between a gate layer and a cathode layer. Is described. The phase shift layer includes a plurality of pairs of AlGaAs semiconductor films having different Al composition ratios. As described above, in the semiconductor light emitting device described in Patent Document 2, the phase shift layer includes a pair of semiconductor films having different Al composition ratios and a plurality of pairs. Therefore, the phase shift layer is formed of a plurality of semiconductor layers. Since the semiconductor light emitting element described in Patent Document 2 is formed of a plurality of semiconductor layers, the film thickness is increased. Due to the increase in film thickness, the semiconductor light-emitting element described in Patent Document 2 has a higher resistance and less carrier injection than the semiconductor light-emitting element 100 of the present embodiment, resulting in lower carrier injection efficiency.

  As described above, in the semiconductor light emitting device 100 of the present embodiment, since the adjustment layer 114 is a single layer, the resistance is lower and the carrier injection efficiency is higher than in the case of using a plurality of layers. Therefore, the thyristor characteristic is improved in the semiconductor light emitting device 100 of the present embodiment.

  Further, in the semiconductor light emitting device 100 of the present embodiment, since the adjustment layer 114 is a single layer, the manufacturing is easier and the manufacturing yield is improved and the manufacturing cost is increased as compared with the case where there are a plurality of layers. Suppress.

  In addition, this Embodiment is an example of this invention, and it cannot be overemphasized that it can change according to a condition within the range which does not deviate from the main point of this invention.

  For example, in this embodiment, the Al composition ratio of the adjustment layer 114 is set to 0.9, which is the same as that of the semiconductor film of the DBR layer 106 in contact with the gate layer 108, but is not limited thereto. For example, the Al composition ratio of the adjustment layer 114 may be higher than the Al composition ratio of the cathode layer 116 and lower than the semiconductor film 106A of the DBR layer 106 in contact with the gate layer 108. Thus, even if the Al composition ratio of the adjustment layer 114 is different from that of the semiconductor film of the DBR layer 106 in contact with the gate layer 108, the Al composition ratio is higher than that of the cathode layer 116 between the gate layer 112 and the cathode layer 116. By providing the adjustment layer 114 having a high (a large band gap), an effect of suppressing the threshold voltage can be obtained as compared with the case where the adjustment layer 114 is not provided. Note that the Al composition ratio of the adjustment layer 114 is preferably within a range in which the difference in characteristics between the PNP transistor in the semiconductor light emitting device 100 and the NPN transistor including the adjustment layer 114 does not affect the threshold voltage.

  The thickness of the adjustment layer 114 is not limited to the thickness described in this embodiment. The film thickness of the adjustment layer 114 may be determined according to the characteristics of the semiconductor light emitting device 100, the characteristics of the NPN transistor including the adjustment layer 114, and the like. From the viewpoint of carrier injection efficiency, the adjustment layer 114 is preferably thin.

  For example, the light emitting layer 110 may be non-doped as shown in this embodiment, or may be p-type or n-type. Note that holes are less p-type or non-doped because they have a lower mobility than electrons and thus have a small spatial expansion (expansion in the thickness direction and in-plane direction of the layer) and high luminous efficiency.

  In the present embodiment, the case where the semiconductor light emitting element 100 is a light emitting thyristor has been described. However, the present invention is not limited thereto, and may be a light emitting diode, for example. In the present embodiment, the case where the semiconductor light emitting element 100 is a PNPN type has been described. However, the present invention is not limited thereto, and may be an NPNP type, for example.

  In the present embodiment, the semiconductor light emitting device 100 using an AlGaAs-based material has been described as a specific example. However, the present invention is not limited to this, and a semiconductor using an InGaAsP-based, AlGaInP-based, InGaN / GaN-based material, or the like. You may apply with respect to a light emitting element.

  In the present embodiment, the case of applying to the light source head 16 of the self-scanning electrophotographic image forming apparatus 10 has been described. However, the present invention is not limited to this, and the semiconductor light emitting element 100 of the present embodiment is replaced with another light source. You may make it apply to a head or another image forming apparatus. Further, the semiconductor light emitting element 100 may be applied to a light source of another device such as a scanner.

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 16 Light source head 100 Semiconductor light emitting element 102 Substrate 104 Buffer layer 106 DBR layer 108 Gate layer 110 Light emitting layer 112 Gate layer 114 Adjustment layer 116 Cathode layer

Claims (4)

A first-conductivity-type multilayer reflector formed on a substrate;
A first semiconductor layer of a second conductivity type formed on the multilayer-film reflective mirror;
A second semiconductor layer of the first conductivity type formed on the first semiconductor layer;
A third semiconductor layer of the second conductivity type, which is a single film formed on the second semiconductor layer;
The second semiconductor layer is formed on the third semiconductor layer and has a band gap equal to that of the first semiconductor layer, a band gap larger than that of the second semiconductor layer, and a band gap smaller than that of the third semiconductor layer. A conductive fourth semiconductor layer;
Only including,
The multilayer mirror is an anode, the first semiconductor layer is a gate, the second semiconductor layer is a gate, the third semiconductor layer and the fourth semiconductor layer are cathodes,
The energy of electrons of the multilayer reflector in contact with the first semiconductor layer in the first transistor formed by the multilayer reflector, the first semiconductor layer, and the second semiconductor layer, and the first semiconductor layer A magnitude relationship with the energy of electrons of the second semiconductor layer in contact with the second semiconductor layer;
Energy of electrons of the first semiconductor layer in contact with the second semiconductor layer in a second transistor formed by the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer; The magnitude relationship with the energy of electrons of the third semiconductor layer in contact with the second semiconductor layer is equivalent.
Semiconductor light emitting device. The band gap of the third semiconductor layer is equal to the band gap of the multilayer reflector in contact with the first semiconductor layer.
The semiconductor light emitting device according to claim 1 . A light source head comprising the semiconductor light emitting element according to claim 1 or 2 as a light source. A photoreceptor,
Charging means for charging the surface of the photoreceptor;
An exposure unit comprising the light source head according to claim 3 and exposing with light emitted from the light source head to form an electrostatic latent image on the surface of the photoreceptor charged by the charging unit;
Developing means for developing the electrostatic latent image formed by the exposure means;
Fixing means for fixing the electrostatic latent image developed by the developing means;
An image forming apparatus.

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