JP6032131B2 - Temperature sensor circuit - Google Patents

Description

  The technology disclosed in this specification relates to a temperature sensor circuit. The technology disclosed in this specification particularly relates to a temperature sensor circuit suitable for integration into an IC.

  The pulse width of the clock signal output from the oscillation circuit often has a temperature-dependent characteristic that varies with temperature. A temperature sensor circuit that measures temperature using this temperature-dependent characteristic has been developed, and examples thereof are disclosed in Patent Documents 1 and 2.

  This type of temperature sensor circuit includes two oscillation circuits. One oscillation circuit generates a temperature-dependent clock signal, and the other oscillation circuit generates a temperature-independent reference clock signal. This type of temperature sensor circuit is characterized in that temperature information is obtained by measuring fluctuations in the pulse width of a temperature-dependent clock signal using a reference clock signal.

JP 2007-187659 A JP 2009-236603 A

  As described above, this type of temperature sensor circuit requires a highly accurate reference clock signal that does not have temperature dependent characteristics. However, in practice, it is difficult to generate a highly accurate reference clock signal due to the influence of process variations. There is a need for a temperature sensor circuit that can obtain temperature information without using a reference clock signal.

  The temperature sensor circuit disclosed in this specification includes an oscillation circuit, a delay circuit, a delay time measurement circuit, and a current adjustment circuit. The oscillation circuit includes a ring oscillator in which a plurality of CMOS inverters are connected in a ring shape, and generates a clock signal. The delay circuit has an inverter chain in which a plurality of CMOS inverters are connected in series, and generates a delay signal using a clock signal. The delay time measuring circuit measures the delay time of the delay signal based on the number of clocks of the clock signal. The current adjustment circuit is connected to at least one of the output terminal of the CMOS inverter of the ring oscillator and the output terminal of the CMOS inverter of the inverter chain. In the temperature sensor circuit disclosed in this specification, the clock measured by the delay time measurement circuit based on the difference between the temperature dependency characteristic with respect to the temperature of the pulse width of the clock signal and the temperature dependency characteristic with respect to the temperature of the delay time of the delay signal. The number is configured to vary with temperature.

  The temperature sensor circuit is characterized by utilizing the difference in temperature dependence characteristics of the pulse width of the clock signal and the delay time of the delay signal. For this reason, even if the delay time of the delay signal is measured using a clock signal having temperature dependent characteristics, the number of clocks to be measured can vary depending on the temperature, so temperature information can be obtained from the number of clocks. It is done. According to the temperature sensor circuit, temperature information can be obtained without using a highly accurate reference clock signal that does not have temperature dependent characteristics. Further, since the current sensor circuit is provided in the temperature sensor circuit, accurate temperature information can be obtained even in a high temperature range.

FIG. 1 is a block diagram showing an outline of a temperature sensor circuit. FIG. 2 is a diagram showing an outline of a ring oscillator included in the oscillation circuit. FIG. 3 is a diagram schematically showing an inverter chain included in the delay circuit. FIG. 4 is a circuit diagram of a CMOS inverter constituting the ring oscillator and the inverter chain. FIG. 5 is a diagram showing temperature-dependent characteristics of the count number measured by the delay time measuring circuit. FIG. 6A shows an operation waveform at a low temperature Ta in the comparative example. FIG. 6B shows an operation waveform at a high temperature Ta in the comparative example. FIG. 7A shows an operation waveform at a low temperature Ta in the embodiment. FIG. 7B shows an operation waveform at a high temperature Ta in the embodiment. FIG. 8 is a block diagram showing an outline of a temperature sensor circuit using a binary counter. FIG. 9 shows the temperature dependence characteristics of the digital output value in the comparative example. FIG. 10 shows the temperature dependence characteristics of the digital output value in the embodiment. FIG. 11 is a schematic cross-sectional view of a CMOS inverter constituting a ring oscillator and an inverter chain. FIG. 12 shows the relationship between temperature and delay time when the gate width of the p-type MOSFET constituting the CMOS inverter is used as a parameter. FIG. 13 shows the relationship between temperature and delay time when the gate width of the n-type MOSFET constituting the CMOS inverter is used as a parameter. FIG. 14 shows an example of a countermeasure for a CMOS inverter in which the rate of change in delay time increases or decreases in a high temperature range. FIG. 15 shows a relationship between an ideal temperature and a delay time of the CMOS inverter constituting the ring oscillator and the inverter chain. FIG. 16A shows an example of a countermeasure when the change rate of the delay time of the CMOS inverter constituting the inverter chain greatly increases in the high temperature range. FIG. 16B shows an example of a countermeasure when the rate of change of the delay time of the CMOS inverter constituting the inverter chain is greatly reduced in the high temperature range. FIG. 17A shows an example of a countermeasure when the rate of change of the delay time of the CMOS inverter constituting the ring oscillator is greatly increased in the high temperature range. FIG. 17B shows an example of a countermeasure when the rate of change of the delay time of the CMOS inverter constituting the ring oscillator is greatly reduced in the high temperature range.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

(Feature 1) One embodiment of the temperature sensor circuit may include an oscillation circuit, a delay circuit, a delay time measurement circuit, and a current adjustment circuit. The oscillation circuit has a ring oscillator in which a plurality of CMOS inverters are connected in a ring shape, and generates a clock signal. The pulse width of the clock signal may vary with temperature. The pulse width of the clock signal may have a positive temperature-dependent characteristic that increases with temperature, or may have a negative temperature-dependent characteristic that decreases with temperature. The delay circuit has an inverter chain in which a plurality of CMOS inverters are connected in series, and generates a delay signal using a clock signal. Here, “using a clock signal” means that a delay signal may be generated by directly delaying the clock signal, or a delay signal may be generated by delaying a signal originating from the clock signal. Good. The latter example includes an example in which a delay signal is generated by delaying a low-frequency signal obtained by lowering the frequency of a clock signal. The delay time of the delay signal may also vary with temperature. The delay time of the delay signal may have a positive temperature-dependent characteristic that increases with temperature, or may have a negative temperature-dependent characteristic that decreases with temperature. When the pulse width of the clock signal has a positive temperature dependency characteristic, it is desirable that the delay time of the delay signal has a positive temperature dependency characteristic. In this embodiment, since both the oscillation circuit and the delay circuit can be constituted by CMOS (Complementary Metal Oxide Semiconductor), it is easy to make one chip. The delay time measuring circuit measures the delay time of the delay signal based on the number of clocks of the clock signal. The delay time measuring circuit may measure the delay time using an analog circuit, or may measure the delay time using a digital circuit. The delay time measuring circuit is desirably a digital circuit for simplifying the circuit configuration and reducing the size. The temperature dependency characteristic of the pulse width of the clock signal is different from the temperature dependency characteristic of the delay time of the delay signal. The current adjustment circuit is connected to at least one of the output terminal of the CMOS inverter of the ring oscillator and the output terminal of the CMOS inverter of the inverter chain. When the current adjustment circuit is provided in the ring oscillator, the current adjustment circuit may be connected to each output terminal of a plurality of CMOS inverters constituting the ring oscillator. Similarly, when the current adjustment circuit is provided in the inverter chain, the current adjustment circuit may be connected to each output terminal of a plurality of CMOS inverters constituting the inverter chain. The current adjustment circuit has a temperature characteristic and is configured to be able to adjust the rate of change of the delay time of the CMOS inverter with respect to the temperature in a high temperature range. An example of the current adjustment circuit includes a diode, a resistor, a capacitor, or a transistor such as a MOSFET.

(Feature 2) The gate length of the field effect transistor constituting the CMOS inverter of the inverter chain may be longer than the gate length of the field effect transistor constituting the CMOS inverter of the ring oscillator. In this case, the current adjustment circuit may be connected to the output terminal of the CMOS inverter of the inverter chain. When the above relationship is established for the gate length, the output of the temperature sensor circuit can have a positive temperature dependency. However, in this specification, it is confirmed that if the gate length of the field effect transistor constituting the CMOS inverter is set to be long in order to establish the above relationship, the linearity of the rate of change of the delay time with respect to the temperature of the CMOS inverter is lost. ing. Therefore, by providing a current adjustment circuit for a CMOS inverter in which the linearity of the rate of change in delay time is lost, the change in linearity of the rate of change in delay time can be improved, and accurate temperature information can be acquired. A temperature sensor circuit is realized.

(Feature 3) In Feature 2, the gate width of the p-type field effect transistor constituting the CMOS inverter of the inverter chain is longer than the gate width of the n-type field effect transistor constituting the CMOS inverter of the inverter chain. Good. In this case, the leak current value flowing through the p-type field effect transistor may be substantially equal to the total value of the leak current value flowing through the n-type field effect transistor and the current value flowing through the current adjustment circuit. According to this embodiment, in the CMOS inverter of the inverter chain, the rate of change of delay time with respect to temperature can have linearity.

(Feature 4) The field effect transistor constituting the CMOS inverter of the ring oscillator and the field effect transistor constituting the CMOS inverter of the inverter chain may be configured to have different channel length modulation effects. According to this embodiment, the temperature dependency characteristic of the ring oscillator and the temperature dependency characteristic of the inverter chain are different due to the difference in the channel length modulation effect. That is, the temperature dependence characteristic of the pulse width of the clock signal generated by the ring oscillator is different from the temperature dependence characteristic of the delay time of the delay signal generated by the inverter chain. In this embodiment, it is possible to generate a clock signal and a delay signal having different temperature-dependent characteristics only by adjusting the channel layout of the field effect transistor constituting the CMOS inverter of both the ring oscillator and the inverter chain.

(Feature 5) The temperature sensor circuit may further include a frequency dividing circuit that generates a low frequency signal obtained by converting the clock signal into a low frequency and provides the low frequency signal to the delay circuit. In this embodiment, the delay time can be the time difference between the rise of the low frequency signal and the rise of the delay signal.

(Characteristic 6) The frequency dividing circuit may include a plurality of stages of binary counters. In this case, the delay time measuring circuit may have a storage device configured to be able to store the count value of the binary counter. Further, the storage device may store the count value of the binary counter in response to the rise of the output of the delay circuit. According to this embodiment, the number of clocks counted by the binary counter in the delay time is stored in the storage device. Further, it is desirable that the number of clocks stored in the storage device is reset by the most significant bit of the binary counter.

  As shown in FIG. 1, the temperature sensor circuit 1 is a one-chip circuit, and includes an oscillation circuit 2, a frequency dividing circuit 3, a delay circuit 4, and a delay time measuring circuit 5. The oscillation circuit 2 is configured to generate a clock signal CLK. The clock signal CLK is a rectangular wave with a duty ratio of 50%, for example. The frequency dividing circuit 3 is configured to convert the clock signal CLK into a low frequency signal S1 having a low frequency. For example, the frequency dividing circuit 3 reduces the frequency of the clock signal CLK to 1/1024 times or 1/2048 times. The delay circuit 4 is configured to generate a delay signal S2 obtained by delaying the low frequency signal S1. The delay time measuring circuit 5 is configured to measure the time difference between the low frequency signal S1 and the delay signal S2 (corresponding to the delay time of the delay signal S2) based on the number of clocks of the clock signal CLK. The delay time measuring circuit 5 is configured to convert the measured number of clocks into digital temperature information Dout and output it.

  As shown in FIG. 2, the oscillation circuit 2 is composed of a ring oscillator in which a plurality of first inverters INV1 are connected in a ring shape. The ring oscillator has, for example, an 11-stage first inverter INV1.

  As shown in FIG. 3, the delay circuit 4 is composed of an inverter chain in which a plurality of second inverters INV2 are connected in series. The inverter chain has, for example, a 50-stage second inverter INV2.

  As shown in FIG. 4, the first inverter INV1 of the ring oscillator and the second inverter INV2 of the inverter chain are both connected in series between the positive power supply line (Vdd line) and the negative power supply line (Vss). A CMOS having one transistor Tr1 and a second transistor Tr2 is provided. The first transistor Tr1 is a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the drain is connected to the Vdd line, and the source is connected to the drain of the second transistor Tr2. The second transistor Tr2 is an n-type MOSFET, the drain is connected to the source of the first transistor Tr1, and the source is connected to the negative power supply line Vss. The connection point between the first transistor Tr1 and the second transistor Tr2 is connected to the gate of the transistor constituting the next stage CMOS inverter. The first parasitic diode D1 and the second parasitic diode D2 will be described in detail in the description of measures for the high temperature range described later.

  In this embodiment, the channel length modulation effect by the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator is different from the channel length modulation effect by the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. It is characterized by having. Specifically, when the gate width is constant, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are equal to the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Shorter than that. In this example, the gate length of the first transistor Tr1 of the first inverter INV1 is shorter than the gate length of the first transistor Tr1 of the second inverter INV2, and the gate length of the second transistor Tr2 of the first inverter INV1 is The gate length of the second transistor Tr2 of the second inverter INV2 is shorter. Instead of this example, only the gate length of either the first transistor Tr1 or the second transistor Tr2 of the first inverter INV1 may be short.

  Usually, the transistors Tr1 and Tr2 have a lower operating current at a higher temperature than a lower temperature, and the operating speed is reduced. For this reason, in the first inverter INV1 of the ring oscillator, the operation speed decreases at a temperature higher than the low temperature, so that the pulse width of the oscillating clock signal CLK increases. That is, the pulse width of the clock signal CLK has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Also, in the second inverter INV2 of the inverter chain, the operation speed decreases at a temperature higher than the low temperature, so the delay time of the delay signal S2 increases. That is, the delay time of the delay signal S2 also has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Here, the channel length modulation effect refers to the amount of current increase in the saturation region of the IV characteristics. For this reason, that the channel length modulation effect is different means that the amount of current increase in the saturation region of the IV characteristic is different. In this embodiment, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are shorter than the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Regarding the current increase amount at, the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are larger than the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. For this reason, when the temperature changes from low to high, the amount of current change in the transistors Tr1 and Tr2 of the ring oscillator is relatively small, and the amount of current change in the transistors Tr1 and Tr2 of the inverter chain is relatively large. As a result, when the temperature changes from low to high, the amount of decrease in the operating speed of the ring oscillator is relatively small, and the amount of decrease in the operating speed of the inverter chain is relatively large.

  The characteristics of the temperature sensor circuit 1 of this embodiment will be described with reference to FIGS. First, the operation of the temperature sensor circuit of the comparative example will be described with reference to FIGS. In the temperature sensor circuit of the comparative example, the channel length modulation effect of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator matches the channel length modulation effect of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. This is an example (the gate widths and gate lengths of the transistors Tr1 and Tr2 of both the first inverter INV1 and the second inverter INV2 match). For this reason, in the comparative example, when the temperature is changed from low temperature to high temperature, the amount of decrease in the operating speed of the ring oscillator matches the amount of decrease in the operating speed of the inverter chain, so the temperature dependence of the clock signal CLK generated by the ring oscillator The characteristics and the temperature dependence characteristics of the delay signal S2 generated by the inverter chain match. As described above, the pulse width of the clock signal CLK has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. The delay time of the delay signal S2 also has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Further, the rate of change of the pulse width of the clock signal CLK with respect to the temperature (ratio of the pulse width at an arbitrary temperature when the pulse width of the reference temperature is “1”) and the rate of change of the delay time of the delay signal S2 with respect to the temperature (reference temperature). (The ratio of the delay times at an arbitrary temperature when the delay time is “1”) is substantially equal to each other, and the temperature-dependent characteristics of the two coincide.

  As shown in FIGS. 6A and 6B, since the delay signal S2 has a positive temperature-dependent characteristic, the time difference between the low frequency signal S1 and the delay signal S2 (delay times T1 and T2 of the delay signal S2) is relatively The relatively high temperature Tb (see FIG. 5) is longer than that at the low temperature Ta (see FIG. 5). However, the pulse width of the clock signal CLK also has a positive temperature-dependent characteristic, and the temperature-dependent characteristics of the clock signal CLK and the delay signal S2 coincide with each other. The number of clocks of the clock signal CLK measured at the respective delay times T1 and T2 of the higher temperature Tb is the same number of 5. Thus, when the temperature dependency characteristic of the clock signal CLK generated by the ring oscillator matches the temperature dependency characteristic of the delay signal S2 generated by the inverter chain, the count number of the clock signal CLK is as shown in FIG. Does not vary with temperature. In the comparative example, it is difficult to measure temperature with high sensitivity.

  On the other hand, in the temperature sensor circuit 1 of this embodiment, the channel length modulation effect of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator and the channel length modulation of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. For this reason, in this embodiment, when the temperature is changed from low to high, the amount of decrease in the operating speed of the ring oscillator and the amount of decrease in the operating speed of the inverter chain are different and are generated by the ring oscillator. The temperature dependency characteristic of the clock signal CLK differs from the temperature dependency characteristic of the delay signal S2 generated by the inverter chain. As described above, the pulse width of the clock signal CLK has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. The delay time of the delay signal S2 also has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. Further, the rate of change of the delay time of the delay signal S2 with respect to the temperature (ratio of the pulse width at any temperature when the pulse width of the reference temperature is “1”) is the rate of change of the pulse width of the clock signal CLK with respect to the temperature (reference temperature). (The ratio of the delay time at an arbitrary temperature when the delay time is set to “1”), the temperature dependence characteristics of the two are different.

  For this reason, as shown in FIG. 7A, at a relatively low temperature Ta, the number of clocks of the clock signal CLK measured at the delay time T3 of the delay signal S2 is six. As shown in FIG. 7B, at the relatively high temperature Tb, the number of clocks of the clock signal CLK measured at the delay time T4 of the delay signal S2 is nine. As described above, when the temperature dependency characteristic of the clock signal CLK generated by the ring oscillator is different from the temperature dependency characteristic of the delay signal S2 generated by the inverter chain, as shown in FIG. The number of clocks measured in 5 varies with temperature. In the present embodiment, temperature information can be obtained by utilizing the difference between the temperature dependency characteristic of the clock signal CLK and the temperature dependency characteristic of the delay signal S2.

(simulation result)
FIG. 8 shows the configuration of the temperature sensor circuit 10 used for the simulation. The temperature sensor circuit 10 includes an oscillation circuit 12, a frequency divider circuit 13, a delay circuit 14, and a delay time measurement circuit 15. As illustrated in FIGS. 2 and 4, the oscillation circuit 12 is a ring oscillator including 11 stages of the first inverter INV1. The frequency dividing circuit 13 is a 10-bit binary counter composed of a NAND type D flip-flop. For this reason, the frequency dividing circuit 13 lowers the frequency of the clock signal CLK to 1/1024 times. As illustrated in FIGS. 3 and 4, the delay circuit 14 is an inverter chain including 50 stages of the second inverter INV2. The delay time measuring circuit 15 is an encoder having a storage device (11-bit × 2 latch circuit) composed of D-type flip-flops. The delay time measuring circuit 15 is configured to be able to input the counter value of the frequency dividing circuit 13. Here, the most significant bit of the frequency dividing circuit 13 is input to the delay circuit 14 and also input to the reset terminal of the storage device of the delay time measuring circuit 15. The output of the delay circuit 14 is input to the set terminal of the storage device of the delay time measurement circuit 15. The storage device of the delay time measurement circuit 15 stores the count value of the frequency divider circuit 13 when “1” is input to the set terminal, and erases the count value stored when “1” is input to the reset terminal. .

  In the first inverter INV1 of the ring oscillator, the size (W / L) of the first transistor Tr is 1 μm / 0.35 μm, and the size (W / L) of the second transistor Tr2 is 3 μm / 0.35 μm. In this simulation, in the second inverter INV2 of the inverter chain, the gate widths W of the first transistor Tr1 and the second transistor Tr2 are matched, and the gate length L is used as a parameter.

  First, the operation of the temperature sensor circuit 10 will be described. In the temperature sensor circuit 10, the count value stored in the storage device of the delay time measuring circuit 15 when the most significant bit of the frequency dividing circuit 13 becomes “1” (corresponding to the rising edge of the low frequency signal S 1). Erased. When the output of the delay circuit 14 becomes “1” (corresponding to the time when the delay signal S2 rises), the storage device of the delay time measurement circuit 15 stores the counter value of the frequency divider circuit 13. That is, the delay time measuring circuit 15 determines the number of clocks counted by the frequency dividing circuit 13 according to the clock signal CLK from the rise of the low frequency signal S1 to the rise of the delay signal S2 (corresponding to the delay time of the delay signal S2). Remember. The delay time measuring circuit 15 converts the measured number of clocks into temperature information Dout which is a digital output value, and outputs it.

  FIG. 9 shows a simulation result when the gate lengths of the first inverter INV1 and the second inverter INV2 are matched. It can be seen that the digital output value is substantially constant with respect to temperature. It is difficult to obtain temperature information with high sensitivity.

  FIG. 10 shows the results when the gate lengths of both the first transistor Tr1 and the second transistor Tr2 of the second inverter INV2 are changed to 0.35 μm, 5 μm, and 10 μm. It can be seen that the greater the gate length, the greater the digital output value varies with temperature. Thus, by changing the gate lengths of the first inverter INV1 and the second inverter INV2, the temperature dependence characteristics of the first inverter INV1 and the second inverter INV2 are different, and temperature information can be obtained based on the difference. I understand.

Hereinafter, other characteristics of the temperature sensor circuits 1 and 10 of this embodiment will be listed.
(1) The temperature sensor circuits 1 and 10 of the present embodiment are configured such that the clock signal CLK output from one oscillation circuit 2 and 12 passes through a line between circuit elements connected in series. . For example, as in the conventional temperature sensor circuit, the circuit configuration is simplified compared to the case where the temperature-dependent clock signal and the reference clock signal output from two oscillation circuits pass through two lines provided in parallel. Can be
(2) The conventional temperature sensor circuit uses the absolute value of the frequency of the temperature-dependent clock signal and the frequency of the reference clock signal, and it is necessary to adjust each frequency accurately. However, it is difficult to accurately adjust each frequency due to the influence of process variations. On the other hand, in the temperature sensor circuits 1 and 10 of the present embodiment, since the relative difference between the temperature dependency characteristic of the first inverter INV1 of the ring oscillator and the temperature dependency characteristic of the second inverter INV2 of the inverter chain is used, process variation Influence is suppressed.
(3) In the temperature sensor circuits 1 and 10 of this embodiment, all circuit elements can be configured by digital circuits. For this reason, there are merits such as easy design, flexibility in different manufacturing processes, suppression of process variations, and reduction in power consumption at a low voltage.

(Measures in high temperature range)
FIG. 11 schematically shows a cross-sectional view of CMOS inverters INV1 and INV2 (see FIG. 4) constituting the ring oscillator and the inverter chain. As shown in FIG. 11, in the first transistor Tr1 which is a p-type MOSFET, a parasitic first parasitic diode D1 exists between the p ⁺ type source and the n-type well, and the second transistor which is an n-type MOSFET. In Tr2, a parasitic second parasitic diode D2 exists between the n ⁺ -type drain and the p-type substrate.

  In the parasitic diodes D1 and D2, a reverse leakage current flows in a high temperature range. Due to this leakage current, the linearity of the temperature dependency characteristic of the clock signal CLK generated by the ring oscillator and the temperature dependency characteristic of the delay signal S2 generated by the inverter chain may be lost in a high temperature range.

  12 and 13 show the relationship between the temperature and the delay time in the inverters INV1 and INV2. In the example of FIG. 12, the gate length of the first transistor Tr1 and the second transistor Tr2 is fixed to 0.25 μm, the gate width of the second transistor Tr2 is fixed to 0.3 μm, and the gate width of the first transistor Tr1 is changed. This is the result when In the example of FIG. 13, the gate length of the first transistor Tr1 and the second transistor Tr2 is fixed to 0.25 μm, the gate width of the first transistor Tr1 is fixed to 0.9 μm, and the gate width of the second transistor Tr2 is changed. This is the result when Since the ring oscillator is composed of a plurality of first inverters INV1, the delay time of each of the first inverters INV1 affects the temperature dependence characteristics with respect to the temperature of the pulse width of the clock signal CLK generated by the ring oscillator. To do. Similarly, since the inverter chain is composed of a plurality of second inverters INV2, the delay time of each second inverter INV2 affects the temperature dependence characteristics with respect to the temperature of the delay signal S2 generated in the inverter chain.

  As shown in FIG. 12, when the gate width of the first transistor Tr1 which is a p-type MOSFET becomes longer, the linearity of the delay time with respect to the temperature is lost in the high temperature range, and the change rate of the delay time is higher in the high temperature range than in the low temperature range. It tends to decrease. On the other hand, as shown in FIG. 13, when the gate width of the second transistor Tr2 which is an n-type MOSFET becomes longer, the linearity of the delay time with respect to the temperature is lost in the high temperature range, and the change rate of the delay time is higher than that in the low temperature range. It tends to increase in range. As described above, based on the gate size (W / L) design of the first transistor Tr1 and the second transistor Tr2 constituting the inverters INV1 and INV2, the rate of change in delay time with respect to temperature may decrease in the high temperature range. In some cases, it may increase.

  For example, when the rate of change of the delay time of the first inverter INV1 constituting the ring oscillator is reduced in the high temperature range, the rate of change of the pulse width of the clock signal CLK generated by the ring oscillator with respect to temperature is also reduced in the high temperature range. At this time, when the rate of change of the delay time of the second inverter INV2 constituting the inverter chain is constant or increased in the high temperature range, the rate of change of the delay time of the delay signal S2 generated by the inverter chain is constant or increased in the high temperature range. As a result, the rate of change of the number of clocks measured by the delay time measuring circuit 15 with respect to the temperature increases in a higher temperature range than in the low temperature range, the linearity of the relationship between the clock number and the temperature collapses in the high temperature range, and accurate temperature information It becomes difficult to obtain.

  Alternatively, when the rate of change of the delay time of the first inverter INV1 constituting the ring oscillator increases in the high temperature range, the rate of change of the pulse width of the clock signal CLK generated by the ring oscillator with respect to temperature also increases in the high temperature range. At this time, when the rate of change of the delay time of the second inverter INV2 constituting the inverter chain is constant or lowered in the high temperature range, the rate of change of the delay time of the delay signal S2 generated by the inverter chain is constant or lowered in the high temperature range. As a result, the rate of change of the number of clocks measured by the delay time measuring circuit 15 with respect to the temperature decreases in a higher temperature range than in the low temperature range, the linearity of the relationship between the clock number and the temperature collapses in the high temperature range, and accurate temperature information is obtained. It becomes difficult to obtain.

  An example of countermeasures against such problems is shown in FIG. For example, the first diode D11 is connected between the output terminal and the Vdd line for the inverters INV1 and INV2 whose rate of change in delay time increases in the high temperature range. The direction of the first diode D11 is the same as that of the first parasitic diode D1 (see FIG. 4) parasitic on the first transistor Tr1 of the p-type MOSFET constituting the inverters INV1 and INV2. As illustrated in FIG. 12, the first diode D11 inserted in this direction tends to reduce the rate of change of the delay time with respect to the temperature of the inverters INV1 and INV2 in the high temperature range. As a result, in the inverters INV1 and INV2 in which the first diode D11 is inserted, the rate of change of the delay time with respect to the temperature is constant from the low temperature range to the high temperature range. Further, for the inverters INV1 and INV2 whose rate of change in delay time with respect to temperature decreases in the high temperature range, the second diode D12 is connected between the output terminal and the Vss line. The direction of the second diode D12 is the same as that of the parasitic diode D2 (see FIG. 4) parasitic on the second transistor Tr2 of the n-type MOSFET constituting the inverters INV1 and INV2. As illustrated in FIG. 13, the second diode D12 inserted in this direction tends to increase the rate of change of the delay time with respect to the temperature of the inverters INV1 and INV2 in the high temperature range. As a result, in the inverters INV1 and INV2 in which the second diode D12 is inserted, the rate of change of the delay time with respect to the temperature is constant from the low temperature range to the high temperature range.

  FIG. 15 shows ideal delay times of the inverters INV1 and INV2. In each of the first inverter INV1 of the ring oscillator and the second inverter INV2 of the inverter chain, the change rate of the delay time with respect to the temperature is constant from the low temperature range to the high temperature range, and the change rate is the same as that of the second inverter INV2 of the inverter chain. Is bigger. When such a relationship is obtained, the rate of change of the number of clocks measured by the delay time measuring circuit 15 with respect to the temperature is constant from the low temperature range to the high temperature range, and the linearity of the relationship between the clock number and the temperature is from the low temperature range. High temperature range is maintained and accurate temperature information is obtained.

  Hereinafter, various countermeasure patterns will be exemplified. In the following, the relationship between the temperature and the delay time when no countermeasure is taken is indicated by a solid line, and the relationship between the temperature and the delay time when a countermeasure is taken is indicated by a broken line.

  In the example shown in FIG. 16A, the rate of change of the delay time with respect to the temperature of the second inverter INV2 constituting the inverter chain increases in the high temperature range. In such a case, the first diode D11 may be inserted into the second inverter INV2 constituting the inverter chain to reduce the rate of change of the delay time in the high temperature range. Or you may insert the 2nd diode D12 with respect to 1st inverter INV1 of a ring oscillator, and may increase the rate of change of the delay time in a high temperature range.

  In the example shown in FIG. 16B, the rate of change of the delay time with respect to the temperature of the second inverter INV2 constituting the inverter chain decreases in the high temperature range. In such a case, the second diode D12 may be inserted into the second inverter INV2 constituting the inverter chain to increase the rate of change of the delay time in the high temperature range. Alternatively, the first diode D11 may be inserted into the first inverter INV1 of the ring oscillator to reduce the change rate of the delay time in the high temperature range.

  In the example shown in FIG. 17A, the rate of change of the delay time with respect to the temperature of the first inverter INV1 constituting the ring oscillator increases in the high temperature range. In such a case, the second diode D12 may be inserted into the second inverter INV2 constituting the inverter chain to increase the rate of change of the delay time in the high temperature range. Alternatively, the first diode D11 may be inserted into the first inverter INV1 of the ring oscillator to reduce the change rate of the delay time in the high temperature range.

  In the example shown in FIG. 17B, the rate of change of the delay time with respect to the temperature of the first inverter INV1 constituting the ring oscillator is reduced in the high temperature range. In such a case, the first diode D11 may be inserted into the second inverter INV2 constituting the inverter chain to reduce the rate of change of the delay time in the high temperature range. Alternatively, the change rate of the delay time in the high temperature range may be increased by inserting the second diode D12 into the first inverter INV1 constituting the ring oscillator.

  16 and 17 exemplify the case where the linearity of one of the first inverter INV1 constituting the ring oscillator and the second inverter INV2 constituting the inverter chain is broken, the first inverter When the linearity of both INV1 and the second inverter INV2 is lost, it is possible to take measures by appropriately combining the techniques exemplified in FIGS.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

DESCRIPTION OF SYMBOLS 1,10: Temperature sensor circuit 2, 12: Oscillator circuit 3, 13: Dividing circuit 4, 14: Delay circuit 5, 15: Delay time measuring circuit

Claims (7)

An oscillation circuit that has a ring oscillator in which a plurality of CMOS inverters are connected in a ring shape and generates a clock signal;
A delay circuit which has an inverter chain in which a plurality of CMOS inverters are connected in series, and generates a delay signal using the clock signal;
A delay time measuring circuit for measuring the delay time of the delay signal based on the number of clocks of the clock signal;
A current adjustment circuit connected to at least one of the output terminal of the CMOS inverter of the ring oscillator and the output terminal of the CMOS inverter of the inverter chain,
The number of clocks measured by the delay time measurement circuit varies with temperature based on the difference between the temperature dependence characteristic of the pulse width of the clock signal with respect to the temperature and the temperature dependence characteristic of the delay signal with respect to the temperature of the delay time. A temperature sensor circuit configured to be. The gate length of the field effect transistor constituting the CMOS inverter of the inverter chain is longer than the gate length of the field effect transistor constituting the CMOS inverter of the ring oscillator,
The temperature sensor circuit according to claim 1, wherein the current adjustment circuit is connected to an output terminal of the CMOS inverter of the inverter chain. The gate width of the p-type field effect transistor constituting the CMOS inverter of the inverter chain is longer than the gate width of the n-type field effect transistor constituting the CMOS inverter of the inverter chain,
3. The temperature according to claim 2, wherein a leakage current value flowing through the p-type field effect transistor is substantially equal to a total value of a leakage current value flowing through the n-type field effect transistor and a current value flowing through the current adjustment circuit. Sensor circuit.   The temperature sensor circuit according to claim 1, wherein the current adjustment circuit is a diode.   5. The field effect transistor constituting the CMOS inverter of the ring oscillator and the field effect transistor constituting the CMOS inverter of the inverter chain are configured to have different channel length modulation effects. The temperature sensor circuit according to any one of the above. A frequency dividing circuit for generating a low-frequency signal obtained by converting the clock signal into a low frequency and providing the low-frequency signal to the delay circuit;
The temperature sensor circuit according to claim 1, wherein the delay time is a time difference between a rise of the low frequency signal and a rise of the delay signal. The frequency divider circuit has a multi-stage binary counter,
The delay time measuring circuit has a storage device configured to be able to store the count value of the binary counter,
The temperature sensor circuit according to claim 6, wherein the storage device stores the count value of the binary counter in response to a rise of the output of the delay circuit.

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