JP5723204B2 - Method for manufacturing semiconductor substrate - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor substrate in which a single crystal silicon layer is provided over an insulating surface and a method for manufacturing a photoelectric conversion device.

A silicon on insulator (hereinafter also referred to as “SOI”) in which a thin single crystal silicon layer is provided on an insulating surface together with a single crystal silicon substrate manufactured by thinly slicing a single crystal silicon ingot. Integrated circuits using a so-called semiconductor substrate have been developed. An integrated circuit using an SOI substrate has attracted attention as an element that reduces the parasitic capacitance between the drain of the transistor and the substrate and improves the performance of the semiconductor integrated circuit.

As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (see, for example, Patent Document 1). In the hydrogen ion addition peeling method, a microbubble layer is formed at a predetermined depth from the surface by adding hydrogen ions to a single crystal silicon substrate, the microbubble layer is used as a cleavage plane, and a thin single crystal silicon layer is formed on a base substrate. This is a method for manufacturing an SOI substrate for bonding the substrates.

The single crystal silicon layer formed by the method as described above is usually about 50 nm to 300 nm and is very thin. Therefore, the single crystal silicon layer formed by the above-described method is extremely suitable for a transistor application that requires high integration, high-speed driving, and low power consumption. On the other hand, when considering applications such as a power device and a photoelectric conversion device, a certain thickness is required for the single crystal silicon layer from the viewpoint of improvement in breakdown voltage and improvement in photoelectric conversion efficiency.

The thickness of the single crystal silicon layer formed using the hydrogen ion implantation separation method mainly depends on the acceleration voltage at the time of ion implantation. If the acceleration voltage is reduced, the ion-implanted layer is formed in a shallow region, so that the single crystal silicon layer becomes thinner. Conversely, if the acceleration voltage is increased, the single crystal silicon layer becomes thicker.

From this, it can be seen that in order to increase the thickness of the single crystal silicon layer, the acceleration voltage is simply increased. However, in reality, it is not easy to increase the acceleration voltage and form a thick single crystal silicon layer. This is because when an ion implantation apparatus suitable for mass production (an apparatus capable of realizing a large current) is used, the acceleration voltage cannot be increased beyond a certain level due to limitations on the apparatus. When an ion implantation apparatus with a small current is used, the acceleration voltage can be increased. However, it takes time to obtain a predetermined implantation amount, which is not preferable in terms of productivity. Further, when ions are accelerated at a high voltage exceeding 100 kV, harmful radiation may be generated, which is problematic in terms of safety.

In order to solve the above-described problems, a method of thickening a single crystal silicon layer by epitaxial growth rather than by an acceleration voltage at the time of ion implantation has been studied (for example, see Patent Documents 1 and 2).

In Patent Document 1, a silane-based gas is reduced by hydrogen by vapor phase growth (vapor phase epitaxial growth) using a CVD (Chemical Vapor Deposition) method, and epitaxially grown on a single crystal silicon layer at 1100 to 1200 ° C. Alternatively, epitaxial growth is performed at 600 to 900 ° C. by molecular beam epitaxy.

In Patent Document 2, an amorphous silicon layer is provided on the surface of a single crystal semiconductor layer by a plasma enhanced CVD (PECVD) method or the like. Thereafter, an amorphous silicon layer is solid-phase grown (solid-phase epitaxial growth) using the single crystal semiconductor layer as a nucleus by heat treatment at 1100 ° C. or more for 60 minutes.

In Patent Document 3, a silicon layer having high crystallinity is formed over a single crystal silicon layer. A single crystal is solid-phase epitaxially grown by forming a silicon layer with low crystallinity on a silicon layer with high crystallinity and performing heat treatment. Formation of a silicon layer with high crystallinity is performed by PECVD with a flow rate ratio of hydrogen gas to silane gas of 50 times or more. For this reason, the growth rate tends to be low. By this method, a new crystal layer of 500 nm can be formed on the single crystal silicon layer, and a Raman spectrum peak value 519.1 cm ⁻¹ and full width at half maximum (FWHM) 5.33 cm ⁻¹ are obtained. ing.

JP 2000-30995 A JP-A-11-74209 JP 2009-283923 A

In the hydrogen ion implantation separation method, a uniform single crystal silicon thin film can be formed at a low temperature. Further, the single crystal silicon substrate after the single crystal silicon thin film is separated can be reused, and resources can be effectively used.

In the case of using the hydrogen ion implantation separation method, the penetration depth of ions into the single crystal silicon substrate is determined by the ion acceleration voltage, and the thickness of the obtained single crystal silicon layer is determined. The single crystal silicon layer is desirably thick enough to increase the photoelectric conversion efficiency of the photoelectric conversion device.

On the other hand, the acceleration voltage of the ion implantation apparatus has a limitation on the apparatus, and there is a concern about generation of radiation that causes a safety problem by increasing the acceleration voltage. For this reason, it is not easy to increase the acceleration voltage and allow ions to penetrate to a desired depth in the single crystal silicon substrate. In addition, in the conventional apparatus, it is difficult to irradiate a large amount of ions while increasing the acceleration voltage, and there is a concern that the takt time may be deteriorated because it takes a long time to obtain a predetermined implantation amount.

Further, the conventional manufacturing method has a problem that it is difficult to increase the growth rate by epitaxial growth beyond a certain level. Further, in order to increase the growth rate, heat treatment must be performed at a high temperature, and it is impossible to apply to a substrate having low heat resistance.

In view of the problems as described above, it is an object to provide a semiconductor substrate having a thick silicon layer with high crystallinity with high productivity.

Another object is to provide a photoelectric conversion device having excellent photoelectric conversion characteristics while effectively using limited resources.

According to one embodiment of the present invention, a single crystal silicon layer provided over a base substrate through an insulating layer is prepared, a substrate temperature is higher than 280 ° C., and the deposition gas containing silicon is not diluted. A silicon layer partially including a needle crystal region having the same crystal orientation as that of the single crystal silicon layer is formed by PECVD method used in the above process, and the needle crystal region is used as a seed crystal in the subsequent heat treatment. A solid phase growth of the part to make the silicon layer a crystalline silicon layer. Here, the deposition gas containing silicon includes SiF ₄ in addition to silane-based gases such as SiH ₄ and Si ₂ H ₆ .

In one embodiment of the present invention, a single crystal silicon layer provided over a base substrate with an insulating layer interposed therebetween is prepared, and part or all of the single crystal silicon layer is melted and recrystallized by laser beam irradiation. Then, planarization and defect recovery are performed, the substrate temperature is over 280 ° C., and the power density is less than 612 mW / cm ² , preferably 102 mW / cm ² or more and 255 mW / cm ² or less, and a silane-based gas is used. A silicon layer partially including a needle crystal region having the same crystal orientation as that of the single crystal silicon layer is formed by a PECVD method used without being diluted, and the silicon layer is formed by using the needle crystal region as a seed crystal in a subsequent heat treatment. The other part is solid-phase grown to make the silicon layer a crystalline silicon layer.

Further, according to one embodiment of the present invention, a single crystal silicon substrate is irradiated with hydrogen ions so that an embrittled region is formed at a predetermined depth from the surface, the embrittled region is used as a cleavage plane, and the single crystal silicon substrate is cleaved. Thus, a thin single crystal silicon layer is bonded to the base substrate. Next, a silicon layer partially including a needle crystal region having the same crystal orientation as the single crystal silicon layer is formed on the single crystal silicon layer of the thin film constituting the semiconductor substrate, and the needle crystal is then subjected to heat treatment. Using the region as a seed crystal, the other part of the silicon layer is solid-phase-grown to form the silicon layer as a crystalline silicon layer. The silicon layer can be formed by a PECVD method using a silane-based gas without diluting, a substrate temperature exceeding 280 ° C. and less than the strain point of the base substrate, and a power density of less than 612 mW / cm ² . When the substrate temperature exceeds 280 ° C., the migration of film formation species on the substrate surface is likely to occur, and a needle-like crystal region having the same crystal orientation as that of the single crystal silicon layer that is the base can be formed. On the other hand, when the power density is 612 mW / cm ² or more, the deposition rate exceeds the time until the crystal region is formed due to migration of the film formation species on the substrate surface, and the acicular crystal region cannot be formed. Further, the average hydrogen concentration in the silicon layer can be set to 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ , so that the distortion of the silicon layer is reduced and the peeling of the silicon layer is suppressed. can do. In addition, the density | concentration whose unit is atoms / cm < ³ > can be measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

Note that in this specification, an ion implantation method or an ion doping method can be used for the hydrogen ion irradiation step. Further, using the deposition gas containing silicon without diluting means that the intentional mixing of other gas or the like that dilutes the deposition gas containing silicon is removed. For example, mixing of other gases or the like, such as adding hydrogen or the like together with a silane-based gas to the chamber of the CVD apparatus, is excluded. In other words, using the deposition gas containing silicon in this specification without diluting means that the atmosphere in the chamber is only the deposition gas containing silicon. However, the inclusion of other components that cannot be controlled with respect to the deposition gas containing silicon is not excluded.

Note that in this specification, a single crystal refers to a crystal whose crystal structure is formed with a certain regularity and whose crystal axis is oriented in a certain direction in any part. However, the present specification does not exclude disorder of regularity such as defects and lattice distortion. Further, the same crystal orientation includes a crystal whose plane orientation has an angle fluctuation in a range of plus or minus 10 degrees.

According to one embodiment of the present invention, a semiconductor layer having a crystalline silicon layer with high crystallinity is formed by forming a silicon layer partially including a needle crystal region over a single crystal silicon layer and performing heat treatment thereafter. Can be made high. Further, according to one embodiment of the present invention, a silicon layer formed over a single crystal silicon layer is difficult to peel, so that the yield of a semiconductor substrate can be improved. In addition, by using the semiconductor substrate, it is possible to provide a photoelectric conversion device that effectively uses resources, has high productivity, has high yield, and has excellent photoelectric conversion characteristics.

Sectional drawing which shows an example of the manufacturing method of a semiconductor substrate. Sectional drawing which shows an example of the manufacturing method of a semiconductor substrate. Sectional drawing which shows an example of the manufacturing method of a semiconductor substrate. The top view and sectional drawing which show an example of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. The energy band figure corresponding to sectional drawing of the unit cell of a photoelectric conversion apparatus. The figure which shows the observation result in an Example. The figure which shows the observation result in an Example. The figure which shows the observation result in an Example. The figure which shows the observation result in an Example. The figure which shows the observation result in a comparative example. The figure which shows the observation result in a comparative example. The figure which shows the observation result in a comparative example. The figure which shows the observation result in a comparative example. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of the manufacturing method of a photoelectric conversion apparatus. Sectional drawing which shows an example of a photoelectric conversion apparatus. Sectional drawing which shows an example of a tandem photoelectric conversion apparatus. Sectional drawing which shows an example of a tandem photoelectric conversion apparatus. The energy band figure corresponding to sectional drawing of the unit cell of a tandem-type photoelectric conversion apparatus. Sectional drawing which shows an example of a stack type photoelectric conversion apparatus. FIG. 6 is a cross-sectional view of a unit cell of a stacked photoelectric conversion device and an energy band diagram corresponding to the unit cell. It is a conceptual diagram explaining the structure of a photovoltaic power generation module. It is a conceptual diagram explaining the example of a solar energy power generation system.

Embodiments and examples according to one embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples. Note that in one embodiment of the invention described below, the same portions are denoted by the same reference numerals in different drawings.

Further, the embodiment described below can be implemented in appropriate combination with the other embodiments described in this specification unless otherwise specified.

(Embodiment 1)
An example of a method for manufacturing a substrate provided with a semiconductor layer will be described with reference to FIGS. Specifically, a method for manufacturing a substrate provided with a single crystal silicon layer through an insulating layer (a method for manufacturing a semiconductor substrate) will be described.

First, a method for providing a single crystal silicon layer over a base substrate is described.

First, a single crystal silicon substrate 100 is prepared (see FIG. 1A).

As a commercially available single crystal silicon substrate, a circular substrate having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), a diameter of 12 inches (300 mm), and a diameter of 16 inches (400 mm) is representative. Any size single crystal silicon substrate can be used. Note that the shape of the single crystal silicon substrate 100 is not limited to a circular shape, and the single crystal silicon substrate 100 can be processed into a rectangular shape or the like.

Next, the insulating layer 101 is formed on the surface of the single crystal silicon substrate 100 (see FIG. 1B).

The insulating layer 101 may have a single-layer structure or a stacked structure of two or more layers, but the surface thereof preferably has a certain flatness. This is because strong bonding is realized by having a certain flatness. For example, the insulating layer 101 is formed so that the average surface roughness (Ra) is 0.5 nm or less. More preferably, it is 0.3 nm or less. The average surface roughness (Ra) in the present specification is an extension of the centerline average roughness defined in JIS B0601 so that it can be applied to the surface. Moreover, it is desirable that the outermost surface has hydrophilicity. As the insulating layer 101, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or the like can be formed. As a method for forming the insulating layer 101, a CVD method such as a PECVD method, a photo CVD method, or a thermal CVD method can be given. In particular, by applying the PECVD method, the flat insulating layer 101 having an average surface roughness (Ra) of 0.5 nm or less (preferably 0.3 nm or less) can be formed.

Note that as the insulating layer 101, a silicon oxide layer formed using an organic silane by a CVD method is particularly preferable. As the organic silane, ethyl silicate (TEOS: Si (OC ₂ H ₅ ) ₄ ), trimethylsilane (TMS: (CH ₃ ) ₃ SiH), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS) , Hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ), and the like can be used. Needless to say, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like may be formed using inorganic silane such as monosilane, disilane, or trisilane.

Here, silicon oxynitride indicates a composition having a higher oxygen content than nitrogen. For example, oxygen is 50 atomic% to 70 atomic%, and nitrogen is 0.5 atomic% to 15 atomic%. Hereinafter, silicon is contained in the range of 25 atomic% to 35 atomic% and hydrogen in the range of 0.1 atomic% to 10 atomic%. Silicon nitride oxide refers to a composition having a nitrogen content higher than that of oxygen. For example, oxygen is 5 atomic% to 30 atomic%, nitrogen is 20 atomic% to 55 atomic%, silicon In the range of 25 atomic% to 35 atomic% and hydrogen in the range of 10 atomic% to 25 atomic%. However, the above ranges are those measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). Further, the content ratio of the constituent elements takes a value that the total does not exceed 100 atomic%.

In this embodiment mode, a method for forming the insulating layer 101 (here, SiO _x ) using a thermal oxidation method is described. In this case, it is preferable that the main component gas is oxygen (O ₂ ) and is thermally oxidized in an oxidizing atmosphere containing halogen. For example, the single crystal silicon substrate 100 is subjected to thermal oxidation treatment in an oxidizing atmosphere containing chlorine (Cl), whereby the insulating layer 101 that has been chlorinated is formed. In this case, the insulating layer 101 is an insulating layer containing chlorine atoms. Chlorine atoms contained in the insulating layer 101 form strain. As a result, the moisture absorption rate of the insulating layer 101 is improved and the diffusion rate is increased. That is, when moisture exists on the surface of the insulating layer 101, the insulating layer 101 can quickly absorb and diffuse moisture present on the surface.

As an example of the thermal oxidation treatment, a temperature of 900 ° C. to 1150 ° C. in an oxidizing atmosphere containing hydrogen chloride (HCl) at a ratio of 0.5 to 10% by volume (typically 3% by volume) with respect to oxygen. (Typically 1000 ° C.). The treatment time may be 0.1 to 6 hours, preferably 0.5 to 1 hour. The thickness of the oxide film formed by the thermal oxidation treatment may be 10 nm to 1000 nm (preferably 50 nm to 300 nm), for example, 100 nm.

Next, the entire surface of the single crystal silicon substrate 100 is irradiated with hydrogen ions 103 having kinetic energy through the insulating layer 101 (see FIG. 1C). As a result, an embrittled region 105 whose crystal structure is damaged to a predetermined depth from the surface of the single crystal silicon substrate 100 can be formed (see FIG. 1D).

The hydrogen ion irradiation step can be performed by an ion doping method using an ion doping apparatus or an ion implantation method using an ion implantation apparatus.

In this embodiment, an example in which an ion doping apparatus is used to irradiate the single crystal silicon substrate 100 with ions that are not mass-separated is described. The ion doping apparatus is a non-mass separation type apparatus that irradiates an object to be processed disposed in a chamber with all ion species generated by plasma excitation of a process gas. In this specification, a method of using an ion doping apparatus to irradiate an object without mass separation of ions generated from a source gas (raw material gas) is referred to as an “ion doping method”.

The main configuration of the ion doping apparatus is a chamber in which an object to be processed is arranged, an ion source that generates desired ions, and an acceleration mechanism for accelerating and irradiating the ions. The ion source includes a gas supply device that supplies a source gas for generating a desired ion species, an electrode for generating a plasma by exciting the source gas, and the like. As an electrode for forming plasma, a filament-type electrode, an electrode for capacitively coupled high-frequency discharge, or the like is used. The acceleration mechanism includes electrodes such as an extraction electrode, an acceleration electrode, a deceleration electrode, and a ground electrode, and a power source for supplying power to these electrodes. The electrode constituting the acceleration mechanism is provided with a plurality of openings and slits, and ions generated by the ion source are accelerated through the openings and slits provided in the electrodes. Note that the configuration of the ion doping apparatus is not limited to that described above, and a mechanism according to need is provided.

As an apparatus for irradiating ions, there is an ion implantation apparatus in addition to an ion doping apparatus. An ion implantation apparatus is an apparatus (mass separation type apparatus) that mass-separates ion species in plasma and irradiates an object to be processed with ion species having a specific mass, and is greatly different from an ion doping apparatus in this respect. Is.

Subsequently, a base substrate 130 is prepared (see FIG. 1E). When using the base substrate 130, it is preferable to clean the surface of the base substrate 130 in advance. Specifically, the surface of the base substrate 130 is subjected to ultrasonic cleaning using hydrochloric acid / hydrogen peroxide (HPM), sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), dilute hydrofluoric acid (DHF), or the like. . By performing such a cleaning process, planarization of the surface of the base substrate 130 and remaining abrasive particles can be removed.

As the base substrate 130, an insulating substrate is preferably used. Specific examples of the insulating substrate include various glass substrates used in the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, quartz substrate, ceramic substrate, sapphire substrate, and plastic substrate. In addition, a single crystal semiconductor substrate (for example, a single crystal silicon substrate) or a polycrystalline semiconductor substrate (for example, a polycrystalline silicon substrate) can be used as the base substrate 130, but in view of mass productivity and cost, It is preferable to use an inexpensive insulating substrate capable of increasing the area. In this embodiment, a glass substrate which is one of insulating substrates is used as the base substrate 130.

Note that a silicon insulating layer containing nitrogen such as a silicon nitride layer or a silicon nitride oxide layer may be formed over the base substrate 130 and may be in close contact with the insulating layer 101. In this case, contamination of the semiconductor by alkali metal, alkaline earth metal, or the like from the base substrate 130 can be prevented.

Next, the single crystal silicon substrate 100 and the base substrate 130 are attached to each other with the insulating layer 101 interposed therebetween (see FIG. 1F).

Note that before the bonding, the surface of the base substrate 130 may be subjected to oxygen plasma treatment or ozone treatment to make the surface hydrophilic. By this treatment, a hydroxyl group is added to the surface of the base substrate 130, so that a hydrogen bond can be formed at the interface for bonding.

Next, heat treatment is performed to separate the single crystal silicon substrate 100 in the embrittled region 105, so that a single crystal silicon layer 131 is provided over the base substrate 130 (see FIG. 1G). By performing the heat treatment, minute holes are formed in the embrittled region 105, and elements added by ion irradiation are precipitated in the minute holes, and the pressure inside the minute holes increases. As the pressure rises, volume changes occur in minute holes in the embrittled region 105 and cracks occur in the embrittled region 105, so that the single crystal silicon substrate 100 is separated along the embrittled region 105. As a result, a single crystal silicon layer 131 separated from the single crystal silicon substrate 100 is formed over the base substrate 130 with the insulating layer 101 interposed therebetween. The thickness of the single crystal silicon layer 131 formed after the separation may be, for example, 10 nm to 500 nm, preferably 50 nm to 200 nm. Note that as a heating means for performing the heat treatment, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, heating may be performed at a heating temperature of 550 ° C. or higher and 730 ° C. or lower and a processing time of 0.5 minutes or longer and within 60 minutes.

Note that as a method for providing a single crystal silicon layer over a base substrate, the following method can be used instead of the above method. A porous silicon layer is formed by anodizing the surface of the single crystal silicon substrate. Next, a single crystal silicon layer is epitaxially grown on the porous silicon layer. Next, a silicon oxide layer is formed over the single crystal silicon layer. Next, after the base substrate and the silicon oxide layer are bonded to each other, the single crystal silicon layer 131 may be formed over the base substrate by a method of separating the single crystal silicon layer from the single crystal substrate with a water jet or the like. .

A method of epitaxially growing a crystalline silicon layer on the semiconductor substrate obtained as described above will be described with reference to FIG.

A semiconductor substrate manufactured in FIG. 1G is prepared (see FIG. 2A).

Next, a silicon layer 136 is formed over the single crystal silicon layer 131 by a PECVD method (see FIG. 2B). The silicon layer 136 is composed of an acicular crystal region 132 at the initial stage of deposition and an amorphous silicon layer 133. The needle-like crystal region 132 is formed by vapor phase epitaxial growth of crystal silicon having the same crystal orientation as that of the single crystal silicon layer 131 as a base when the silicon layer 136 is formed. That is, the acicular crystal region 132 and the amorphous silicon layer 133 constituting the silicon layer 136 are formed at a time. Note that plasma generated here is, for example, RF (3 to 30 MHz, typically 13.56 MHz, 27.12 MHz) plasma, VHF plasma (30 MHz to 300 MHz, typically 60 MHz), microwave (1 Ghz or more, Plasma (typically 2.45 GHz) can be used. The plasma is preferably generated by pulse oscillation.

The silicon layer 136 is formed using only a deposition gas containing silicon, for example, SiH ₄ as a source gas. Here, the deposition gas containing silicon includes Si ₂ H ₆ and SiF ₄ . At this time, the power density is less than 612 mW / cm ² . Preferably, it is 102 mW / cm ² or more and 255 mW / cm ² or less. For example, a high frequency power source of 60 MHz can be used. At this time, when the substrate temperature is higher than 280 ° C. and lower than the strain point of the base substrate, preferably 400 ° C. or higher and lower than the strain point of the base substrate, migration of the film formation species easily occurs on the surface of the base substrate 130, which is the base. The acicular crystal region 132 having the same crystal orientation as that of the single crystal silicon layer 131 can be formed. On the other hand, when the power density is 612 mW / cm ² or more, the deposition rate exceeds the time until the crystal region is formed due to migration of the film formation species on the substrate surface, and the acicular crystal region cannot be formed. Therefore, the power density is set so that the deposition rate is sufficiently slow with respect to the time until the crystal region is formed by migration of the film-forming species on the substrate surface. However, if the power density is too small, it takes a long time to make the thickness sufficiently thick, so it is desirable to control the power density.

Note that, due to the presence of hydrogen contained in the silicon layer, the rearrangement of silicon during solid phase epitaxial growth can proceed smoothly. When the deposition gas containing silicon is diluted with hydrogen, hydrogen atoms bonded to silicon are easily desorbed, and the amount of hydrogen in the silicon layer is reduced. Therefore, hydrogen is preferably contained in the formed amorphous silicon layer by not diluting the deposition gas containing silicon with hydrogen dilution or other gas. The deposition gas containing silicon is not limited to using SiH ₄ described above, and Si ₂ H ₆ or SiF ₄ may be used.

At this time, if the average hydrogen concentration in the amorphous silicon layer 133 is 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ , solid phase epitaxial growth is likely to proceed, and amorphous This is preferable because distortion of the quality silicon layer 133 can be reduced and peeling can be suppressed.

Other conditions for forming the silicon layer 136 using the PECVD method are a chamber internal pressure of 150 Pa, an electrode interval of 10 mm, and a SiH ₄ gas flow rate of 800 sccm. Note that the above formation conditions are merely examples, and the present embodiment is not construed as being limited thereto.

Note that before the silicon layer 136 is formed, an oxide layer such as a natural oxide layer formed on the surface of the single crystal silicon layer 131 is preferably removed. This is because when an oxide layer is present on the surface of the single crystal silicon layer 131, the epitaxial growth cannot proceed from directly above the single crystal silicon layer 131, and the crystallinity is lowered. Here, the removal of the oxide layer can be performed by exposure to a hydrofluoric acid solution or hydrogen plasma.

Thereafter, heat treatment is performed in an inert atmosphere such as nitrogen at a temperature exceeding 500 ° C. and below the base substrate strain point. For the heat treatment, a resistance heating furnace, an RTA apparatus, or a microwave heating apparatus can be used. In addition, before raising to the maximum temperature, it is preferable to hold for about 1 to 2 hours at a temperature equal to or higher than the substrate temperature at the time of forming the silicon layer and lower than the temperature at which the solid phase epitaxial growth of the silicon layer occurs. By doing so, gradual dehydrogenation occurs in the silicon layer, and the peeling of the silicon layer can be suppressed as compared with the case of rapid heating. Further, since defects are generated by dehydrogenation, a rearrangement of silicon atoms related to solid phase epitaxial growth is promoted, so that a silicon layer with higher crystallinity can be epitaxially grown. In this embodiment, heat treatment is performed for 1 hour at a temperature of 600 ° C. using a resistance heating furnace. Thereby, the amorphous silicon layer 133 is solid phase epitaxially grown. According to this embodiment, a thick crystalline silicon layer 134 can be formed (see FIG. 2C). At this time, the needle crystal region 132 functions as a seed crystal, and the upper amorphous silicon layer 133 can be epitaxially grown.

By the heat treatment for the epitaxial growth, the single crystal silicon layer 131 is simultaneously recovered with defects or the like generated during the hydrogen ion irradiation, whereby the single crystal silicon layer 135 with higher crystallinity can be obtained.

Thus, a semiconductor substrate having a thickened crystalline silicon layer can be obtained. In the present embodiment, solid phase epitaxial growth can be performed at a very low temperature as compared with a conventional method using solid phase epitaxial growth. This is due to the method of forming a silicon layer for solid phase epitaxial growth. In addition to promoting the rearrangement of silicon bonds by releasing a large amount of hydrogen in the silicon layer and releasing the hydrogen in the layer during solid phase epitaxial growth, the needle crystal region exists as a seed crystal, Solid phase epitaxial growth can be performed satisfactorily even at low temperature heat treatment.

In this embodiment, the growth rate of the epitaxially grown silicon layer can be increased, so that the throughput in manufacturing the semiconductor substrate can be improved.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor substrate having a crystalline silicon layer with higher crystallinity than that in Embodiment 1 will be described with reference to FIGS. In this embodiment mode, after the single crystal silicon layer 131 is transferred to the base substrate 130 in Embodiment Mode 1, the single crystal silicon layer 131 is recrystallized by laser beam irradiation, and at the same time, planarization and defect recovery are performed. The form is shown. Therefore, repetitive description of the same portion as in Embodiment 1 or a portion having a similar function is omitted.

As in Embodiment Mode 1, the single crystal silicon layer 131 is transferred to the base substrate 130 through the steps of FIGS. Note that as a method for providing a single crystal silicon layer over a base substrate, the following method can be used instead of the above method. A porous silicon layer is formed by anodizing the surface of the single crystal silicon substrate. Next, a single crystal silicon layer is epitaxially grown on the porous silicon layer. Next, a silicon oxide layer is formed over the single crystal silicon layer. Next, after the base substrate and the silicon oxide layer are bonded to each other, the single crystal silicon layer 131 may be formed over the base substrate by a method of separating the single crystal silicon layer from the single crystal substrate with a water jet or the like. .

Next, the single crystal silicon layer 131 is irradiated with a laser beam 140 (see FIG. 3A). By irradiating the single crystal silicon layer 131 with the laser beam 140 to melt or recrystallize part or all of the single crystal silicon layer 131, crystal defects in the single crystal silicon layer 131 can be recovered. The melting of the single crystal silicon layer by laser beam irradiation is preferably partial melting. This is because when the single crystal silicon layer is completely melted, the single crystal silicon after becoming a liquid phase may be microcrystallized due to disordered nucleation and crystallinity may be lowered. On the other hand, when the single crystal silicon layer is partially melted, crystal growth proceeds from a solid phase portion that is not melted, so that crystal defects can be recovered without reducing crystallinity. Note that in this specification, complete melting means that the single crystal silicon layer is melted to the vicinity of the lower interface to be in a liquid phase. Partial melting means that a part of the single crystal silicon layer (for example, the upper layer part) is melted to become a liquid phase, while the other (for example, the lower layer part) is not melted and remains in a solid phase.

For example, by irradiating the single crystal silicon layer 131 with the laser beam 140, at least the surface side of the single crystal silicon layer 131 is melted and recrystallized in the subsequent cooling process using the lower layer portion in the solid state as a seed layer. Turn into. In that process, a single crystal silicon layer 141 whose surface is flattened and crystal defects are recovered is formed (see FIG. 3B). As the laser beam 140, for example, it is preferable to apply a second harmonic of a XeCl excimer laser or a YAG laser.

Applying laser beam treatment as a method for reducing crystal defects in the single crystal silicon layer 131 is preferable because the base substrate 130 is not directly heated and an increase in temperature of the base substrate 130 can be suppressed. In particular, when a glass substrate with low heat resistance is applied as the base substrate 130, crystal defect recovery by laser beam treatment is preferable.

In the laser beam treatment, it is preferable that at least an irradiation region of the laser beam 140 is heated to a temperature of 250 ° C. to 600 ° C. By heating the irradiation region, the melting time by irradiation with the laser beam 140 can be lengthened, and defect recovery can be performed effectively. Although the laser beam 140 melts the surface side of the single crystal silicon layer 131, the base substrate 130 is hardly heated, so that a base substrate with low heat resistance such as a glass substrate can be used.

Next, a silicon layer 146 is formed over the single crystal silicon layer 141 by a PECVD method (see FIG. 3C). The silicon layer 146 includes a needle crystal region 142 in the initial stage of film growth and an amorphous silicon layer 143. The acicular crystal region 142 and the amorphous silicon layer 143 constituting the silicon layer 146 are formed at a time. Note that plasma generated here is, for example, RF (3 to 30 MHz, typically 13.56 MHz, 27.12 MHz) plasma, VHF plasma (30 MHz to 300 MHz, typically 60 MHz), microwave (1 Ghz or more, Plasma (typically 2.45 GHz) can be used. The plasma is preferably generated by pulse oscillation.

The silicon layer 146 is formed using only a deposition gas containing silicon, for example, SiH ₄ . At this time, the power density is less than 612 mW / cm ² . Preferably, it is 102 mW / cm ² or more and 255 mW / cm ² or less. For example, a high frequency power source of 60 MHz can be used. At this time, when the substrate temperature is higher than 280 ° C. and lower than the strain point of the base substrate, preferably 400 ° C. or higher and lower than the strain point of the base substrate, migration of the film formation species easily occurs on the surface of the base substrate 130. The acicular crystal region 142 having the same crystal orientation as that of the layer 141 can be formed. On the other hand, when the power density is 612 mW / cm ² or more, the deposition rate exceeds the time until the crystal region is formed due to migration of the film formation species on the substrate surface, and the acicular crystal region cannot be formed. Therefore, the power density is set such that the deposition rate is sufficiently slow with respect to the time until the crystal region is formed by migration of the film formation species on the substrate surface. However, if the power density is too small, it takes a long time to make the thickness sufficiently thick, so it is desirable to control the power density.

At this time, if the average hydrogen concentration in the amorphous silicon layer 143 is 2 × 10 ¹⁸ or more and less than 3.5 × 10 ²¹ , solid phase epitaxial growth is likely to proceed, and distortion of the amorphous silicon layer 143 is reduced. It is preferable because peeling can be suppressed.

Other conditions for forming the silicon layer 146 using the PECVD method are a chamber internal pressure of 150 Pa, an electrode interval of 10 mm, and a SiH ₄ gas flow rate of 800 sccm. Note that the above formation conditions are merely examples, and the present embodiment is not construed as being limited thereto.

Note that before the silicon layer 146 is formed, an oxide layer such as a natural oxide layer formed on the surface of the single crystal silicon layer 141 is preferably removed. This is because when an oxide layer is present on the surface of the single crystal silicon layer 141, epitaxial growth cannot proceed from the single crystal silicon layer 141, and crystallinity is lowered. Here, the removal of the oxide layer can be performed using a hydrofluoric acid-based solution or hydrogen plasma.

Thereafter, heat treatment is performed in an inert atmosphere such as nitrogen at a temperature exceeding 500 ° C. and below the base substrate strain point. For the heat treatment, a resistance heating furnace, an RTA apparatus, or a microwave heating apparatus can be used. In addition, before raising to the maximum temperature, it is preferable to hold for about 1 to 2 hours at a temperature equal to or higher than the substrate temperature at the time of film formation and below a temperature at which solid phase epitaxial growth occurs. In this embodiment, heat treatment is performed for 1 hour at a temperature of 600 ° C. using a resistance heating furnace. As a result, the amorphous silicon layer 143 undergoes solid phase epitaxial growth. According to this embodiment, a thick crystalline silicon layer 144 can be formed (see FIG. 3D). At this time, the needle crystal region 142 functions as a seed crystal, and the upper amorphous silicon layer 143 can be epitaxially grown.

By the laser beam irradiation, surface irregularities generated when the single crystal silicon layer 131 is separated can be reduced, and further, crystal defects generated during the hydrogen ion irradiation can be recovered. Therefore, the crystalline silicon layer 144 is flat and crystal defects can be reduced. The crystallinity of the semiconductor substrate manufactured in this embodiment will be described later in Example 1.

Through the above steps, a semiconductor substrate having a flat and thick single crystal silicon layer can be obtained. In this embodiment, the growth rate of the epitaxially grown silicon layer can be increased. In addition, since there are few surface irregularities, it is not necessary to perform another planarization process such as surface polishing, and the throughput in manufacturing a semiconductor substrate can be improved.

This embodiment can be combined with any of the other embodiments in this specification as appropriate.

(Embodiment 3)
An embodiment in which a photoelectric conversion device is manufactured using the semiconductor substrate manufactured by the method of Embodiments 1 and 2 is described. Therefore, repetitive description of the same portions as in Embodiment Modes 1 and 2 or portions having similar functions is omitted.

FIG. 4A is a schematic diagram (plan view) of the top surface of the photoelectric conversion device 200 according to this embodiment. FIG. 4B is a schematic cross-sectional view of the photoelectric conversion device 200 according to this embodiment. Note that FIG. 4B is an example of a cross-sectional view corresponding to the line OP cut in FIG.

A photoelectric conversion device 200 described in this embodiment has a structure in which an insulating layer 204, a first electrode 206, and a unit cell 220 are sequentially stacked over a base substrate 202. Here, the unit cell 220 includes a first impurity semiconductor layer 208 having one conductivity type, a single crystal silicon layer 251, a crystal silicon layer 253, and a second impurity semiconductor layer 214 having a conductivity type different from the one conductivity type. It has a laminated structure.

An auxiliary electrode 216 is formed in a region where the unit cell 220 of the first electrode 206 is not formed, thereby enabling extraction of electric energy to the outside. A second electrode 218 is formed on the unit cell 220. That is, the electrode for taking out electric energy to the outside is formed so as to be exposed on one surface of the base substrate 202. Note that the second electrode 218 has a lattice shape (comb shape, comb shape, comb tooth shape). By adopting such a shape, the light receiving area of the unit cell 220 can be sufficiently increased.

As the base substrate 202, a substrate having an insulating surface listed in the base substrate 130 described in Embodiment 1 or an insulating substrate can be used.

The insulating layer 204 has a function of bonding the base substrate 202 and the first electrode 206. In this sense, the insulating layer 204 can be referred to as a bonding layer. In addition, since the first electrode 206 is formed in contact with the unit cell 220, the unit cell 220 is fixed to the base substrate 202 by the insulating layer 204.

Note that the surface of the insulating layer 204 which is attached to the base substrate 202 (or the first electrode 206) preferably has a certain flatness. This is because strong bonding is realized by having a certain flatness. For example, the insulating layer 204 is formed so that the average surface roughness (Ra) is 0.5 nm or less. More preferably, it is 0.3 nm or less.

In the unit cell 220, the first impurity semiconductor layer 208 and the second impurity semiconductor layer 214 are silicon layers to which an impurity element imparting a predetermined conductivity type is added. Here, the first impurity semiconductor layer 208 and the second impurity semiconductor layer 214 have different conductivity types. That is, when the first impurity semiconductor layer 208 is p-type, the second impurity semiconductor layer 214 is n-type, and when the first impurity semiconductor layer 208 is n-type, the second impurity semiconductor layer 208 is n-type. The semiconductor layer 214 is p-type. As the impurity element imparting p-type, a Group 13 element such as boron or aluminum can be used. As the impurity element imparting n-type, a Group 15 element such as phosphorus or arsenic can be used.

The single crystal silicon layer 251 can be formed by dividing a single crystal silicon substrate. For example, after an ion such as hydrogen is introduced into a single crystal silicon substrate at a high concentration to form an embrittlement region, the single crystal substrate and the base substrate are bonded together, and then the single crystal silicon substrate is formed in the embrittlement region Is divided and transferred to the base substrate. After that, the single crystal silicon layer 251 can be formed by laser beam irradiation. As the single crystal silicon substrate, a single crystal silicon wafer may be used. Note that as a method for providing a single crystal silicon layer over a base substrate, the following method can be used instead of the above method. A porous silicon layer is formed by anodizing the surface of the single crystal silicon substrate. Next, a single crystal silicon layer is epitaxially grown on the porous silicon layer. Next, a silicon oxide layer is formed over the single crystal silicon layer. Next, after the base substrate and the silicon oxide layer are bonded to each other, the single crystal silicon layer 251 may be formed over the base substrate by a method of separating the single crystal silicon layer from the single crystal substrate with a water jet or the like. . As the laser beam, for example, it is preferable to apply a second harmonic of a XeCl excimer laser or a YAG laser.

The crystalline silicon layer 253 is formed based on a silicon layer formed over the single crystal silicon layer 251. Specifically, the silicon layer is subjected to heat treatment, and epitaxial growth using the single crystal silicon layer 251 as a seed crystal proceeds to form the crystalline silicon layer 253.

Here, the silicon layer to be the crystalline silicon layer 253 is formed by a method similar to that of the crystalline silicon layer 134 illustrated in FIG.

In consideration of photoelectric conversion efficiency, the combined thickness of the single crystal silicon layer 251 and the crystal silicon layer 253 is 800 nm or more, preferably 10 μm or more. The thickness of the single crystal silicon layer 251 may be 10 nm or more and 500 nm or less, preferably about 50 nm or more and 200 nm or less, and the thickness of the crystalline silicon layer 253 is 300 nm or more, preferably 10 μm or more.

Note that the single crystal silicon layer 251 and the crystalline silicon layer 253 may have different conductivity types. For example, a single crystal silicon layer 251 manufactured using a p-type single crystal silicon substrate is p-type, and a single crystal silicon layer 251 manufactured using an n-type single crystal silicon substrate is n-type. On the other hand, the crystalline silicon layer 253 is i-type (intrinsic semiconductor) when an impurity imparting conductivity type is not included in the source gas at the time of formation.

Next, an example of a method for manufacturing the photoelectric conversion device 200 according to this embodiment will be described with reference to FIGS.

First, a single crystal silicon substrate 203 is prepared. In the single crystal silicon substrate 203, an embrittled region 205 is formed in a region having a predetermined depth from one surface thereof, and a first impurity semiconductor layer 208 is formed in the vicinity of the one surface. A first electrode 206 and an insulating layer 204 are sequentially formed over one surface of the single crystal silicon substrate 203 (on the first impurity semiconductor layer 208) (see FIG. 5E).

The formation order of the embrittlement region 205, the first impurity semiconductor layer 208, the first electrode 206, and the insulating layer 204 is not particularly limited, and for example, the order shown in the following (1) to (4) may be adopted. it can.

(1) A protective layer is formed on one surface of a single crystal silicon substrate, and an impurity element imparting one conductivity type is irradiated from the surface of the protective layer to form a first impurity semiconductor on one surface side of the single crystal silicon substrate. After the layer is formed, ions are irradiated from the surface of the protective layer to form an embrittled region in a region having a predetermined depth of the single crystal silicon substrate. After the protective layer is removed, a first electrode is formed over the first impurity semiconductor layer, and an insulating layer is formed over the first electrode.

(2) After forming a protective layer on one surface of the single crystal silicon substrate and irradiating the surface of the protective layer with ions to form an embrittled region in a predetermined depth region of the single crystal silicon substrate, the protective layer A first impurity semiconductor layer is formed on one surface side of the single crystal silicon substrate by irradiating an impurity element imparting one conductivity type from the surface. After the protective layer is removed, a first electrode is formed over the first impurity semiconductor layer, and an insulating layer is formed over the first electrode.

(3) A first electrode is formed on one surface of the single crystal silicon substrate. The surface of the first electrode is irradiated with ions to form an embrittled region in a region having a predetermined depth of the single crystal silicon substrate. Further, the surface of the first electrode is irradiated with an impurity element imparting one conductivity type, so that a first impurity semiconductor layer is formed on one surface side of the single crystal silicon substrate. After that, an insulating layer is formed over the first electrode.

(4) A first electrode is formed on one surface of the single crystal silicon substrate. The surface of the first electrode is irradiated with an impurity element imparting one conductivity type, and a first impurity semiconductor layer is formed on one surface side of the single crystal silicon substrate. Further, ions are irradiated onto the surface of the first electrode to form an embrittled region in a region having a predetermined depth of the single crystal silicon substrate, and then an insulating layer is formed over the first electrode.

In the present embodiment, the case (1) will be described with reference to FIG.

First, the protective layer 207 is formed over one surface of the single crystal silicon substrate 203. Then, the surface of the protective layer 207 is irradiated with an impurity element 230 imparting one conductivity type (see FIG. 5A). As a result, the first impurity semiconductor layer 208 can be formed by adding the impurity element 230 to the single crystal silicon substrate 203 (see FIG. 5B).

The planar shape of the single crystal silicon substrate 203 is not particularly limited, but when the base substrate to be fixed later is rectangular, the single crystal silicon substrate 203 is preferably rectangular. The surface of the single crystal silicon substrate 203 is preferably mirror-polished.

As the protective layer 207, silicon oxide or silicon nitride is preferably used. As a manufacturing method, for example, a PECVD method or a sputtering method may be used. Further, the protective layer 207 can be formed by oxidizing the surface of the single crystal silicon substrate 203 with an oxidizing chemical solution or oxygen radical. Alternatively, the protective layer 207 may be formed by oxidizing the surface of the single crystal silicon substrate 203 by a thermal oxidation method. By forming the protective layer 207, when the embrittlement region is formed in the single crystal silicon substrate 203 or when the impurity element 230 imparting one conductivity type is added to the single crystal silicon substrate 203, the single crystal silicon substrate 203 is formed. It is possible to prevent the surface of the glass from being damaged.

The first impurity semiconductor layer 208 is formed by adding an impurity element 230 imparting one conductivity type to the single crystal silicon substrate 203. Note that since the protective layer 207 is formed over the single crystal silicon substrate 203, the impurity element 230 imparting one conductivity type passes through the protective layer 207 and is added to the single crystal silicon substrate 203. Here, the thickness of the first impurity semiconductor layer 208 is 10 nm to 150 nm, preferably 10 nm to 50 nm.

As the impurity element 230 imparting one conductivity type, for example, boron is used. Thus, the p-type first impurity semiconductor layer 208 can be formed. Note that the first impurity semiconductor layer 208 can also be formed by a thermal diffusion method. However, in the thermal diffusion method, high-temperature treatment at about 900 ° C. or higher is performed, and therefore, it is necessary to perform it before forming the embrittled region.

The first impurity semiconductor layer 208 formed by the above method is disposed on the surface opposite to the light incident surface. Here, in the case where a p-type substrate is used as the single crystal silicon substrate 203, the first impurity semiconductor layer 208 is a high-concentration p-type region. As a result, the high-concentration p-type region and the low-concentration p-type region are sequentially arranged from the side opposite to the light incident surface, and a back surface field (BSF) is formed. That is, electrons cannot enter the high-concentration p-type region, and carrier recombination caused by photoexcitation can be reduced.

Next, the surface of the protective layer 207 is irradiated with ions 240 (see FIG. 5C). As a result, the embrittled region 205 can be formed in the single crystal silicon substrate 203 (see FIG. 5D). Here, as the ions 240, it is preferable to use ions generated using a source gas containing hydrogen (in particular, H ⁺ , H ₂ ⁺ , H ₃ ^{+ and the} like). Note that the depth at which the embrittled region 205 is formed is controlled by the acceleration voltage when the ions 240 are irradiated. Further, the thickness of the single crystal silicon layer separated from the single crystal silicon substrate 203 is determined by the depth at which the embrittlement region 205 is formed.

The embrittlement region 205 has a depth of 500 nm or less, preferably a depth of 400 nm or less, more preferably 50 nm or more and 300 nm or less from the surface of the single crystal silicon substrate 203 (more precisely, the surface of the first impurity semiconductor layer 208). To a depth of. When the embrittled region 205 is formed in a shallow region, the separated single crystal silicon substrate remains thick, so that the number of times the single crystal silicon substrate is repeatedly used can be increased. However, in the case where the embrittled region 205 is formed in a shallow region, the acceleration voltage is lowered, so it is necessary to consider productivity and the like.

The irradiation with the ions 240 can be performed using an ion doping apparatus or an ion implantation apparatus. Since an ion doping apparatus usually does not involve mass separation, even if the single crystal silicon substrate 203 is enlarged, the entire surface of the single crystal silicon substrate 203 can be irradiated with ions 240 uniformly.

Note that since the ions 240 are irradiated through the first impurity semiconductor layer 208, the first impurity semiconductor layer 208 can also be hydrogenated.

After the embrittlement region 205 is formed, the protective layer 207 is removed, and the first electrode 206 and the insulating layer 204 are formed over the first impurity semiconductor layer 208 (see FIG. 5E).

Here, the first electrode 206 needs to be able to withstand heat treatment in a later step. Therefore, the first electrode 206 is preferably formed using a refractory metal material. For example, titanium, molybdenum, tungsten, tantalum, chromium, nickel, or the like can be used. Alternatively, a stacked structure of the above metal material and a nitride of the above metal material may be employed. For example, a stacked structure of a titanium nitride layer and a titanium layer, a stacked structure of a tantalum nitride layer and a tantalum layer, a stacked structure of a tungsten nitride layer and a tungsten layer, or the like can be used. In the case of using a stacked structure of nitride as described above, nitride is preferably formed so as to be in contact with the first impurity semiconductor layer 208. By forming nitride in this manner, adhesion between the first electrode 206 and the first impurity semiconductor layer 208 can be improved. Note that the first electrode 206 can be formed by an evaporation method or a sputtering method. The thickness is preferably 30 nm or more.

The insulating layer 204 can be formed in a manner similar to that of the insulating layer 101 described in Embodiment 1.

Note that when the surface of the first electrode 206 has a certain flatness, specifically, when the average surface roughness (Ra) is 0.5 nm or less (preferably 0.3 nm or less), insulation is performed. In some cases, the layers 204 can be attached without being formed. In this case, the insulating layer 204 may not be formed.

Next, the surface of the insulating layer 204 and the surface of the base substrate 202 are brought into close contact with each other and pressed, so that the stacked structure including the single crystal silicon substrate 203 is bonded to the base substrate 202 (FIG. 6A). reference.).

At this time, surfaces to be bonded (here, one surface of the insulating layer 204 and one surface of the base substrate 202) are sufficiently cleaned. This is because if there is minute dust or organic contamination on the surface related to the bonding, the probability of occurrence of bonding failure increases.

Note that a silicon insulating layer containing nitrogen such as a silicon nitride layer or a silicon nitride oxide layer may be formed over the base substrate 202 and may be in close contact with the insulating layer 204. Also in this case, the contamination of the semiconductor by the alkali metal or alkaline earth metal from the base substrate 202 can be prevented.

Next, heat treatment is performed to increase the bonding strength. The temperature at this time needs to be set so that the separation in the embrittled region 205 does not proceed. For example, it can be less than 400 ° C, preferably 300 ° C or less. The heat treatment time is not particularly limited, and optimal conditions may be set as appropriate based on the relationship between the processing speed and the bonding strength. As an example, heat treatment conditions of about 200 ° C. for 2 hours can be employed. Here, it is also possible to perform local heat treatment by irradiating only the region related to bonding with microwaves. Note that the heat treatment may be omitted when there is no problem in the bonding strength.

Next, the single crystal silicon layer 210 is separated from the single crystal silicon substrate 203 in the embrittlement region 205 (see FIG. 6B). The single crystal silicon substrate 203 is separated by heat treatment. The heat treatment temperature can be based on the heat resistant temperature of the base substrate 202. For example, when a glass substrate is used as the base substrate 202, the heat treatment temperature is preferably 400 ° C. or higher and 650 ° C. or lower. However, if it is a short time, you may perform the heat processing of 400 to 700 degreeC. Of course, when the heat resistant temperature of the glass substrate is higher than 700 ° C., the heat treatment temperature may be set higher than 700 ° C.

By performing the heat treatment as described above, a volume change of minute holes formed in the embrittled region 205 occurs, and a crack occurs in the embrittled region 205. As a result, the single crystal silicon substrate 203 is divided along the embrittled region 205. Since the insulating layer 204 is bonded to the base substrate 202, the single crystal silicon layer 210 separated from the single crystal silicon substrate 203 remains on the base substrate 202. In addition, this heat treatment heats the interface related to the bonding between the base substrate 202 and the insulating layer 204, so that a covalent bond is formed at the interface related to the bonding and the bonding force between the base substrate 202 and the insulating layer 204 is further improved. To do.

Note that the total thickness of the single crystal silicon layer 210 and the first impurity semiconductor layer 208 substantially corresponds to the depth at which the embrittlement region 205 is formed, and is 500 nm or less, preferably 400 nm or less, more preferably 50 nm or more and 300 nm or less.

Through the above steps, the single crystal silicon layer 210 fixed over the base substrate 202 can be obtained. Note that the separated single crystal silicon substrate 203 can be reused after being subjected to a regeneration process. The single crystal silicon substrate 203 after the regeneration treatment may be used as a substrate for obtaining a single crystal silicon layer, or may be used for other purposes. When used as a substrate for obtaining a single crystal silicon layer, a plurality of photoelectric conversion devices can be manufactured from one single crystal silicon substrate.

Next, the single crystal silicon layer 210 is irradiated with a laser beam 250 (see FIG. 6C). As a result, at least the surface side of the single crystal silicon layer 210 is melted, and the lower layer portion in the solid phase is seeded. As a layer, it is recrystallized in the subsequent cooling process (see FIG. 6D). In that process, the single crystal silicon layer 251 in which the single crystal silicon layer 210 is planarized and crystal defects are recovered can be formed. As the laser beam 250, for example, it is preferable to apply a second harmonic of a XeCl excimer laser or a YAG laser.

Applying laser beam treatment as a method for reducing crystal defects in the single crystal silicon layer 210 is preferable because the base substrate 202 is not directly heated and an increase in temperature of the base substrate 202 can be suppressed. In particular, when a glass substrate with low heat resistance is applied as the base substrate 202, crystal defect recovery by laser beam treatment is preferable.

In the laser beam treatment, it is preferable that at least a laser beam irradiation region is heated to a temperature of 250 ° C. to 600 ° C. By heating the irradiation region, the melting time by the laser beam irradiation can be lengthened, and the defect can be effectively recovered. Although the laser beam 250 melts the surface side of the single crystal silicon layer 210, the base substrate 202 is hardly heated, so that a base substrate with low heat resistance such as a glass substrate can be used.

Next, a silicon layer 256 including a needle crystal region 252 and an amorphous silicon layer 211 is formed over the single crystal silicon layer 251 (see FIG. 6E). When the silicon layer 256 is formed, the needle crystal region 252 is formed on the single crystal silicon layer 251 by vapor phase epitaxial growth. The acicular crystal region 252 stops vapor phase epitaxial growth during the growth, and the amorphous silicon layer 211 grows from the middle. This is because when a glass substrate having low heat resistance is used as the base substrate, film formation at a high temperature sufficient for complete vapor phase growth cannot be performed. In this case, the needle crystal region 252 is a silicon layer having the same crystal orientation as that of the single crystal silicon layer 251. Note that plasma generated here is, for example, RF (3 to 30 MHz, typically 13.56 MHz, 27.12 MHz) plasma, VHF plasma (30 MHz to 300 MHz, typically 60 MHz), microwave (1 Ghz or more, Plasma (typically 2.45 GHz) can be used. The plasma is preferably generated by pulse oscillation.

The silicon layer 256 is formed only with a deposition gas containing silicon, for example, SiH ₄ . At this time, the power density is less than 612 mW / cm ² . Preferably, it is 102 mW / cm ² or more and 255 mW / cm ² or less. For example, a high frequency power source of 60 MHz can be used. At this time, when the substrate temperature is higher than 280 ° C. and lower than the strain point of the base substrate, preferably 400 ° C. or higher and lower than the strain point of the base substrate, migration of the film formation species easily occurs on the surface of the base substrate 202, and single crystal silicon A needle crystal region 252 having the same crystal orientation as the layer 251 can be formed. On the other hand, when the power density is 612 mW / cm ² or more, the deposition rate exceeds the time until the crystal region is formed due to migration of the film formation species on the substrate surface, and the acicular crystal region cannot be formed. Therefore, the power density is set such that the deposition rate is sufficiently slow with respect to the time until the crystal region is formed by migration of the film formation species on the substrate surface. However, if the power density is too small, it takes a long time to make the thickness sufficiently thick, so it is desirable to control the power density.

Note that due to the presence of hydrogen contained in the amorphous silicon layer, the rearrangement of silicon during solid phase epitaxial growth can proceed smoothly. When the deposition gas containing silicon is diluted with hydrogen, hydrogen atoms bonded to silicon are easily desorbed, and the amount of hydrogen in the amorphous silicon layer is reduced. Therefore, it is preferable that hydrogen be contained in the formed amorphous silicon layer by not diluting with hydrogen or other gas. The deposition gas containing silicon is not limited to using SiH ₄ described above, and Si ₂ H ₆ or SiF ₆ may be used.

At this time, if the average hydrogen concentration in the amorphous silicon layer 211 is 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ , solid-phase epitaxial growth is likely to proceed, and the amorphous silicon layer 211 is amorphous. This is preferable because distortion of the silicon layer 211 can be reduced and peeling can be suppressed.

Other conditions for forming the silicon layer 256 using the PECVD method are a chamber internal pressure of 150 Pa, an electrode interval of 10 mm, and a SiH ₄ gas flow rate of 800 sccm. Note that the above formation conditions are merely examples, and the present embodiment is not construed as being limited thereto.

Note that a natural oxide layer or the like formed over the surface of the single crystal silicon layer 251 is preferably removed before the silicon layer 256 is formed.

Thereafter, heat treatment is performed in an inert atmosphere such as nitrogen at a temperature exceeding 500 ° C. and below the base substrate strain point. For the heat treatment, a resistance heating furnace, an RTA apparatus, or a microwave heating apparatus can be used. In addition, before raising to the maximum temperature, it is preferable to hold for about 1 to 2 hours at a temperature equal to or higher than the substrate temperature at the time of film formation and below a temperature at which solid phase epitaxial growth occurs. In this embodiment, heat treatment is performed at a temperature of 600 ° C. for 1 hour using a resistance heating furnace. Thereby, the amorphous silicon layer 211 is solid phase epitaxially grown. According to this embodiment, a thick crystalline silicon layer 253 can be formed (see FIG. 7A). At this time, the needle-like crystal region 252 functions as a seed crystal, and the upper amorphous silicon layer 211 can be solid-phase epitaxially grown.

Thus, a stacked structure of the single crystal silicon layer 251 and the crystal silicon layer 253 is formed. Here, in consideration of the photoelectric conversion efficiency, the photoelectric conversion device is required to have a silicon layer with a thickness of 800 nm or more and high crystallinity. Therefore, for example, when the thickness of the single crystal silicon layer 251 is 300 nm, the crystal silicon layer 253 is preferably at least 500 nm or more. Here, in order to form the crystalline silicon layer 253 having a thickness of 500 nm or more, it is not preferable from the viewpoint of formation speed to use only the vapor phase epitaxial growth method. On the other hand, when the crystalline silicon layer 253 is formed using only the solid phase epitaxial growth method, a problem of peeling of the semiconductor layer occurs due to heat treatment or the like during the solid phase growth. This is because a silicon layer (for example, an amorphous silicon layer) immediately after formation contains a large amount of hydrogen.

In the present embodiment, when the silicon layer 256 is formed, the needle crystal region 252 is formed by vapor phase epitaxial growth. After that, by performing solid phase epitaxial growth, the amorphous silicon layer 211 is changed to a crystalline silicon layer 253. At this time, by setting the substrate temperature at the time of forming the silicon layer 256 to exceed 280 ° C., the average hydrogen concentration in the film is set to 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ . Thereby, the problem of peeling of the silicon layer can be solved while ensuring the formation speed. That is, a crystalline silicon layer can be formed with high productivity and high yield.

Next, an impurity element 260 imparting a conductivity type different from that of the first impurity semiconductor layer 208 is added to one surface side of the crystalline silicon layer 253 (a surface side not in contact with the single crystal silicon layer 251) (FIG. 7B )reference.). As a result, the second impurity semiconductor layer 214 can be formed (see FIG. 7C). For example, phosphorus or arsenic is added as the impurity element 260, and the n-type second impurity semiconductor layer 214 is formed. In the case where a glass substrate is used as the base substrate 202, an impurity element is added by ion implantation or ion doping because it cannot withstand the process temperature of the thermal diffusion method.

Alternatively, the second impurity semiconductor layer 214 may be formed using amorphous silicon over the crystalline silicon layer 253. Since the region mainly functioning as a photoelectric conversion layer is formed using a single crystal silicon layer, even if the second impurity semiconductor layer 214 is formed using an amorphous semiconductor, there is no significant problem.

Note that the thickness of the second impurity semiconductor layer 214 is preferably about 20 nm to 200 nm, preferably about 10 nm to 100 nm. By forming the second impurity semiconductor layer 214 to be thin, carrier recombination in the second impurity semiconductor layer 214 can be prevented.

As described above, a unit in which the first impurity semiconductor layer 208 of one conductivity type, the single crystal silicon layer 251, the crystal silicon layer 253, and the second impurity semiconductor layer 214 having a conductivity type different from the one conductivity type are sequentially stacked. A cell 220 can be obtained.

After that, the first impurity semiconductor layer 208, the single crystal silicon layer 251, the crystal silicon layer 253, and the second impurity semiconductor layer 214 which are provided over the first electrode 206 are etched, and one of the first electrodes 206 is etched. A portion (preferably an end portion of the first electrode 206) is exposed (see FIG. 7D).

Here, part of the first electrode 206 is exposed in order to form an auxiliary electrode (or auxiliary wiring) later. In order to function as a photoelectric conversion device, it is necessary to extract electric energy from the electrodes corresponding to the positive electrode and the negative electrode, but the upper portion of the first electrode 206 is covered with a single crystal silicon layer or the like, and the first Since the base substrate 202 is provided below the electrodes, it is difficult to extract electric energy as it is. Therefore, a part of the layer formed above the first electrode 206 is etched so that a part of the first electrode 206 is exposed and an auxiliary electrode (or auxiliary wiring) that can be routed can be formed. To do.

Specifically, a mask may be formed over the second impurity semiconductor layer 214 using an insulating layer such as a resist or a silicon nitride layer, and etching may be performed using the mask. The etching can be dry etching using, for example, a fluorine-based gas such as NF ₃ or SF ₆ , and at least the first electrode 206 and the layer (the first layer formed above the first electrode 206) And the impurity semiconductor layer 208, the single crystal silicon layer 251, the crystal silicon layer 253, and the second impurity semiconductor layer 214) may be performed under such a condition that a sufficient selection ratio can be secured. Note that the unnecessary mask is removed after the etching. Further, a laser scribing method may be used instead of etching using a mask.

Although the example in which the first electrode 206 is exposed after the second impurity semiconductor layer 214 is formed is described in this embodiment mode, the second impurity semiconductor layer 214 is formed after the first electrode 206 is exposed. May be.

Next, the auxiliary electrode 216 in contact with the exposed first electrode 206 and the second electrode 218 over the second impurity semiconductor layer 214 are formed (see FIG. 7E).

The auxiliary electrode 216 is provided to facilitate extraction of photoelectrically converted electric energy. That is, the auxiliary electrode 216 functions as an extraction electrode (also referred to as a collecting electrode).

As shown in FIG. 4A, the second electrode 218 is formed to have a lattice shape (or comb shape, comb shape, or comb tooth shape) when viewed from above. By setting it as such a shape, sufficient light can enter into the unit cell 220, and the light absorption efficiency of the unit cell 220 can be improved. The shape of the second electrode 218 is not particularly limited, but the smaller the area of the second electrode 218 on the unit cell 220 (second impurity semiconductor layer 214), the more the light absorption efficiency is improved. Needless to say. Note that the second electrode 218 can be formed in the same step as the auxiliary electrode 216.

The auxiliary electrode 216 and the second electrode 218 may be formed by a printing method or the like using aluminum, silver, lead tin (solder), or the like. For example, it can be formed by a screen printing method using a silver paste.

Thus, the photoelectric conversion device 200 can be manufactured.

Note that a passivation layer 219 having an antireflection function is preferably formed on the exposed portion of the unit cell 220 and the exposed portion of the first electrode 206 (see FIG. 8).

For the passivation layer 219, a material whose refractive index is intermediate between the incident surface of the unit cell 220 (in this embodiment, the second impurity semiconductor layer 214) and air is used. In addition, a material that transmits light of a predetermined wavelength is used so as not to prevent light from entering the unit cell 220. By using such a material, reflection on the incident surface of the unit cell 220 can be prevented. Examples of such a material include silicon nitride, silicon nitride oxide, and magnesium fluoride. In addition, the presence of the passivation layer 219 can reduce carrier recombination on the surface of the crystalline silicon and can increase photoelectric conversion efficiency.

The passivation layer 219 is provided so as to cover the exposed portion of the unit cell 220 and the exposed portion of the first electrode 206. For example, after the passivation layer 219 is formed over the unit cell 220 and the first electrode 206, the passivation layer 219 is etched so that the second impurity semiconductor layer 214 and a part of the first electrode 206 are exposed. Then, an auxiliary electrode 216 in contact with the first electrode 206 and a second electrode 218 in contact with the second impurity semiconductor layer 214 are formed. Note that after the auxiliary electrode 216 and the second electrode 218 are formed, the passivation layer 219 may be formed so that the auxiliary electrode 216 and the second electrode 218 are partially exposed by etching.

FIG. 9A illustrates an example of a schematic cross-sectional view of the unit cell 220 of the photoelectric conversion device. Here, a first impurity semiconductor layer 208 (p ⁺ layer) to which a p-type impurity element is added at a high concentration, a p-type single crystal silicon layer 251 (p layer), and an i-type crystal silicon layer 253 ( i layer) and a second impurity semiconductor layer 214 to which an n-type impurity element is added (an n ⁺ layer or an n layer) are sequentially arranged. One embodiment of the disclosed invention is described here. It is not interpreted in a limited way. In the case of a single crystal silicon layer, the band gap energy is about 1.12 eV. Light (energy: hν) is incident from the second impurity semiconductor layer 214 side.

FIG. 9B is an energy band diagram of the unit cell 220 illustrated in FIG. Here, Ec indicates the bottom of the conduction band, and Ev indicates the top of the valence band. Ef represents Fermi level energy. Egc ₁ is the band gap energy in the single crystal silicon layer 251 and the crystal silicon layer 253.

Due to the band structure shown in FIG. 9B, electrons generated by photoexcitation flow in the direction of the n ⁺ layer (or n layer), and holes generated by photoexcitation flow in the direction of the p ⁺ layer. . This is the basic principle of photoelectric conversion. Here, in order to increase the efficiency of photoelectric conversion, it is important to increase the number of carriers generated by photoexcitation. In order to increase photoexcited carriers, the light absorption layer (in this embodiment, a single crystal silicon layer) may have a certain thickness. In the case where a crystalline silicon layer is used as the light absorption layer, the thickness may be set to 800 nm or more from the light absorption coefficient of the crystalline silicon layer and the spectrum of sunlight.

In this respect, in this embodiment, the thickness of the crystalline silicon layer is increased by using an epitaxial growth technique, and the single crystal silicon layer 251 and the crystalline silicon layer 253 are combined to have a thickness of 800 nm or more. Therefore, sufficient carriers can be generated in the single crystal silicon layer, and the photoelectric conversion efficiency can be improved.

As described above, by using the epitaxial growth technique described in this embodiment, a silicon layer with high crystallinity of 800 nm or more that functions as a photoelectric conversion layer can be obtained. Thereby, compared with the case where a bulk single crystal silicon substrate is used, the consumption of single crystal silicon can be suppressed. In the past, the structure supporting the photoelectric conversion device was also formed of single crystal silicon. However, by using a single crystal silicon layer obtained by slicing a single crystal silicon substrate, the consumption of single crystal silicon was greatly increased. Can be reduced. Further, since the single crystal silicon substrate after the single crystal silicon layer is separated can be repeatedly used, resources can be effectively used.

Further, in this embodiment, a silicon layer having an average hydrogen concentration of 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ is used. Accordingly, even when the single crystal silicon layer is formed thick, peeling of the single crystal silicon layer can be prevented. That is, a photoelectric conversion layer having a necessary thickness can be formed using only a minimum necessary material with a high yield.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a method for manufacturing a photoelectric conversion device, which is different from that in the above embodiment, will be described. Specifically, in the above embodiment, the formation order of the embrittlement region 205, the first impurity semiconductor layer 208, the first electrode 206, and the insulating layer 204 has been described using (1) as an example. In the embodiment, examples of (2), (3), and (4) will be described. Note that the order other than the formation order of the embrittlement region 205, the first impurity semiconductor layer 208, the first electrode 206, and the insulating layer 204 is the same as that in the above embodiment; thus, description thereof is omitted.

Hereinafter, the example (2) will be described with reference to FIG.

First, the protective layer 207 is formed over one surface of the single crystal silicon substrate 203. Then, the surface of the protective layer 207 is irradiated with ions 240 (see FIG. 18A). As a result, an embrittled region 205 is formed in the single crystal silicon substrate 203 (see FIG. 18B).

Next, the surface of the protective layer 207 is irradiated with an impurity element 230 imparting one conductivity type (see FIG. 18C). As a result, the region of the single crystal silicon substrate 203 to which the impurity element 230 is added can be the first impurity semiconductor layer 208 (see FIG. 18D). Note that since the embrittlement region 205 is already formed here, the impurity element 230 is preferably added by an ion implantation method or an ion doping method. This is because there is a high possibility that the single crystal silicon substrate 203 is separated in the embrittled region 205 when a method that requires high temperature treatment such as a thermal diffusion method is used.

After that, the protective layer 207 is removed, and the first electrode 206 is formed. After that, the insulating layer 204 is formed over the first electrode 206 (see FIG. 18E). The subsequent steps are the same as in the previous embodiment.

As described above, in (2), the embrittled region is formed by irradiating the single crystal silicon substrate to which the impurity element 230 is not added with the ions 240.

Hereinafter, the example (3) will be described with reference to FIG.

First, the first electrode 206 is formed over one surface of the single crystal silicon substrate 203, and the surface of the first electrode 206 is irradiated with ions 240 (see FIG. 19A). As a result, an embrittled region 205 is formed in the single crystal silicon substrate 203 (see FIG. 19B).

After that, the surface of the first electrode 206 is irradiated with an impurity element 230 imparting one conductivity type (see FIG. 19C). As a result, the region of the single crystal silicon substrate 203 to which the impurity element 230 is added can be the first impurity semiconductor layer 208 (see FIG. 19D).

Then, the insulating layer 204 is formed over the first electrode 206 (see FIG. 19E). The subsequent steps are the same as in the previous embodiment.

As described above, in (3), since the first electrode 206 functions as a protective layer, it is not necessary to separately provide a protective layer, which leads to shortening of the process.

Hereinafter, the example (4) will be described with reference to FIG.

First, the first electrode 206 is formed over one surface of the single crystal silicon substrate 203, and then the surface of the first electrode 206 is irradiated with the impurity element 230 imparting one conductivity type (FIG. 20A). reference.). As a result, the region of the single crystal silicon substrate 203 to which the impurity element 230 is added can be the first impurity semiconductor layer 208 (see FIG. 20B).

After that, the surface of the first electrode 206 is irradiated with ions 240 (see FIG. 20C). As a result, an embrittled region 205 is formed in the single crystal silicon substrate 203 (see FIG. 20D).

Then, the insulating layer 204 is formed over the first electrode 206 (see FIG. 20E). The subsequent steps are the same as in the previous embodiment.

As described above, in (4), since the first electrode 206 functions as a protective layer, it is not necessary to separately provide a protective layer, which leads to shortening of the process.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, another embodiment of a method for manufacturing a photoelectric conversion device will be described.

FIG. 21 shows a mode of a photoelectric conversion device in which the first electrode 206 and the base substrate 202 are directly bonded to each other. When the surface of the first electrode 206 is flat, for example, when the average surface roughness (Ra) of the surface of the first electrode 206 is 0.5 nm or less, preferably 0.3 nm or less, the insulating layer The first electrode 206 and the base substrate 202 can be bonded to each other without forming 204 (see FIG. 5 and the like).

The above bonding is performed by bringing the surface of the sufficiently cleaned first electrode 206 into close contact with the surface of the base substrate 202. Prior to bonding, the surface of the first electrode 206 or the surface of the base substrate 202 may be activated. Further, heat treatment or pressure treatment may be performed after the bonding. By forming the first electrode 206 having a flat surface as in this embodiment mode, it is not necessary to provide the insulating layer 204 and the process is shortened. Note that the above description does not exclude the formation of the insulating layer 204. For example, it can be said that forming an insulating layer or the like that functions as a blocking layer is preferable from the viewpoint of improving reliability.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, an example of a so-called tandem photoelectric conversion device in which a plurality of unit cells are stacked is described. In this embodiment, a case where two unit cells are stacked will be described.

FIG. 22 is a schematic cross-sectional view of a tandem photoelectric conversion device 300 according to this embodiment. The photoelectric conversion device 300 has a structure in which a unit cell 220 (may be referred to as a first unit cell) and a unit cell 330 (may be referred to as a second unit cell) are stacked on a base substrate 202. A first electrode 206 is provided between the base substrate 202 and the unit cell 220, and an insulating layer 204 is provided between the first electrode 206 and the base substrate 202. In this embodiment mode, the structures and manufacturing methods of the base substrate 202, the insulating layer 204, the first electrode 206, and the unit cell 220 are the same as those in Embodiment Mode 3, and thus description of overlapping portions is omitted.

The photoelectric conversion device 300 is configured such that light enters from above (in the surface side of the unit cell 330) in the drawing. Further, the band gap energy of the semiconductor layer constituting the unit cell 330 is larger than the band gap energy of the semiconductor layer constituting the unit cell 220. For example, a non-single-crystal semiconductor layer can be used for the unit cell 330, and a single-crystal semiconductor layer can be used for the unit cell 220. By laminating photoelectric conversion layers having different band gaps, a wavelength band that can be efficiently absorbed is expanded, and photoelectric conversion efficiency can be improved. In particular, sunlight has a wide wavelength band from the short wavelength side to the long wavelength side, and it is extremely effective to adopt the configuration as in this embodiment. Moreover, light can be efficiently absorbed by disposing a photoelectric conversion layer having a large band gap on the light incident side.

The unit cell 330 has a conductivity type different from that of the third impurity semiconductor layer 322, the non-single-crystal semiconductor layer 324, and the third impurity semiconductor layer 322 to which one conductivity type is imparted over the unit cell 220. In addition, the fourth impurity semiconductor layer 326 has a stacked structure. Here, the third impurity semiconductor layer 322 has a conductivity type opposite to that of the second impurity semiconductor layer 214 of the unit cell 220.

For the non-single-crystal semiconductor layer 324 of the unit cell 330, amorphous silicon, microcrystalline silicon, or the like can be used. The third impurity semiconductor layer 322 and the fourth impurity semiconductor layer 326 are an amorphous semiconductor layer or a microcrystalline semiconductor layer containing an impurity element having a predetermined conductivity type. In addition, amorphous silicon carbide or the like may be used. In the case where the third impurity semiconductor layer 322 is p-type, the fourth impurity semiconductor layer 326 is n-type, but the third impurity semiconductor layer 322 is n-type and the fourth impurity semiconductor layer 326 is p-type. It is good.

The non-single-crystal semiconductor layer 324 can be formed by a PECVD method. For example, an amorphous silicon layer may be formed using a deposition gas containing silicon. Note that the non-single-crystal semiconductor layer 324 can also be formed by a sputtering method. The non-single-crystal semiconductor layer 324 has a thickness of 50 nm to 600 nm, preferably 100 nm to 200 nm. Since the band gap of amorphous silicon is about 1.75 eV, light having a wavelength band shorter than 600 nm can be sufficiently absorbed by using such a thickness.

For the non-single-crystal semiconductor layer 324, a microcrystalline semiconductor (typically, microcrystalline silicon) may be used. In this case, a microcrystalline semiconductor is preferably formed after a very thin amorphous semiconductor layer of about several nm is formed over the unit cell 220. By doing so, it is possible to prevent the single crystal semiconductor layer from being formed due to the epitaxial growth from the single crystal semiconductor layer. Note that the third impurity semiconductor layer 322 may be formed using a single crystal semiconductor layer; in this case, a thin amorphous semiconductor layer having a thickness of about several nm is formed over the second impurity semiconductor layer 214 or the third impurity semiconductor layer 214. May be formed over the impurity semiconductor layer 322.

A first electrode 206 is provided on the base substrate 202 side of the unit cell 220, and a second electrode 332 is provided on the surface side of the unit cell 330. Further, an auxiliary electrode 317 connected to the first electrode 206 and an auxiliary electrode 319 connected to the second electrode 332 are provided. The auxiliary electrode 317 and the auxiliary electrode 319 function as extraction electrodes (also referred to as collecting electrodes) that extract electric energy converted by the photoelectric conversion layer.

In the case where the unit cell 330 is formed of a non-single crystal semiconductor, the carrier lifetime tends to be shortened, which may cause a decrease in photoelectric conversion efficiency. In order to prevent this, in this embodiment mode, the second electrode 332 is formed over the entire surface of the substrate. Here, in order to allow sufficient light to enter the unit cell 330 and the unit cell 220, the second electrode 332 is formed using a material having high sunlight transmittance. Further, the auxiliary electrode 319 in contact with the second electrode 332 has a lattice shape (or comb shape, comb shape, or comb tooth shape).

Next, an example of a method for manufacturing the photoelectric conversion device 300 according to this embodiment will be described with reference to FIGS. Note that since the manufacturing method of the second impurity semiconductor layer 214 is similar to that of Embodiment Mode 3, description thereof is omitted here.

After the second impurity semiconductor layer 214 is formed, a third impurity semiconductor layer 322, a non-single-crystal semiconductor layer 324, and a fourth impurity semiconductor layer 326 are sequentially formed over the second impurity semiconductor layer 214 ( (See FIG. 23A).

Here, the third impurity semiconductor layer 322 is an amorphous semiconductor layer or a microcrystalline semiconductor layer having a conductivity type different from that of the second impurity semiconductor layer 214. For example, when the second impurity semiconductor layer 214 is n-type, the third impurity semiconductor layer 322 may be a p-type amorphous semiconductor layer (for example, a p-type amorphous silicon layer) or a p-type amorphous semiconductor layer. A microcrystalline semiconductor layer (eg, a p-type microcrystalline silicon layer) is used. The thickness of the third impurity semiconductor layer 322 may be approximately 10 nm to 100 nm.

The non-single-crystal semiconductor layer 324 is preferably an intrinsic semiconductor layer that does not contain an impurity element imparting conductivity type (eg, an i-type amorphous silicon layer or an i-type microcrystalline silicon layer). The thickness is 50 nm to 600 nm, preferably 100 nm to 200 nm.

The fourth impurity semiconductor layer 326 is an amorphous semiconductor layer or a microcrystalline semiconductor layer having a conductivity type different from that of the third impurity semiconductor layer 322. For example, in the case where the third impurity semiconductor layer 322 is p-type, the fourth impurity semiconductor layer 326 is changed to an n-type amorphous semiconductor layer (eg, an n-type amorphous silicon layer) or an n-type amorphous semiconductor layer. A microcrystalline semiconductor layer (eg, an n-type microcrystalline silicon layer) is used. The thickness of the fourth impurity semiconductor layer 326 may be approximately 10 nm to 100 nm.

The third impurity semiconductor layer 322, the non-single-crystal semiconductor layer 324, and the fourth impurity semiconductor layer 326 can be formed by a CVD method or a sputtering method. Note that in the case where a non-single-crystal silicon layer is formed by a vapor deposition method such as a PECVD method, p-type can be imparted by adding diborane or the like to a source gas. On the other hand, when it is desired to impart n-type, phosphine or the like may be added to the source gas.

Through the above steps, the third impurity semiconductor layer 322 to which one conductivity type is imparted, the non-single-crystal semiconductor layer 324, and the fourth impurity semiconductor layer 326 to which a conductivity type different from that of the third impurity semiconductor layer 322 is imparted are sequentially formed. A stacked unit cell 330 can be obtained.

Next, the second electrode 332 is formed over the fourth impurity semiconductor layer 326 (see FIG. 23B). The second electrode 332 can be formed by a sputtering method or a vacuum evaporation method. The second electrode 332 is preferably formed using a material that sufficiently transmits sunlight. As the material, a metal oxide having conductivity such as indium tin oxide (ITO), indium zinc oxide, zinc oxide, tin oxide may be used. The second electrode 332 has a thickness of about 40 nm to 200 nm (preferably about 50 nm to 100 nm) and a sheet resistance of 200 Ω / sq. What is necessary is just to form so that it may become the following grade.

In this embodiment mode, the second electrode 332 is selectively formed over the unit cell 330. For example, the second electrode 332 is formed using a shadow mask. By selectively forming the second electrode 332, it can be used as an etching mask when a part (preferably an end portion) of the first electrode 206 is exposed later.

Note that the second electrode 332 may be formed using a conductive high molecular material (also referred to as a conductive polymer). As the conductive polymer material, a π-electron conjugated conductive polymer can be used. For example, polyaniline, polypyrrole, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof may be used.

Next, using the second electrode 332 as a mask, the fourth impurity semiconductor layer 326, the non-single-crystal semiconductor layer 324, the third impurity semiconductor layer 322, the second impurity semiconductor layer 214, the crystalline silicon layer 253, the single crystal The silicon layer 251 and the first impurity semiconductor layer 208 are etched to expose part of the first electrode 206 (see FIG. 23C).

The above etching may be dry etching using a fluorine-based gas such as NF ₃ or SF ₆ , and the first electrode 206 and the stack formed above the first electrode 206 (unit cell 220 and What is necessary is just to carry out on the conditions which can fully ensure the selection ratio with each layer which comprises the unit cell 330). Here, since the second electrode 332 can be used as a mask, it is not necessary to newly provide an etching mask. Of course, the mask may be formed using a resist or an insulating layer. Further, a laser scribing method may be used instead of etching using a mask.

After that, an auxiliary electrode 317 connected to the first electrode 206 and an auxiliary electrode 319 connected to the second electrode 332 are formed (see FIG. 23D).

The auxiliary electrode 319 is formed in a lattice shape (or a comb shape, a comb shape, or a comb tooth shape) as viewed from above, like the second electrode 218 shown in FIG. By setting it as such a shape, sufficient light can enter into the unit cell 330 and the unit cell 220, and light absorption efficiency can be improved. The auxiliary electrode 317 is formed in contact with the first electrode 206 exposed by the previous etching.

The auxiliary electrode 317 and the auxiliary electrode 319 may be formed by a method such as a printing method using aluminum, silver, lead tin (solder), or the like. For example, it can be formed by a screen printing method using a silver paste.

Through the above steps, a so-called tandem photoelectric conversion device 300 can be manufactured.

Although not shown in this embodiment mode, it is preferable to form a passivation layer similar to the passivation layer 219 shown in FIG. 8 having an antireflection function also for the tandem photoelectric conversion device 300.

FIG. 24A illustrates an example of a schematic cross-sectional view of the unit cell 220 and the unit cell 330 of the photoelectric conversion device. Here, a first impurity semiconductor layer 208 (p ⁺ layer) to which a p-type impurity element is added at a high concentration, a p-type single crystal silicon layer 251 (p layer), and an i-type crystal silicon layer 253 ( unit cell 220 in which an i layer) and a second impurity semiconductor layer 214 to which an n-type impurity element is added (an n ⁺ layer or an n layer) are sequentially stacked, and a p-type third impurity semiconductor layer 322 ( p ⁺ layer or p layer), an i-type non-single-crystal semiconductor layer 324 (i layer), and an n-type fourth impurity semiconductor layer 326 (n ⁺ layer or n layer) are arranged in this order. Although the cell 330 is shown, one embodiment of the disclosed invention is not construed as being limited thereto. Note that when the single crystal semiconductor layer in the unit cell 220 is made of single crystal silicon, the band gap energy is about 1.12 eV, and the non-single crystal semiconductor layer in the unit cell 330 is made of amorphous silicon. In some cases, the band gap energy is about 1.75 eV. Light (energy: hν) is incident from the fourth impurity semiconductor layer 326 side.

FIG. 24B is an energy band diagram of the unit cell 220 and the unit cell 330 illustrated in FIG. Here, Ec indicates the bottom of the conduction band, and Ev indicates the top of the valence band. Ef represents Fermi level energy. Egc ₁ is the band gap energy (about 1.12 eV) in the unit cell 220, and Egc ₂ is the band gap energy (about 1.75 eV) in the unit cell 330.

Due to the band structure shown in FIG. 24B, electrons generated by photoexcitation in each unit cell flow in the direction of the n ⁺ layer (or n layer) of each unit cell. It flows in the direction of the p ⁺ layer (or p layer) of each unit cell. This is the basic principle of photoelectric conversion. Since a recombination current flows at a connection portion between the unit cell 220 and the unit cell 330, the current can be taken out to the outside.

By using the unit cell 220 having a single crystal semiconductor layer as a bottom cell, light having a wavelength of 800 nm or more can be absorbed and subjected to photoelectric conversion. In addition, by using the unit cell 330 having a non-single-crystal semiconductor layer as a top cell, it is possible to absorb and photoelectrically convert light having a wavelength of less than 800 nm, in which energy is not absorbed more efficiently than the single-crystal semiconductor layer. It becomes. By adopting a structure in which unit cells having different band gaps are stacked (so-called tandem structure), photoelectric conversion efficiency can be greatly improved.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 7)
In this embodiment, an example of a photoelectric conversion device in which a plurality of unit cells is stacked is described. Specifically, a so-called stacked photoelectric conversion device 400 in which three unit cells are stacked will be described.

FIG. 25 is a schematic cross-sectional view of the stack type photoelectric conversion device 400 according to this embodiment. The photoelectric conversion device 400 includes a unit cell 220 (may be referred to as a first unit cell), a unit cell 330 (may be referred to as a second unit cell), and a unit cell 440 (first unit cell) on the base substrate 202. 3 may be referred to as a unit cell 3). A first electrode 206 is provided between the base substrate 202 and the unit cell 220, and an insulating layer 204 is provided between the first electrode 206 and the base substrate 202. In this embodiment mode, the structures and manufacturing methods of the base substrate 202, the insulating layer 204, the first electrode 206, and the unit cell 220 are the same as those in Embodiment Mode 3, and thus description of overlapping portions is omitted. In addition, since the configuration and the manufacturing method of the unit cell 330 are the same as those in Embodiment 6, the description of the overlapping parts is omitted.

The photoelectric conversion device 400 has a structure in which light is incident from above (the surface side of the unit cell 440) in the drawing. Further, the band gap energy of the semiconductor layers constituting the unit cell 440, the unit cell 330, and the unit cell 220 is larger toward the light incident side. That is, the band gap energy is the unit cell 440, the unit cell 330, and the unit cell 220 in descending order. In this way, by making the band gap energy of each unit cell different and arranging them from the incident side in the descending order of the band gap energy, light can be efficiently absorbed.

For example, when single crystal silicon is used as the semiconductor layer constituting the unit cell 220, the band gap energy is about 1.12 eV, so that the unit cell 330 and the unit cell 440 have a larger band gap energy. Use materials. Specifically, for example, a material (such as amorphous silicon germanium) having a band gap energy of about 1.45 eV to 1.65 eV is used as the semiconductor layer of the unit cell 330, and a band is used as the semiconductor layer of the unit cell 440. A material having a gap energy of about 1.7 eV or more and 2.0 eV or less (amorphous silicon, amorphous silicon carbide, or the like) may be used.

The unit cell 440 has a conductivity type different from that of the fifth impurity semiconductor layer 442 to which one conductivity type is imparted, the non-single-crystal semiconductor layer 444, and the fifth impurity semiconductor layer 442 over the unit cell 330. The sixth impurity semiconductor layer 446 is stacked in order. Here, the fifth impurity semiconductor layer 442 has a conductivity type opposite to that of the fourth impurity semiconductor layer 326 of the unit cell 330.

A first electrode 206 is provided on the base substrate 202 side of the unit cell 220, and a second electrode 452 is provided on the surface side of the unit cell 440. In addition, an auxiliary electrode 453 connected to the first electrode 206 and an auxiliary electrode 454 connected to the second electrode 452 are provided. The auxiliary electrode 453 and the auxiliary electrode 454 function as extraction electrodes (also referred to as collecting electrodes) that extract electric energy converted by the photoelectric conversion layer.

FIG. 26A illustrates an example of a schematic cross-sectional view of the unit cell 220, the unit cell 330, and the unit cell 440 of the photoelectric conversion device. Here, a first impurity semiconductor layer 208 (p ⁺ layer) to which a p-type impurity element is added at a high concentration, a p-type single crystal silicon layer 251 (p layer), and an i-type crystal silicon layer 253 ( unit cell 220 in which an i layer) and a second impurity semiconductor layer 214 (n ⁺ layer or n layer) to which an n-type impurity element is added are sequentially stacked, a p-type third impurity semiconductor layer 322 (p ⁺ Layer or p layer), an i-type non-single-crystal semiconductor layer 324 (i layer), and an n-type fourth impurity semiconductor layer 326 (n ⁺ layer or n layer) are sequentially arranged. 330 and a p-type fifth impurity semiconductor layer 442 (p ⁺ layer or p-layer), an i-type non-single-crystal semiconductor layer 444 (i-layer), and an n-type sixth impurity semiconductor layer 446 ( n ⁺ layer or an n layer) is shown for the unit cell 440 arranged in this order, It is but one embodiment of the disclosed invention is not construed as being limited thereto.

FIG. 26B is an energy band diagram of the unit cell 220, the unit cell 330, and the unit cell 440 illustrated in FIG. Here, Ec indicates the bottom of the conduction band, and Ev indicates the top of the valence band. Ef represents Fermi level energy. Egc ₁ is the band gap energy of the unit cell 220, Egc ₂ is the band gap energy of the unit cell 330, and Egc ₃ is the band gap energy of the unit cell 440.

Due to the band structure shown in FIG. 26B, electrons generated by photoexcitation in each unit cell flow in the direction of the n ⁺ layer (or n layer) of each unit cell. It flows in the direction of the p ⁺ layer (or p layer) of each unit cell. This is the basic principle of photoelectric conversion. Since a recombination current flows in the connection portion between the unit cell 220 and the unit cell 330 and in the connection portion between the unit cell 330 and the unit cell 440, the current can be taken out to the outside.

As described above, by adopting a so-called stack type structure, a wide efficient absorption wavelength band can be taken, so that the photoelectric conversion efficiency can be greatly improved.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 8)
A photovoltaic power generation module can be manufactured using the photoelectric conversion device obtained in any of Embodiments 3 to 7, for example. In this embodiment, an example of a solar power generation module using the photoelectric conversion device described in Embodiment 3 is illustrated in FIG. The photovoltaic power generation module 1028 includes a unit cell 220 provided on the base substrate 202. Between the base substrate 202 and the unit cell 220, an insulating layer 204 and a first electrode 206 are provided from the base substrate 202 side. Further, the first electrode 206 is connected to the auxiliary electrode 216.

The auxiliary electrode 216 and the second electrode 218 are formed on one surface side of the base substrate 202 (side on which the unit cell 220 is formed), and a back electrode 1026 and a back electrode for an external terminal connector at the end of the base substrate 202 1027, respectively. FIG. 27B is a cross-sectional view corresponding to CD in FIG. 27A, in which the auxiliary electrode 216 is connected to the back electrode 1026 through the through hole of the base substrate 202, and the second electrode 218 is the back surface. A state of connection with the electrode 1027 is shown.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 9)
FIG. 28 illustrates an example of a solar power generation system using the solar power generation module 1028 described in Embodiment 7. The charge control circuit 1029 charges the storage battery 1030 using electric power supplied from one or a plurality of photovoltaic power generation modules 1028. Further, when the storage battery 1030 is sufficiently charged, the power supplied from the solar power generation module 1028 is directly output to the load 1031.

When an electric double layer capacitor is used as the storage battery 1030, a chemical reaction is not required for charging, and thus rapid charging is possible. Moreover, compared with the lead acid battery etc. which utilize a chemical reaction, a lifetime can be raised about 8 times and charging / discharging efficiency can be raised about 1.5 times. The solar power generation system described in this embodiment can be used for various loads 1031 that use electric power, such as lighting and electronic devices.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

In this example, a single crystal silicon layer formed over a glass substrate is described using one embodiment of the disclosed invention.

First, a single crystal silicon layer is formed over a glass substrate using the method described in Embodiment Mode 2. In this example, a stacked structure including a silicon oxide layer having a thickness of 100 nm and a single crystal silicon layer having a thickness of 150 nm was formed on a glass substrate having a thickness of 0.7 mm. Then, a needle crystal region and an amorphous silicon layer were formed on the single crystal silicon layer in a single step.

The conditions for forming the acicular crystal region and the amorphous silicon layer are as follows.
・ Film formation method: PECVD
・ Raw material gas: SiH ₄ (800 sccm)
-Power density (frequency): 102 mW / cm ² (60 MHz)
・ Pressure: 150Pa
・ Electrode spacing: 10 mm
-Substrate temperature: 400 ° C
・ Thickness: 1μm

At the stage where the needle crystal region and the amorphous silicon layer were formed, the characteristics of the silicon layer were investigated. Specifically, Raman spectrum evaluation, cross-section STEM (Scanning Transmission Electron Microscopy), and SIMS analysis were performed. For Raman spectrum evaluation, a double Raman spectroscope U1000 manufactured by Horiba Joban Yvon was used. For evaluation of STEM, an HD-2300 type ultra-thin film evaluation apparatus manufactured by Hitachi High-Technologies Corporation was used. For the SIMS analysis, a quadrupole secondary ion mass spectrometer PHI ADEPT1010 manufactured by ULVAC-PHI Co., Ltd. was used. In the SIMS analysis, Cs ⁺ having an acceleration voltage of 1.0 kV was irradiated as primary ions.

Thereafter, the amorphous silicon layer was crystallized by solid phase epitaxial growth. Specifically, heat treatment was performed for 1 hour at a temperature of 600 ° C. in a nitrogen atmosphere using a resistance heating furnace. At this stage, the acicular crystal region and the amorphous silicon layer were not peeled off. After the above heat treatment, Raman spectrum evaluation, cross-sectional STEM image observation, and SIMS analysis were performed.

FIG. 10A shows a cross-sectional STEM image of the sample before the heat treatment. The sample includes a glass substrate 1300, a silicon oxide layer 1301, a single crystal silicon layer 1302, a needle crystal region 1303, and an amorphous silicon layer 1304. At this time, the coating 1305 and the coating 1306 are provided to facilitate cross-sectional STEM observation. FIG. 10B is a cross-sectional STEM image of the sample enlarged from FIG. Here, the electron diffraction patterns of the portions indicated by DIFF1, DIFF2, and DIFF3 were evaluated. The magnification of FIG. 10 (A) is 50,000 times, and the magnification of FIG. 10 (B) is 200,000 times. Further, electron diffraction images in DIFF1, DIFF2, and DIFF3 in FIG. 10B are shown in FIGS. 10C, 10D, and 10E, respectively. FIG. 10C shows that DIFF1 is amorphous because no electron diffraction is observed. 10D and 10E show almost the same electron beam diffraction images, and it can be seen that the needle crystal region of DIFF2 has the same crystal orientation as the single crystal silicon layer of DIFF3. It is one of the important features in the present invention that the acicular crystal region has the same crystal orientation as the single crystal silicon layer.

FIG. 11 shows the Raman spectrum evaluation and cross-sectional STEM image of the sample. FIG. 11A shows a Raman spectrum of the sample before the heat treatment, and FIG. 11C shows a cross-sectional STEM image of the sample before the heat treatment. FIG. 11B shows a Raman spectrum of the heat-treated sample, and FIG. 11D shows a cross-sectional STEM image of the heat-treated sample. By performing the heat treatment, the acicular crystal region 1303 and the amorphous silicon layer 1304 become the crystalline silicon layer 1310. From these comparisons, it can be seen that the characteristics of the silicon layer change greatly before and after the heat treatment. For example, the peak wave number of the Raman spectrum of the sample after the heat treatment is 519.85 cm ⁻¹ and the FWHM is 3.20 cm ⁻¹ . Since the peak wave number in the Raman spectrum evaluation of single crystal silicon is 520 cm ⁻¹ , it can be seen that the epitaxially grown silicon layer has crystallinity very close to that of the single crystal.

FIG. 12 shows the SIMS analysis result of the sample before the heat treatment. FIG. 13 shows the SIMS analysis result of the sample after the heat treatment. By comparing FIG. 12 and FIG. 13, it can be seen that the average hydrogen concentration in the crystalline silicon layer after the heat treatment is reduced as compared with the amorphous silicon layer before the heat treatment. This is presumably because the Si—H bond was broken by the heat treatment of the solid phase epitaxial growth, the hydrogen in the amorphous silicon layer was desorbed, and the rearrangement of the Si—Si bond was promoted.

By using such a silicon layer with favorable crystallinity, a photoelectric conversion device having excellent characteristics can be manufactured.

(Comparative Example 1)
For comparison, an example is shown in which a silicon layer is formed on a single crystal silicon layer with a substrate temperature of 210 ° C., 280 ° C., 400 ° C. and a power density of 102 mW / cm ² , 612 mW / cm ² , and 1633 mW / cm ² .

The other silicon layer formation conditions are as follows.
・ Film formation method: PECVD
・ Raw material gas: SiH ₄ (800 sccm)
・ Power supply frequency: 60 MHz
・ Pressure: 150Pa
・ Electrode spacing: 10 mm
・ Thickness: 1μm

FIG. 14 shows a cross-sectional STEM of a sample in which a silicon layer is formed on a single crystal silicon layer at different substrate temperatures and power densities. 14A to 14C, the substrate temperature is 210 ° C. 14D to 14F, the substrate temperature is 280 ° C. In FIGS. 14G to 14I, the substrate temperature is 400.degree. In addition, in FIGS. 14A, 14D, and 14G, the power density is 102 mW / cm ² . In FIGS. 14B, 14E, and 14H, the power density is 612 mW / cm ² . In FIGS. 14C, 14F, and 14I, the power density is 1633 mW / cm ² . At this time, the acicular crystal region 1303 was observed only in FIG. Further, when heat treatment was performed at 600 ° C. for 1 hour in a nitrogen atmosphere in a resistance heating furnace, peeling of the amorphous silicon layer 1304 was observed on a part or the whole surface of the substrate except for FIG. . The peeling of the amorphous silicon layer 1304 became lighter as the substrate temperature was higher and the power density was lower.

In FIG. 14, SIMS analysis of the amorphous silicon layer 1304 was performed on a part of the sample where the amorphous silicon layer 1304 was peeled off and a sample where peeling was not caused. The hydrogen concentration at this time is shown in FIG. A solid line 1401 indicates the hydrogen concentration of the sample illustrated in FIG. 14G, a solid line 1402 indicates the hydrogen concentration of the sample illustrated in FIG. 14H, and a solid line 1403 indicates the hydrogen concentration of the sample illustrated in FIG. A solid line 1404 indicates the hydrogen concentration of the sample shown in FIG. A broken line 1405 indicates a hydrogen concentration of 3.5 × 10 ²¹ atoms / cm ³ . As for the conditions where peeling occurred, the average hydrogen concentration in the film was as high as 3.5 × 10 ²¹ atoms / cm ³ or more, and there was a possibility that the amorphous silicon layer was distorted.

In this comparative example, it was found that the conditions for forming the silicon layer are important for epitaxial growth of the crystalline silicon layer on the single crystal silicon layer. It was also found that the silicon layer on the single crystal silicon layer was easily peeled depending on the hydrogen concentration in the film. By this comparative example, it can be confirmed that the disclosed embodiment is effective in improving the yield.

(Comparative Example 2)
For comparison, an example is shown in which epitaxial growth of a crystalline silicon layer on a single crystal silicon layer is attempted using a source gas obtained by diluting SiH ₄ with H ₂ (Sample 1).

The formation conditions of the silicon layer in sample 1 are as follows.
・ Film formation method: PECVD
Source gas: SiH ₄ (290 sccm) + H ₂ (1740 sccm)
-Power density (frequency): 60 mW / cm ² (60 MHz)
-Substrate temperature: 280 ° C
・ Pressure: 140Pa
・ Electrode spacing: 15mm
・ Thickness: 500nm

The conditions for forming the silicon layer in one embodiment of the disclosed invention are described below.
・ Film formation method: PECVD
・ Raw material gas: SiH ₄ (800 sccm)
-Power density (frequency): 102 mW / cm ² (60 MHz)
-Substrate temperature: 400 ° C
・ Pressure: 150Pa
・ Electrode spacing: 10 mm
・ Thickness: 1μm

FIG. 16 shows a comparison of cross-sectional STEMs of samples before heat treatment. A cross-sectional STEM image of a sample of one embodiment of the disclosed invention is illustrated in FIG. A cross-sectional STEM image of Sample 1 is shown in FIG. FIG. 16A is composed of a needle crystal region 1303 and an amorphous silicon layer 1304, whereas FIG. 16B is composed of a crystalline silicon layer 1307 and an amorphous silicon layer 1308. . FIG. 17 shows a Raman spectrum and a cross-sectional STEM image of the sample after the heat treatment. Here, the heat treatment means heat treatment at 600 ° C. for 1 hour in a nitrogen atmosphere using a resistance heating furnace. At this time, FIG. 17A shows a Raman spectrum of the sample of the disclosed invention, and FIG. 17C shows a cross-sectional STEM image of the sample of the disclosed invention. FIG. 17B shows a Raman spectrum of Sample 1, and FIG. 17D shows a cross-sectional STEM image of Sample 1. In the sample 1, uniform solid phase epitaxial growth does not proceed by the heat treatment after formation, and a polycrystalline silicon region 1311 is formed. As a result of Raman spectrum evaluation of this silicon layer, the peak wave number was 518.90 cm ⁻¹ and the FWHM was 5.18 cm ⁻¹ . In addition, in the case of using one embodiment of the disclosed invention, the peak wave number was 519.85 cm ⁻¹ and the FWHM was 3.20 cm ⁻¹ . One embodiment of the disclosed invention is close to the peak wave number of 520 cm ⁻¹ of single crystal silicon and has a small FWHM, which indicates that crystallinity is favorable.

In contrast to the comparative example, it was found that the crystallinity of the silicon layer was excellent in one embodiment of the disclosed invention. By using a silicon layer with excellent crystallinity, a photoelectric conversion device with favorable characteristics can be manufactured.

100 single crystal silicon substrate 101 insulating layer 103 hydrogen ion 105 embrittlement region 130 base substrate 131 single crystal silicon layer 132 acicular crystal region 133 amorphous silicon layer 134 crystalline silicon layer 135 single crystal silicon layer 136 silicon layer 140 laser beam 141 Single crystal silicon layer 142 Acicular crystal region 143 Amorphous silicon layer 144 Crystal silicon layer 146 Silicon layer 200 Photoelectric conversion device 202 Base substrate 203 Single crystal silicon substrate 204 Insulating layer 205 Embrittlement region 206 First electrode 207 Protective layer 208 First impurity semiconductor layer 210 Single crystal silicon layer 211 Amorphous silicon layer 212 Crystal silicon layer 214 Second impurity semiconductor layer 216 Auxiliary electrode 218 Second electrode 219 Passivation layer 220 Unit cell 230 Impurity element 240 ON 250 laser beam 251 single crystal silicon layer 252 acicular crystal region 253 crystal silicon layer 256 silicon layer 260 impurity element 280 substrate temperature 300 photoelectric conversion device 317 auxiliary electrode 319 auxiliary electrode 322 third impurity semiconductor layer 324 non-single crystal semiconductor layer 326 Fourth impurity semiconductor layer 330 Unit cell 332 Second electrode 400 Photoelectric conversion device 440 Unit cell 442 Fifth impurity semiconductor layer 444 Non-single crystal semiconductor layer 446 Sixth impurity semiconductor layer 452 Second electrode 453 Auxiliary electrode 454 Auxiliary electrode 550 Heating temperature 1026 Back surface electrode 1027 Back surface electrode 1028 Photovoltaic power generation module 1029 Charge control circuit 1030 Storage battery 1031 Load 1300 Glass substrate 1301 Silicon oxide layer 1302 Single crystal silicon layer 1303 Needle crystal region 304 amorphous silicon layer 1305 coated 1306 coating 1307 crystal silicon layer 1308 amorphous silicon layer 1310 crystal silicon layer 1401 solid 1402 solid 1403 solid 1404 solid 1405 dashed

Claims (3)

Prepare an SOI substrate having a single crystal silicon layer over an insulating film on a base substrate,
A silicon layer is formed on the single crystal silicon layer by a plasma enhanced CVD method using a source gas of 100% deposition gas,
The silicon layer has an acicular crystal region and an amorphous region, and a hydrogen concentration in the silicon layer is 2 × 10 ¹⁸ atoms / cm ³ or more and less than 3.5 × 10 ²¹ atoms / cm ³ ,
A method for manufacturing a semiconductor substrate, wherein the acicular crystal region is used as a seed crystal, the amorphous region is solid-phase grown, and the silicon layer is a crystalline silicon layer. In claim 1 ,
The plasma-excited CVD method is performed by supplying power from a high-frequency power source of less than 612 mW / cm ² and performing the substrate temperature at 400 ° C. or higher and lower than the strain point of the base substrate. In claim 1 or claim 2 ,
The method for manufacturing a semiconductor substrate, wherein the deposition gas is SiH ₄ , Si ₂ H ₆ , or SiF ₄ .