JP5714169B2 - Control device and information processing device - Google Patents

Description

  Embodiments described herein relate generally to a control device and an information processing device.

  In recent years, in a wide range of computer systems ranging from information devices such as mobile phones, slate terminals, and tablet terminals to large-scale systems such as supercomputers, system power saving has become an important issue. As one method of power saving, there is a power gating technique that supplies power only to a portion (unit) that needs power.

  For example, when the processor of the computer system is in an idle state in which no processing is performed, power saving is achieved by stopping power supply to a cache memory in which a part of a plurality of data used for the processor processing is stored. Can do.

Masaaki Kondo, Toshiya Kousuda, Hiroshi Sasaki, Hiroshi Nakamura et al. Examination of architecture support technology for fine-grained sleep control by compiler IPSJ Technical Report. Computer Architecture Research Report 2009-ARC-184 (14), 1- 8, 2009-07-28

  The above computer system has a prefetch function that predicts data that is likely to be used by the processor in the near future from a plurality of data stored in the main storage device, and reads the predicted data onto the cache memory in advance. It is common. Here, for example, when power supply to the cache memory is stopped even though the data read by the prefetch is stored in the cache memory, the data read onto the cache memory by the prefetch is erased. Therefore, when using the data, it is necessary to read the data into the cache memory again. For this reason, there is a problem that power used for prefetch is wasted.

  The problem to be solved by the present invention is to provide a control device and an information processing device capable of preventing the power used for prefetching from being wasted.

The control device according to the embodiment is in an idle state in which the processing device is not executing processing, and when the number of data streams predicted by the processing device is less than a threshold, the power supply unit stops the power supply to the cache memory When the number of data streams predicted by the processing device is equal to or greater than the threshold, the power supply unit is controlled to continue supplying power to the cache memory.

The block diagram of the control system of 1st Embodiment. The conceptual diagram which shows an example of the prediction algorithm of 1st Embodiment. 1 is a block diagram of a cache memory according to a first embodiment. The figure which shows the structural example of the tag of 1st Embodiment. The functional block diagram of the control system of 1st Embodiment. The flowchart which shows an example of the power supply control process of 1st Embodiment. The flowchart which shows an example of the determination process of 1st Embodiment. The block diagram of the cache memory of 2nd Embodiment. The flowchart which shows an example of the power supply control process of 2nd Embodiment. The flowchart which shows an example of the determination process of 2nd Embodiment. The figure which shows an example of the command which a processing apparatus performs in 3rd Embodiment. The block diagram of the cache memory of 3rd Embodiment. The figure which shows the structural example of the tag of 3rd Embodiment. The flowchart which shows an example of the power supply control process of 3rd Embodiment. The flowchart which shows an example of the determination process of 3rd Embodiment.

  Hereinafter, embodiments of a control device and an information processing device according to the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration example of a control system 100 according to the first embodiment. As shown in FIG. 1, the control system 100 includes a processing device 10, a cache unit 20, a main storage device 30, and a power supply unit 40 that supplies power. The cache unit 20 and the main storage device 30 are connected to each other via the bus 110. In addition, although detailed illustration is omitted here, the control system 100 according to the present embodiment includes a ROM, an external storage device such as an HDD and an SSD, a display device such as a display, an input device such as a mouse and a keyboard, In addition, it includes a communication I / F device and the like, and has a hardware configuration using a normal computer.

  The processing device 10 processes data. The processing device 10 executes various processes and controls the operation of the entire control system 100. The processing device 10 can be configured by a control device such as a CPU (Central Processing Unit). The main storage device 30 stores a plurality of data used for processing executed by the processing device 10.

  The cache unit 20 includes a cache controller 50 and a cache memory 60. The cache controller 50 includes an operation control unit 51 and a prefetch unit 52. The operation control unit 51 controls a data read operation from the main storage device 30, a data write operation to the cache memory 60, and the like. The prefetch unit 52 predicts data that is likely to be accessed in the future from among a plurality of data stored in the main storage device 30, and executes prefetch that is read (loaded) onto the cache memory 60 in advance. More specifically, the prefetch unit 52 reads data selected by the prediction algorithm based on the memory access history of the processing device 10 in advance onto the cache memory 60.

  FIG. 2 is a conceptual diagram illustrating an example of a prediction algorithm. In the example of FIG. 2, the processing device 10 performs access in the order of the data of the number 10, the data of the number 11, and the data of the number 12. I predict. Then, the prefetch unit 52 sequentially selects data having the number 17 as data that is likely to be accessed in the future, and reads the selected data onto the cache memory 60. Here, the prediction algorithm for predicting one data stream (access line) that is continuously accessed has been described as an example. However, the present invention is not limited to this, and the prediction algorithm may be accessed in the future. Any data can be used as long as it predicts high data. For example, when the processing apparatus 10 performs interleaved access, it may predict a plurality of access lines (data streams) simultaneously, or predict stride access that is accessed at regular intervals. There may be.

  Returning to FIG. 1 again, the description will be continued. The cache memory 60 stores a part of a plurality of data stored in the main storage device 30. The cache memory 60 is composed of a volatile memory such as a static RAM (Random Access Memory), for example, and the stored contents are lost when the supply of power is stopped. FIG. 3 is a block diagram illustrating a configuration example of the cache memory 60. The cache memory 60 includes a data array unit 62 in which cached data (hereinafter referred to as “cache data”) 61 is arranged and stored, and a plurality of tags 63 corresponding to the plurality of cache data 61 on a one-to-one basis. A tag array unit 64 to be stored and an unused prefetch bit counter 65 are provided.

  FIG. 4 is a diagram illustrating a configuration example of the tag 63. As shown in FIG. 4, the tag 63 includes a memory address 71, a dirty bit 72, an invalid bit 73, and a prefetch bit 74. The memory address 71 is information indicating the position (block) of the corresponding main storage device 30. The dirty bit 72 is information indicating whether or not the content of the cache data 61 matches the content of the data stored at the position indicated by the memory address 71 in the main storage device 30. In this example, when the content of the cache data 61 does not match the content of the data stored in the position indicated by the memory address 71 in the main storage device 30, the dirty bit is set to “1”, and the cache data When the content of 61 matches the content of the data stored at the position indicated by the memory address 71 in the main storage device 30, the dirty bit is set to “0”. The invalid bit is information indicating whether or not the corresponding cache data 61 is stored in the data array unit 62. The invalid bit is set to “1” when the cache data 61 is stored in the data array unit 62, and the invalid bit is set to “0” when the cache data 61 is not stored in the data array unit 62. Is done.

  The prefetch bit 74 is information indicating whether or not the corresponding cache data 61 is data read onto the cache memory 60 by prefetch. When the cache data 61 is data read onto the cache memory 60 by prefetch, the prefetch bit 74 is set to “1” indicating that it is valid, and the cache data 61 is stored on the cache memory 60 by prefetch. In the case where the data is not read, the prefetch bit 74 is set to “0” indicating that it is invalid. Further, when the processing device 10 accesses the cache data 61 read onto the cache memory 60 by prefetching, the prefetch bit corresponding to the cache data 61 is changed from “1” to “0”. Is set.

  In the present embodiment, when the cache controller 50 (prefetch unit 52) reads the data of the main storage device 30 onto the cache memory 60 by prefetch, the cache controller 50 (prefetch unit 52) stores the read data in the tag array unit 64 and the read data. A tag 63 corresponding to is created and stored in the tag array unit 64. In the present embodiment, the cache controller 50 (operation control unit 51), when the processing device 10 accesses the cache data 61 read onto the cache memory 60 by prefetch, The prefetch bit 74 corresponding to 61 is set from “1” to “0”.

  The unused prefetch bit counter 65 counts the number of cache data 61 read onto the cache memory 60 by prefetch. More specifically, the unused prefetch bit counter 65 counts the total number of tags 63 in which the prefetch bit 74 is set to “1”.

  FIG. 5 is a block diagram illustrating functions realized when the processing apparatus 10 executes a program stored in an HDD (not illustrated). That is, it can also be understood as a functional block diagram of the control system 100. As shown in FIG. 5, the functions of the control system 100 include a detection unit 81, a determination unit 82, a power supply control unit 83, and a restart processing unit 84. It should be noted that at least some of these functions can be realized by individual circuits (hardware).

  The detection unit 81 detects whether or not the processing apparatus 10 is in an idle state in which no processing is performed. When the detection unit 81 detects that the processing device 10 is in the idle state, the determination unit 82 determines whether to stop supplying power to the cache memory 60 according to the prefetch state. In the present embodiment, the determination unit 82 determines to stop supplying power to the cache memory 60 when the number of cache data 61 read onto the cache memory 60 by prefetch is less than the threshold. On the other hand, when the number of cache data 61 read onto the cache memory 60 by the prefetch is equal to or greater than the threshold value, the determination unit 82 determines that the power supply to the cache memory 60 is continued (not stopped).

  More specifically, the determination unit 82 determines to stop supplying power to the cache memory 60 when the count value of the unused prefetch bit counter 65 is less than the threshold value. On the other hand, when the count value of the unused prefetch bit counter 65 is equal to or greater than the threshold value, the determination unit 82 determines that the supply of power to the cache memory 60 is not stopped. The threshold value can be set to an arbitrary value. Since the threshold value depends on the performance of each element module of the control system 100, it is preferable to adopt a value suitable for the control system 100. For example, when the processing device 10 performs interleaved access, the threshold value is 0.5 times the maximum number of data that can be prefetched (indicating that two of the three access lines can be predicted). If the speed at the time of resumption is important, a small value such as 1 can be adopted as the threshold value, or a value obtained by experimental adjustment can be adopted as the threshold value.

  When the determination unit 82 determines that the supply of power to the cache memory 60 is to be stopped, the power supply control unit 83 controls the power supply unit 40 to stop supplying power to the cache memory 60. On the other hand, when the determination unit 82 determines that the supply of power to the cache memory 60 is not stopped, the power supply control unit 83 controls the power supply unit 40 to continue supplying power to the cache memory 60.

  When the supply of power to the cache memory 60 is stopped, the restart processing unit 84 controls the power supply unit 40 to restart the supply of power to the cache memory 60 when a predetermined return factor is received. The type of return factor is arbitrary. For example, interrupt processing may be a return factor. In this case, when the supply of power to the cache memory 60 is stopped, the restart processing unit 84 controls the power supply unit 40 to restart the supply of power to the cache memory 60 when an interrupt process is accepted. .

  FIG. 6 is a flowchart illustrating an example of a power supply control process executed by the control system 100. This power supply control process is realized by the processing device 10 executing a predetermined software program. As illustrated in FIG. 6, when the detection unit 81 detects that the processing device 10 is in an idle state (result of step S1: YES), the determination unit 82 executes a determination process (step S2).

  FIG. 7 is a flowchart illustrating an example of the determination process in step S2. As shown in FIG. 7, first, the determination unit 82 refers to the count value of the unused prefetch bit counter 65 (step 101). Next, the determination unit 82 determines whether or not the count value of the unused prefetch bit counter 65 (the total number of tags 63 in which the prefetch bit 74 is set to “1”) is equal to or greater than a threshold value (step S102). When the count value of the unused prefetch bit counter 65 is equal to or greater than the threshold (result of step S102: YES), the determination unit 82 determines not to stop supplying power to the cache memory 60 (step S103). On the other hand, when the count value of the unused prefetch bit counter 65 is less than the threshold (result of step S102: NO), the determination unit 82 determines to stop supplying power to the cache memory 60 (step S104). The above is the content of the determination process.

  Returning to FIG. 6 again, the description will be continued. If it is determined that the supply of power to the cache memory 60 is to be stopped as a result of the determination process in step S2 (result of step S3: YES), the power supply control unit 83 turns the power supply so as to stop the supply of power to the cache memory 60. The unit 40 is controlled (step S4). On the other hand, when it is determined not to stop the power supply to the cache memory 60 (the result of step S3: NO), the power supply control unit 83 controls the power supply unit 40 to continue the power supply to the cache memory 60. (Step S5).

  As described above, in the present embodiment, when the number of cache data 61 read onto the cache memory 60 by the prefetch is equal to or greater than the threshold value, the cache memory 60 can be stored even when the processing apparatus 10 is in the idle state. Since the power supply is not stopped, it is possible to prevent the power used for prefetching from being wasted.

(Second Embodiment)
Next, a second embodiment will be described. The determination unit 82 of the second embodiment determines that the power supply to the cache memory 60 is stopped when the prefetch unit 52 cannot predict data that is likely to be accessed in the future, and the prefetch unit 52 If the data that is highly likely to be received can be predicted, it is different from the first embodiment described above in that it is determined not to stop the power supply to the cache memory. Parts common to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  FIG. 8 is a block diagram illustrating a configuration example of the cache memory 600 according to the second embodiment. As shown in FIG. 8, the cache memory 600 is different from the first embodiment in that it has a prefetch operation counter 66 instead of the above-described unused prefetch bit counter 65, but other configurations are the same as those in the first embodiment. This is the same as the cache memory 60. In the present embodiment, the prefetch unit 52 sets the count value of the prefetch operation counter 66 to “0” when data that is likely to be accessed in the future among a plurality of data stored in the main storage device 30 cannot be predicted. Set. On the other hand, the prefetch unit 52 sets the count value of the prefetch operation counter 66 to “1” when data that is likely to be accessed in the future among a plurality of data stored in the main storage device 30 can be predicted. . For example, when the processing apparatus 10 performs an interleaved access, the prefetch unit 52 can set the count value of the prefetch operation counter 66 to a value indicating the number of access lines that can be predicted. .

  When the count value of the prefetch operation counter 66 is “1”, the determination unit 82 according to the present embodiment determines that power supply to the cache memory 60 is not stopped. On the other hand, when the count value of the prefetch operation counter 66 is “0”, the determination unit 82 determines to stop supplying power to the cache memory 60. For example, when the processing apparatus 10 performs an interleaved access, the determination unit 82 determines to continue supplying power to the cache memory 60 when the count value of the prefetch operation counter 66 is equal to or greater than the threshold value. However, when the count value is less than the threshold value, it can be determined that the supply of power to the cache memory 60 is stopped. In this case, the threshold value can be set to an arbitrary value.

  FIG. 9 is a flowchart illustrating an example of a power supply control process according to the second embodiment. Although the contents of the determination process in step S12 are different from those of the first embodiment, other contents are the same as those of the power supply control process of the first embodiment.

  FIG. 10 is a flowchart illustrating an example of the determination process in step S12. As shown in FIG. 10, first, the determination unit 82 refers to the count value of the prefetch operation counter 66 (step 201). Next, the determination unit 82 determines whether or not the count value of the prefetch operation counter 66 is “1” (step S202). That is, the determination unit 82 determines whether the prefetch unit 52 can predict data that is likely to be accessed in the future. If the count value of the prefetch operation counter 66 is “1” (result of step S202: YES), the determination unit 82 determines not to stop supplying power to the cache memory 60 (step S203). On the other hand, when the count value of the prefetch operation counter 66 is less than the threshold value, the determination unit 82 determines to stop supplying power to the cache memory 60 (step S204). The above is the content of the determination process.

  As described above, in this embodiment, if the prefetch unit 52 can predict data that is likely to be accessed in the future, the cache memory 60 can be used even when the processing device 10 is in the idle state. Since the supply of power to is not stopped, it is possible to prevent the power used for prefetch from being wasted.

(Third embodiment)
Next, a third embodiment will be described. The control system according to the third embodiment includes a designation unit that designates repetitive data indicating data that is repeatedly used among a plurality of data stored in the main storage device 30. In addition, the determination unit 82 of the third embodiment stores the number of cache data 61 that matches the repeated data specified by the specification unit among the cache data 61 stored in the cache memory 6000 and the cache data 6000 by prefetching. If the sum of the read cache data 61 and the number of cache data 61 is less than the threshold, it is determined that the supply of power to the cache memory 6000 is stopped. On the other hand, when the sum of the number of cache data 61 that matches the repeated data and the number of cache data 61 read onto the cache memory 6000 by prefetch is equal to or greater than the threshold value, the determination unit 82 determines the power for the cache memory 6000. Is determined not to stop the supply. Although different from the first embodiment in the above points, portions common to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 11 is a diagram illustrating an example of an instruction executed by the processing device 10 in the third embodiment. As shown in FIG. 11, the instructions executed by the processing device 10 include a repeated use data designation instruction 1101 and a repeated use data counter initialization instruction 1102. The repeated use data designation command 1101 designates the top memory address and data size of the repeated use data in order to indicate the range of repeated use data. The above-described designation unit is a function realized by the processing device 10 repeatedly executing the usage data designation command 1101. In addition, when the processing apparatus 10 executes the repeated use data counter initialization instruction 1102, a count value of a later used repeat data counter 67 is initialized (reset) to “0”.

  FIG. 12 is a block diagram illustrating a configuration example of the cache memory 6000 according to the third embodiment. As shown in FIG. 12, the cache memory 6000 is different from the first embodiment in that it further includes a repeated use data counter 67. Further, the configuration of the tag 63 is different from that of the first embodiment. This will be specifically described below.

  FIG. 13 is a diagram illustrating a configuration example of the tag 63 according to the third embodiment. The tag 63 is different from the first embodiment in that the tag 63 further includes a repeated use bit 75. The repeated use bit 75 is information indicating whether or not the corresponding cache data 61 matches the repeated use data designated by the designation unit. When the corresponding cache data 61 matches the repeated use data, the repeated use bit is set to “1”, and when the corresponding cache data 61 does not match the repeated use data, the repeated use bit is set to “0”. Is done. When the cache controller 50 (prefetch unit 52) reads the data of the main storage device 30 onto the cache memory 60 by prefetching, if the read data matches the repeated use data, the repeated use bit 75 is set to “1”. If the read data does not match the repeated use data, the repeated use bit is set to “0”. In this embodiment, the repeated use bit 75 set to “1” continues to hold the value “1” unless the above-described repeated use data counter initialization instruction 1102 is executed. For example, even when the processing device 10 accesses the cache data 61 corresponding to the repeated use bit 75 set to “1”, the value of the repeated use bit 75 is not reset to “0”.

  Returning to FIG. 12, the description will be continued. The repeated use data counter 67 counts the number of cache data 61 that matches the repeated use data specified by the specifying unit. More specifically, the repeated use data counter 67 counts the total number of tags 63 in which the repeated use bit 75 is set to “1”.

  In the present embodiment, the determination unit 82 determines to stop supplying power to the cache memory 60 when the sum of the count value of the unused prefetch bit counter 65 and the count value of the repeated use data counter 67 is less than the threshold value. . On the other hand, when the sum of the count value of the unused prefetch bit counter 65 and the count value of the repeated use data counter 67 is equal to or greater than the threshold value, the determination unit 82 determines that the supply of power to the cache memory 60 is not stopped. The threshold value can be set to an arbitrary value. Since the threshold value depends on the performance of each element module of the control system 100, it is preferable to adopt a value suitable for the control system 100.

  FIG. 14 is a flowchart illustrating an example of a power supply control process according to the third embodiment. Although the contents of the determination process in step S22 are different from those of the first embodiment, other contents are the same as those of the power supply control process of the first embodiment.

  FIG. 15 is a flowchart illustrating an example of the determination process in step S22. As shown in FIG. 15, first, the determination unit 82 refers to the count values of the unused prefetch bit counter 65 and the repeated use data counter 67 (step 301). Next, the determination unit 82 determines whether or not the sum of the count value of the unused prefetch bit counter 65 and the count value of the repeated use data counter 67 is equal to or greater than a threshold value (step S302). If the sum of the count value of the unused prefetch bit counter 65 and the count value of the repeated use data counter 67 is equal to or greater than the threshold (result of step S302: YES), the determination unit 82 must stop supplying power to the cache memory 60. Determination is made (step S303). On the other hand, when the sum of the count value of the unused prefetch bit counter 65 and the count value of the repeated use data counter 67 is less than the threshold value (result of Step S302: NO), the determination unit 82 stops supplying power to the cache memory 60. Then, it determines (step S304). The above is the content of the determination process.

  As described above, in the present embodiment, the total of the number of cache data 61 that matches the repeated use data specified by the specifying unit and the number of cache data 61 read onto the cache memory 60 by prefetching. Is equal to or greater than the threshold value, the supply of power to the cache memory 60 is not stopped even when the processing apparatus 10 is in the idle state, so that it is possible to prevent the power used for prefetching from being wasted.

  As mentioned above, although embodiment of this invention was described, this embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  Further, the program executed by the processing device 10 of each of the above-described embodiments may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. In addition, the program executed by the processing device 10 of each of the above embodiments may be provided or distributed via a network such as the Internet. The program executed by the processing device 10 of each of the above embodiments may be provided by being incorporated in advance in a ROM or the like.

10 processing unit 20 cache unit 30 main storage unit 40 power supply unit 50 cache controller 51 operation control unit 52 prefetch unit 60 cache memory 61 cache data 62 data array unit 63 tag 64 tag array unit 65 unused prefetch bit counter 66 prefetch operation counter 67 Usage data counter 71 Memory address 72 Dirty bit 73 Invalid bit 74 Prefetch bit 75 Repetitive usage bit 81 Detection unit 82 Determination unit 83 Power supply control unit 84 Restart processing unit 100 Control system 110 Bus 600 Cache memory 1101 Usage data specification instruction 1102 Usage data counter Initialization instruction 6000 Cache memory

Claims (4)

When the processing device is in an idle state where processing is not being performed, and the number of data streams predicted by the processing device is less than the threshold, the power supply unit is controlled to stop supplying power to the cache memory,
When the number of data streams predicted by the processing device is equal to or greater than the threshold in the idle state, the power supply unit is controlled to continue supplying power to the cache memory.
Control device. Having a processing device for processing,
The processor predicts a data stream;
When the processing device is in an idle state where processing is not being performed and the number of data streams predicted by the processing device is less than a threshold, the supply of power to the cache memory is stopped,
In the idle state, if the number of data streams predicted by the processing device is equal to or greater than the threshold, supply of power to the cache memory is continued.
Information processing device. The number of data streams processor predicts is less than the threshold, if the processor is idle not running processing, controls the power supply unit to stop the supply of power to the cache memory,
When the number of data streams predicted by the processing device is equal to or greater than the threshold and the processing device is in an idle state in which processing is not being performed, the power supply unit is controlled to continue supplying power to the cache memory To
Control device. Having a processing device for processing,
The processor predicts a data stream;
When the number of data streams predicted by the processing device is less than a threshold and the processing device is in an idle state where processing is not being performed, the supply of power to the cache memory is stopped,
When the number of data streams predicted by the processing device is equal to or greater than the threshold value and the processing device is in an idle state in which processing is not being performed, supply of power to the cache memory is continued.
Information processing device.

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