JP5634092B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including an overvoltage protection circuit.

  In recent years, various devices and chargers using rechargeable batteries such as lithium ion batteries have been developed. Accordingly, semiconductor integrated circuits have been developed that detect the voltages of a plurality of batteries connected in series and control the voltages of the batteries based on the detected voltages.

  In this type of semiconductor integrated circuit, a protection circuit for protecting the internal circuit from a surge voltage overvoltage applied to the input terminal, and a clamp circuit are provided between the power supply line and the ground.

  Patent Document 1 discloses a semiconductor integrated circuit in which the circuit scale is reduced by sharing one protection circuit with a plurality of input terminals. Patent Document 2 discloses a semiconductor integrated circuit in which the circuit area of a clamp circuit provided between a power supply line and ground is reduced.

Japanese Patent Laid-Open No. 2001-267596 JP 2009-104455 A

  However, in the above-described semiconductor integrated circuit for battery control, a circuit element may be connected between adjacent terminals. For example, in order to discharge a battery, a switching element is connected between two adjacent input terminals. When the switching element is turned on, the positive terminal and the negative terminal of the battery are short-circuited, the battery is discharged, and the battery voltage decreases. In such a semiconductor integrated circuit, when a surge voltage is applied between the input terminals, there is a problem that the switching element is destroyed.

The semiconductor integrated circuit of the present invention has been made in view of the above-described problems, and is a semiconductor integrated circuit that includes a plurality of terminals and in which a battery is connected between adjacent terminals, and between the adjacent terminals. An overvoltage protection element connected between a connected circuit element and an adjacent terminal and protecting the circuit element from an overvoltage applied between adjacent terminals; a power line; and the power line and the plurality of terminals. And an additional overvoltage protection element connected between the terminals on the highest voltage side, wherein the additional overvoltage protection element is not connected between adjacent terminals .

  According to the semiconductor integrated circuit of the present invention, when a surge voltage is applied between adjacent terminals, circuit elements connected between the adjacent terminals can be protected from electrostatic breakdown due to the surge voltage.

1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a circuit diagram of a clamp circuit. FIG. 6 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

[First Embodiment]
A semiconductor integrated circuit 100 according to a first embodiment of the present invention will be described with reference to FIGS. As shown in the figure, the semiconductor integrated circuit 100 includes terminals P0 to P14, diode-connected MOS transistors MN0 to MN15 (an example of “an overvoltage protection element” according to the present invention, protection diode circuits HD0 to HD14, battery discharge MOSs). Transistors T1 to T14 An example of the “circuit element” and “switching element” of the present invention includes a battery voltage detection control circuit 10 and an overvoltage protection clamp circuit 20. In FIG. Illustrations of P2 to P10 and corresponding circuits are omitted.

  In the semiconductor integrated circuit 100, circuits (MOS transistor MN14, battery discharge MOS transistor T14, etc.) formed corresponding to two adjacent terminals (for example, terminal P14 and terminal P13) form one cell. This cell is repeatedly arranged.

  Batteries BV1 to BV14 such as lithium ion batteries are connected between adjacent terminals P0 to P14. That is, the positive terminal of the battery BV14 is connected to the terminal P14, and the negative terminal of the battery BV14 is connected to the terminal P13. The positive terminal of the battery BV13 is connected to the terminal P13, and the negative terminal of the battery BV13 is connected to the terminal P12. In this way, the batteries BV1 to BV14 are connected in series outside the semiconductor integrated circuit 100 and generate a high voltage.

  The battery discharge MOS transistors T1 to T14 are respectively connected between adjacent terminals of the terminals P0 to P14 via wiring. For example, the battery discharge MOS transistor T14 is connected between the terminals P14 and P13, and the battery discharge MOS transistor T13 is connected between the terminals P13 and P12.

  The battery voltage detection control circuit 10 detects the voltages of the batteries BV1 to BV14 by detecting the voltage between the adjacent terminals P0 to P14, and according to the detection result, the battery discharge MOS transistor T1. ~ T14 is a circuit configured to control on / off of T14.

  That is, when the battery voltage detection control circuit 10 detects that one of the batteries BV1 to BV14 has a higher voltage than another battery, the battery voltage detection control circuit 10 turns on the battery discharge MOS transistor connected between the corresponding terminals. As a result, the positive terminal and the negative terminal of the battery are short-circuited, so that the battery is discharged and the voltage of the battery decreases.

  For example, when the battery voltage detection control circuit 10 detects that the voltage of the battery BV14 is higher than the voltage of the battery BV13, the battery discharge MOS transistor T14 connected between the terminal P14 and the terminal P13 is connected to the battery discharge MOS transistor T14. Turn on. Thereby, each voltage of battery BV1-BV14 can be made uniform.

  The diode-connected MOS transistors MN0 to MN15 are formed of a low breakdown voltage, for example, a 5V breakdown voltage N-channel MOS transistor to which a gate G, a source S, and a back gate are connected, and the source S is an anode and the drain D is a cathode. Function as a diode. The MOS transistors MN1 to MN14 are respectively connected between adjacent terminals of the terminals P0 to P14 via wirings.

  For example, the MOS transistor MN14 is connected between the terminal P14 and the terminal P13 via a wiring, and the MOS transistor MN13 is connected between the terminal P13 and the terminal P12 via a wiring. The MOS transistors MN0 to MN15 are normally off, but are turned on when a surge voltage is applied between the corresponding terminals to protect the battery discharge MOS transistors T1 to T14. In this case, a diode or a P-channel type MOS transistor can be used instead of the MOS transistors MN0 to MN15. However, the MOS transistors MN0 to MN15 are preferable as the overvoltage protection element. This is because the N-channel MOS transistors MN0 to MN15 have a high current drive capability and are suitable for extracting a surge voltage at high speed.

  The MOS transistor MN15 is connected between the terminal P14 and the power supply line 30. In normal use, the terminal P <b> 14 and the power supply line 30 are connected via a wiring outside the semiconductor integrated circuit 100. In this case, the MOS transistor MN15 is used to protect the semiconductor integrated circuit 100 from electrostatic breakdown due to a surge when the semiconductor integrated circuit 100 is assembled into a package. After the terminal P14 and the power supply line 30 are short-circuited by connection, the MOS transistor MN15 does not function as an electrostatic breakdown protection element.

  The protection diode circuits HD0 to HD14 are connected to the terminals P0 to P14 via wiring, respectively. The protection diode circuits HD0 to HD14 include a first diode D1 connected between the terminal PX (X = 0 to 14) and the power supply line 30, and a second diode connected between the terminal PX and the ground. D2 is provided. In this case, since the voltage VDDH is applied to the first diode D1 and the second diode D2 connected in series, it is necessary to be a high voltage diode that can withstand this.

  The clamp circuit 20 is a circuit that clamps the potential VDDH of the power supply line 30 when a surge voltage is applied. For example, as shown in FIG. 2, eight low breakdown voltages in which the gate, the source, and the back gate are short-circuited. MOS transistors MP1 to MP8 are connected in series. In this case, the MOS transistors MP1 to MP8 are preferably formed of a P channel type in order to prevent a latch-up phenomenon.

  Hereinafter, a protection operation when a surge voltage is applied to the semiconductor integrated circuit 100 will be described.

(1) When a surge voltage is applied between adjacent terminals:
For example, it is assumed that a surge voltage, for example, several hundred volts is applied between the terminal P14 and the terminal P13. In this case, when the terminal P13 has a high potential and the terminal P14 has a low potential due to the polarity of the surge voltage, the diode-connected MOS transistor MN14 is turned on in the forward direction. Conversely, when the terminal P13 is at a low potential and the terminal P14 is at a high potential, a reverse bias is applied to the MOS transistor MN14, so that the MOS transistor MN14 is turned on by avalanche breakdown.

  As a result, a surge current flows through the MOS transistor MN14, and the surge voltage between the terminal P14 and the terminal P13 is rapidly attenuated, so that the electrostatic discharge of the battery discharge MOS transistor T14 connected between the terminal P14 and the terminal P13. Destruction is prevented. The same applies when a surge voltage is applied between other adjacent terminals.

(2) When a surge voltage is applied to the terminal:
(A) When a positive (+) surge voltage is applied to each terminal PX with reference to the ground potential VSS: For example, when a positive surge voltage is applied to the terminal P14 with reference to the ground potential VSS, A surge current path is formed through the clamp circuit 20 to the ground via the first diode D1 forward bias of the protection diode circuit HD14. This surge current path removes a surge current associated with the surge voltage. Thereby, internal circuits such as the battery discharge MOS transistors T1 to T14 and the battery voltage detection control circuit 10 are protected from electrostatic breakdown due to surge voltage. The same applies to the other terminals P0 to P13.

  (B) When a negative (−) surge voltage is applied to each terminal PX with reference to the ground potential VSS: For example, when a negative surge voltage is applied to the terminal P14 with reference to the ground potential VSS, protection from the ground A surge current path is formed through the second diode D2 forward bias of the diode circuit HD14 to the terminal P14. This surge current path removes a surge current associated with the surge voltage. As a result, internal circuits such as the battery discharge MOS transistors T1 to T14 and the battery voltage detection control circuit 10 are protected from destruction due to the surge voltage. The same applies to the other terminals P0 to P13.

  (C) When a positive (+) surge voltage is applied to each terminal PX with reference to the potential VDDH of the power supply line 30: For example, a positive (+) surge voltage is applied to the terminal P14 with reference to the potential VDDH In this case, a surge current path from the terminal P14 to the power supply line 30 through the first diode D1 forward bias of the protection diode circuit HD14 is formed. This surge current path removes a surge current associated with the surge voltage. As a result, internal circuits such as the battery discharge MOS transistors T1 to T14 and the battery voltage detection control circuit 10 are protected from destruction due to the surge voltage. The same applies to the other terminals P0 to P13.

  (D) When a negative (−) surge voltage is applied to each terminal PX with reference to the potential VDDH of the power supply line 30: For example, a negative (−) surge voltage is applied to the terminal P14 with reference to the potential VDDH. In this case, a surge current path is formed from the power supply line 30 through the clamp circuit 20 to the terminal P14 through the second diode D2 forward bias of the protection diode circuit HD14. This surge current path removes a surge current associated with the surge voltage.

  As a result, internal circuits such as the battery discharge MOS transistors T1 to T14 and the battery voltage detection control circuit 10 are protected from destruction due to the surge voltage. The same applies to the other terminals P0 to P13.

  As described above, according to the semiconductor integrated circuit 100, when a surge voltage is applied between adjacent terminals, or when a surge voltage is applied to each terminal, the battery discharge MOS transistors T1 to T14, etc. The electrostatic breakdown of the internal circuit can be prevented.

  In the present embodiment, the semiconductor integrated circuit 100 is configured with 14 cells so that the 14 batteries BV1 to BV14 can be connected. However, the number of cells is appropriately increased or decreased within a range of 1 or more. Can do. The battery discharge MOS transistors T1 to T14 connected between adjacent terminals are merely examples, and other circuit elements may be connected instead. Even in such a case, the circuit elements can be protected by the diode-connected MOS transistors MN0 to MN15.

[Second Embodiment]
A semiconductor integrated circuit 200 according to a second embodiment of the present invention will be described with reference to FIG. In FIG. 3, the terminals P3 to P9 and the corresponding circuits are not shown for convenience.

  In the semiconductor integrated circuit 100 of the first embodiment, the protection diode circuits HD0 to HD14 are provided at the terminals P0 to P14, and the clamp circuit 20 is also provided, so that the circuit scale of the protection circuit is large. .

  Therefore, in the semiconductor integrated circuit 200 of the present embodiment, in order to reduce the circuit scale, HD1, HD3, HD5, HD7, Only HF9, HD11, and HD13 are left, and HD0, HD2, HD4, HD6, HF8, HD12, and HD14 corresponding to the other terminal terminals P0 and the like are deleted. That is, the protection diode circuit is provided every other terminal, and the number thereof is almost halved.

  Further, the surge circuit is secured by eliminating the clamp circuit 20 and providing seven diode-connected MOS transistors MP11 to MP17 instead. As a result, the circuit scale can be reduced while ensuring the overvoltage protection performance. Other circuit configurations are the same as those of the first embodiment.

  That is, the semiconductor integrated circuit 200 includes terminals P0 to P14, diode-connected MOS transistors MN0 to MN15 (an example of the “overvoltage protection element” of the present invention), protection diode circuits HD1, HD3, HD5, HD7, HD9, HD11, HD13, battery discharge MOS transistors T1 to T14 An example of the “circuit element” and “switching element” of the present invention, a battery voltage detection control circuit 10, and diode-connected MOS transistors MP11 to MP17.

  One diode-connected MOS transistor MP11 to MP17 is provided in each of two cells. In this case, the MOS transistors MP11 to MP17 are P-channel MOS transistors to which a gate G, a source S, and a back gate are connected, and function as diodes having the source S as a cathode and the drain D as an anode.

  For example, the MOS transistor MP11 is connected between the ground and the terminal P2 via a wiring. The MOS transistor MP16 is connected between the terminals P10 and P12 via a wiring. The MOS transistor MP17 is connected between the terminals P12 and P14 via a wiring. As a whole, the MOS transistors MP11 to MP17 are connected in series between the terminal P14 and the ground.

  When the batteries BV1 to BV14 are connected to the semiconductor integrated circuit 200, the voltages of two series batteries are respectively applied as reverse bias to the diode-connected MOS transistors MP11 to MP17, so that the MOS transistors MP11 to MP17 It is necessary to have a pressure resistance that can withstand this. And, when a surge voltage is applied to each terminal, the polarity of the surge voltage is turned on in the forward direction when the forward bias is applied, and avalanche breakdown is caused when the reverse bias is applied.

  The MOS transistors MP11 to MP17 can be formed of an N-channel type, but the latch-up phenomenon can be prevented by forming the P-channel type.

  Hereinafter, a protection operation when a surge voltage is applied to the semiconductor integrated circuit 200 will be described.

(3) When a surge voltage is applied between adjacent terminals:
This case is the same as in the first embodiment. That is, by providing the diode-connected MOS transistors MN1 to MN14 between adjacent terminals, the electrostatic discharge breakdown of the battery discharge MOS transistors T1 to T14 can be prevented.

(4) When a surge voltage is applied to the terminals:
(A) When a positive (+) surge voltage is applied to each terminal PX with reference to the ground potential VSS: In this case, a surge current path is formed from all terminals PX toward the ground. . Thereby, internal circuits such as the battery discharge MOS transistors T1 to T14 and the battery voltage detection control circuit 10 are protected from electrostatic breakdown due to surge voltage.

  For example, when a positive (+) surge voltage is applied to the terminal P14 with respect to the ground potential VSS, a surge current path is formed from the terminal P14 to the ground through the seven-stage MOS transistors MP11 to MP17. For the terminal P13, a surge current path is formed from the terminal P13 through the MOS transistor MN13 to the ground through the six-stage MOS transistors MP11 to MP16.

  For the terminal P12, a surge current path is formed from the terminal P12 to the ground through the six-stage MOS transistors MP11 to MP16. For the terminal P11, a surge current path is formed from the terminal P11 through the MOS transistor MN11 to the ground through the five-stage MOS transistors MP11 to MP15.

  That is, a lower surge current path having a lower resistance is formed at the lower terminal, which is advantageous in terms of overvoltage protection and electrostatic breakdown protection. Further, all the terminals PX are more advantageous than the first embodiment.

  (B) When a negative (−) surge voltage is applied to each terminal PX with reference to the ground potential VSS: In this case, for the terminals P1, P3, P5, P7, P9, P11, and P13, protection diodes are used. Since circuits HD1, HD3, HD5, HD7, HD9, HD11, and HD13 are provided, this is the same as in the first embodiment. For example, for the terminal P13, a surge current path from the ground to the terminal P13 through the second diode D2 forward bias is formed. This surge current path removes a surge current associated with the surge voltage.

  For the terminal P14, a surge current path is formed from the second diode D2 (forward bias) of the protection diode circuit HD13 through the MOS transistor MN14 to the terminal P14. The same applies to the terminals P4, P6, P8, P10, and P12. This surge current path is disadvantageous in terms of overvoltage protection because, for example, the MOS transistor MN14 has a resistance component larger than that of the first embodiment.

  However, for these terminals, a surge current path by newly added MOS transistors MP11 to MP17 is formed in parallel with the surge current path, so that overvoltage protection performance equivalent to that of the first embodiment is comprehensively provided. have.

  For example, for the terminal P14, a surge current path from the second diode D2 (forward bias) of the protection diode circuit HD11 through the MOS transistor MN12 and the MOS transistor MP17 to the terminal P14 is arranged in parallel. Further, a surge current path from the ground to the terminal P14 through the seven-stage MOS transistors MP11 to MP17 is provided in parallel.

  For the terminal P12, a surge current path from the second diode D2 (forward bias) of the protection diode circuit HD10 through the MOS transistor MN10 and the MOS transistor MP16 to the terminal P12 is arranged in parallel. A surge current path from the ground to the terminal P12 through the six-stage MOS transistors MP11 to MP16 is provided in parallel.

  For the terminal P2, a surge current path is formed from the ground to the terminal P2 through the one-stage MOS transistor MP11. In this surge current path, a surge current path from the second diode D2 (forward bias) of the protection diode circuit HD1 through the MOS transistor MN2 to the terminal P2 is arranged in parallel, which is compared with the first embodiment. It has rather advantageous overvoltage protection performance.

  (C) When a positive (+) surge voltage is applied to each terminal PX with reference to the potential VDDH of the power supply line 30: In this case, for the terminals P1, P3, P5, P7, P9, P11, and P13, Since the protection diode circuits HD1, HD3, HD5, HD7, HD9, HD11, and HD13 are provided, respectively, this is the same as in the first embodiment. For example, for the terminal P13, a current path from the terminal P13 to the power supply line 30 through the first diode D1 forward bias is formed. By this current path, the surge current accompanying the surge voltage is removed.

  For the terminal P12, a surge current path is formed from the MOS transistor MN13 to the power supply line 30 through the first diode D1 (forward bias) of the protection diode circuit HD13. The same applies to the terminals P2, P4, P6, P8, and P10.

  This surge current path is disadvantageous in terms of overvoltage protection because, for example, the MOS transistor MN13 has a resistance component larger than that of the first embodiment. However, for these terminals, since a new surge current path by newly added MOS transistors MP11 to MP17 is formed in parallel with the surge current path, the overvoltage equivalent to the first embodiment is comprehensively obtained. Has protection performance.

  For example, for the terminal P12, a surge current path from the terminal P12 to the power supply line 30 through the MOS transistor MP17 and the MOS transistor MN15 is arranged in parallel.

  For the terminal P10, a surge current path that reaches the power supply line 30 through the MOS transistors MP16 and MP17 and the MOS transistor MN15, and the first diode D1 (forward bias) of the MOS transistor MP16, the MOS transistor MN13, and the protection diode circuit HD13. A surge current path that passes through the power line 30 is provided in parallel.

  Further, the terminal P14 has a surge current path extending from the terminal P14 through the single MOS transistor MN15 to the power supply line 30, and thus has an overvoltage protection performance that is rather advantageous as compared with the first embodiment. ing.

  (D) When a negative (-) surge voltage is applied to each terminal PX with reference to the potential VDDH of the power supply line 30: In this case, the power supply line 30 in FIG. A surge current path is formed. For example, when a negative (−) surge voltage is applied to the terminal P0 with respect to the potential VDDH, the reverse bias of the seven-stage MOS transistors MP11 to MP17 is applied from the power line 30 via the reverse bias of the MOS transistor MN15. A surge current path passing through to the terminal P0 is formed.

  For the terminal P1, a surge current path is formed from the power supply line 30 through the MOS transistor MN15 to the terminal P1 through the six-stage MOS transistors MP12 to MP17 and the MOS transistor MN2. For the terminal P12, a surge current path is formed from the power supply line 30 through the MOS transistor MN15 and the MOS transistor MP17 to the terminal P12. For the terminal P13, a surge current path is formed through the MOS transistor MN15 and the MOS transistor MN14 to reach the terminal P13. For the terminal P14, a surge current path is formed which reaches the terminal P14 through the MOS transistor MN15.

  That is, the upper terminal is formed with a low-resistance surge current path, which is advantageous in terms of overvoltage protection. Further, all the terminals PX are more advantageous than the first embodiment.

  In the present embodiment, the semiconductor integrated circuit 200 is composed of 14 cells so that 14 batteries BV1 to BV14 can be connected, but the number can be appropriately increased or decreased within a range of 2 or more. it can.

P0 to P14 Terminals MN0 to MN15 Diode-connected MOS transistors MP1 to MP7, MP11 to MP17 Diode-connected MOS transistors HD0 to HD14 Protection diode circuit D1 First diode D2 Second diode T1 to T14 Battery discharge MOS transistor DESCRIPTION OF SYMBOLS 10 Battery voltage detection control circuit 20 Clamp circuit 100, 200 Semiconductor integrated circuit

Claims (6)

A semiconductor integrated circuit comprising a plurality of terminals, each having a battery connected between adjacent terminals,
Circuit elements connected between adjacent terminals;
An overvoltage protection element connected between adjacent terminals and protecting the circuit element from an overvoltage applied between adjacent terminals;
A power line;
An additional overvoltage protection element connected between the power line and the terminal on the highest voltage side among the plurality of terminals, and the additional overvoltage protection element is not connected between adjacent terminals. A semiconductor integrated circuit. A semiconductor integrated circuit comprising a plurality of terminals, each having a battery connected between adjacent terminals,
A switching element connected between adjacent terminals;
An overvoltage protection element connected between adjacent terminals and protecting the switching element from an overvoltage applied between adjacent terminals;
A battery voltage detection control circuit that detects the voltage of the battery connected to the adjacent terminal and controls on / off of the switching element according to the detection result of the battery voltage;
A power line;
An additional overvoltage protection element connected between the power line and the terminal on the highest voltage side among the plurality of terminals, and the additional overvoltage protection element is not connected between adjacent terminals. A semiconductor integrated circuit.   3. The semiconductor integrated circuit according to claim 1, wherein the overvoltage protection element comprises a diode or a MOS transistor whose gate and source are short-circuited.   4. The semiconductor integrated circuit according to claim 1, further comprising: a clamp circuit connected between the power supply line and ground and clamping a potential of the power supply line. 5.   5. The semiconductor integrated circuit according to claim 4, wherein the clamp circuit is formed by connecting a plurality of MOS transistors whose gates and sources are short-circuited in series.   A protection diode circuit connected to each of the plurality of terminals, the protection diode circuit being connected between the terminal and the ground; a first diode connected between the terminal and the power line; 6. The semiconductor integrated circuit according to claim 1, further comprising a second diode.

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