JP5687223B2 - Signal processing device, rotation angle detection device, and adjustment value setting device - Google Patents

Description

  The present invention is a Hall electromotive force that receives an output signal from a magnetoelectric conversion element such as a Hall element that can switch the direction of a bias current, and obtains a detection output having a value corresponding to a rotational angular displacement from a reference position in a magnetic field. The present invention relates to a signal processing device such as a signal detection device.

In recent years, as a device for measuring the rotation angle of a rotating shaft of a motor or a rotating body in a servo mechanism, a non-contact rotation angle sensor using a Hall element having excellent durability and reliability has been widely used. ing.
In such a non-contact rotation angle sensor using a Hall element, a change in Hall electromotive force generated in the Hall element is measured by a magnetic field generated by a magnet that is displaced in synchronization with the rotational displacement of the rotating body. Is detected by applying a digitizing process (AD conversion), and the rotation angle of the magnet (and hence the rotating body) is obtained based on the detected value (see, for example, Non-Patent Document 1, Patent Document 1, and Patent Document 2). .

FIG. 11 shows a non-contact rotation angle sensor using a silicon monolithic Hall element as an example of the non-contact rotation angle sensor as described above.
In the non-contact rotation angle sensor of FIG. 11, Hall elements X 1, X 2, Y 1, Y 2 and a signal processing circuit are formed in a silicon substrate 30.
A Vx signal can be obtained by calculating the difference between the Hall electromotive force signal generated in the Hall element X1 and the Hall electromotive force signal generated in the Hall element X2.

Similarly, the Vy signal can be obtained by calculating the difference between the Hall electromotive force signal generated in the Hall element Y1 and the Hall electromotive force signal generated in the Hall element Y2.
The Vx signal and Vy signal obtained as described above have the relationship of the following expression (1) with respect to the angle θ between the magnetic field created by the magnet attached to the rotating body and the rotation angle sensor.

In the above equation (1), Vamp, x and Vamp, y are magnetic sensitivities relating to the pair of Hall elements X1 and X2 and Hall elements Y1 and Y2, respectively.
Ideally, Vamp, x = Vamp, y is desirable, but for reasons such as process gradients in the semiconductor manufacturing process, Vamp, x ≠ Vamp, y, and each such pair of Hall elements X1 and The mismatch of the magnetic sensitivities of X2 and Hall elements Y1 and Y2 becomes one factor of the angle detection error in the rotation angle sensor.

  For example, when there is a magnetic sensitivity mismatch of 1% between Vamp, x and Vamp, y in the rotation angle sensor (when Vamp, x: Vamp, y = 1.00: 1.01), as in the following equation (2) When the true value of the angle is 45 °, an angle error of about 0.29 degrees occurs in the angle detection result output from the rotation angle sensor.

When a silicon monolithic Hall element is formed using a CMOS process, the mismatch between the magnetic sensitivities Vamp, x and Vamp, y is usually about 2% at the maximum.
On the other hand, when realizing a highly accurate rotation angle sensor by suppressing the angle error of the rotation angle sensor to about 0.03 degrees, the mismatch between the magnetic sensitivities Vamp, x and Vamp, y is 0.1% or Therefore, it is necessary to correct with a resolution lower than that, and the signal processing circuit is required to have a gain adjustment function with an extremely high resolution.

FIG. 12 shows a conventional example of a Hall electromotive force signal detection apparatus that cancels the offset of the Hall element by periodically switching the direction of the bias current of the Hall element in accordance with a clock signal having a frequency f_Mod (period T_Mod). FIG.
When the Hall electromotive force signal detection device of FIG. 12 is applied to a rotation angle sensor using Hall elements, a system corresponding to a pair of Hall elements X1 and X2 and a system corresponding to a system of Hall elements Y1 and Y2 12 is provided for each of the two systems, and the above-described magnetic sensitivities Vamp, x and Vamp, are obtained by performing precise gain adjustment with the Hall electromotive force signal detectors in both systems. The y mismatch is minimized.

In FIG. 12, the Hall electromotive force signal detected from the Hall element 410 through the switch circuit 420 is input to the primary ΔΣ modulator 440 through the demodulator 430, and the ΔΣ modulator 440 causes the reference voltage + Vref, -Quantized to 1 bit with respect to Vref.
The ΔΣ modulator 440 includes an adder 441, an integrator 442, a comparator 443, and a 1-bit DA converter 444.

The Hall electromotive force signal quantized to 1 bit as described above is output as a detection output signal through the low-pass filter 450. The cut-off frequency f_LPF of the low-pass filter 450 is set sufficiently lower than the sampling frequency f_SAMP and the clock frequency f_Mod of the ΔΣ modulator 440.
Note that a clock signal is supplied from the clock signal generator 460 to the switch circuit 420, and a switching operation synchronized with the clock signal (accordingly, a modulation process) is performed. The demodulator 430 is also supplied with a clock signal from the clock signal generator 460 and performs demodulation processing in synchronization with the clock signal.

The operation of switching the direction of the bias current of the Hall element in the Hall electromotive force signal detection apparatus of FIG. 12 will be described in more detail with reference to FIG.
FIG. 13 is a diagram for explaining detection of Hall electromotive force when the direction of the drive current (bias current) for biasing the Hall element is alternately switched between 0 degrees and 90 degrees with respect to the reference direction. is there. FIG. 13A shows the case where the direction of the bias current is 0 degree, and FIG. 13B shows the case where the direction of the bias current is 90 degrees.

In FIG. 13, the Hall element is modeled as a four-terminal element composed of four resistors, and is driven with a constant current. As shown in the figure, the magnetic flux B is assumed to be perpendicular to the paper surface and directed in the depth direction.
The voltage signals V_Sig_0deg and V_Sig_90deg measured when the direction of the bias current to the Hall element is alternately switched between 0 degree and 90 degrees are the same as the Hall electromotive force signal V_Hall and the offset Expressed as the sum of V_Offset.

   Here, as shown in Expression (4), the Hall electromotive force signal V_Hall can be modulated by the clock signal by alternately switching the direction of the bias current of the Hall element between 0 degree and 90 degrees. .

  On the other hand, as shown in Expression (5), the offset V_Offset has a substantially constant value even when the driving direction of the Hall element is alternately switched between 0 degrees and 90 degrees.

  As described above, when the operation of alternately switching the direction of the bias current of the Hall element between 0 degree and 90 degrees is repeated with a period T_Mod (frequency f_Mod = 1 / T_Mod), a signal output from the Hall element V_Sig_Mod is as shown in FIG.

FIG. 14 is a signal waveform diagram representing the signal V_Sig_Mod output from the Hall element in a timing relationship with related signals.
As shown in FIG. 14, the signal V_Sig_Mod output from the Hall element is obtained by superimposing the offset V_Offset on the Hall electromotive force signal V_Hall modulated by the clock signal from the clock signal generator 460 (FIG. 12). The waveform repeats with a period T_Mod.

  The signal V_Sig_Mod in FIG. 14 is input to the demodulator 430 (see FIG. 12), demodulated in synchronization with the same clock signal used to switch the direction of the bias current of the Hall element, and becomes the signal V_Sig_Dmod. . The demodulation process in the demodulator 430 is an operation of switching the sign of the signal V_Sig_Mod according to the phase of the clock signal, as shown in the equation (6).

In this signal V_Sig_Dmod, the Hall electromotive force signal component V_Hall is demodulated to DC, while the offset component V_Offset is modulated by the clock signal used for the above-described modulation processing.
As a result, the output signal V_Sig_Dmod of the demodulator 430 is expressed as shown in the following equation (7).

FIG. 15 is a diagram illustrating a frequency spectrum of the signal V_Sig_Mod and the signal V_Sig_Dmod after passing through the demodulator 430 (FIG. 12). FIG. 15A shows the frequency spectrum of the signal V_Sig_Mod, and FIG. 15B shows the frequency spectrum of the signal V_Sig_Dmod.
In the signal V_Sig_Mod of FIG. 15A, the Hall electromotive force signal is modulated to the modulation frequency f_Mod, and an offset V_Offset that is a DC signal is superimposed.
In the signal V_Sig_Dmod after passing through the demodulator in FIG. 15B, the Hall electromotive force signal V_Hall is demodulated to DC, while the offset V_Offset is modulated to the modulation frequency f_Mod.
By passing the signal V_Sig_Dmod having the spectrum as shown in FIG. 15 through the low-pass filter 450 having the cutoff frequency f_LPF as shown in FIG. 12, the component of the frequency f_Mod in the equation (7) can be removed.

  A method for canceling the offset V_Offset from the Hall electromotive force signal V_Sig_Mod as described above is known (see, for example, Non-Patent Document 2). Non-Patent Document 2 discloses a method of removing an offset from a Hall electromotive force signal as a “Connection commutation method”, and this method is already widely used as a technique for offset cancellation for a Hall element.

In the signal spectrum shown in FIG. 15 above, the sampling frequency f_SAMP of the sampling clock of the ΔΣ modulator is sufficiently higher than the modulation frequency f_Mod, so that noise aliasing (aliasing) does not occur. .
FIG. 16 is a diagram illustrating a circuit configuration of a ΔΣ modulator having a gain adjustment function. Note that the circuit itself configured as shown in FIG. 16 is known (see Non-Patent Document 3).

In the circuit of FIG. 16, the input signal is the signal V_Sig_Dmod output from the demodulator 430 (FIG. 12), and the signal output from this circuit is ΔΣ modulated with respect to V_Sig_Dmod with reference voltages + Vref and −Vref as references. This is ΔΣ (V_Sig_Dmod) obtained.
In the circuit of FIG. 16, the integrator is configured as a switched capacitor circuit, and is driven by two-phase non-overlap clocks φ1 and φ2.

In the circuit of FIG. 16, since the amount of charge input to the integrator changes according to the value of the gain adjustment signal (hereinafter, appropriately referred to as GAIN_ADJ signal), when the GAIN_ADJ signal becomes “1”, ΔΣ The gain of the modulator is (1−α1) times. In FIG. 16, each switch is turned on when the conditions attached to the symbols, for example, φ1 = 1, GAIN_ADJ = 1, φ1 = 1, GAIN_ADJ = 0, φ2 = 1, etc. are satisfied. Become.
The following table summarizes the gain switching status of the ΔΣ modulator using the GAIN_ADJ signal.

FIG. 17 is a diagram illustrating the relationship between the sampling clock supplied to the ΔΣ modulator of FIG. 16 and a gain adjustment signal having a certain duty ratio.
As shown in FIG. 17, when the GAIN_ADJ signal is generated so that the duty ratio is α2, the gain correction that is (1−α1) times per sampling operation is performed at the frequency of α2. Therefore, the gain of the ΔΣ modulator is given by the following equation (8).

  In such gain adjustment, in addition to the resolution at the capacitor = α1, the resolution based on the timing that can be managed with high accuracy on the time axis that the duty ratio of the GAIN_ADJ signal = α2 can be used. It is possible to obtain a high resolution for gain adjustment.

JP 2010-217150 A JP 2010-217151 A

ADS1208 data sheet from Texas Instruments (2nd-Order Delta-Sigma Modulator with Excitation for Hall Elements) Published by R S Popovic, Hall Effect Devices (ISBN-10: 0750300965) Inst of Physics Pub Inc (1991/05) van der Horn, Huijsing INTEGRATED SMART SENSORS (ISBN 0-7923-8004-5) Published by Kluwer Academic Publishers (1998)

FIG. 18 is a signal waveform diagram representing the signal V_Sig_Mod output from the Hall element in a timing relationship with related signals. FIG. 18 particularly illustrates a situation in which the effect of offset cancellation is impaired when the above-described gain adjustment function is combined with the above-described method of performing offset cancellation by modulating and demodulating the Hall electromotive force signal. doing.
In the situation illustrated in FIG. 18, the clock signal period T_Mod for modulating the Hall electromotive force signal is an integral multiple of the sampling period of the ΔΣ modulator.

  In the case of FIG. 18, the timing at which the GAIN_ADJ signal becomes “1” matches the phase at which the bias direction of the Hall element is 0 degrees each time, and thus is output from the demodulator 430 (FIG. 12). The gain is adjusted each time only during the low level period of the signal V_Sig_Dmod, and therefore the offset cancellation effect due to the cancellation of the V_Sig_Dmod with the high level period does not occur, and the offset shown in the above-described equation (5) It can be seen that the accuracy of cancellation is impaired.

The problems of the prior art will be described in more detail.
That is, FIG. 19 shows a more specific case where the accuracy of offset cancellation is impaired when the above gain adjustment function is combined with the method of performing offset cancellation by modulating and demodulating the Hall electromotive force signal described above. Show. FIG. 19A shows the sampling clock of the ΔΣ modulator, and the waveform of the chopper clock (period T_chop) whose phase is switched every time the sampling clock is generated eight times is as shown in FIG. That is, the chopper clock is generated by dividing the sampling clock by 16. If the GAIN_ADJ signal is generated once in synchronization with the chopper clock, the result is as shown in FIG. In the example of FIG. 19C, the GAIN_ADJ signal is generated when the chopper clock is in the high level period. The GAIN_ADJ signal is always generated only when the chopper clock is at the high level. Has been. For this reason, while the gain adjustment of the DC component (Hall electromotive force signal V_Hall) of the signal V_Sig_Dmod is performed, the gain adjustment also affects the AC component (offset V_Offset). Therefore, the accuracy of offset cancellation shown in the above-described equation (5) is impaired.

  FIG. 20 shows another case where the accuracy of offset cancellation is impaired. In this example, every time the sampling clock is generated 16 times, the GAIN_ADJ signal is generated 3 times. In this case, the GAIN_ADJ signal is generated once when the chopper clock is in the high level period and is generated twice when it is in the low level period. For this reason, the GAIN_ADJ signal acts to depress the average value for the AC component (offset V_Offset), and the accuracy of offset cancellation is impaired.

As a result of analysis and consideration of the conventional technology as described above, the inventor found that the accuracy of offset suppression as described above is effective when the conventional technologies related to gain adjustment and offset cancellation are combined. I found out that there was a problem of damage.
That is, the Hall electromotive force signal detected from the Hall element is modulated by sequentially switching the direction of the bias current supplied to the Hall element in synchronization with the two-phase clock signal, and the modulated Hall electromotive force signal is modulated. A modulation-demodulation process for demodulating the signal in synchronization with the clock signal, then ΔΣ modulation by a ΔΣ modulator, and an offset cancellation processing method for frequency-separating and removing an offset component from the ΔΣ modulated signal; If the gain adjustment signal based on the gain adjustment signal for adjusting the duty ratio in the repetition of the integration operation in the integrator of the ΔΣ modulator is simply combined, the accuracy of the offset cancellation is impaired. And the technique which avoids the problem that the precision of offset cancellation in the above is impaired has not yet been proposed.

  Accordingly, an object of the present invention is to provide a method for performing offset cancellation by modulating and demodulating a Hall electromotive force signal detected by sequentially switching the direction of a bias current supplied to the Hall element by a clock signal, and a Hall electromotive force. The accuracy of offset cancellation is not compromised while combining the gain adjustment method by adjusting the duty ratio in the integration operation of the integrator of the ΔΣ modulator to process the signal and obtain the detection output The Hall electromotive force signal detection device is to be realized.

In order to achieve the above object, the following technologies are proposed here.
(1) A magnetoelectric transducer element that outputs a signal that varies according to the magnetic field strength and includes a magnetic signal component and an offset signal component;
A clock signal output unit for outputting a clock signal;
A signal adjustment unit that demodulates the magnetic signal component into a direct current component and modulates an offset signal component into an alternating current component among signals output from the magnetoelectric conversion element unit every time the clock signal is generated N times;
A sensitivity correction unit that outputs a signal obtained by modulating the output signal of the signal adjustment unit at a frequency of adjustment value n ′ times each time the clock signal is counted N ′ times;
An A / D converter for A / D converting the output signal of the sensitivity correction unit in synchronization with the clock signal;
With
N, n, N ′, n ′ are natural numbers, N, N ′ are powers of 2, N ′> n ′, N ′ ≧ 2N,
n ′ = 2n−1
A signal processing device characterized by satisfying

(2) In the above (1), the N ′ is 256, and the adjustment value n ′ is an odd number of 1 or more and 15 or less.
(3) In the above (1) or (2), the clock signal output unit outputs a clock signal at predetermined time intervals.
(4) The signal processing device according to any one of (1) to (3), wherein the sensitivity correction unit modulates an output signal of the signal adjustment unit at predetermined time intervals.
(5) A rotation angle detection device including the signal processing device according to any one of (1) to (4).
(6) An adjustment value setting device for setting the adjustment value n ′ in the signal processing device according to any one of (1) to (4),
A storage unit for storing the adjustment value n ′ as a binary number of a plurality of bits;
Of the bits stored as the adjustment value n ′, the storage unit can set a logical value 1 in advance for the least significant bit, and can set a logical value 1 or a logical value 0 for the other bits. An adjustment value setting device characterized by that.

  A method of modulating and demodulating an electromotive force signal detected by sequentially switching the direction of a bias current supplied to the magnetoelectric conversion element alternately with a clock signal to perform offset cancellation, and processing the electromotive force signal to obtain a detection output Therefore, it is possible to realize a signal processing device that does not impair the accuracy of offset cancellation while combining with a method of performing gain adjustment by adjusting the duty ratio in the repetition of the integration operation in the integrator.

It is a figure showing the Hall electromotive force signal detection apparatus as embodiment of this invention. It is a block diagram which shows the structure of a bit stream generator. It is a signal waveform diagram which shows Hall electromotive force signal V_Hall, offset component V_Offset, and gain adjustment signal GAIN_ADJ on a time axis. The signal component shown in FIG. 3A is multiplied by the gain adjustment signal GAIN_ADJ shown in FIG. 3C, and the offset component shown in FIG. 3B is multiplied by the gain adjustment signal GAIN_ADJ shown in FIG. FIG. FIG. 5 is a signal waveform diagram showing signals obtained by adding a signal component and an offset component included in an original signal V_Sig_Dmod to each signal shown in FIGS. It is a signal waveform diagram which shows an example in which the effect of offset cancellation was impaired. It is a graph which shows the influence of an offset in case the period of a chopper clock is 16. It is a graph which shows the influence of the offset in this embodiment. It is a perspective view which shows the structure of an adjustment value installation apparatus. It is a flowchart explaining an adjustment value installation process. It is a figure which shows the conventional non-contact rotation angle sensor using a silicon monolithic Hall element. It is a figure showing the prior art example of the Hall electromotive force signal detection apparatus of the system which switches the direction of the bias current of a Hall element periodically, and cancels the offset of a Hall element. It is a figure for demonstrating the detection of Hall electromotive force when the direction of the bias current of the Hall element is alternately switched between 0 degrees and 90 degrees with respect to the reference direction. It is a signal waveform diagram which represented the signal output from a Hall element in the timing relationship with a related signal. It is a figure showing the frequency spectrum of the signal which the Hall electromotive force signal modulated with the clock signal and this signal demodulated with this clock signal. It is a figure which shows the circuit structure of the delta-sigma modulator provided with the gain adjustment function. FIG. 12 is a diagram illustrating a relationship between a sampling clock supplied to the ΔΣ modulator of FIG. 11 and a gain adjustment signal having a certain duty ratio. FIG. 6 is a signal waveform diagram showing a signal output from the Hall element in a timing relationship with a related signal when the effect of offset cancellation is impaired. It is a signal waveform diagram which shows one specific example in which the effect of offset cancellation is impaired. It is a signal waveform diagram which shows the other specific example in which the effect of offset cancellation is impaired.

Hereinafter, the present invention will be clarified by describing embodiments of the present invention in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a functional block diagram showing a Hall electromotive force signal detection apparatus according to an embodiment of the present invention.
When this Hall electromotive force signal detection device is applied to a rotation angle sensor using a Hall element as a magnetoelectric conversion element, a first system corresponding to a pair of Hall elements X1 and X2, and these Hall elements X1 and X2 A circuit having the same configuration as in FIG. 1 is provided for each of the second system corresponding to the other pair of Hall elements Y1 and Y2 aligned in a direction perpendicular to the alignment direction of the Hall elements.

This enables precise gain adjustment so that the mismatch between the magnetic sensitivity Vamp, x relating to the pair of Hall elements X1 and X2 and the magnetic sensitivity Vamp, y relating to the other pair of Hall elements Y1 and Y2 is minimized.
That is, in this embodiment, a clock signal generator 161 that generates a clock signal (sampling clock) with a period T is provided, and the clock signal (period T) generated by the clock signal generator 161 is divided to obtain a chopper clock. A frequency divider 165 for generating (period T_chop) is provided. The chopper clock generated by the frequency divider 165 is supplied to the switch circuit 120 and the demodulator 130. In addition, a bit stream generator 200 to which a clock frequency is supplied is provided.

The bit stream generator 200 is a circuit that generates a GAIN_ADJ signal, and is a known one as described in Non-Patent Document 3. Specifically, the bitstream generator 200 is a digital bitstream generator as shown in FIG. 2, and includes an x-bit shift register 201, a full adder 202, and a register 203.
The adjustment value n ′ is the generation frequency of the GAIN_ADJ signal, and the sampling clock is the same as the ΔΣ modulator sampling clock (clock signal). In this configuration, the adjustment value n ′ is accumulated by the full adder 202 and the register 203 for each sampling clock, and the accumulation result exceeds the full ^adder range N ′ (normally N ′ = 2 ^{x ′ in} the case of x′-bit). When overflow occurs, the GAIN_ADJ signal is generated. That is, while the ΔΣ modulator sampling clock is counted 2x ′ times, the GAIN_ADJ signal is generated n ′ times, and the correction frequency α2 is expressed by n ′ / N ′.

Returning to FIG. 1, the Hall element 110 is supplied with a bias current that is sequentially switched in a direction orthogonal to each other by the switch circuit 120, and the polarity is inverted in synchronization with the switching. A Hall electromotive force signal is output via the switch circuit 120.
The Hall electromotive force signal output as described above is a signal modulated by the switching frequency in the switching circuit 120, that is, the chopper clock. Then, the modulated signal is demodulated by the demodulator 130 by a demodulation operation synchronized with the same frequency as the frequency in the above-described modulation. An amplifier (preamplifier circuit) 125 is provided at the subsequent stage of the switch circuit 120, and the signal V_Sig_Mod amplified by the amplifier 125 is supplied to the demodulator 130.

The signal demodulated by the demodulator 130 is input to the first-order ΔΣ modulator 140 and is quantized to 1 bit with reference to the reference voltages + Vref and −Vref.
The ΔΣ modulator 140 includes an adder 141, an integrator 142, a comparator 143, a 1-bit DA converter 144, an amplifier 210, and a multiplier 220.
The gain adjustment in the ΔΣ modulator 140 is performed using a gain adjustment signal supplied from the bit stream generator 220.

That is, an amplifier 210 that multiplies the signal V_Sig_Dmod, which is the output of the demodulator 130, by a gain α1, and a multiplier 220 that multiplies the output of the amplifier 210 and the GAIN_ADJ signal. The output of the multiplier 220 is supplied to the adder 141.
In the configuration of the present embodiment, the adjustment amount as the gain adjustment circuit can be arbitrarily set by appropriately selecting the adjustment value n ′ supplied to the bit stream generator 200. That is, before the rotation angle detection device is shipped, the Hall electromotive force in the state where the adjustment value n ′ is 0 (the GAIN_ADJ signal is not input) and the magnet having a known magnitude is applied to the Hall element. Measure the signal V_Det. Gain adjustment so that the Hall electromotive force signal V_Det at that time is deviated from a signal of a magnitude that should be output according to the known magnetism, and the deviation becomes zero The adjustment value n ′ is selected and set in a memory or the like in the bitstream generator 200.

The Hall electromotive force signal quantized to 1 bit as described above is output as a detection output signal through the low-pass filter 150.
The cut-off frequency f_LPF of the low-pass filter 150 is set sufficiently lower than the sampling frequency f_SAMP and the clock frequency f_Mod of the ΔΣ modulator 140. This is because offset cancellation is performed by modulating and demodulating the Hall electromotive force signal as described above, then performing ΔΣ modulation by a ΔΣ modulator, and frequency-separating and removing offset components from the ΔΣ modulated signal. This is because the processing is performed effectively.

In addition, regarding the operation of switching the direction of the bias current of the Hall element in the Hall electromotive force signal detection device of FIG. 1, the above description is incorporated with reference to FIG.
FIG. 3 shows (a) a Hall electromotive force signal V_Hall that is a signal component (DC component) included in the signal V_Sig_Dmod, (b) an offset component (AC component) V_Offset included in the signal V_Sig_Dmod, and (c). It is a figure which shows the gain adjustment signal GAIN_ADJ on a time-axis, respectively.

  Since the gain adjustment by the gain adjustment signal GAIN_ADJ is to multiply the signal V_Sig_Dmod by a pulse signal having a magnitude of α1 at a frequency of α2, the signal components shown in FIG. The gain adjustment signal GAIN_ADJ shown in 3 (c) is multiplied, and the offset component shown in FIG. 3 (b) is multiplied by the gain adjustment signal GAIN_ADJ shown in FIG. 3 (c).

  The results of these multiplications are as shown in FIGS. That is, the Hall electromotive force signal V_Hall, which is the signal component (DC component) included in the signal V_Sig_Dmod, is a pulse train that always has an amplitude in the positive direction in synchronization with the gain adjustment signal GAIN_ADJ, and the offset component (AC component) V_Offset In this manner, a pulse train whose amplitudes are alternately reversed in the positive direction and the negative direction in synchronization with the gain adjustment signal GAIN_ADJ.

  4A and 4B are added to the original signal V_Sig_Dmod. Therefore, considering each signal component, the signals are as shown in FIGS. 5A and 5B. That is, the Hall electromotive force signal V_Hall is a signal in which a small amplitude is always added in the positive direction in synchronization with the gain adjustment signal GAIN_ADJ with respect to the DC component that is the original signal, and the offset component (AC component) V_Offset is In this manner, a pulse train whose amplitudes are alternately reversed in the positive direction and the negative direction in synchronization with the gain adjustment signal GAIN_ADJ.

  For this reason, by integrating the signal shown in FIG. 5A, the gain adjustment is performed on the Hall electromotive force signal V_Hall according to the magnitude and frequency of occurrence of the gain adjustment signal GAIN_ADJ. On the other hand, even if the signal shown in FIG. 5B is integrated, since the integral value of the gain adjustment signal GAIN_ADJ is 0, the accuracy of offset cancellation can be maintained. Incidentally, if the GAIN_ADJ signal is generated at the timing shown in FIG. 18, the GAIN_ADJ signal is superimposed on the offset component V_Offset as shown in FIG. 6A. As shown in b), the effect of offset cancellation is impaired.

That is, FIG. 7 shows that when the cycle of the chopper clock is 16, the GAIN_ADJ signal is generated at a frequency of n ′ every time the clock signal is generated 256 (= N ′ = 2 ⁸ ) times. It is a graph which shows the influence of the offset corresponding to shaking the n 'from 0 to 255.
The best when only the influence of the offset is considered is one of the portions indicated by A in FIG. 7, that is, the case where the influence on the offset becomes zero. In this best case, since the GAIN_ADJ signal is superimposed by the same number of times in the positive and negative directions of the offset component V_Offset, the integral value becomes zero.

The GAIN_ADJ signal, which corresponds to such a best case, allows the offset signal to be integrated and canceled with high precision so that a relatively high level period and a low level period form a pair in a continuous period. become.
However, the portion indicated by A in FIG.
Therefore, in this embodiment, by making it possible to easily select an appropriate value as the adjustment value n ′, the burden on the designer is reduced, and a Hall electromotive force signal detection device having an accuracy within an allowable range is ensured. We are trying to make it easier to get to.

Here, the gain of the ΔΣ modulator is determined by the product (α1 × α2) of the resolution (α1) in the capacitor and the duty ratio (α2) of the GAIN_ADJ signal, as given by the above equation (8).
When a large gain adjustment is necessary, there is no particular problem because both α1 and α2 are large, but in practice, there is often no need for such a large gain adjustment.

When the gain adjustment width itself is small, it is necessary to either reduce the capacitance value of the capacitor C1 shown in FIG. 16 sufficiently or to reduce the duty ratio of the GAIN_ADJ signal sufficiently.
Although it is easy to reduce the capacitance of the capacitor C1, if the accuracy of the semiconductor manufacturing process is not sufficiently high, the variation among devices becomes large, and it may take time to adjust the gain.

Therefore, it is considered that the capacitance value of the capacitor C1 is not reduced so much, but the duty ratio α2 of the GAIN_ADJ signal is reduced, and the influence on the offset is not significantly deteriorated.
Specifically, in the present embodiment, an odd number (= 2n−1) is used as the adjustment value n ′.

Here, if one cycle of the chopper clock is 360 degrees, the GAIN_ADJ signal is generated at a position that divides the angular range of 360 degrees × N ′ / 2N by 2n−1. In this case, the following relational expression holds for each phase of the chopper clock for generating the GAIN_ADJ signal.
That is, when each phase of the chopper clock is written in a sequence of numbers,

It becomes.
When the above equation (9) is MOD-calculated, the following equation (10) is obtained.

From the above equation (10), the configuration in which the range of chopper clock 360 degrees × N ′ / 2N is divided by n ′ (= 2n−1) is that the range of 360 degrees is equally divided by odd numbers (2n−1). Is equivalent to
If the 360 degree range is divided by an odd number, the sign of the sine function at each phase will be either if it contains a lot of + only once or if it contains a lot of-only once. Strictly speaking, it is not 0, but it can be said that it is almost balanced. In other words, if the device is devised as in the present embodiment, a configuration in which a + or − offset is taken only once in a cycle of N ′ / 2N times the chopper clock cycle.

FIG. 8 shows the influence on the offset at each adjustment value n ′ in the present embodiment. Compared to the worst case shown in the parts B and C of FIG. It is suppressed to about 8.
FIG. 9 is a perspective view showing a schematic configuration of the adjustment value setting device 300 used when setting the adjustment value n ′, and FIG. 10 is a flowchart showing a procedure for setting the adjustment value n ′.

  That is, the adjustment value setting apparatus 300 sets the Hall electromotive force signal detection apparatus 301 in an unadjusted gain state, which is sequentially conveyed on the slider 350, on the test board 310 for gain adjustment one by one by the handler 302, The Hall electromotive force signal detection device 302 whose gain adjustment has been completed on the test board 310 is returned to the slider 350 by the handler 303 and sequentially carried out.

  On the test board 310, an X-direction magnetic field application coil 311X and a Y-direction magnetic field application coil 311Y are provided. A current of a predetermined magnitude is supplied to the coils 311X and 311Y in order by the inspection unit 320. Thus, a known magnetic field is generated. Then, the magnitude of each magnetic field is measured by the Hall electromotive force signal detection device 301 during gain adjustment set on the test board 310, and the measured value is displayed on the monitor 360. Based on the deviation between the displayed measurement and the known reference value, an adjustment value n ′ is selected, and the adjustment value n ′ is set to the Hall occurrence during gain adjustment set on the test board 310 by the inspection unit 32. The data is written in the power signal detection device 301. The adjustment value n ′ is specifically stored in a nonvolatile memory provided in the bit stream generator 200.

The adjustment value setting process in the adjustment value setting device 300 is shown in more detail in FIG.
That is, first, in step S100, the element before sensitivity correction (the Hall electromotive force signal detection device 301 without gain adjustment) is moved from the slider 350 onto the test board 310 by the handler 303 and fixed.

Next, the process proceeds to step S110, and the X-direction magnetic field application coil 311X is energized, and the X-direction magnetic sensitivity Vamp, x (unit: V / T) is calculated in the state where the X-direction magnetic field is generated. Read out from the element. Specifically, the inspection unit 350 reads the Hall electromotive force signal V_Det from the low-pass filter 150 shown in FIG.
Next, the process proceeds to step S120, and the same procedure as in step S110 is performed, and the magnetic sensitivity Vamp, y (unit: V / T) in the Y direction is read from the element through the inspection unit 350.

Next, the process proceeds to step S130, and the magnitude of sensitivity mismatch between XY is calculated from the calculation of 1- (Vamp, Y / Vamp, X).
Then, the process proceeds to step S140, where the adjustment value n ′ is determined according to the magnitude of the sensitivity mismatch, and the non-volatile memory (in the bit stream generator 200 in the bit electromotive force signal detecting device 301) is built in the Hall electromotive force signal detection device 301 through the inspection unit 350. The value of the adjustment value n ′ is written into the non-volatile memory. When the process of step S140 is completed, the processes after step S100 are executed again for the next element.

Here, in the process in step S140, only an odd number is forcibly set as the adjustment value n ′.
Specifically, the adjustment value n ′ can be written in a binary number of multiple bits (for example, 4 bits “0000 to 1111”), and among the 4 bits, the least significant bit has a logical value of 1 in advance. Is set so that the operator cannot change it. For other bits, a logical value 1 or a logical value 0 can be freely set. That is, in the present embodiment, only an odd number from 1 to 15 in decimal is set as the adjustment value n ′. Considering that this is a practical case where the nonvolatile memory in the bitstream generator 200 has a 4-bit configuration, it is not possible to set the adjustment value n ′ to an odd number between 1 and 15. This is preferable as a realistic response.

For example, in the configuration of the present embodiment, even if the operator tries to set “1000” (decimal number 8) as the adjustment value n ′, “1001” (decimal number 9) is automatically set. It will be.
Since only an odd number is set as the adjustment value n ′ in this way, the influence of the adjustment value n ′ on the offset becomes a predetermined value as shown in FIG. That is, the effect of the offset does not become zero, but a minimum value is sufficient.

Therefore, even an unskilled operator does not select the adjustment value n ′ that erroneously affects the offset and becomes the portion B or C in FIG. 7, thereby ensuring the effect of the offset. Can be obtained.
Further, as shown in FIG. 1, in the configuration in which the gain adjustment signal generator 145 is provided in the ΔΣ modulator 140, the gain adjustment signal generator 145 is not provided outside the ΔΣ modulator, and the gain is adjusted in the ΔΣ modulator 140. It is possible to complete the process related to the adjustment.

On the other hand, the gain adjustment signal generator 145 may be arranged outside the ΔΣ modulator 140. When this configuration is adopted, the configuration of the ΔΣ modulator itself is simplified.
Here, in the present embodiment, a signal adjustment unit is configured by the switch circuit 120 and the demodulator 130, and a sensitivity correction unit is configured by the bitstream generator 200, the amplifier 210, and the multiplier 220, and among the ΔΣ modulator 140, The configuration other than the sensitivity correction unit corresponds to the A / D conversion unit.

(Modifications, etc.)
In the above description with reference to FIG. 13 showing the Hall element as a model, the direction of the bias current of the Hall element is alternately switched between 0 degrees and 90 degrees. The possibility of selection is not limited to the above.
That is, as long as the Hall electromotive force signal V_Sig_Mod generated by the Hall element is modulated by the clock signal described above, as long as the Hall electromotive force signal is detected by switching the direction of the bias current of the Hall element, the selection is performed. A case where the direction of the bias current is set to 180 degrees, 270 degrees, or the like may be included as a selectable direction.
Moreover, it is preferable from a viewpoint of design ease that a clock signal is produced | generated for every fixed time interval. The GAIN_ADJ signal is generated at regular time intervals, but is preferable from the viewpoint of ease of design. That is, if the clock signal is generated every predetermined time interval T, the GAIN_ADJ signal is preferably generated every predetermined time interval (N ′ / n ′) × T.

  The scope of the present invention is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that provide equivalent effects to those intended by the present invention. Further, the scope of the present invention is not limited to the combinations of features of the invention defined by claim 1, but can be defined by any desired combination of specific features among all the disclosed features. .

110, 410 ............ Hall element 120, 420 ............ Bias current source 130, 430 .................. Demodulator 140, 440 ........................... ΔΣ modulator 141, 441 ... Adders 142, 442 ......... Integrators 143, 443 ... Comparators 144, 444 ... 1-bit DA Converters 150 and 450... Low-pass filters 161 and 460... Clock signal generator 165. …………… Bitstream Generator

Claims (6)

A magnetoelectric transducer element that outputs a signal that varies according to the magnetic field intensity and includes a magnetic signal component and an offset signal component;
A clock signal output unit for outputting a clock signal;
A signal adjustment unit that demodulates the magnetic signal component into a direct current component and modulates an offset signal component into an alternating current component among signals output from the magnetoelectric conversion element unit every time the clock signal is generated N times;
A sensitivity correction unit that outputs a signal obtained by modulating the output signal of the signal adjustment unit at a frequency of adjustment value n ′ times each time the clock signal is counted N ′ times;
An A / D converter for A / D converting the output signal of the sensitivity correction unit in synchronization with the clock signal;
With
N, n, N ′, n ′ are natural numbers, N, N ′ are powers of 2, N ′> n ′, N ′ ≧ 2N,
n ′ = 2n−1
A signal processing device characterized by satisfying   The signal processing apparatus according to claim 1, wherein N ′ is 256, and the adjustment value n ′ is an odd number of 1 or more and 15 or less. The signal processing apparatus according to claim 1, wherein the clock signal output unit outputs a clock signal at predetermined time intervals.   The signal processing apparatus according to claim 1, wherein the sensitivity correction unit modulates an output signal of the signal adjustment unit at predetermined time intervals.   A rotation angle detection device comprising the signal processing device according to claim 1. An adjustment value setting device for setting the adjustment value n ′ in the signal processing device according to claim 1,
A storage unit for storing the adjustment value n ′ as a binary number of a plurality of bits;
Of the bits stored as the adjustment value n ′, the storage unit can set a logical value 1 in advance for the least significant bit, and can set a logical value 1 or a logical value 0 for the other bits. An adjustment value setting device characterized by that.

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