JP5580458B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a seal ring surrounding a chip region and a manufacturing method thereof.

  Some semiconductor devices have a seal ring region provided so as to surround the chip region in plan view in order to prevent water from entering the chip region in which the electric circuit is formed. The seal ring region has a seal ring formed on the substrate so as to extend in the thickness direction of the substrate. Since this seal ring functions as a protective wall against water, water can be prevented from entering the tip region.

  This seal ring may be broken in a dicing process during manufacturing of the semiconductor device. This destruction phenomenon will be explained step by step. First, chipping occurs at the edge of the substrate due to dicing. Starting from this chipping, cracks progress in the interlayer insulating film provided on the substrate. When this crack reaches the seal ring, the seal ring is broken. When this breakdown occurs, water easily enters the chip region, which causes a problem that the reliability of the semiconductor device is lowered.

  This problem is more likely to occur when a low dielectric constant film made of a low-k material or an ULK (Ultra Low-k) material is used as an interlayer insulating film to reduce parasitic capacitance. This is because the low-k material and the ULK material have a low mechanical strength and thus are more susceptible to cracking. For example, when Young's modulus is used as an index of mechanical strength, the Young's modulus of SiO (silicon oxide) which is a general material of an interlayer insulating film (non-low-k film) is about 75 GPa, whereas low− The Young's modulus of the organic silica glass which is one of the k materials is about 10 GPa to 25 GPa. In addition, the ULK material, which is a porous material for further lowering the dielectric constant, has a smaller Young's modulus. For this reason, in the semiconductor device using the low dielectric constant film, the problem of the seal ring destruction due to the crack is more likely to occur.

  Further, in a semiconductor device, a configuration in which another interlayer insulating film having higher mechanical strength is arranged on one interlayer insulating film made of a low dielectric constant film material is often used. In this case, a crack extending from one interlayer insulating film is unlikely to enter another interlayer insulating film having a larger mechanical strength. For this reason, cracks are difficult to escape above the semiconductor device, and are likely to advance along the in-plane direction of the semiconductor device. As a result, the possibility that the seal ring is broken due to the crack reaching the seal ring becomes higher.

  As described above, since cracks in the interlayer insulating film can adversely affect the reliability of the semiconductor device, a technique for suppressing the occurrence of cracks has been proposed. For example, Japanese Laid-Open Patent Publication No. 2004-153015 (Patent Document 1) proposes providing a dummy pattern formation region around a guard ring (seal ring). This dummy pattern formation region has a plurality of dummy patterns at each of a plurality of locations in plan view. The plurality of dummy patterns are arranged along the thickness direction, and are integrated by via connection along the thickness direction. According to this publication, the interlayer insulating film in the vicinity of the dummy pattern can be reinforced by via connection, so that the generation of cracks in the interlayer insulating film is prevented.

JP 2004-153015 (Fig. 1-3)

  The technique of the above publication is a technique for preventing cracks from occurring in the interlayer insulating film. However, in the dicing process, a large stress frequently occurs, so even if the technique disclosed in the above publication is applied, it is difficult to sufficiently prevent the generation of cracks in the interlayer insulating film.

  And once a crack generate | occur | produces, this crack can be extended so that the reinforced part among the interlayer insulation films may be sewn. That is, this crack can be extended to avoid the dummy pattern integrated with the via, and finally reach the seal ring. As a result, there is a problem that the seal ring may be broken.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which a seal ring is not easily broken due to a crack in an interlayer insulating film, and a manufacturing method thereof.

According to one embodiment, the semiconductor device includes a chip region, a seal ring region surrounding the chip region in plan view, and an outer region surrounding the outer periphery of the seal ring region in plan view. The outer region is provided on a semiconductor substrate, a first stacked body including a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate, and the first stacked body. In addition, a second stacked body including a second interlayer insulating film having a second dielectric constant larger than the first dielectric constant and a plurality of layers provided in the first stacked body so as to overlap each other in plan view A plurality of first metal regions including a first metal layer and a plurality of second metal regions including a plurality of second metal layers provided in the second stacked body so as to overlap each other in plan view. Including. The plurality of second metal regions are arranged in an array of columns and rows in plan view. The column and row arrangement includes at least four columns that extend substantially parallel to adjacent portions of the seal ring region in plan view. In plan view, the first row of at least four rows is closest to the seal ring region, the fourth row of at least four rows is furthest from the seal ring region, and the second and third rows of at least four rows. A column exists between the first and fourth columns, the second column is closer to the first column, and the third column is closer to the fourth column. The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region. In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and is separated from the seal ring region. . The plurality of first metal regions and the plurality of second metal regions are not connected by vias.
According to one embodiment, the semiconductor device includes a chip region, a seal ring region surrounding the chip region in plan view, and an outer region surrounding the outer periphery of the seal ring region in plan view. The outer region is provided on a semiconductor substrate, a first stacked body including a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate, and the first stacked body. In addition, a second stacked body including a second interlayer insulating film having a second dielectric constant larger than the first dielectric constant and a plurality of layers provided in the first stacked body so as to overlap each other in plan view A plurality of first metal regions including a first metal layer and a plurality of second metal regions including a plurality of second metal layers provided in the second stacked body so as to overlap each other in plan view. Including. The plurality of second metal regions are arranged in an array of columns and rows in plan view. The column and row arrangement includes at least four columns that extend substantially parallel to adjacent portions of the seal ring region in plan view. In plan view, the first row of at least four rows is closest to the seal ring region, the fourth row of at least four rows is furthest from the seal ring region, and the second and third rows of at least four rows. A column exists between the first and fourth columns, the second column is closer to the first column, and the third column is closer to the fourth column. The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region.

According to another embodiment, a semiconductor device includes a semiconductor substrate, a chip region formed on the semiconductor substrate, a seal ring region surrounding the chip region formed on the semiconductor substrate in plan view, and a planar surface. A first region including an outer region surrounding the outer periphery of the seal ring region formed on the semiconductor substrate in view, and a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate in the outer region. And a second insulating layer including a second interlayer insulating film having a second dielectric constant greater than the first dielectric constant provided on the first insulating layer in the outer region, A plurality of first metal regions including at least one first metal layer provided in the first insulating layer; and a plurality of first metal regions including at least one second metal layer provided in the second insulating layer. 2 metal regions. The plurality of second metal regions are arranged in a plurality of rows extending substantially parallel to adjacent portions of the seal ring region, and the second metal regions in the directly adjacent rows are in a plan view. They are staggered against each other. In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and is separated from the seal ring region. . The plurality of first metal regions and the plurality of second metal regions are not connected by vias.
According to another embodiment, a semiconductor device includes a semiconductor substrate, a chip region formed on the semiconductor substrate, a seal ring region surrounding the chip region formed on the semiconductor substrate in plan view, and a planar surface. A first region including an outer region surrounding the outer periphery of the seal ring region formed on the semiconductor substrate in view, and a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate in the outer region. And a second insulating layer including a second interlayer insulating film having a second dielectric constant greater than the first dielectric constant provided on the first insulating layer in the outer region, A plurality of first metal regions including at least one first metal layer provided in the first insulating layer; and a plurality of second metal regions including at least one second metal layer. . The plurality of second metal regions are arranged in a plurality of rows extending substantially parallel to adjacent portions of the seal ring region, and the second metal regions in the directly adjacent rows are in a plan view. They are staggered against each other.

According to still another embodiment, a semiconductor device includes a semiconductor substrate, a chip region formed on the semiconductor substrate, a seal ring region surrounding the chip region formed on the semiconductor substrate in plan view, An outer region surrounding the outer periphery of the seal ring region formed on the semiconductor substrate in plan view, and a first interlayer insulating film having a first dielectric constant and provided on the semiconductor substrate in the outer region. A first insulating layer, and a second insulating layer including a second interlayer insulating film having a second dielectric constant larger than the first dielectric constant, which is provided on the first insulating layer in the outer region. A plurality of first metal regions including at least one first metal layer provided in the first insulating layer and a plurality including at least one second metal layer provided in the second insulating layer. Semiconductor device comprising a second metal region It is. The plurality of second metal regions are arranged in an array of columns and rows in plan view. The column and row arrangement includes at least four columns that extend substantially parallel to adjacent portions of the seal ring region in plan view. In plan view, the first row of at least four rows is closest to the seal ring region, the fourth row of at least four rows is furthest from the seal ring region, and the second and third rows of at least four rows. A column exists between the first and fourth columns, the second column is closer to the first column, and the third column is closer to the fourth column. The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region. In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and is separated from the seal ring region. . The plurality of first metal regions and the plurality of second metal regions are not connected by vias.
According to still another embodiment, a semiconductor device includes a semiconductor substrate, a chip region formed on the semiconductor substrate, a seal ring region surrounding the chip region formed on the semiconductor substrate in plan view, An outer region surrounding the outer periphery of the seal ring region formed on the semiconductor substrate in plan view, and a first interlayer insulating film having a first dielectric constant and provided on the semiconductor substrate in the outer region. A first insulating layer, and a second insulating layer including a second interlayer insulating film having a second dielectric constant larger than the first dielectric constant, which is provided on the first insulating layer in the outer region. A plurality of first metal regions including at least one first metal layer provided in the first insulating layer, and a plurality of second metal regions including at least one second metal layer. It is a semiconductor device. The plurality of second metal regions are arranged in an array of columns and rows in plan view. The column and row arrangement includes at least four columns that extend substantially parallel to adjacent portions of the seal ring region in plan view. In plan view, the first row of at least four rows is closest to the seal ring region, the fourth row of at least four rows is furthest from the seal ring region, and the second and third rows of at least four rows. A column exists between the first and fourth columns, the second column is closer to the first column, and the third column is closer to the fourth column. The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region.

  A semiconductor device according to one aspect of the present embodiment is a semiconductor device having a chip region, a seal ring region surrounding the chip region in plan view, and a dummy region surrounding the outer periphery of the seal ring region in plan view. The dummy region includes a semiconductor substrate, first and second stacked bodies, at least one first region, and at least one second region. The first stacked body is provided on the semiconductor substrate and includes a first interlayer insulating film having a first mechanical strength. The second stacked body is provided on the first stacked body, and includes a second interlayer insulating film having a mechanical strength larger than the first mechanical strength. The first region has a plurality of first metal layers provided in the first stacked body so as to overlap each other in a plan view, and vias connecting the plurality of first metal layers to each other. The second region has a plurality of second metal layers provided in the second stacked body so as to overlap each other in a plan view, and vias connecting the plurality of second metal layers to each other. The second region overlaps at least a part of the first region in plan view, is not connected to the first region by a via, and has a second interlayer insulating film between the first region and the second region. It is sandwiched.

  A semiconductor device according to another aspect of the present embodiment is a semiconductor device having a chip region, a seal ring region surrounding the chip region in plan view, and a dummy region surrounding the outer periphery of the seal ring region in plan view. The dummy region includes a semiconductor substrate, first and second stacked bodies, at least one first region, and at least one second region. The first stacked body is provided on the semiconductor substrate and includes a first interlayer insulating film having a first mechanical strength. The second stacked body is provided on the first stacked body, and includes a second interlayer insulating film having a mechanical strength larger than the first mechanical strength. The first region has a plurality of first metal layers provided in the first stacked body so as to overlap each other in plan view. The second region has a plurality of second metal layers provided in the second stacked body so as to overlap each other in plan view. The second region overlaps with a part of the first region in plan view and is provided at a position shifted from the position of the first region so as to be separated from the seal ring region.

  A method for manufacturing a semiconductor device according to one aspect of the present embodiment includes the following steps.

  A wafer including a chip region, a seal ring region surrounding the chip region in plan view, and a dummy region surrounding the outer periphery of the seal ring region in plan view is formed. The wafer is cut along the outer periphery of the dummy area. The dummy region includes a semiconductor substrate, first and second stacked bodies, and first and second regions. The first stacked body is provided on the semiconductor substrate and includes a first interlayer insulating film having a first mechanical strength. The second stacked body is provided on the first stacked body, and includes a second interlayer insulating film having a mechanical strength larger than the first mechanical strength. The first region has a plurality of first metal layers provided in the first stacked body so as to overlap each other in a plan view, and vias connecting the plurality of first metal layers to each other. The second region has a plurality of second metal layers provided in the second stacked body so as to overlap each other in a plan view, and vias connecting the plurality of second metal layers to each other. The second region overlaps at least a part of the first region in plan view, is not connected to the first region by a via, and has a second interlayer insulating film between the first region and the second region. It is sandwiched.

  A method for manufacturing a semiconductor device according to another aspect of the present embodiment includes the following steps.

  A wafer including a chip region, a seal ring region surrounding the chip region, and a dummy region surrounding the outer periphery of the seal ring region is formed. The wafer is cut along the outer periphery of the dummy area. The dummy region includes a semiconductor substrate, first and second stacked bodies, and first and second regions. The first stacked body is provided on the semiconductor substrate and includes a first interlayer insulating film having a first mechanical strength. The second stacked body is provided on the first stacked body, and includes a second interlayer insulating film having a mechanical strength larger than the first mechanical strength. The first region has a plurality of first metal layers provided in the first stacked body so as to overlap each other in plan view. The second region has a plurality of second metal layers provided in the second stacked body so as to overlap each other in plan view. The second region overlaps with a part of the first region in plan view and is provided at a position shifted from the position of the first region so as to be separated from the seal ring region.

  According to the semiconductor device according to one aspect of the present embodiment, an insulating film including the second interlayer insulating film is sandwiched between the first and second regions in a part of the second stacked body. A part is formed. Since this portion is sandwiched between the first and second regions, it has a small film thickness and is not reinforced by via connection. Therefore, this portion is a portion where cracks are likely to occur locally in the second laminate. Due to the presence of the crack-prone portion, the first laminated body having the first interlayer insulating film having low mechanical strength is changed to the second laminated body having the second interlayer insulating film having high mechanical strength. , Cracks are easier to extend. That is, since the cracks are easily extended upward, the cracks are easily removed upward from the semiconductor device before reaching the seal ring. Therefore, occurrence of seal ring breakage due to cracks is suppressed, so that a highly reliable semiconductor device can be obtained.

  According to the semiconductor device according to another aspect of the present embodiment, the second region that closes the upper side of the portion sandwiched between the first and second regions is separated from the seal ring in plan view. Are provided at positions shifted from the position of the first region. For this reason, the crack which extended this pinched | interposed part can go upwards in the position further distant from the seal ring area, without being interrupted by the second area. This makes it easier for cracks to escape above the semiconductor device before reaching the seal ring. Therefore, occurrence of seal ring breakage due to cracks is suppressed, so that a highly reliable semiconductor device can be obtained.

It is a figure which shows roughly the planar layout of the semiconductor device in Embodiment 1 of this invention. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view schematically showing a state when a crack occurs in FIG. 2. FIG. 4 is a schematic sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. 4. FIG. 5 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. FIG. 5 is a schematic cross-sectional view taken along line VII-VII in FIG. 4. It is the schematic which shows the planar layout of the metal layer provided in the interlayer insulation film of the semiconductor device in Embodiment 1 of this invention. It is the schematic which shows the planar layout of the 1st area | region provided in the 1st laminated body of the semiconductor device in Embodiment 1 of this invention. It is the schematic which shows the planar layout of the 2nd area | region provided in the 2nd laminated body of the semiconductor device in Embodiment 1 of this invention. It is the schematic which shows the planar layout of the 3rd area | region provided in the 3rd laminated body of the semiconductor device in Embodiment 1 of this invention. FIG. 6 is an enlarged view of the periphery of the second region in FIG. 5. It is the schematic which shows the planar layout of the wafer used for the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows roughly the mode of the dicing process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic fragmentary sectional view for demonstrating the extension path | route of the crack in a common semiconductor device. FIG. 3 is a partial cross sectional view schematically showing an example of a crack extension path in the semiconductor device in the first embodiment of the present invention. It is a fragmentary sectional view which shows roughly the structure of the semiconductor device in a comparative example. It is the figure on which the schematic sectional drawing in alignment with the XVIII-XVIII line | wire of FIG. 17 and the extension path | route of the crack in planar view were overlaid. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. FIG. 20 is a schematic cross-sectional view taken along line XX-XX in FIG. 19. FIG. 21 is a schematic cross-sectional view taken along line XXI-XXI in FIG. 20. FIG. 21 is a schematic cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 21 is a schematic cross-sectional view taken along line XXIII-XXIII in FIG. 20. It is a fragmentary sectional view which shows roughly an example of the extension path | route of the crack in the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows roughly an example of the extension path | route of the crack in the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 4 of this invention. FIG. 30 is a schematic cross-sectional view along the line XXX-XXX in FIG. 29. FIG. 30 is a schematic cross-sectional view along the line XXXI-XXXI in FIG. 29. FIG. 30 is a schematic cross-sectional view taken along line XXXII-XXXII in FIG. 29. It is a fragmentary sectional view which shows roughly an example of the extension path | route of the crack in the semiconductor device in Embodiment 4 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 5 of this invention. FIG. 35 is a schematic sectional view taken along line XXXV-XXXV in FIG. 34. FIG. 35 is a schematic sectional view taken along line XXXVI-XXXVI in FIG. 34. FIG. 35 is a schematic cross-sectional view along the line XXXVII-XXXVII in FIG. 34. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 6 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 6 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 6 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 7 of this invention. FIG. 42 is a schematic sectional view taken along line XLII-XLII in FIG. 41. FIG. 42 is a schematic sectional view taken along line XLIII-XLIII in FIG. 41. FIG. 42 is a schematic cross-sectional view taken along line XLIV-XLIV in FIG. 41. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 8 of this invention. FIG. 46 is a schematic sectional view taken along line XLVI-XLVI in FIG. 45. FIG. 46 is a schematic cross-sectional view taken along line XLVII-XLVII in FIG. 45. FIG. 46 is a schematic cross-sectional view taken along line XLVIII-XLVIII in FIG. 45. It is a fragmentary sectional view which shows roughly the structure of the semiconductor device in Embodiment 9 of this invention. FIG. 50 is a schematic cross-sectional view taken along line LL in FIG. 49. FIG. 50 is a schematic cross-sectional view taken along line LI-LI in FIG. 49. FIG. 50 is a schematic cross-sectional view taken along line LII-LII in FIG. 49.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, a schematic configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS.

  FIG. 1 schematically shows a planar layout of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device SD1 of the present embodiment has a chip region CR, a seal ring region SR, and a dummy region DR as a planar layout. The seal ring region SR surrounds the chip region CR in plan view. The dummy area DR surrounds the outer periphery of the seal ring area SR in plan view. The outer peripheral side surface of the dummy region DR is a dicing surface DS that is a cut surface in the dicing process.

  FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. Referring to FIG. 2, the semiconductor device SD1 includes a semiconductor substrate SB, a semiconductor element 71, an element isolation insulating film 72, insulating films 73, 75, and 76, contacts 74, wirings 77, and a protective film 78. And layers M1 to M9. In the chip region CR, a semiconductor element 71 having a source / drain region 70 is formed on the semiconductor substrate SB. The protective film 78 is made of silicon nitride. The contact 74 is formed so as to penetrate the insulating film 73. On the insulating film 73 and the contact 74, layers M1 to M9 are sequentially provided. Each of the layers M1 to M9 has a metal part and an insulator part. The layers M1 to M9 constitute an electric circuit including the semiconductor element 71 in the chip region CR, and a seal ring SL in the seal ring region SR. Further, an opening OP provided in the protective film 78 is provided so as to expose the insulating film 76 in a form extending in parallel with the seal ring SL and surrounding the seal ring SL. When the semiconductor device SD1 is sealed in the package, the opening OP is broken due to the stress of the sealing material such as resin being transmitted through the hard protective film 78 and reaching the seal ring SL and the wiring 77. It is to prevent. Further, the opening OP is prevented from being broken when the protective film 78 is cut in the dicing process at the time of manufacturing and the stress related to dicing is transmitted through the hard protective film 78 and reaches the seal ring SL and the wiring 77. It is also what you do.

  FIG. 3 is a cross-sectional view schematically showing a state where a crack occurs in FIG. Referring to FIG. 3, semiconductor device SD1 may have chipping TP and crack CK due to a dicing process during manufacturing. The chipping TP is a chip on the side surface of the semiconductor substrate SB. The crack CK is missing from the chipping TP to the upper side (the protective film 78 side) of the semiconductor device SD1 in the dummy region DR. That is, the crack CK occurs only in the dummy region DR and does not reach the seal ring SL provided in the seal ring region SR. For this reason, the seal ring SL is not damaged by the crack CK, and maintains the function of preventing water from entering the chip region CR. Thereby, the semiconductor device SD1 has high reliability.

Next, the configuration of the semiconductor device SD1 will be described in more detail.
Referring mainly to FIGS. 2 and 5, in the design of the wiring structure of semiconductor device SD1, layers M1 to M9 forming a multilayer wiring structure are composed of a layer M1, a layer M2 to M5, and a layer It is handled by being divided into a part composed of M6 and M7 and a part composed of layers M8 and M9. The material and dimension rule of the interlayer insulating film are selected for each part.

  The interlayer insulating film ID0 which is an insulator portion in the layer M1 is formed of a non-low material such as SiO or a low-k material such as SiOC. The layer M1 has a function as a local wiring for constituting a basic circuit including the semiconductor element 71 in the chip region CR. Further, the layer M1 has a metal portion forming a part of the seal ring SL in the seal ring region SR. The layer M1 has a metal layer L0 in the dummy region DR. The metal layer L0 is formed in the interlayer insulating film ID0 by a single damascene method. As shown in FIG. 8, the planar layout of the metal layer L0 has a square shape with one side having a length LW0. The length LW0 is, for example, 1.5 μm.

  The layers M2 to M5 have the first stacked body LB1 as an insulator part. The first stacked body LB1 includes an etching stopper film ES1a, a first interlayer insulating film ID1a, a cap film CP1a, an etching stopper film ES1b, a first interlayer insulating film ID1b, a cap film CP1b, and an etching stopper. This is a stacked body in which a film ES1c, a first interlayer insulating film ID1c, a cap film CP1c, an etching stopper film ES1d, a first interlayer insulating film ID1d, and a cap film CP1d are sequentially stacked. The material of the first interlayer insulating films ID1a to ID1d is a ULK material having a smaller relative dielectric constant and smaller mechanical strength than the material of the interlayer insulating film ID0. The etching stopper films ES1a to ES1d are made of a SiCO / SiCN laminated material. The material of the cap films CP1a to CP1d is SiOC.

  Further, the layers M2 to M5 have a metal portion formed by a dual damascene method. This metal part has a function as an intermediate wiring on the local wiring in the chip region CR. Further, this metal portion forms part of the seal ring SL in the seal ring region SR. In addition, this metal part forms a first region Ra1 provided in the first stacked body LB1 in the dummy region DR.

  The first region Ra1 includes a plurality of first metal layers L1 provided in the first stacked body LB1 so as to overlap each other in plan view, and a via V1 that connects the plurality of first metal layers L1 to each other. have. As shown in FIG. 9, the planar layout of the first region Ra1 includes a square shape having a side length LW1 corresponding to the first metal layer L1, and a square having a side length LV1 corresponding to the via V1. It consists of a shape. A plurality of square shapes corresponding to the vias V1 are arranged along a square outer peripheral portion corresponding to the first metal layer L1. The length LW1 is equal to the length LW0 (FIG. 8), for example, 1.5 μm. For example, in the figure, length SV1 = 0.12 μm and length SW1 = 0.05 μm. In plan view, the via V1 is arranged around the first metal layer L1 along the four sides of the first metal layer L1 (hereinafter, this arrangement is referred to as a via V1 peripheral arrangement).

  The layers M6 and M7 have the second stacked body LB2 as an insulator part. The second stacked body LB2 is a stacked body in which an etching stopper film ES2a, a second interlayer insulating film ID2a, an etching stopper film ES2b, and a second interlayer insulating film ID2b are sequentially stacked. The material of the second interlayer insulating films ID2a and ID2b is a low-k material having a higher relative dielectric constant and higher mechanical strength than the ULK material forming the first interlayer insulating films ID1a to ID1d. For example, SiOC. The etching stopper films ES2a and ES2b are made of a SiCO / SiCN laminated material.

  The layers M6 and M7 have metal parts formed by a dual damascene method. This metal part has a function as a first semi-global wiring on the intermediate wiring in the chip region CR. Further, this metal portion forms part of the seal ring SL in the seal ring region SR. In addition, the metal portion forms a second region Ra2 provided in the second stacked body LB2 in the dummy region DR.

  The second region Ra2 includes a plurality of second metal layers L2 provided in the second stacked body LB2 so as to overlap each other in plan view, and vias V2 that connect the plurality of second metal layers L2 to each other. have. As shown in FIG. 10, the planar layout of the second region Ra2 includes a square shape having a side length LW2 corresponding to the second metal layer L2, and a square having a side length LV2 corresponding to the via V2. It consists of a shape. A plurality of square shapes corresponding to the vias V2 are arranged along the outer periphery of the square shape corresponding to the second metal layer L2. Length LW2 is equal to each of lengths LW0 (FIG. 8) and LW1 (FIG. 9), and is, for example, 1.5 μm. For example, in the figure, length SV2 = 0.18 μm and length SW2 = 0.065 μm. In plan view, the via V2 is arranged around the second metal layer L2 along the four sides of the second metal layer L2 (hereinafter, this arrangement is referred to as a via V2 peripheral arrangement).

  The second region Ra2 overlaps the first region Ra1 in plan view. Further, the second region Ra2 is not connected to the first region Ra1 by a via, and the second interlayer insulating film ID2a is sandwiched between the first region Ra1.

  The layers M8 and M9 have the third stacked body LB3 as an insulator portion. The third stacked body LB3 includes an etching stopper film ES3a, a third interlayer insulating film ID3a, an etching stopper film ES3b, a third interlayer insulating film ID3b, an etching stopper film ES3c, and a third interlayer insulating film. This is a stacked body in which ID3c, etching stopper film ES3d, and third interlayer insulating film ID3d are stacked in this order. The material of the third interlayer insulating films ID3a to ID3d is a non-low material having a higher relative dielectric constant and higher mechanical strength than the low-k material forming the second interlayer insulating films ID2a and ID2b. -K material, for example SiO. The etching stopper films ES3a to ES3d are made of a SiCO / SiCN laminated material or a SiCN single layer material.

  The layers M8 and M9 have metal parts formed by a dual damascene method. This metal part has a function as a second semi-global wiring on the first semi-global wiring in the chip region CR. Further, this metal portion forms part of the seal ring SL in the seal ring region SR. In addition, this metal part forms a third region Ra3 provided in the third stacked body LB3 in the dummy region DR.

  The third region Ra3 includes a plurality of third metal layers L3 provided in the third stacked body LB3 so as to overlap each other in plan view, and a via V3 that connects the plurality of third metal layers L3 to each other. have. As shown in FIG. 11, the planar layout of the third region Ra3 includes a square shape having a side length LW3 corresponding to the third metal layer L3 and a square having a side length LV3 corresponding to the via V3. It consists of a shape. A plurality of square shapes corresponding to the vias V3 are arranged along a square outer peripheral portion corresponding to the third metal layer L3. The length LW3 is equal to each of the lengths LW0 to LW2 (FIGS. 8 to 10), for example, 1.5 μm. For example, in the figure, length SV3 = 0.68 μm and length SW3 = 0.5 μm. In plan view, the via V3 is arranged around the third metal layer L3 along the four sides of the third metal layer L3 (hereinafter, this arrangement is referred to as a via V3 peripheral arrangement).

  The third region Ra3 overlaps with the second region Ra2 in plan view. Further, the third region Ra3 is not connected to the second region Ra2 by a via, and the third interlayer insulating film ID3a is sandwiched between the second region Ra2.

  Referring mainly to FIG. 4, the third region Ra3 has an occupation area of 30% to 50% in the dummy region DR and a pattern having an area of 1 square μm to 4 square μm in plan view. Have. Each of the first region Ra1 and the second region Ra2 also has a similar occupied area and a pattern having the same area.

  The third regions Ra3 are regularly arranged in plan view. Regarding the direction along the extending direction of the seal ring SL, the third regions Ra3 are linearly arranged at the same interval. Further, with respect to the direction orthogonal to the extending direction of the seal ring SL (lateral direction in FIG. 4), the third regions Ra3 are arranged in a staggered manner at the same interval. In other words, the third regions Ra3 formed in adjacent rows are formed with a predetermined pitch shift from each other, and in other words, the third regions Ra3 are arranged along a plurality of rows in plan view. The third regions Ra3 arranged in adjacent rows are arranged in a staggered manner by being alternately arranged. Thus, it is avoided that the seal ring SL and the dicing surface DS are linearly connected by the interlayer insulating film along a direction orthogonal to the extending direction of the seal ring SL. Each of the first region Ra1 and the second region Ra2 is similarly arranged.

  Each of the layers M1 to M9 has a metal part including a barrier metal part located on the bottom part and the side part, and a Cu (copper) part covered with the barrier metal part. For example, as shown in FIG. 12, the second region Ra2 has barrier metal portions BMa and BMb and Cu portions CLa and CLb.

  Further, the first region Ra1, the second region Ra2, and the third region Ra3 directly under the opening OP may not be formed. Thereby, it becomes easy to observe the peeling state of the interlayer insulating film caused by the chipping TP described later with an automatic visual inspection apparatus. That is, there is an effect that the analysis of defects becomes easy.

Next, a method for manufacturing the semiconductor device SD1 will be described.
FIG. 13 schematically shows a planar layout of a wafer used in the method for manufacturing a semiconductor device in the first embodiment of the present invention. Referring to FIG. 13, first, a wafer WF is formed by a normal wafer process. Wafer WF has a plurality of semiconductor devices SD1 and a cutting region RR in a planar layout. Each semiconductor device SD1 has a chip region CR, a seal ring region SR surrounding the chip region CR, and a dummy region DR surrounding the outer periphery of the seal ring region SR in a planar layout.

  FIG. 14 is a partial cross sectional view schematically showing a dicing step in the method for manufacturing a semiconductor device in the first embodiment of the present invention. Referring to FIG. 14, the wafer WF is cut along the outer periphery of the dummy region DR by pressing the dicing blade DB against the cutting region RR. By this dicing process, the semiconductor device SD1 cut out from the wafer WF is obtained.

Next, a crack extension path that may occur in the dicing process will be described in detail.
First, the general theory of the crack extension path will be explained. FIG. 15 is a schematic partial cross-sectional view for explaining a crack extension path in a general semiconductor device.

  Referring to FIG. 15, a general semiconductor device SDO includes a semiconductor substrate SB, an insulating film FL formed on the semiconductor substrate SB, and a seal ring SL formed in the insulating film FL. . In the dicing process of the manufacturing method of the semiconductor device SDO, chipping TP may occur on the dicing surface DS side of the semiconductor substrate SB. Then, starting from this chipping TP, a stress that causes the crack to extend upward is applied to the insulating film FL. The cracks in the insulating film FL caused by this stress are classified into three types of cracks CK1, cracks CK2, and cracks CK3 in the initial stage of the cracks.

  The crack CK1 is a crack that tends to extend almost directly above the semiconductor substrate SB. Since the crack CK1 extends without approaching the seal ring region SR, it does not cause the seal ring SL to be broken. On the other hand, the crack CK3 is a crack that passes through the dummy region DR obliquely upward and heads toward the seal ring region SR. The crack CK3 may reach the seal ring SL and break it.

  The crack CK2 is a crack that passes through only the dummy region DR obliquely upward and tries to escape from the semiconductor device SDO. When the insulating film FL has a substantially uniform mechanical strength, such a crack maintains the initial course, passes only through the dummy region DR obliquely upward, and escapes from the semiconductor device SDO. However, in the case where the insulating film FL has a laminated structure in which the mechanical strength increases toward the upper side, the crack CK2V having a course toward the seal ring SL is prevented in the middle while the crack is prevented from going upward. May change to a dashed arrow). As such a laminated structure, for example, a structure in which a film made of a low-k material is laminated on a film made of a ULK material, or a film made of a non-low-k material is laminated on a film made of a low-k material. There is a structured etc. In the semiconductor device having such a laminated structure, the seal ring SL may be broken by the crack CK2V.

  Next, an example of an actual crack extension path when a stress for generating the crack CK2 (FIG. 15) is applied to the semiconductor device SD1 will be described. Assuming that the first region Ra1 to the third region Ra3 are not provided, it is between the first stacked body LB1 and the second stacked body LB2 or between the second stacked body LB2 and the third stacked body. There is a possibility that the crack CK changes like a crack CK2V (FIG. 15) between the body LB3 and the crack CK2V reaches the seal ring SL. However, in the present embodiment, the crack is induced to escape above the semiconductor device SD1 before reaching the seal ring SL. The crack extension path will be described in detail below.

  Referring to FIG. 16, at arrow a, as an initial stage, the crack passes through interlayer insulating film ID0, etching stopper film ES1a, and first interlayer insulating film ID1a, and reaches the bottom surface of first region Ra1.

  At the arrow b, the path of the crack changes in the horizontal direction along the bottom surface of the first region Ra1. This is because the crack cannot be extended into the first region Ra1 having a large mechanical strength because it is made of metal, and extends the interface between the first region Ra1 and the first interlayer insulating film ID1a. It is. Moreover, since this interface is an interface between a metal and an insulator, the adhesion strength is small. Because of this low adhesion strength, the cracks try to extend this interface even more.

  At the arrow c, the crack course that has passed through the bottom surface of the first region Ra1 returns to the diagonally upward direction (the direction of the crack CK2 in FIG. 15), which is the original course, in the stress state. The cap film CP1a, the etching stopper film ES1b, the first interlayer insulating film ID1b, the cap film CP1b, the etching stopper film ES1c, the first interlayer insulating film ID1c, the cap film CP1c, the etching stopper film ES1d, and the first interlayer insulating film It passes through ID1d and the cap film CP1d and reaches the bottom surface of the second stacked body LB2. Here, the possibility that cracks pass between the plurality of first metal layers L1 included in the first region Ra1 located immediately on the seal ring SL side (left side in the drawing) of the arrow c is reduced. This is because the region between the pair of first metal layers L1 facing each other is reinforced by the via V1, and thus cracks are unlikely to occur.

At the arrow d, the path of the crack changes in the horizontal direction along the interface between the first stacked body LB1 and the second stacked body LB2. That is, the crack is difficult to extend upward in the figure. This is because the region above the arrow d has a thick insulating film and a high mechanical strength in terms of material characteristics. Further, since the interface is a CMP (Chemical Mechanical Polishing) surface in the dual damascene method for forming the first region Ra1, the interface strength is relatively small. For this reason, cracks try to extend this interface even more.

  In the region sandwiched between the first region Ra1 and the second region Ra2 by the arrow e, the crack extends into the second stacked body LB2. This is because the thickness of the insulating film is small in the region sandwiched between the first region Ra1 and the second region Ra2, and cracks are likely to occur. The course of the crack that has entered the second laminate LB2 returns to the diagonally upward direction (the direction of the crack CK2 in FIG. 15), which is the original course, in a stress state. The crack passes through the etching stopper film ES2a and the second interlayer insulating film ID2a and reaches the bottom surface of the second region Ra2.

At the arrows f to i, cracks extend as with the arrows b to e.
At the arrows j and k, the crack extends like the arrows b and c described above. That is, the crack passes through the upper portion of the semiconductor device SD1 in the dummy region DR without reaching the seal ring region SR. As a result, a crack CK (FIG. 3) is formed in the semiconductor device SD1.

  As described above, when the stress for generating the crack CK2 (FIG. 15) is applied to the semiconductor device SD1 of the present embodiment, the generation of the crack CK2V (FIG. 15) reaching the seal ring SL is prevented. Instead, a crack CK (FIG. 3) is generated in the dummy region DR so as to escape above the semiconductor device SD1. Further, the peripheral arrangement of the via V1, the peripheral arrangement of the via V2, and the peripheral arrangement of the via V3 make it difficult for the cracks to extend inside the first to third regions Ra1 to Ra3. it can.

  The same applies to the case where a stress is applied to the semiconductor device SD1 so as to generate the crack CK3 (FIG. 15).

Next, a comparative example for the present embodiment will be described.
FIG. 17 is a partial cross-sectional view schematically showing a configuration of a semiconductor device in a comparative example. Referring to FIG. 17, the semiconductor device SDC of the comparative example has a region RaC that is a metal part. The region RaC includes a first metal layer L10, a first region Ra1, a second region Ra2, a third region Ra3, and vias V1C, V2C, and V3C. The metal layer L0, the first region Ra1, the second region Ra2, and the third region Ra3 are integrated by the vias V1C, V2C, and V3C. For this reason, the region RaC is a group of regions that are difficult to crack.

  FIG. 18 is a diagram in which a schematic cross-sectional view taken along line XVIII-XVIII in FIG. 17 and a crack extension path in plan view are superimposed. Referring mainly to FIG. 18, region RaC is a region in which cracks are difficult to occur as described above, and includes interlayer insulating film ID0 and first stacked body LB1 to third stacked body LB3 (FIG. 17). It is formed so as to penetrate the laminated body LB in the thickness direction. For this reason, the crack shown with the arrow in a figure cannot penetrate | invade area | region RaC. As a result, the crack may extend in the laminated body LB where the crack is more likely to enter than the region RaC, as the region RaC is sewn. Then, the crack reaches the seal ring SL and may break it.

  According to the semiconductor device SD1 of the present embodiment, as shown in FIG. 16, in a part of the second stacked body LB2, the second interlayer insulation is provided between the first region Ra1 and the second region Ra2. A portion where the insulating film including the film ID2a is sandwiched (for example, the peripheral portion of the arrow e) is formed. Since this portion is sandwiched between the first region Ra1 and the second region Ra2, it has a small film thickness. Further, this portion is not reinforced by via connection. Therefore, this portion is a portion where local cracks easily occur in the second stacked body LB2. Due to the presence of the crack-prone portion, as indicated by an arrow e, the second laminate layer LB1 having the high mechanical strength is provided from the first stacked body LB1 having the first interlayer insulating films ID1a to ID1d having the low mechanical strength. A crack becomes easy to extend to the 2nd layered product LB2 which has insulating films ID2a and ID2b. That is, since the cracks easily extend upward in the drawing, the cracks easily escape above the semiconductor device SD1 before reaching the seal ring SL. Therefore, destruction of the seal ring SL due to cracks is suppressed, and thus a highly reliable semiconductor device SD1 can be obtained.

  Similarly to the third region Ra3 shown in FIG. 4, each of the first region Ra1 and the second region Ra2 occupies an area of 30% to 50% in plan view. Thereby, since the region where the crack indicated by each of the arrow c and the arrow e (FIG. 16) is generated is ensured in a well-balanced manner, the crack can be guided above the semiconductor device SD1 as shown in FIG.

  Each of the metal layer L0, the first region Ra1, the second region Ra2, and the third region Ra3 (FIGS. 8 to 11) has a pattern with an area of 1 square μm or more and 4 square μm or less in plan view. have.

  When the metal layer L0, the first region Ra1, the second region Ra2, and the third region Ra3 are scattered at the time of cutting with the dicing blade DB (FIG. 14) in the dicing process, the area is 4 square. When the thickness is not more than μm, the area of the metal piece is almost the same as the cross-sectional area of the abrasive grains used in a large amount in the dicing process, so that a substantial adverse effect due to the metal piece hardly occurs. If the area is less than 1 square μm, the area of the region for generating the crack indicated by the arrow e (FIG. 16) is insufficient in plan view, and the effect of guiding the crack upward is reduced.

  On the other hand, if this area exceeds 4 square μm, when cutting with the dicing blade DB (FIG. 14) in the dicing process, it is larger than the cross-sectional area of the abrasive grains used in large quantities in the dicing process. As a result, the area that is actually processed becomes large, which causes a reduction in reliability of the semiconductor device due to the occurrence of a cutting burr and a defective cutting due to the adhering of cutting waste to the blade.

  Further, the semiconductor device SD1 has an interlayer insulating film ID0 (FIG. 5) having a mechanical strength larger than that of the first interlayer insulating films ID1a to ID1d (FIG. 5). Thereby, in the layer M1 (FIG. 2), an interlayer insulating film material having higher mechanical strength than the layers M2 to M5 (FIG. 2) is used. As a result, a combination of interlayer insulating film materials that are usually selected for the reason of design of the semiconductor device SD1 can be applied. For example, the interlayer insulating film ID0 can be formed of a low-k material, and the first interlayer insulating films ID1a to ID1d can be formed of a ULK material. Alternatively, for example, the interlayer insulating film ID0 can be formed of a non-low-k material, and the first interlayer insulating films ID1a to ID1d can be formed of a low-k material.

  Also, the semiconductor device SD1 (FIG. 5) of the present embodiment does not have vias V1C, V2C, and V3C, unlike the semiconductor device SDC (FIG. 17) of the comparative example. Therefore, the design work of the semiconductor device is simplified by an amount corresponding to the vias V1C, V2C, and V3C.

  Further, as shown in FIG. 4, the third regions Ra3 are arranged in a staggered manner with respect to the direction orthogonal to the extending direction of the seal ring SL (the horizontal direction in FIG. 4). Thereby, the seal ring SL and the dicing surface DS are linear along the direction orthogonal to the extending direction of the seal ring SL (lateral direction in the figure) and receive the action of the third region Ra3. The occurrence of such cracks is suppressed. The same applies to the first region Ra1 and the second region Ra2.

(Embodiment 2)
FIG. 19 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the second embodiment of the present invention. 20 is a schematic cross-sectional view taken along line XX-XX in FIG. 21 to 23 are schematic cross-sectional views taken along lines XXI-XXI, XXII-XXII, and XXIII-XXIII in FIG. Each of the cross-sectional positions in FIGS. 20 to 23 corresponds to FIGS. 4 to 7 in the first embodiment.

  Referring mainly to FIGS. 20 to 23, semiconductor device SD2 of the present embodiment includes each of first region Ra1, second region Ra2, and third region Ra3 of semiconductor device SD1 (FIG. 5). Instead, the first region Rb1, the second region Rb2, and the third region Rb3 are provided. Each of first region Rb1, second region Rb2, and third region Rb3 has no via.

  The second region Rb2 is provided at a position shifted from the position of the first region Rb1 so as to overlap a part of the first region Rb1 and to be separated from the seal ring region SR in plan view. The third region Rb3 overlaps with a part of the second region Rb2 in plan view and is provided at a position shifted from the position of the second region Rb2 so as to be separated from the seal ring region SR.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  FIG. 24 is a partial cross-sectional view schematically showing an example of a crack extension path in the semiconductor device according to the second embodiment of the present invention. FIG. 24 corresponds to FIG. 16 in the first embodiment.

  Referring to FIG. 24, in plan view, the first region Rb2 that closes the upper side of the portion sandwiched between the first region Rb1 and the second region Rb2 is separated from the seal ring SL. Is provided at a position shifted from the position of the region Rb1. For this reason, the crack indicated by the arrow f extending the sandwiched portion is directed upward without being blocked by the second region Rb2 at a position further away from the seal ring region SR (right side in the drawing). (See arrow g).

  Similarly, in plan view, the third region Rb3 that closes the upper side of the portion sandwiched between the second region Rb2 and the third region Rb3 is separated from the seal ring SL in the second region Rb2. It is provided at a position shifted from the position. For this reason, the crack of the arrow j extending this part can go upward without being blocked by the third region Rb3 at a position further away from the seal ring region SR (a position on the right side in the figure) ( (See arrow k).

  Therefore, as compared with the case where there is no shift in the position of each of the second region Rb2 and the third region Rb3 in plan view, the crack is likely to escape above the semiconductor device SD2 before reaching the seal ring SL. Therefore, since the occurrence of the seal ring SL breakage due to the crack is suppressed, a highly reliable semiconductor device SD2 can be obtained.

(Embodiment 3)
Each of FIGS. 25 to 27 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the third embodiment of the present invention. The cross-sectional positions in FIGS. 25 to 27 correspond to the cross-sectional positions in FIGS. 21 to 23 of the second embodiment.

  Referring mainly to FIGS. 25 to 27, semiconductor device SD3 of the present embodiment includes first region Rb1, second region Rb2, and third region of semiconductor device SD2 (FIG. 21) in the second embodiment. Instead of each region Rb3, a first region Ra1, a second region Ra2, and a third region Ra3 are provided.

  Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  FIG. 28 is a partial cross sectional view schematically showing an example of a crack extension path in the semiconductor device according to the third embodiment of the present invention. FIG. 28 is a diagram corresponding to FIG. 24 in the second embodiment.

  Referring to FIG. 28, the second region Ra2 that closes the upper side of the portion sandwiched between the first region Ra1 and the second region Ra2 is separated from the seal ring SL by the first region Ra1. It is provided at a position shifted from the position. For this reason, the crack of the arrow f extending this part can go upward without being blocked by the second region Ra2 at a position further away from the seal ring region SR (right position in the figure) ( (See arrow g).

  Similarly, the third region Ra3 that closes the upper side of the portion sandwiched between the second region Ra2 and the third region Ra3 is shifted from the position of the second region Ra2 so as to be separated from the seal ring SL. Is provided. For this reason, the crack of the arrow j extending this part can go upward without being blocked by the third region Ra3 at a position further away from the seal ring region SR (a position on the right side in the figure) ( (See arrow k).

  Therefore, as compared with the case where there is no displacement of the positions of the second region Ra2 and the third region Ra3, it becomes easier for the crack to escape above the semiconductor device SD3 before reaching the seal ring SL. Therefore, since the occurrence of the seal ring SL breakage due to the crack is suppressed, a highly reliable semiconductor device SD3 can be obtained.

  The plurality of first metal layers L1 included in each first region Ra1 are connected to each other by a via V1. As a result, the region between the pair of first metal layers L1 facing each other is less likely to crack due to reinforcement by the via V1. Therefore, the possibility that cracks pass between the plurality of first metal layers L1 included in the first region Ra1 located immediately on the seal ring SL side (left side in the drawing) of the arrow c is reduced. That is, as shown by the arrow c, the crack can be more reliably guided to the upper end of the first stacked body LB1. As a result, a crack extending in the second stacked body LB2 on the first stacked body LB1 is generated at a position further away from the seal ring region SR (a position on the right side in the figure) as indicated by an arrow e. Can be made.

  The plurality of second metal layers L2 included in each second region Ra2 are connected to each other by a via V2. As a result, the region between the pair of second metal layers L2 facing each other is less likely to crack due to reinforcement by the via V2. Therefore, the possibility that cracks pass between the plurality of second metal layers L2 included in the second region Ra2 located immediately on the seal ring SL side (left side in the drawing) of the arrow g is reduced. That is, as indicated by the arrow g, the crack can be more reliably guided to the upper end of the second stacked body LB2. As a result, a crack extending into the third laminated body LB3 on the second laminated body LB2 is generated at a position further away from the seal ring region SR (right position in the figure) as indicated by an arrow i. Can be made.

  The plurality of third metal layers L3 included in each third region Ra3 are connected to each other by a via V3. As a result, the region between the pair of third metal layers L3 facing each other is less likely to crack due to reinforcement by the via V3. Therefore, the possibility that a crack passes between the plurality of third metal layers L3 included in the third region Ra3 located immediately on the seal ring SL side (left side in the drawing) of the arrow k is reduced. That is, as indicated by the arrow k, the crack can be more reliably guided to the upper end of the third stacked body LB3. As a result, the crack can be removed above the semiconductor device SD3 at a position further away from the seal ring region SR (a position on the right side in the figure).

(Embodiment 4)
FIG. 29 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the fourth embodiment of the present invention. Each of FIG. 30 to FIG. 32 is a schematic cross-sectional view along the line XXX-XXX, XXXI-XXXI, and XXXII-XXXII in FIG. Each of the cross-sectional positions in FIGS. 29 to 32 corresponds to FIGS. 4 to 7 in the first embodiment.

  Referring mainly to FIG. 29, in the semiconductor device SD4 of the present embodiment, the planar layout of the third region Ra3 is related to the direction orthogonal to the extending direction of the seal ring SL (lateral direction of FIG. 29). In principle, it consists of individual patterns arranged in a staggered pattern at the same interval. However, in the region divided by the broken line DC, as shown by the two-dot chain line in the drawing, a part of the pattern is missing in the middle of the arrangement, and the third region Ra3 is not formed in this part.

  The planar layout of each of the first region Ra1 and the second region Ra2 is the same as the planar layout of the third region Ra3.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  FIG. 33 is a partial cross sectional view schematically showing an example of a crack extension path in the semiconductor device in the fourth embodiment of the present invention. FIG. 33 corresponds to FIG. 16 in the first embodiment.

  Referring mainly to FIG. 33, in the present embodiment, as compared with the first embodiment (FIG. 16), the first region Ra1 on the arrow b and the seal ring SL side immediately (with respect to this) The distance from the first region Ra1 on the left side in the drawing is greatly separated. That is, a sufficient distance is secured between the crack indicated by the arrow b and the lower surface of the first region Ra1, which is located away from the crack in the seal ring SL direction (left direction in the drawing), that is, the surface where the crack is likely to occur. Has been. As a result, the crack indicated by the arrow b immediately extends to the lower surface of the first region Ra1 on the seal ring SL side (left side in the drawing), that is, the crack extends laterally instead of the direction indicated by the arrow c. Is suppressed. That is, as shown by the arrow c, the crack can be more reliably guided to the upper end of the first stacked body LB1. Thereby, a crack can be more reliably pulled out above the semiconductor device SD4.

(Embodiment 5)
FIG. 34 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the fifth embodiment of the present invention. Each of FIGS. 35 to 37 is a schematic cross-sectional view taken along the line XXXV-XXXV, XXXVI-XXXVI, and XXXVII-XXXVII in FIG. 34. Each of the cross-sectional positions in FIGS. 34 to 37 corresponds to FIGS. 20 to 23 in the second embodiment.

  Referring mainly to FIG. 34, the planar layout of third region Rb3 is, in principle, arranged in a staggered manner at the same interval with respect to the direction orthogonal to the extending direction of seal ring SL (lateral direction in FIG. 34). Consists of individual patterns. However, as shown by the area partitioned by the broken line DC, a part of the pattern is missing in the middle of the arrangement, and the third area Rb3 is not formed in this part.

  In addition, as for the planar layout of each of the first region Rb1 and the second region Rb2, a part of the pattern is missing in the middle of the arrangement as in the planar layout of the third region Rb3.

  Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the present embodiment, as in the fourth embodiment, the crack can be more reliably guided upward in the region partitioned by the broken line DC (FIG. 34). Thereby, a crack can be more reliably pulled out above the semiconductor device SD5.

(Embodiment 6)
38 to 40 are partial cross sectional views schematically showing a configuration of the semiconductor device according to the sixth embodiment of the present invention. Each of the cross-sectional positions in FIGS. 38 to 40 corresponds to FIGS. 35 to 37 in the fifth embodiment.

  Referring mainly to FIGS. 38 to 40, semiconductor device SD6 of the present embodiment includes first region Rb1, second region Rb2, and semiconductor device SD5 (FIGS. 35 to 37) of the fifth embodiment. Instead of each of the third region Rb3, the first region Ra1, the second region Ra2, and the third region Ra3 are provided.

  Since the configuration other than the above is substantially the same as the configuration of the fifth embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

According to the present embodiment, the same effect as in the fifth embodiment can be obtained.
The plurality of first metal layers L1 included in each first region Ra1 are connected to each other by a via V1. As a result, the region between the pair of first metal layers L1 facing each other is less likely to crack due to reinforcement by the via V1. Therefore, the possibility that cracks pass between the plurality of first metal layers L1 included in the first region Ra1 is reduced. Therefore, a crack can be more reliably guided to the upper end of the first stacked body LB1.

  The plurality of second metal layers L2 included in each second region Ra2 are connected to each other by a via V2. As a result, the region between the pair of second metal layers L2 facing each other is less likely to crack due to reinforcement by the via V2. Therefore, the possibility that cracks pass between the plurality of second metal layers L2 included in the second region Ra2 is reduced. Therefore, a crack can be more reliably guided to the upper end of the second stacked body LB2.

  The plurality of third metal layers L3 included in each third region Ra3 are connected to each other by a via V3. As a result, the region between the pair of third metal layers L3 facing each other is less likely to crack due to reinforcement by the via V3. Therefore, the possibility that cracks pass between the plurality of third metal layers L3 included in the third region Ra3 is reduced. Therefore, a crack can be more reliably guided to the upper end of the third stacked body LB3. As a result, the crack can be removed above the semiconductor device SD6 at a position further away from the seal ring region SR (right position in the figure).

(Embodiment 7)
FIG. 41 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the seventh embodiment of the present invention. Each of FIG. 42 to FIG. 45 is a cross-sectional view along the XLII-XLII line, XLIII-XLIII line, and XLIV-XLIV line of FIG. Each cross-sectional position in FIGS. 41 to 45 corresponds to FIGS. 4 to 7 in the first embodiment.

  Referring mainly to FIG. 41, in the semiconductor device SD7 of the present embodiment, the third region Ra3 is provided for every second region in the direction orthogonal to the extending direction of the seal ring SL (lateral direction in FIG. 41). Arranged in a staggered pattern.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, as in the first embodiment, a straight line is formed between the seal ring SL and the dicing surface DS along a direction (lateral direction in the figure) perpendicular to the extending direction of the seal ring SL. And cracks that do not receive the action of the third region Ra3 are suppressed. The same applies to the first region Ra1 and the second region Ra2.

(Embodiment 8)
FIG. 45 is a partial cross sectional view schematically showing a configuration of the semiconductor device in the eighth embodiment of the present invention. Each of FIG. 46 to FIG. 48 is a schematic cross-sectional view along the XLVI-XLVI line, XLVII-XLVII line, and XLVIII-XLVIII line of FIG. The cross-sectional positions in FIGS. 45 to 48 correspond to FIGS. 41 to 44 in the seventh embodiment.

  Referring mainly to FIG. 45, in the semiconductor device SD8 of the present embodiment, the planar layout of the third region Ra3 is related to the direction orthogonal to the extending direction of the seal ring SL (lateral direction of FIG. 45). In principle, it consists of two individual patterns arranged in a staggered pattern. However, in the region partitioned by the broken line DC, as shown by the two-dot chain line in the drawing, a part of the pattern is missing in the middle of the arrangement, and the third region Ra3 is not formed in this part. In addition, in the planar layout of each of the first region Ra1 and the second region Ra2, a part of the pattern is missing in the middle of the arrangement, like the planar layout of the third region Ra3.

  Since the configuration other than the above is substantially the same as the configuration of the seventh embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the present embodiment, the same effect as in the seventh embodiment can be obtained. Similarly to the fourth embodiment, the crack can be more reliably guided upward in the region partitioned by the broken line DC (FIG. 45). Thereby, a crack can be more reliably pulled out above the semiconductor device SD8.

(Embodiment 9)
FIG. 49 is a partial cross sectional view schematically showing a configuration of a semiconductor device in the ninth embodiment of the present invention. Each of FIG. 50 to FIG. 52 is a schematic cross-sectional view along the line LL, LI-LI, and LII-LII in FIG. 49 to 52 correspond to those in FIGS. 4 to 7 in the first embodiment.

  Referring mainly to FIG. 49, in semiconductor device SD9 of the present embodiment, third region Ra3 has an arrangement along direction AL intersecting with the extending direction of seal ring SL and direction AL in plan view. And an arrangement along the direction forming the angle TH. Each of the first region Ra1 and the second region Ra2 has the same arrangement in plan view.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, each of the first region Ra1, the second region Ra2, and the third region Ra3 includes an array along a direction that forms an angle TH with respect to the direction AL. . This prevents cracks extending along the direction AL from reaching the seal ring SL linearly from the dicing surface DS via only the interlayer insulating film.

  In the semiconductor devices SD3 to 9 in the above third to ninth embodiments, the insulating films 75 and 76, the wiring 77, the protective film 78, the opening OP, and the layers are the same as the semiconductor devices SD1 and SD2 in the first and second embodiments. It has a structure below M1 and layer M1 (semiconductor substrate SB side) (not shown in the third to ninth embodiments).

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device having a seal ring surrounding a chip region and a manufacturing method thereof.

  BMa, BMb Barrier metal part, CK, CK1-CK3, CK2V crack, CLa, CLb Cu part, CP1a-CP1d cap film, CR chip region, DB dicing blade, DR dummy region, DS dicing surface, ES1a-ES1d, ES2a, ES2b, ES3a to ES3d Etching stopper film, ID0 interlayer insulating film, ID1a to ID1d First interlayer insulating film, ID2a, ID2b Second interlayer insulating film, ID3a to ID3d Third interlayer insulating film, L0 metal layer, L1 first 1 metal layer, L2 second metal layer, L3 third metal layer, LB1 first laminate, LB2 second laminate, LB3 third laminate, M1-M9 layers, Ra1, Rb1 first Region, Ra2, Rb2 second region, Ra3, Rb3 third region, RR cut region SB semiconductor substrate, SDC, SDO, SD1 to SD9 semiconductor device, SL seal ring, SR seal ring region, TP chipping, V1 to V3 via, WF wafer, 71 semiconductor element, 72 element isolation insulating film, 73, 75, 76, 78 insulating film, 74 contacts, 77 wiring, 78 protective film.

Claims (17)

Chip area,
A seal ring region surrounding the chip region in plan view;
A semiconductor device comprising an outer region surrounding the outer periphery of the seal ring region in plan view,
The outer region is
A semiconductor substrate;
A first stacked body including a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate;
A second laminate including a second interlayer insulating film provided on the first laminate and having a second dielectric constant greater than the first dielectric constant;
A plurality of first metal regions including a plurality of first metal layers provided in the first stacked body so as to overlap each other in plan view;
A plurality of second metal regions including a plurality of second metal layers provided in the second stacked body so as to overlap each other in plan view,
The plurality of second metal regions are arranged in an array of columns and rows in plan view,
The array of columns and rows includes at least four columns extending substantially parallel to adjacent portions of the seal ring region in plan view, and the first of the at least four columns in plan view. The row is closest to the seal ring region, the fourth row of the at least four rows is furthest from the seal ring region, and the second and third rows of the at least four rows are the first and fourth rows. The second column is closer to the first column, the third column is closer to the fourth column,
The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region. and,
In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and the seal ring region Away from
The semiconductor device, wherein the plurality of first metal regions and the plurality of second metal regions are not connected by vias .   The semiconductor device according to claim 1, wherein a part of the second interlayer insulating film is sandwiched between the second metal region and the first metal region.   The first metal layers are arranged so as to completely overlap with each other in the plan view, and the second metal layers are arranged so as to completely overlap with each other in the plan view. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein each of the first and second metal layers has four sides in a plan view.   2. The semiconductor device according to claim 1, wherein each of the first and second metal regions has a pattern having an area of 1 square μm or more and 4 square μm or less in plan view. A semiconductor substrate;
A chip region formed on the semiconductor substrate;
A seal ring region surrounding the chip region formed on the semiconductor substrate in plan view;
An outer region surrounding an outer periphery of the seal ring region formed on the semiconductor substrate in a plan view;
A first insulating layer including a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate in the outer region;
A second insulating layer including a second interlayer insulating film having a second dielectric constant greater than the first dielectric constant provided on the first insulating layer in the outer region;
A plurality of first metal regions including at least one first metal layer provided in the first insulating layer;
A plurality of second metal regions including at least one second metal layer provided in the second insulating layer ,
The plurality of second metal regions are arranged in a plurality of rows extending substantially parallel to adjacent portions of the seal ring region, and the second metal regions in the directly adjacent rows are planar. In a staggered manner with respect to each other ,
In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and the seal ring region Away from
The semiconductor device, wherein the plurality of first metal regions and the plurality of second metal regions are not connected by vias . The semiconductor device according to claim 6 , wherein a part of the second interlayer insulating film is sandwiched between the second metal region and the first metal region. The first insulating layer includes a plurality of first metal layers, and the plurality of first metal layers are arranged so as to completely overlap with each other in a plan view,
Wherein said second insulating layer is a plurality of second metal layers, said plurality of second metal layers are also arranged so as to completely overlap becoming the same shape as each other in a plan view, in claim 6 The semiconductor device described. The semiconductor device according to claim 6 , wherein each of the first and second metal layers has four sides in a plan view. Each of the said 1st and 2nd metal area | region is a semiconductor device of Claim 6 which has a pattern of the area of 1 square micrometer or more and 4 square micrometers or less in planar view. The semiconductor device according to claim 6 , wherein the columns are shifted from each other by the same pitch so as to be arranged in a staggered pattern in a plan view. A semiconductor substrate;
A chip region formed on the semiconductor substrate;
A seal ring region surrounding the chip region formed on the semiconductor substrate in plan view;
An outer region surrounding an outer periphery of the seal ring region formed on the semiconductor substrate in a plan view;
A first insulating layer including a first interlayer insulating film having a first dielectric constant provided on the semiconductor substrate in the outer region;
A second insulating layer including a second interlayer insulating film having a second dielectric constant greater than the first dielectric constant provided on the first insulating layer in the outer region;
A plurality of first metal regions including at least one first metal layer provided in the first insulating layer;
A plurality of second metal regions including at least one second metal layer provided in the second insulating layer ,
The plurality of second metal regions are arranged in an array of columns and rows in plan view,
The array of columns and rows includes at least four columns extending substantially parallel to adjacent portions of the seal ring region in plan view, and the first of the at least four columns in plan view. The row is closest to the seal ring region, the fourth row of the at least four rows is furthest from the seal ring region, and the second and third rows of the at least four rows are the first and fourth rows. The second column is closer to the first column, the third column is closer to the fourth column,
The column and row arrangement further includes a plurality of rows extending from the first to fourth columns, the rows being inclined with respect to a line perpendicular to the adjacent portion of the seal ring region. and,
In plan view, each of the second metal regions is provided at a position shifted from each of the first metal regions so as to overlap a part of each of the first metal regions, and the seal ring region Away from
The semiconductor device, wherein the plurality of first metal regions and the plurality of second metal regions are not connected by vias . The semiconductor device according to claim 12 , wherein a part of the second interlayer insulating film is sandwiched between the second metal region and the first metal region. The first insulating layer includes a plurality of first metal layers, and the plurality of first metal layers are arranged so as to completely overlap with each other in a plan view,
Wherein said second insulating layer is a plurality of second metal layers, said plurality of second metal layers are also arranged so as to completely overlap becoming the same shape as each other in a plan view, to claim 12 The semiconductor device described. The semiconductor device according to claim 12 , wherein each of the first and second metal layers has four sides in a plan view. 13. The semiconductor device according to claim 12 , wherein each of the first and second metal regions has a pattern having an area of 1 square μm or more and 4 square μm or less in plan view. The semiconductor device according to claim 12 , wherein the rows are shifted from each other by the same pitch so as to be arranged in a staggered manner in a plan view.

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