JP5549011B2 - Semiconductor surface light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor surface light emitting device and a method for manufacturing the same.

  A photonic crystal is a nanostructure whose refractive index changes periodically, and the wavelength of light passing through the nanostructure can be controlled. As a next generation semiconductor surface light emitting device, a photonic crystal surface emitting laser (hereinafter referred to as PCSEL) using a two-dimensional photonic crystal (hereinafter referred to as 2DPC) has been proposed. PCSEL has the characteristics that its optical characteristics are determined by the size and shape of the microstructure and does not depend on the material. Conventional semiconductor light emitting devices such as large area, single mode, two-dimensional polarization control, and emission angle control It has new characteristics that are difficult to realize by itself, and has the potential to open up the possibilities of high-power semiconductor lasers.

In actual production of 2DPC, a wafer bonding technique is used, and the following problems (1) to (3) are present.
(1) It is difficult to produce a large area 2DPC. That is, when the wafer to be bonded has a warp, when there is dust between the wafers, or when there are large irregularities on the wafer surface, these wafers cannot be bonded well.
(2) The 2DPC layer includes a cavity, has a large coupling coefficient κ, and is not suitable for increasing the area. The reason is that in order to distribute light uniformly in the 2DPC layer, the normalized coupling coefficient κL in the in-plane direction with respect to the electrode length L is preferably about 1 to 2, but the 2DPC layer includes a cavity. This is because the value of κ is a value of 1000 cm ⁻¹ or more, and the value of L is limited to several tens of μm.
(3) Since defects are formed at the interface between the bonded wafers, there are difficulties in life and reliability.

As a 2DPC manufacturing means for solving the above problems, there is a regrowth type PCSEL utilizing crystal regrowth, and this has the following advantages.
(1) It is easy to produce a large area 2DPC. That is, when regrowth is used, there is no need to bond crystals.
(2) When the 2DPC layer is completely embedded, the coupling coefficient κ is reduced to about 1/10 of the coupling coefficient when the wafers are bonded, so that the area can be easily increased.
(3) Since the interface of the 2DPC layer is embedded with an epi layer, there are few defects and the reliability is improved.
(4) Since the 2DPC layer does not include cavities, it has excellent heat dissipation and is suitable for high output.

  From the above viewpoint, the regrowth type PCSEL is superior to the bonded type PCSEL in aiming at the practical use of the high output PCSEL.

  Patent Document 1 proposes that a hexagonal convex portion is embedded in a semiconductor layer as a photonic crystal that does not generate a cavity in crystal regrowth. In this case, the side surface is the (1-100) plane with respect to the main surface (0001) plane of the convex portion.

  In Patent Document 2, the crystal growth of a zinc blende structure using a (111) substrate having a polar surface or an (n11) substrate having 2 semipolar surfaces (2 ≦ n ≦ 6 is desirable) is repeated. Growth embedding is performed, and lateral growth is used as the means.

JP 2009-206157 A JP 2010-114384 A

  However, when the inventors of the present invention have made a hole in the zinc flash structure semiconductor layer and regrown the crystal in the hole, the surface morphology of the compound semiconductor layer formed thereon is not sufficient, and the crystal inside It was discovered that a large dislocation occurred. That is, since the crystallinity of the formed semiconductor layer is not sufficient, the characteristics of the semiconductor surface light emitting element are not sufficient.

  This invention is made | formed in view of such a subject, and it aims at providing the semiconductor surface light emitting element which can improve a characteristic, and its manufacturing method.

  In order to solve the above-described problem, a semiconductor surface light emitting device according to the present invention is formed by periodically forming a plurality of holes in a basic layer made of a first compound semiconductor having a zinc flash structure, and having a zinc flash structure in the hole. A photonic crystal layer obtained by growing a buried layer made of a second compound semiconductor, and an active layer that supplies light to the photonic crystal layer, and the main surface of the basic layer is (001) And the side surface of the hole includes at least three different {100} planes, or planes obtained by rotating these planes around the normal of the main surface with a rotation angle of less than ± 35 degrees. It is characterized by that.

  If the side surface of the hole is formed by four different {110} planes, the buried layer grown perpendicular to the (110) and (-1-10) side surfaces has (110) and (-1-10) Facet When these facets come into contact with each other at the center, it was found that the crystals were disturbed and the final crystallinity was deteriorated. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside. Further, when (110) and (−1-10) are included in the side surface of the hole, Facet that appears in the early stage of the regrowth embedding process (for example, (113), (−1-13), that is, (113) A surface) Multiple Facet competition occurs above and partially regrowth. There is also a mechanism that this region becomes the nucleus of dislocation formation.

  On the other hand, when the side surface shape of the hole is that of the present invention, the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good, the flatness is high, and it is relatively generated inside. It can be seen that the amount of dislocations decreased. When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by setting the shape of the hole to that of the present invention.

  Further, the side surface of the hole includes four different {100} planes, or planes obtained by rotating these planes around a normal line of the main surface with a rotation angle of less than ± 35 degrees. And

  In the case of the present invention, the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good and the flatness is high, and the characteristics of the semiconductor surface light emitting device can be improved as described above. .

  The rotation angle is set to be ± 25 degrees or less. When the rotation angle is ± 25 degrees or less, the surface morphology is remarkably improved and the crystallinity of the semiconductor layer is improved as compared with the case of 35 degrees.

  The rotation angle is set to be ± 20 degrees or less. When the rotation angle is ± 20 degrees or less, the surface morphology is further improved as compared with the case of 25 degrees, and the crystallinity of the semiconductor layer is improved.

  The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.

  In addition, the manufacturing method of the semiconductor surface light emitting element for manufacturing the above-described semiconductor surface light emitting element includes a step of forming the hole and a step of growing the buried layer. In addition, before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} by a rotation angle within ± 10 degrees around the normal of the main surface by etching, You may include the process of forming in the semiconductor substrate in which a base layer is formed. According to this method, when the above-described element is formed, the regrowth surface is roughened by forming dislocations in the regrowth layer of the alignment mark, and can be used as a reference position for optical exposure.

  According to the semiconductor surface light emitting device and the manufacturing method thereof of the present invention, since the crystallinity of the semiconductor layer constituting the semiconductor surface light emitting device is improved, it is possible to improve characteristics such as light emission output and life.

It is a perspective view of the semiconductor surface light emitting element which shows a semiconductor surface light emitting element partially broken. It is a top view of basic layer 6A formed on the wafer. It is a front view of a wafer. It is a figure which shows the electron micrograph of 6 A of basic layers in which the hole was formed. It is a figure which shows the optical microscope photograph of the surface of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the detailed structure of the shape of a hole. It is sectional drawing of a semiconductor surface light emitting element. It is sectional drawing of the direction parallel to the orientation flat of 6 A of basic layers. It is sectional drawing of the direction perpendicular | vertical to the orientation flat of 6 A of basic layers. It is a top view of basic layer 6A formed on the wafer concerning the 1st comparative example. It is a figure which shows the electron micrograph of 6 A of basic layers in which the hole concerning the 1st comparative example was formed. FIG. 4 is a view showing an optical micrograph of the surface of a semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device according to the first comparative example. It is a figure which shows the concept of crystallinity deterioration. It is a figure which shows the electron micrograph of 6 A of basic layers in which the hole concerning the 2nd comparative example was formed. It is a figure which shows the optical microscope photograph of the surface of the semiconductor layer located in the outermost surface side of the semiconductor surface light emitting element which concerns on a 2nd comparative example. It is a figure explaining rotation of the direction of a hole. It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which rotated the (100) side surface of the hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. . It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which rotated the (110) side surface of the hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. . It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which rotated the (110) side surface of the hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. . It is a figure which shows the shape of the hole by which a part of corner was notched. It is a top view of basic layer 6A formed on the wafer. It is a figure which shows the shape of a hole. It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which has a right-angle trapezoidal hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which has a right-angle trapezoidal hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the electron micrograph of the surface (left side) of the basic layer which has a right-angle trapezoidal hole, and the optical micrograph of the surface (right side) of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the detailed structure of the shape of a hole. It is a figure explaining rotation of the direction of a hole. It is a figure shown about the shape of various holes. FIG. 5 is a diagram for explaining a first manufacturing method of a photonic crystal layer. FIG. 6 is a diagram for explaining a second manufacturing method of the photonic crystal layer.

  Hereinafter, the semiconductor surface light emitting device and the manufacturing method thereof according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a perspective view of a semiconductor surface light emitting device, with the semiconductor surface light emitting device partially cut away.

  The semiconductor surface light emitting device includes a lower clad layer 2, a lower light guide layer 3, an active layer 4, an upper light guide layer 5, a photonic crystal layer 6, an upper clad layer 7, and a contact layer 8 that are sequentially formed on a semiconductor substrate 1. It has. On the back side of the semiconductor substrate 1, an electrode E <b> 1 is provided on the entire surface, and an electrode E <b> 2 is provided in the center portion of the contact layer 8.

The materials / thicknesses of these compound semiconductor layers are as follows. Note that an intrinsic semiconductor having an impurity concentration of 10 ¹⁵ / cm ³ or less has no conductivity type. In addition, the density | concentration when an impurity is added is 10 < ¹⁷ > -10 < ²⁰ > / cm < ³ >. Further, the following is an example of the present embodiment, and any structure including the active layer 4 and the photonic crystal layer 6 has a degree of freedom in the material system, film thickness, and layer configuration. The numerical values in parentheses are those used in the experiments described later, the growth temperature of AlGaAs by MOCVD is 500 ° C. to 850 ° C., 550 to 700 ° C. is adopted in the experiments, and the Al raw material during growth TMA (trimethylaluminum) as the gallium source, TMG (triethylgallium) as the gallium source, AsH _{3 (} arsine) as the As source, Si ₂ H ₆ (disilane) as the source for the N-type impurity, P type DEZn (diethyl zinc) was used as a raw material for impurities.
Contact layer 8: P-type GaAs / 50 to 500 nm (200 nm)
Upper clad layer 7: P-type AlGaAs (Al _0.4 Ga _0.6 As) /1.0 to 3.0 μm (2.0 μm)
Photonic crystal layer 6:
Basic layer 6A: GaAs / 50 to 200 nm (100 nm)
Buried layer 6B: AlGaAs (Al _0.4 Ga _0.6 As) / 50 to 200 nm (100 nm)
Upper light guide layer 5:
Upper layer: GaAs / 10-200 nm (50 nm)
Lower layer: p-type or intrinsic AlGaAs / 10 to 100 nm (50 nm)
Active layer 4 (multiple quantum well structure):
AlGaAs / InGaAs MQW / 10 to 100 nm (30 nm)
Lower light guide layer 3: AlGaAs / 0 to 300 nm (150 nm)
Lower clad layer 2: N-type AlGaAs / 1.0 to 3.0 μm (2.0 μm)
Semiconductor substrate 1: N-type GaAs / 80 to 350 μm (200 μm)

  When a current is passed between the upper and lower electrodes E1, E2, a current flows in a region R immediately below the electrode E2, this region emits light, and the laser beam LB is output in a direction perpendicular to the substrate.

  FIG. 2 is a plan view of the basic layer 6A formed on the wafer. In the plan view, for the purpose of clarifying the understanding, a plurality of holes H are described which are much larger than the actual scale, and the number thereof is smaller than the actual scale. FIG. 3 is a front view of the wafer.

  The main surface of the wafer (substrate) is the (001) plane, and in the drawing, the main surface (001) of the basic layer 6A is exposed on the surface. The a-axis, b-axis, and c-axis of the zinc-blende structure crystal are shown in the drawing as the X-axis, Y-axis, and Z-axis, respectively. The directions of the X axis, the Y axis, and the Z axis are [100], [010], and [001], respectively.

  An orientation flat (hereinafter referred to as orientation flat) OF is formed at one end of the wafer, and the orientation flat OF is perpendicular to the [110] direction. The orientation flat OF has a (−1-10) plane. A plurality of holes H (H1 to H10) are formed in the basic layer 6A, and each hole H has a depth in the thickness direction of the semiconductor substrate.

  The outline of the hole H in the planar shape is a rectangle, and each side of the rectangle is inclined 45 degrees with respect to the direction [1-10] in which the orientation flat OF extends. That is, the four side surfaces of the hole H have a (100) plane, a (0-10) plane, a (-100) plane, and a (010) plane, respectively. As crystallographically equivalent planes, these planes can be represented as {100} planes.

  The gravity center positions of the holes H in the plane are arranged at equal intervals along the [1-10] direction, and are also arranged at equal intervals along the [110] direction. In the drawing, the case where the former interval (for example, between H1 and H2) is shorter than the latter interval (for example, between H1 and H6) is shown, but the present invention is not limited to this. Further, another hole H4 is arranged on an extension line along the [110] direction of the midpoint position of the former interval (for example, between H1 and H2).

In the embodiment, the interval in the [1-10] direction of the center of gravity of the hole H is 330 nm, and the interval in the [110] direction is 570 nm. The shape of the hole is a rectangle, the length of each side is 165 nm, and the area is 2.7 × 10 ⁴ nm ² . In addition, the line group which connects the gravity center position of the hole H can comprise a square lattice, a rectangular lattice, and a triangular lattice, and may be a random arrangement | positioning.

  Since the buried layer 6B shown in FIG. 1 is buried in the hole H of the basic layer 6A, its side surface is in contact with the side surface of the hole H, and its plane orientation matches the plane orientation of the side surface of the hole H. Yes.

  As described above, the above-described semiconductor surface light-emitting device has a plurality of holes H periodically formed in the basic layer 6A made of the first compound semiconductor (GaAs) having the zinc flash structure, and the zinc H structure having the zinc flash structure. A photonic crystal layer 6 formed by growing a buried layer 6B made of a second compound semiconductor (AlGaAs) is provided. Of course, since the photonic crystal is formed, the refractive index of the first compound semiconductor is different from that of the second compound semiconductor. In the description, a scanning electron microscope (SEM) was used as the electron microscope. The cross-sectional SEM image was taken after the cross-section was stain-etched with ammonia perwater.

  FIG. 4 is a view showing an electron micrograph of the basic layer 6A in which holes are formed.

  FIG. 4A shows a plan photograph of the hole H, and the square hole H is shown. FIG. 4B shows a cross-sectional image of the basic layer cut before the orientation flat parallel direction (before formation of the buried layer), and FIG. 4C shows the basic layer cut along the orientation flat parallel direction (the buried layer). A cross-sectional image before layer formation) is shown. 4D shows a cross-sectional image of the basic layer cut after the orientation flat parallel direction (after formation of the buried layer), and FIG. 4E shows the basic layer cut along the parallel orientation direction of the orientation flat (embedded layer). The cross-sectional image after layer formation is shown.

  The filling process is continued until the upper cladding layer is formed, and then the contact layer is formed. In these buried layers and the upper cladding layer, no large dislocations are observed, and it can be seen that they have good crystallinity.

  FIG. 5 is a view showing an optical micrograph of the surface of the semiconductor layer (contact layer) located on the outermost surface side of the semiconductor surface light emitting device in the case of FIG. 4. The surface of the contact layer is flat, has excellent morphology, and almost no irregularities are observed. This indirectly indicates that the crystallinity is excellent inside.

  FIG. 6 is a diagram showing a detailed configuration of the hole shape.

  The dimensions of each side of the rectangle circumscribing the outline of the hole H in the XY plane are L1 and L2. A rectangle similar to this rectangle is assumed, and one corner is inscribed. The inscribed rectangle has the same center of gravity G as the circumscribed rectangle, and the rotation position in the XY plane is also the same. In this case, the distances between the corresponding sides are ΔL11, ΔL12, ΔL21, and ΔL22, respectively.

  This is a case where (ΔL11 + ΔL12) / L1 is less than 29% and (ΔL21 + ΔL22) / L2 is less than 29%, and the maximum value of the area of the hole in the XY plane (area of the outermost surface) is When the area of the circumscribed rectangle is 50% or more, the shape of the hole is recognized as a rectangle, and the side surface of the hole H is recognized as including four {100} planes.

  FIG. 7 is a cross-sectional view of a semiconductor surface light emitting device. This example shows a cross section parallel to the orientation flat.

  As described above, the semiconductor surface light emitting device includes the lower cladding layer 2, the lower light guide layer 3, the active layer 4, the upper light guide layer 5, the photonic crystal layer 6, and the upper cladding layer that are sequentially formed on the semiconductor substrate 1. 7 and a contact layer 8 are provided. Here, the active layer 4 supplies light to the photonic crystal layer 6, and includes upper and lower semiconductor layers 4A and 4C and a central semiconductor layer 4B sandwiched between them. The relationship of these energy band gaps is the same as that of a normal laser, and is set so as to have a multiple quantum well structure in which a 4B QW (quantum well) layer is sandwiched between 4A and 4C guide layers. The photonic crystal layer 6 is used to generate laser light by light resonance. That is, this semiconductor surface light emitting device is a photonic crystal surface emitting laser, but if the laser oscillation does not occur, the structure can be used as a light emitting diode.

  FIG. 8 is an example of a cross-sectional shape in the initial stage of regrowth embedding in a direction parallel to the orientation flat of the basic layer 6A. FIG. 9 is an example of a cross-sectional shape in the initial stage of regrowth embedding in a direction perpendicular to the orientation flat of the basic layer 6A. is there. As shown in these drawings, each hole H has inclined surfaces (F1 to F8) inclined with respect to the {100} side surfaces. The plane orientations of the inclined surfaces F1 to F8 are (1-11), (-111), (1-13), (-113), (-1-13), (113), (-1), respectively. 10) and (110).

  FIG. 10 is a plan view of the basic layer 6A formed on the wafer according to the first comparative example. Assuming that the semiconductor surface light emitting device shown in FIGS. 1 to 9 is an example, the element of the first comparative example is different from the example only in the shape of the hole H. That is, each side surface of the hole H is constituted by a {110} plane. More specifically, the respective sides are (110), (1-10), (-1-10), and (-110).

  FIG. 11 is a view showing an electron micrograph of the basic layer 6A in which holes are formed according to the first comparative example.

  FIG. 11A shows a plan photograph of the hole H, and the square hole H is shown. FIG. 11B shows a cross-sectional image of the basic layer cut before the orientation flat parallel direction (before formation of the buried layer), and FIG. 11C shows the basic layer cut along the orientation flat parallel direction (embedded layer). A cross-sectional image before layer formation) is shown. FIG. 11D shows a cross-sectional image of the basic layer cut after the orientation flat parallel direction (after formation of the buried layer), and FIG. 11E shows the basic layer cut along the parallel orientation direction of the orientation flat (embedded layer). The cross-sectional image after layer formation is shown.

  The filling process is continued until the upper cladding layer is formed, and then the contact layer is formed. Large dislocations are observed in these buried layers and the upper cladding layer (see FIGS. 11D and 11E), indicating that the crystallinity is not good.

  FIG. 12 is a view showing an optical micrograph of the surface of the semiconductor layer (contact layer) located on the outermost surface side of the semiconductor surface light emitting device according to the first comparative example.

  The surface of the contact layer is rough, the morphology is low, and many irregularities are observed. This indirectly indicates that the crystallinity is poor inside.

  Thus, it was found that the crystallinity is low when the side surface of the hole is formed by four different {110} planes. Consider this principle.

  FIG. 13 is a diagram showing the concept of crystallinity degradation.

  In the first comparative example, (110) and (-1-10) Facets appear in the buried layer grown perpendicularly to the side surfaces of (110) and (-1-10) (A), and the crystal growth proceeds. Accordingly, it was found that when these facets come into contact with each other at the center, the crystals are disturbed (B) and the final crystallinity is deteriorated. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside. Further, when (110) and (−1-10) are included in the side surface of the hole, Facet that appears in the early stage of the regrowth embedding process (for example, (113), (−1-13), that is, (113) A surface) Multiple Facet competition occurs above and partially regrowth. There is also a mechanism that this region becomes the nucleus of dislocation formation.

  On the other hand, in the present invention, the main surface of the basic layer 6A is the (001) plane, and the side surface of the hole H is surrounded by the {100} plane. Therefore, the dislocation formation mechanism due to the above (110) and (-1-10) is suppressed, and it is considered that the crystallinity is improved.

  An experiment was also performed when the shape of the hole H was circular.

  FIG. 14 is a view showing an electron micrograph of the basic layer 6A in which holes are formed according to the second comparative example. Only the shape of the hole H is different from the first comparative example, and the others are the same. The opening diameter of the hole H is 120 nm.

  FIG. 14A shows a plane photograph of the hole H, and the circular hole H is shown. FIG. 14B shows a cross-sectional image of a basic layer cut before the orientation flat parallel direction (before formation of the buried layer), and FIG. 14C shows a basic layer cut along the orientation flat parallel direction (the buried layer). A cross-sectional image before layer formation) is shown. FIG. 14D shows a cross-sectional image of the basic layer cut after the orientation flat parallel direction (after formation of the buried layer), and FIG. 14E shows the basic layer cut along the parallel orientation direction of the orientation flat (embedded layer). The cross-sectional image after layer formation is shown.

  The filling process is continued until the upper cladding layer is formed, and then the contact layer is formed. Large dislocations are not observed in these buried layers and upper cladding layers (see FIGS. 14D and 14E).

  However, the surface morphology is getting worse.

  FIG. 15 is an optical micrograph of the surface of the semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device according to the second comparative example. The surface of the contact layer is rough, the morphology deteriorates, and many irregularities are observed. This is because dislocations are not observed in the observation range of FIG. 14, but dislocations are formed when examined in a wider area, leading to deterioration of the surface morphology.

  Next, the hole H according to the embodiment was rotated around the Z axis passing through the center of gravity G, and the tolerance of the rotation angle was investigated.

  FIG. 16 is a diagram for explaining the rotation of the hole direction.

  A perpendicular line is drawn from the center of gravity G in the plane of the hole H toward the one side (010) plane, and an angle formed by the perpendicular line VR and [0-10] is defined as a rotation angle φ. That is, assuming that the hole H has a rectangular shape, a vertical line VR is drawn on one side thereof. When there is a slight fluctuation in the shape of the hole H, a rectangle circumscribing the hole is defined as the shape of the hole H.

  FIG. 17 is an electron micrograph (left side) of the surface of the basic layer obtained by rotating the (100) side face (facet) of the hole according to the example, and the surface of the semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device. It is a figure which shows an optical microscope photograph (right side). The length of each side of the square hole is 140 nm, the interval between the centers of the holes H in the [1-10] direction is 335 nm, and the interval in the [110] direction is 580 nm. When the rotation angle φ is 35 degrees, the surface morphology is deteriorated, and when φ is smaller than that, the surface morphology is good.

FIG. 18 is an electron micrograph (left side) of the surface of the basic layer obtained by rotating the (110) side face (face) of the hole according to the first comparative example, and the semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device. It is a figure which shows the optical microscope photograph (right side) of the surface.
The length of each side of the rectangular hole is 100 nm and 200 nm, the interval between the centers of gravity of the hole H in the [1-10] direction is 335 nm, and the short side is parallel to the [1-10] direction. The spacing in the [110] direction is 580 nm. Since the rotation angle φ is 20 degrees (the rotation angle in the embodiment is 25 degrees), the surface morphology is improved, and when φ is smaller than that, the surface morphology is deteriorated.

  FIG. 19 is an electron micrograph (left side) of the surface of the basic layer in which the (110) side face (face) of the hole of the first comparative example is rotated, and the surface of the semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device It is a figure which shows the optical microscope photograph (right side). Compared with the case of FIG. 18, the long side is parallel to the [1-10] direction. Since the rotation angle φ is 20 degrees or more (the rotation angle φ in the embodiment is 25 degrees or less), the surface morphology is improved, and when φ is smaller than that, the surface morphology is deteriorated.

  FIG. 20 is a diagram illustrating the shape of the hole H in which some of the corners C2 and C2 are cut out of the four corners C1 to C4. Since the mechanism of dislocation formation due to (110) and (-1-10) is suppressed, it is considered that the same crystallinity and surface morphology improvement effect as described above can be obtained.

  In the above embodiment, the shape of the hole H is rectangular, but it may be a right trapezoid.

  FIG. 21 is a plan view of the basic layer 6A formed on the wafer.

  In the semiconductor surface light emitting device of this embodiment, only the shape of the hole H is changed to a right trapezoid. Other structures are the same as those described above. The plane including each side of the right trapezoid is (010), (0-10), (100), (hk0). That is, three side surfaces belong to the {100} plane.

  FIG. 22 is a diagram showing the shape of the hole H. FIG.

  Here, an angle (acute angle) formed by the (010) plane and the (hk0) plane is θ. In FIG. 22, the plane orientation of the (hk0) plane is a plane orientation parallel to the vector V [h1, k1, 0] where h1 = −sin θ and k1 = cos θ. In the following description, FF represents Filling Factor. Filling factor is an index for measuring the size of the photonic crystal, and is the ratio of the area occupied by the photonic crystal shape (area of the hole H) to the area of the unit period of the two-dimensional structure. In the following example, the length a (lattice constant) per unit period of the two-dimensional structure is 335 nm.

  FIG. 23 shows an electron micrograph of the surface (left side) of the basic layer 6A having a right trapezoidal hole, and an optical micrograph of the surface (right side) of the semiconductor layer (contact layer) located on the outermost surface side of the semiconductor surface light emitting element. FIG.

  Although θ was set to 60 degrees and FF was changed from 11% to 33%, no significant change was observed in the surface morphology, and all were good.

  24 and 25 show an electron micrograph of the surface (left side) of the basic layer having a right trapezoidal hole and an optical micrograph of the surface of the semiconductor layer (right side) located on the outermost surface side of the semiconductor surface light emitting device. FIG.

  FF was set to 15% (design value) and θ was changed from 30 to 80 degrees, but no significant change was observed in the surface morphology, and all were good.

  FIG. 26 is a diagram showing a detailed configuration of the hole shape.

  In the right trapezoid circumscribing the outline of the hole H in the XY plane, the larger dimension of the upper base or the lower base is L1, and the distance between opposing parallel sides is L2. A right trapezoid similar to this right trapezoid is assumed, and one corner is inscribed. The inscribed right trapezoid has the same center of gravity G as the circumscribed right trapezoid, and the rotation position in the XY plane is also the same. In this case, the separation distances in the direction parallel to the upper base of the trapezoid of the corresponding side are ΔL11 and ΔL12, and the separation distances in the trapezoid height direction are ΔL21 and ΔL22.

  This is a case where (ΔL11 + ΔL12) / L1 is less than 29% and (ΔL21 + ΔL22) / L2 is less than 29%, and the maximum value of the area of the hole in the XY plane (area of the outermost surface) is When the area of the circumscribed right trapezoid is 50% or more, the shape of the hole H is recognized as a right trapezoid, and the side surface of the hole H is recognized as including three {100} planes.

  FIG. 27 is a diagram illustrating rotation in the direction of the hole H in the case of a right trapezoid.

  As in the case of the rectangle described above, a perpendicular line is drawn from the center of gravity G in the plane of the hole H toward the one side (010) plane, and the angle formed by the perpendicular line VR and [0-10] is the rotation angle φ. To do. That is, assuming that the hole H has a rectangular shape, a vertical line VR is drawn on one side thereof. When there is a slight fluctuation in the shape of the hole H, a rectangle circumscribing the hole is defined as the shape of the hole H. In this case, the allowable range of the rotation angle φ at which a good crystal is obtained is the same as in the case of the rectangle described above. This is because when the rotation angle φ exceeds the allowable range, {100} Facet approaches (110) and (−1-10), the above-described dislocation generation mechanism works. This is because the three {100} Facets are common, and the mechanism of dislocation generation is suppressed if the rotation angle φ is within the allowable range.

  FIG. 28 is a diagram showing various hole shapes.

  The dotted line in the figure indicates the {100} plane. FIG. 28A shows the shape of the above-described embodiment. In (B), a part of one side of (A) is missing and the side surface of the buried layer has a recess (concave surface). In (C), a part of the two sides of (A) is missing and the side surface of the buried layer has a recess (concave surface). In (D), a part of the three sides of (A) is missing and the side surface of the buried layer has a recess (concave surface). In (E), a part of the four sides of (A) is missing and the side surface of the buried layer has a recess (concave surface). Note that there may be a plurality of concave portions shown in (B) to (E), or the concave portions may be replaced with convex portions. (F) is a case where a part of the center of the buried layer of (A) is missing. There may be a plurality of regions lacking (F).

  Even in these cases, it is considered that the above-described effects are exhibited because the mechanism of dislocation generation due to the above (110) and (-1-10) is suppressed.

  (G) is a projection (convex surface) shape in which the hypotenuse of the side surface of the buried layer in (A) has two planes. In (H), the side surface of the buried layer in (A) has a convex (convex) shape in which a large number of planes are continuous. In (I), the side surface of the buried layer in (A) has a shape in which the hypotenuse has two convex portions (convex surfaces). In (J), the side surface of the buried layer in (A) has a shape in which one side has a V-groove-shaped recess (concave surface).

  In these cases, it is considered that the above-described crystallinity and surface morphology can be improved for the same reason that the dislocation generation mechanism is suppressed.

  (K) is a convex portion (convex surface) shape in which the hypotenuse of the side surface of the buried layer in (A) is curved. (L) is a concave (concave) shape in which the hypotenuse of the side surface of the buried layer in (A) is a curved line. (M) represents an example of a shape in which the length of one side is an uneven shape formed by a {100} plane having a length of 5 nm or more, and the shape of the envelope connecting the deepest portion of the concave portion on the side surface is a rectangle. In addition, although the shape of the concavo-convex envelope formed by the {100} plane is a rectangle in (M), it may be an arbitrary shape such as a triangle (N) or a circle (O).

  In these cases, it is considered that the above-described crystallinity and surface morphology can be improved for the same reason that the dislocation generation mechanism is suppressed.

  As described above, in the above-described embodiment, the side surface of the hole H has at least three different {100} planes, or a rotational angle of less than ± 35 degrees around these planes about the normal of the main surface. Includes a surface rotated by. In such a case, the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good, the flatness is high, and the amount of dislocation generated inside is relatively high. It can be seen that is decreasing. When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by adopting the hole-shaped configuration described above.

  In particular, as in the embodiment shown in FIGS. 1-9, the side surface of the hole includes four different {100} faces, or these faces are mainly used as in the embodiment shown in FIGS. When a surface rotated around the surface normal by a rotation angle of less than ± 35 degrees is included, the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good, and the flatness is The characteristics of the semiconductor surface light emitting device can be improved.

  Further, when the rotation angle φ is ± 25 degrees or less, the surface morphology is remarkably improved and the crystallinity of the semiconductor layer is improved as compared with the case of 35 degrees. When the rotation angle φ is ± 20 degrees or less, the surface morphology is further improved as compared with the case of 25 degrees, and the crystallinity of the semiconductor layer is improved.

  The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.

  FIG. 29 is a diagram for explaining a first manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  In order to take alignment after epitaxial growth, a SiN layer AG is formed on the basic layer 6A by PCVD (plasma CVD), and then a resist R is formed on the SiN layer AG (C). Further, the resist R is exposed and developed (D), the SiN layer AG is etched using the resist R as a mask, and a part of the SiN layer AG is left to form an alignment mark (E). The remaining resist is removed (F).

  Next, a resist R2 is applied to the basic layer 6A, a two-dimensional fine pattern is drawn on the resist R2 by an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist R2 (H). Thereafter, using the resist R2 as a mask, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (forming a hole H) (I), and the resist is removed (J). The depth of the hole H is 100 nm.

  Thereafter, regrowth is performed using the MOCVD method.

  In the regrowth process, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (K). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (L), the resist R3 is patterned (M), and an electrode E is deposited on the resist R3 (N). The electrode material is removed leaving only the electrode (Cr / Au) E2 by lift-off (O). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (P).

  FIG. 30 is a diagram for explaining a second manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  Next, a resist R2 is applied on the basic layer 6A (B), a two-dimensional fine pattern is drawn with an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist (C). At this time, squares with sides of 120 nm surrounded by (110) Facets are arranged at 330 nm intervals at the alignment mark position of the photomask to be used, and the area of the entire region is set to 100 μm × 100 μm. As will be described later, this pattern is used as a reference for alignment of optical exposure after regrowth.

  Thereafter, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (D), and the resist is removed (E). Since the position of the mark is also etched, a pattern (alignment mark) is formed at this position. This pattern has side surfaces surrounded by four {110} planes, but may be rotated slightly (within ± 10 degrees). In this pattern, dislocations are formed even by regrowth, so that the regrowth surface becomes rough. Therefore, the rough surface can be used as a reference for alignment in optical exposure after regrowth. Thereafter, regrowth is performed using the MOCVD method. Thus, before the step of performing the regrowth of the buried layer, the {110} plane or {110} was rotated by a rotation angle within ± 10 degrees around the normal line of the main surface (001) by etching. By forming the alignment mark including the surface in an appropriate location (outside area of the light emitting element formation scheduled area) of the semiconductor substrate on which the basic layer 6A is formed, the normal alignment mark forming process can be omitted. .

  In the regrowth step, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (F). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (G), the resist R3 is patterned by optical exposure (H), and an electrode E is deposited on the resist R3 (I). Then, the electrode material is removed by lifting off, leaving only the electrode (Cr / Au) E2 (J). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (K).

  According to this method, when the above-described element is formed, a pattern surrounded by the {110} plane is formed before regrowth, and this is used as a reference position for alignment of optical exposure after regrowth. Can be used.

  The depth of the hole H may be shallower than the basic layer 6A or slightly deeper. The (001) wafer may be an off-substrate.

  In addition, although the manufacturing method by the electron beam exposure method was demonstrated in the embodiment as the manufacturing method of the hole H, you may use other microfabrication techniques, such as optical exposures, such as nanoimprint, interference exposure, FIB, and a stepper.

6A: basic layer, 6B: buried layer, H: hole.

Claims (7)

  A photonic crystal in which a plurality of holes are periodically formed in a basic layer made of a first compound semiconductor having a zinc flash structure, and a buried layer made of a second compound semiconductor having a zinc flash structure is grown in the hole. And an active layer that supplies light to the photonic crystal layer, the main surface of the basic layer is a (001) plane, and the side surface of the hole has at least three different {100} planes Alternatively, the semiconductor surface light emitting device includes a surface obtained by rotating these surfaces at a rotation angle of less than ± 35 degrees around a normal line of the main surface. The side surface of the hole includes four different {100} planes, or planes obtained by rotating these planes around the normal of the main surface with a rotation angle of less than ± 35 degrees.
The semiconductor surface light emitting device according to claim 1. The rotation angle is set to ± 25 degrees or less,
The semiconductor surface-emitting device according to claim 1 or 2, The rotation angle is set to ± 20 degrees or less,
The semiconductor surface-emitting device according to claim 1 or 2, The first compound semiconductor is GaAs;
The second compound semiconductor is AlGaAs;
The semiconductor surface light-emitting device according to claim 1, wherein the semiconductor surface light-emitting device is provided. In the manufacturing method of the semiconductor surface light emitting element which manufactures the semiconductor surface light emitting element of any one of Claims 1 thru | or 5,
Forming the hole;
Growing the buried layer;
A method for manufacturing a semiconductor surface light emitting device, comprising: Before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} at a rotation angle within ± 10 degrees around the normal of the main surface by etching is used as the base layer. The method of manufacturing a semiconductor surface light emitting device according to claim 6, further comprising a step of forming the semiconductor substrate on the semiconductor substrate on which the semiconductor surface is formed.