JP5488917B2 - Semiconductor surface light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor surface light emitting device and a method for manufacturing the same.

  A photonic crystal is a nanostructure whose refractive index changes periodically, and the wavelength of light passing through the nanostructure can be controlled. As a next generation semiconductor surface light emitting device, a photonic crystal surface emitting laser (hereinafter referred to as PCSEL) using a two-dimensional photonic crystal (hereinafter referred to as 2DPC) has been proposed. PCSEL has the characteristics that its optical characteristics are determined by the size and shape of the microstructure and does not depend on the material. Conventional semiconductor light emitting devices such as large area, single mode, two-dimensional polarization control, and emission angle control It has new characteristics that are difficult to realize by itself, and has the potential to open up the possibilities of high-power semiconductor lasers.

In actual production of 2DPC, a wafer bonding technique is used, and the following problems (1) to (3) are present.
(1) It is difficult to produce a large area 2DPC. That is, when the wafer to be bonded has a warp, when there is dust between the wafers, or when there are large irregularities on the wafer surface, these wafers cannot be bonded well.
(2) The 2DPC layer includes a cavity, has a large coupling coefficient κ, and is not suitable for increasing the area. The reason is that in order to distribute light uniformly in the 2DPC layer, the normalized coupling coefficient κL in the in-plane direction with respect to the electrode length L is preferably about 1 to 2, but the 2DPC layer includes a cavity. This is because the value of κ is a value of 1000 cm ⁻¹ or more, and the value of L is limited to several tens of μm.
(3) Since defects are formed at the interface between the bonded wafers, there are difficulties in life and reliability.

As a 2DPC manufacturing means for solving the above problems, there is a regrowth type PCSEL utilizing crystal regrowth, and this has the following advantages.
(1) It is easy to produce a large area 2DPC. That is, when regrowth is used, there is no need to bond crystals.
(2) When the 2DPC layer is completely embedded, the coupling coefficient κ is reduced to about 1/10 of the coupling coefficient when the wafers are bonded, so that the area can be easily increased.
(3) Since the interface of the 2DPC layer is embedded with an epi layer, there are few defects and the reliability is improved.
(4) Since the 2DPC layer does not include cavities, it has excellent heat dissipation and is suitable for high output.

  From the above viewpoint, the regrowth type PCSEL is superior to the bonded type PCSEL in aiming at the practical use of the high output PCSEL.

  Patent Document 1 proposes that a hexagonal convex portion is embedded in a semiconductor layer as a photonic crystal that does not generate a cavity in crystal regrowth. In this case, the side surface is the (1-100) plane with respect to the main surface (0001) plane of the convex portion.

  In Patent Document 2, regrowth is performed in a zinc blendestructure crystal growth using a (111) substrate having a polar plane or an (n11) substrate having a semipolar plane (2 ≦ n ≦ 6 is desirable). Embedding is performed, and lateral growth is used as the means.

JP 2009-206157 A JP 2010-114384 A

  However, when the inventors of the present invention have made a hole in the zinc flash structure semiconductor layer and regrown the crystal in the hole, the surface morphology of the compound semiconductor layer formed thereon is not sufficient, and the crystal inside It was discovered that a large dislocation occurred. That is, since the crystallinity of the formed semiconductor layer is not sufficient, the characteristics of the semiconductor surface light emitting element are not sufficient.

  This invention is made | formed in view of such a subject, and it aims at providing the semiconductor surface light emitting element which can improve a characteristic, and its manufacturing method.

  In order to solve the above-described problem, a semiconductor surface light emitting device according to the present invention is formed by periodically forming a plurality of holes in a basic layer made of a first compound semiconductor having a zinc flash structure, and having a zinc flash structure in the hole. A photonic crystal layer obtained by growing a buried layer made of a second compound semiconductor, and an active layer that supplies light to the photonic crystal layer, and the main surface of the basic layer is (001) A side surface of the hole includes a {110} plane, or a plane obtained by rotating the plane around a normal to the main surface at a rotation angle of less than ± 15 degrees, , At least one {110} plane that is an interface with the side surface, or a convex or concave portion that protrudes from a plane obtained by rotating these planes around the normal of the main surface at a rotation angle of less than ± 15 degrees It is characterized by having.

  If the side surface of the hole is formed by four different {110} planes, the buried layer grown perpendicular to the (110) and (-1-10) side surfaces has (110) and (-1-10) Facet When these facets come into contact with each other at the center, it was found that the crystals were disturbed and the final crystallinity was deteriorated. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside. Further, when (110) and (−1-10) are included in the side surface of the hole, Facet that appears in the early stage of the regrowth embedding process (for example, (113), (−1-13), that is, (113) A surface) Multiple Facet competition occurs above and partially regrowth. There is also a mechanism that this region becomes the nucleus of dislocation formation.

  On the other hand, in the case where the side surface shape of the hole and the buried layer is that of the present invention, the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good, and the flatness is high. It can be seen that the amount of dislocations generated has decreased. When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by setting the shape of the hole to that of the present invention.

  The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.

  In addition, the manufacturing method of the semiconductor surface light emitting element for manufacturing the above-described semiconductor surface light emitting element includes a step of forming the hole and a step of growing the buried layer. In addition, before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} by a rotation angle within ± 10 degrees around the normal of the main surface by etching, You may include the process of forming in the semiconductor substrate in which a base layer is formed. According to this method, when the above-described element is formed, the regrowth surface is roughened by forming dislocations in the regrowth layer of the alignment mark, and can be used as a reference position for optical exposure.

  According to the semiconductor surface light emitting device and the manufacturing method thereof of the present invention, since the crystallinity of the semiconductor layer constituting the semiconductor surface light emitting device is improved, it is possible to improve characteristics such as light emission output and life.

It is a perspective view of the semiconductor surface light emitting element which shows a semiconductor surface light emitting element partially broken. It is a top view of basic layer 6A formed on the wafer. It is a front view of a wafer. It is a figure which shows the shape of a hole. It is a figure which shows the electron micrograph (A) of basic layer 6A in which the hole was formed, and the optical micrograph (B) of the surface of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the electron micrograph (A) of basic layer 6A in which the hole was formed, and the optical micrograph (B) of the surface of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the electron micrograph (A) of basic layer 6A in which the hole was formed, and the optical micrograph (B) of the surface of the semiconductor layer located in the outermost surface side of a semiconductor surface light emitting element. It is a figure which shows the detailed structure of the shape of a hole. It is sectional drawing of a semiconductor surface light emitting element. It is a top view of basic layer 6A formed on the wafer concerning the 1st comparative example. FIG. 3 is a view showing a surface photograph of a basic layer and a cross-sectional photograph of a semiconductor surface light emitting device according to a first comparative example. FIG. 4 is a view showing an optical micrograph of the surface of a semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device according to the first comparative example. It is a figure explaining the state of deterioration of crystallinity. It is a figure which shows the surface photograph of the basic layer which concerns on a 2nd comparative example, and the cross-sectional photograph of a semiconductor surface light emitting element. It is a figure which shows the optical microscope photograph of the surface of the semiconductor layer located in the outermost surface side of the semiconductor surface light emitting element which concerns on a 2nd comparative example. It is a figure shown about the shape of various holes. It is a figure shown about the shape of various holes. FIG. 5 is a diagram for explaining a first manufacturing method of a photonic crystal layer. It is a figure for demonstrating the 2nd manufacturing method of a photonic crystal layer.

  Hereinafter, the semiconductor surface light emitting device and the manufacturing method thereof according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a perspective view of a semiconductor surface light emitting device, with the semiconductor surface light emitting device partially cut away.

  The semiconductor surface light emitting device includes a lower clad layer 2, a lower light guide layer 3, an active layer 4, an upper light guide layer 5, a photonic crystal layer 6, an upper clad layer 7, and a contact layer 8 that are sequentially formed on a semiconductor substrate 1. It has. On the back side of the semiconductor substrate 1, an electrode E <b> 1 is provided on the entire surface, and an electrode E <b> 2 is provided in the center portion of the contact layer 8.

The materials / thicknesses of these compound semiconductor layers are as follows. Note that an intrinsic semiconductor having an impurity concentration of 10 ¹⁵ / cm ³ or less has no conductivity type. In addition, the density | concentration when an impurity is added is 10 < ¹⁷ > -10 < ²⁰ > / cm < ³ >. Further, the following is an example of the present embodiment, and any structure including the active layer 4 and the photonic crystal layer 6 has a degree of freedom in the material system, film thickness, and layer configuration. The numerical values in parentheses are those used in the experiments described later, the growth temperature of AlGaAs by MOCVD is 500 ° C. to 850 ° C., 550 to 700 ° C. is adopted in the experiments, and the Al raw material during growth TMA (trimethylaluminum) as the gallium source, TMG (triethylgallium) as the gallium source, AsH _{3 (} arsine) as the As source, Si ₂ H ₆ (disilane) as the source for the N-type impurity, P type DEZn (diethyl zinc) was used as a raw material for impurities.
Contact layer 8: P-type GaAs / 50 to 500 nm (200 nm)
Upper clad layer 7: P-type AlGaAs (Al _0.4 Ga _0.6 As) /1.0 to 3.0 μm (2.0 μm)
Photonic crystal layer 6:
Basic layer 6A: GaAs / 50 to 200 nm (100 nm)
Buried layer 6B: AlGaAs (Al _0.4 Ga _0.6 As) / 50 to 200 nm (100 nm)
Upper light guide layer 5:
Upper layer: GaAs / 10-200 nm (50 nm)
Lower layer: p-type or intrinsic AlGaAs / 10 to 100 nm (50 nm)
Active layer 4 (multiple quantum well structure):
AlGaAs / InGaAs MQW / 10 to 100 nm (30 nm)
Lower light guide layer 3: AlGaAs / 0 to 300 nm (150 nm)
Lower clad layer 2: N-type AlGaAs / 1.0 to 3.0 μm (2.0 μm)
Semiconductor substrate 1: N-type GaAs / 80 to 350 μm (150 μm)

  When a current is passed between the upper and lower electrodes E1, E2, a current flows in a region R immediately below the electrode E2, this region emits light, and the laser beam LB is output in a direction perpendicular to the substrate.

  FIG. 2 is a plan view of the basic layer 6A formed on the wafer. In the plan view, for the purpose of clarifying the understanding, a plurality of holes H are described which are much larger than the actual scale, and the number thereof is smaller than the actual scale. FIG. 3 is a front view of the wafer.

  The main surface of the wafer (substrate) is the (001) plane, and in the drawing, the main surface (001) of the basic layer 6A is exposed on the surface. The a-axis, b-axis, and c-axis of the zinc-blende structure crystal are shown in the drawing as the X-axis, Y-axis, and Z-axis, respectively. The directions of the X axis, the Y axis, and the Z axis are [100], [010], and [001], respectively.

  An orientation flat (hereinafter referred to as orientation flat) OF is formed at one end of the wafer, and the orientation flat OF is perpendicular to the [110] direction. The orientation flat OF has a (-1-10) plane. A plurality of holes H (H1 to H10) are formed in the basic layer 6A, and each hole H has a depth in the thickness direction of the semiconductor substrate.

  The outline of the hole H in the planar shape is a shape in which a convex portion is coupled to one side of the rectangle and the one side facing the convex portion is expanded, and each side of the rectangle has a direction [1-10] or [ 110]. That is, the five side surfaces of the hole H other than the convex portion have a (−1-10) plane, a (−110) plane, a (1-10) plane, a (h1k10) plane, and a (h2k20) plane, respectively. Yes. As crystallographically equivalent planes, the (110) plane, the (−110) plane, and the (1-10) plane can be represented as {110} planes.

  The gravity center positions of the holes H in the plane are arranged at equal intervals along the [1-10] direction, and are also arranged at equal intervals along the [110] direction. In the drawing, the case where the former interval (for example, between H1 and H2) is shorter than the latter interval (for example, between H1 and H6) is shown, but the present invention is not limited to this. Further, another hole H4 is arranged on an extension line along the [110] direction of the midpoint position of the former interval (for example, between H1 and H2).

In the embodiment, the interval in the [1-10] direction of the center of gravity of the hole H is 335 nm, and the interval in the [110] direction is 580 nm. The shape of the hole includes a rectangle, and the lengths of two sides constituting the rectangle are 120 nm and 100 nm, and the area is 1.2 × 10 ⁴ nm ² . In addition, the line group which connects the gravity center position of the hole H can comprise a square lattice, a rectangular lattice, and a triangular lattice, and may be a random arrangement | positioning.

  Since the buried layer 6B shown in FIG. 1 is buried in the hole H of the basic layer 6A, its side surface is in contact with the side surface of the hole H, and its plane orientation matches the plane orientation of the side surface of the hole H. Yes.

  As described above, the above-described semiconductor surface light-emitting device has a plurality of holes H periodically formed in the basic layer 6A made of the first compound semiconductor (GaAs) having the zinc flash structure, and the zinc H structure having the zinc flash structure. A photonic crystal layer 6 formed by growing a buried layer 6B made of a second compound semiconductor (AlGaAs) is provided. Of course, since the photonic crystal is formed, the refractive index of the first compound semiconductor is different from that of the second compound semiconductor.

  FIG. 4 is a diagram showing the shape of the hole.

  The hole H as a design value shown in FIG. 4A includes a rectangular portion HA, a convex portion HB protruding from one side of the rectangular portion HA, and a convex portion HC protruding in the opposite direction from one side facing the one side. I have. The side surface of the hole H including each of the four sides of the rectangle HA is composed of {110} planes. The protrusion distance from one side of the protrusion HB (50 nm in this example) is shorter than the protrusion distance of the protrusion HC (20 nm in this example). The length of each side of the rectangle in this example is 100 nm, and the hole H forms a square.

  The actual hole H shown in FIG. 4B breaks the convex portion of the basic layer, corresponds to the main body portion HA1 corresponding to the rectangular portion HA, the convex portion HB1 corresponding to the convex portion HB, and the convex portion HC. The convex portion HC1 has a combined shape. In other words, the buried layer 6B has a main body HA1 and convex portions HB1 and HC1. Two opposing side surfaces of the main body HA1 are perpendicular to [1-10] and have (1-10) plane and (−110) plane, and the remaining planes are perpendicular to [110] ( -110) plane. In this example, the distance between the (1-10) plane and the (−110) plane of the main body HA1 is 120 nm. The protruding distance S1 from one side (110) of the convex portion HB1 is shorter than the protruding distance S2 of the convex portion HC1. In crystal growth, the preferable range of the value of S1 is 15 nm or more. Note that S2 may be zero. This is because, due to the effect of S1, the dislocation generation mechanism resulting from (-1-10) described with reference to FIG. 13 is halved, and the generated dislocation is halved. In crystal growth, the preferred range of the value of S2 is 0 nm or more. In addition, as for the shape of the hole H, S1 and S2 may be upside down, and it is good also considering a convex part as a recessed part. Further, a plurality of convex portions and concave portions may exist on an arbitrary {110}. Even when this concave portion is formed, it is considered that the dislocation generation mechanism is suppressed as in the case of the convex portion.

  The above-described semiconductor surface light emitting device was formed and evaluated. In the description, a scanning electron microscope (SEM) was used as the electron microscope. The cross-sectional SEM image was taken after the cross-section was stain-etched with ammonia perwater.

  5 to 7 are an electron micrograph (A) of the basic layer 6A in which the hole H is formed and an optical micrograph (B) of the surface of the semiconductor layer (contact layer) located on the outermost surface side of the semiconductor surface light emitting device. FIG.

  5, the [110] direction length of the main body HA1 (see FIG. 4) is 100 nm, the [1-10] direction length is 120 nm, and the [110] direction length of the convex portion HB1 is 15 nm. Yes, the [1-10] direction length is 40 nm, the [110] direction length of the convex portion HC1 is 15 nm, and the [1-10] direction length is 60 nm.

  In addition, the [110] direction length of the main body HA1 (see FIG. 4) in the case of FIG. 6 is 100 nm, the [1-10] direction length is 120 nm, and the [110] direction length of the convex portion HB1 is 30 nm. Yes, the [1-10] direction length is 40 nm, the [110] direction length of the protrusion HC1 is 20 nm, and the [1-10] direction length is 60 nm.

  In addition, the [110] direction length of the main body HA1 (see FIG. 4) in the case of FIG. 7 is 100 nm, the [1-10] direction length is 120 nm, and the [110] direction length of the convex portion HB1 is 40 nm. Yes, the [1-10] direction length is 50 nm, the [110] direction length of the convex portion HC1 is 30 nm, and the [1-10] direction length is 50 nm.

  In the following description, FF represents Filling Factor. The Filling Factor is an index for measuring the size of the photonic crystal, and is the ratio of the area occupied by the photonic crystal shape (hole area) to the area of the unit period of the two-dimensional structure. In the following example, the length a (lattice constant) per unit period of the two-dimensional structure (length in the [1-10] direction) is 335 nm.

  FIG. 5 shows a case where FF is 12.5%, FIG. 6 shows a case where FF is 14.5%, and FIG. 7 shows a case where FF is 16.7%. In any case, the protrusions have better morphology and crystallinity than those of the comparative examples (FIGS. 11, 12, 14, and 15), but the surface morphology is increased as the FF increases. Is further improved. Therefore, the FF is preferably 12.5% or more, and the [110] direction length of the protrusion HB1 is preferably 15 nm or more, or the total of the FF increments by the protrusion HB1 and the protrusion HC1 is preferably 1% or more. If the concave portion is provided instead of the convex portion, the length in the [110] direction is preferably 15 nm or more, or the total FF increment by all the concave portions is preferably 1% or more. In addition, it is preferable that the protrusion amount or retraction amount of a convex part or a recessed part does not exceed the maximum diameter of the main-body part except each.

  FIG. 8 is a diagram showing a detailed configuration of the shape of the hole H.

  The buried layer 6B in the hole H includes a main body HA1, a convex portion HB1, and a convex portion HC1. A polygon (decagon) circumscribing the outline of the hole H is set in the XY plane. Each side has a (-1-10) plane, (h6k60) plane, (h5k50) plane, (h4k40) plane, (h3k30) plane, (-1-10) plane, counterclockwise from the (-110) plane, It has a (1-10) plane, a (h1k10) plane, and a (h2k20) plane. h1 to h6 and k1 to k6 are values of appropriate Miller indices representing plane orientations. The main body HA1 has a quadrangular shape,

  In the buried layer 6B, the total length L of the corresponding sides in the XY plane whose separation distance from the (hkl) plane is 20 nm or less is 50% or more of the length of the corresponding sides of the circumscribed polygon. When the continuous length of the side that satisfies the above is 10 nm or more, the side surface of the buried layer 6B includes the (hkl) plane. When the side surface of the buried layer 6B has a plurality of convex portions, concave portions are formed between the convex portions. In this case, a line segment (group) connecting the deepest portions in the concave portions is used as the buried layer. When the relation with the corresponding side (hkl) of the polygon circumscribing it is considered as the side face of 6B, the side face of the buried layer 6B includes the (hkl) face. .

  That is, for example, when the (hkl) plane is the (−110) plane, the length between the intersection points P1 and P2 with the diagonal line of the polygon circumscribing the main body HA1 is (−110) of the circumscribed polygon. When the length of the side including the surface is 50% or more of the length L1 and the condition for the continuous length is satisfied, the main body HA1 includes the (−110) surface.

  For example, when the (hkl) plane is the (1-10) plane, the length between the intersection points P3 and P6 with the diagonal line of the polygon circumscribing the main body HA1 is (1-10) of the circumscribed polygon. When the length of the side including the surface is 50% or more of the length L1 and the condition for the continuous length is satisfied, the main body HA1 includes the (1-10) surface.

  Similarly, for example, when the (hkl) plane is the (−1-10) plane on the left side of the drawing, the length between the intersection points P3 and P4 with the diagonal line of the polygon drawing circumscribing the main body HA1 is When the length L3 of the side including the (−1-10) plane on the left side of the polygon is 50% or more and the condition for the continuous length is satisfied, the main body HA1 includes the (−1-10) plane. I will do it.

  Similarly, for example, when the (hkl) plane is the (−1-10) plane on the right side of the drawing, the length between the intersection points P5 and P1 with the diagonal line of the polygon drawing circumscribing the main body HA1 is When the length L4 of the side including the (−1-10) plane on the right side of the polygon is 50% or more and the condition of the continuous length is satisfied, the main body HA1 includes the (−1-10) plane. I will do it. The sides corresponding to L3 and L4 are included in the (-1-10) plane, and L3 + L4 <L2 × 50%.

  The distance between the opposing {110} faces of the circumscribed polygon, that is, the distance between the (1-10) face and the (−110) face is L2, and L2 is 120 nm, for example.

  FIG. 9 is a cross-sectional view of a semiconductor surface light emitting device. This example shows a cross section parallel to the orientation flat.

  As described above, the semiconductor surface light emitting device includes the lower cladding layer 2, the lower light guide layer 3, the active layer 4, the upper light guide layer 5, the photonic crystal layer 6, and the upper cladding layer that are sequentially formed on the semiconductor substrate 1. 7 and a contact layer 8 are provided. Here, the active layer 4 supplies light to the photonic crystal layer 6, and includes upper and lower semiconductor layers 4A and 4C and a central semiconductor layer 4B sandwiched between them. The relationship of these energy band gaps is the same as that of a normal laser, and is set so as to have a multiple quantum well structure in which a 4B QW (quantum well) layer is sandwiched between 4A and 4C guide layers. The photonic crystal layer 6 is used to generate laser light by light resonance. That is, this semiconductor surface light emitting device is a photonic crystal surface emitting laser, but if the laser oscillation does not occur, the structure can be used as a light emitting diode.

  Each hole H may have inclined surfaces F3 and F4 inclined with respect to the {110} side surfaces, and F3 and F4 may be curved surfaces.

  FIG. 10 is a plan view of the basic layer 6A formed on the wafer according to the first comparative example. Assuming that the semiconductor surface light emitting device shown in FIGS. 1 to 9 is an example, the element of the first comparative example is different from the example only in the shape of the hole H. That is, the side surfaces of the holes H are each constituted only by {110} planes. More specifically, the respective sides are (110), (1-10), (-1-10), and (-110).

  FIG. 11 is a view showing an electron micrograph of the basic layer 6A in which holes are formed according to the first comparative example.

  FIG. 11A shows a plan photograph of the hole H, and the square hole H is shown. FIG. 11B shows a cross-sectional image of the basic layer cut before the orientation flat parallel direction (before formation of the buried layer), and FIG. 11C shows the basic layer cut along the orientation flat parallel direction (embedded layer). A cross-sectional image before layer formation) is shown. FIG. 11D shows a cross-sectional image of the basic layer cut after the orientation flat parallel direction (after formation of the buried layer), and FIG. 11E shows the basic layer cut along the parallel orientation direction of the orientation flat (embedded layer). The cross-sectional image after layer formation is shown.

  The filling process is continued until the upper cladding layer is formed, and then the contact layer is formed. Large dislocations are observed in these buried layers and the upper cladding layer (see FIGS. 11D and 11E), indicating that the crystallinity is not good.

  FIG. 12 is a view showing an optical micrograph of the surface of the semiconductor layer (contact layer) located on the outermost surface side of the semiconductor surface light emitting device according to the first comparative example.

  The surface of the contact layer is rough, the morphology is bad, and many irregularities are observed. This indirectly indicates that the crystallinity is poor inside.

  Thus, it was found that the crystallinity is low when the side surface of the hole is formed by four different {110} planes. Consider this principle.

  FIG. 13 is a diagram showing the concept of crystallinity degradation.

  In the first comparative example, (110) and (-1-10) Facets appear in the buried layer grown perpendicularly to the side surfaces of (110) and (-1-10) (A), and the crystal growth proceeds. Accordingly, it was found that when these facets come into contact with each other at the center, the crystals are disturbed (B) and the final crystallinity is deteriorated. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside. Further, when (110) and (−1-10) are included in the side surface of the hole, Facet that appears in the early stage of the regrowth embedding process (for example, (113), (−1-13), that is, (113) A surface) Multiple Facet competition occurs above and partially regrowth. There is also a mechanism that this region becomes the nucleus of dislocation formation.

  On the other hand, in the present invention, the main surface of the basic layer 6A is the (001) plane, and the side surface (interface with the hole H) of the buried layer 6B has the protrusion HB1 protruding from the {110} plane. . Therefore, the dislocation formation mechanism due to the above (110) and (−1-10) is suppressed, and it is considered that the crystallinity is improved.

  An experiment was also performed when the shape of the hole H was circular.

  FIG. 14 is a view showing an electron micrograph of the basic layer 6A in which holes are formed according to the second comparative example. Only the shape of the hole H is different from the first comparative example, and the others are the same. The opening diameter of the hole H is 110 nm.

  FIG. 14A shows a plane photograph of the hole H, and the circular hole H is shown. FIG. 14B shows a cross-sectional image of a basic layer cut before the orientation flat parallel direction (before formation of the buried layer), and FIG. 14C shows a basic layer cut along the orientation flat parallel direction (the buried layer). A cross-sectional image before layer formation) is shown. FIG. 14D shows a cross-sectional image of the basic layer cut after the orientation flat parallel direction (after formation of the buried layer), and FIG. 14E shows the basic layer cut along the parallel orientation direction of the orientation flat (embedded layer). The cross-sectional image after layer formation is shown.

  The filling process is continued until the upper cladding layer is formed, and then the contact layer is formed. Large dislocations are not observed in these buried layers and upper cladding layers (see FIGS. 14D and 14E).

  However, the surface morphology is getting worse.

  FIG. 15 is an optical micrograph of the surface of the semiconductor layer located on the outermost surface side of the semiconductor surface light emitting device according to the second comparative example. The surface of the contact layer is rough, the morphology deteriorates, and many irregularities are observed. This is because dislocations are not observed in the observation range of FIG. 14, but dislocations are formed when examined in a wider area, leading to deterioration of the surface morphology.

  FIG. 16 is a diagram showing the shapes of various holes (embedded layer 6B). The dotted line in the figure indicates the {110} plane. Each figure in FIG. 17 is obtained by rotating each figure in FIG. 16 by 90 degrees in the XY plane, but these are the same crystallographically.

In FIG. 16 or FIG. 17A, the position of the upper convex portion is slightly changed to the left side from the shape of the above-described embodiment, and the lower convex portion is removed. The upper convex portion may be a concave portion.
In (B), a part of one side of (A) is missing and the side surface of the buried layer has a recess (concave surface). (C) is one in which a part of the two sides of (A) is missing and the side surface of the buried layer has a concave portion (concave surface), and also has a convex portion on the lower side. (D) makes the main-body-part shape of (A) trapezoid. (E) is a parallelogram of the main body shape of (A). (F) is a smoothed corner of the main body of (A). (G) shows the shape of the main body portion of (A) as a triangle, and (H) shows the shape of the main body portion of (A) as a pentagon. Is shown to be opposite, but crystallographically opposite is meaningless. (I) is a hexagonal shape of the main body of (A). (J) enlarges the shape of each convex part extended from two opposing sides in the embodiment, and makes the shape of these convex parts asymmetric. The planar shape of one convex part is a rectangle. (K) shows a quadrangle covered with one or more irregular shapes consisting of a suitable side surface (hk0) having a side length of 5 nm or more on the (110) and (-1-10) planes. The (hk0) plane is preferably {100}. (L) represents a shape having a chip in the uneven shape in the shape of (K). (M) represents a shape having an uneven shape only on one {110} plane in the shape of (K). (N) represents a shape having a curved side surface in the shape of (K). (O) represents an example of a shape including two or more of the same {110} planes in (K). In (K) to (O), if one side includes (110) or (-1-10), each point of the apex of the convex portion on the side surface of the hole H (the deepest portion of the concave portion in the embedded layer 6B). The shape of the envelope connecting the two lines may not be a quadrangle.

  Even in these cases, it is considered that the above-described effects are exhibited because the mechanism of dislocation formation due to (110) and (−1-10) described with reference to FIG. 13 is suppressed.

  As described above, in the above-described embodiment, the side surface of the hole H has a {110} surface, and the buried layer 6B has at least one {110} surface that is an interface with the side surface of the hole H. It has a convex part HB1 protruding from. In this case, it can be seen that the surface morphology of the semiconductor layer formed on the photonic crystal layer is very good, the flatness is high, and the amount of dislocation generated inside is relatively reduced. . When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by adopting the hole-shaped configuration described above.

  The side surfaces including (110) and (-1-10) in the shape of the hole described above allow rotation (within ± 15 degrees) around the normal of the main plane (001) in the XY plane. However, the same effect can be obtained.

  The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.

  FIG. 18 is a diagram for explaining a first manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  In order to take alignment after epitaxial growth, a SiN layer AG is formed on the basic layer 6A by PCVD (plasma CVD), and then a resist R is formed on the SiN layer AG (C). Further, the resist R is exposed and developed (D), the SiN layer AG is etched using the resist R as a mask, and a part of the SiN layer AG is left to form an alignment mark (E). The remaining resist is removed (F).

  Next, a resist R2 is applied to the basic layer 6A, a two-dimensional fine pattern is drawn on the resist R2 by an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist R2 (H). Thereafter, using the resist R2 as a mask, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (forming a hole H) (I), and the resist is removed (J). The depth of the hole H is 100 nm.

  Thereafter, regrowth is performed using the MOCVD method.

  In the regrowth process, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (K). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (L), the resist R3 is patterned (M), an electrode E is deposited from above the resist R3 (N), and lift-off is performed. The electrode material is removed leaving only the electrode (Cr / Au) E2 (O). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (P).

  FIG. 19 is a diagram for explaining a second manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  Next, a resist R2 is applied on the basic layer 6A (B), a two-dimensional fine pattern is drawn with an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist (C). At this time, squares with sides of 120 nm surrounded by (110) Facets are arranged at 330 nm intervals at the alignment mark position of the photomask to be used, and the area of the entire region is set to 100 μm × 100 μm. As will be described later, this pattern is used as a reference for alignment of optical exposure after regrowth.

  Thereafter, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (D), and the resist is removed (E). Since the position of the mark is also etched, a pattern (alignment mark) is formed at this position. This pattern has side surfaces surrounded by four {110} planes, but may be rotated slightly (within ± 10 degrees). In this pattern, dislocations are formed even by regrowth, so that the regrowth surface becomes rough. Therefore, the rough surface can be used as a reference for alignment in optical exposure after regrowth. Thereafter, regrowth is performed using the MOCVD method. Thus, before the step of performing the regrowth of the buried layer, the {110} plane or {110} was rotated by a rotation angle within ± 10 degrees around the normal line of the main surface (001) by etching. By forming the alignment mark including the surface in an appropriate location (outside area of the light emitting element formation scheduled area) of the semiconductor substrate on which the basic layer 6A is formed, the normal alignment mark forming process can be omitted. .

  In the regrowth step, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (F). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (G), the resist R3 is patterned by optical exposure (H), and an electrode E is deposited on the resist R3 (I). Then, the electrode material is removed by lifting off, leaving only the electrode (Cr / Au) E2 (J). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (K).

  According to this method, when the above-described element is formed, by forming a pattern surrounded by the {110} plane before the regrowth, the reference position for alignment of the optical exposure after the regrowth is formed. Can be used as

  The depth of the hole H may be shallower than the basic layer 6A or slightly deeper. The (001) wafer may be an off-substrate.

  In addition, although the manufacturing method by the electron beam exposure method was demonstrated in the embodiment as the manufacturing method of the hole H, you may use other microfabrication techniques, such as optical exposures, such as nanoimprint, interference exposure, FIB, and a stepper.

6A: basic layer, 6B: buried layer, H: hole.

Claims (4)

A photonic crystal in which a plurality of holes are periodically formed in a basic layer made of a first compound semiconductor having a zinc flash structure, and a buried layer made of a second compound semiconductor having a zinc flash structure is grown in the hole. A layer, and an active layer that supplies light to the photonic crystal layer,
With
The main surface of the basic layer is a (001) plane,
The side surface of the hole includes a {110} surface or a surface obtained by rotating the surface around a normal to the main surface at a rotation angle of less than ± 15 degrees, and the embedded layer includes the side surface and At least one {110} plane, or a convex or concave portion protruding from a plane obtained by rotating these planes around the normal of the main surface at a rotation angle of less than ± 15 degrees. A semiconductor surface light emitting device. The first compound semiconductor is GaAs;
The second compound semiconductor is AlGaAs;
The semiconductor surface light emitting device according to claim 1. In the manufacturing method of the semiconductor surface light emitting element which manufactures the semiconductor surface light emitting element of Claim 1 or 2,
Forming the hole;
Growing the buried layer;
A method for manufacturing a semiconductor surface light emitting device, comprising: Before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} at a rotation angle within ± 10 degrees around the normal of the main surface by etching is used as the base layer. 4. The method of manufacturing a semiconductor surface light emitting device according to claim 3, further comprising a step of forming the semiconductor substrate on the semiconductor substrate on which the semiconductor surface is formed.