JP5460069B2 - Semiconductor substrate, semiconductor package, and semiconductor substrate manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor substrate having a through electrode, a semiconductor package, and a method for manufacturing the semiconductor substrate.

An example of a semiconductor package incorporating this type of semiconductor substrate having a through electrode is shown in FIG.
In this semiconductor package, a through hole 21 is formed in the semiconductor substrate 1 by dry etching or the like, and an insulating film is deposited on the side wall of the through hole 21 by a CVD method or the like. An electrode penetrating the semiconductor substrate (called a penetrating electrode) is formed by forming a seed layer on the insulating film and filling a conductive material by plating or the like.

  After or before the formation of the through-hole 21, the wiring layer 5A is formed on the upper surface of the semiconductor substrate 1, and the circuit element 22 mounted on the semiconductor substrate 1 or built in the semiconductor substrate 1 itself and the through-electrode And are electrically connected.

  Also, in this type of semiconductor substrate 1 having this through electrode, after forming the wiring layer 3A on the lower surface of the semiconductor substrate 1, it is flip-chip connected to a substrate 17 such as a resin substrate, and the connection portion is connected by an underfill material 18. After the protection, the entire substrate is covered with a resin 19, and a semiconductor package is manufactured by mounting a conductive member 20 such as a solder ball on the substrate 17, and is electrically connected to an external circuit such as a printed circuit board via the conductive member 20. Has been.

  When circuit elements are formed in the semiconductor substrate 1, an insulating layer is often formed on the upper surface of the semiconductor substrate 1. In order to form a conduction path between the upper surface and the lower surface of the semiconductor substrate 1, it is necessary to form the through hole 21 in the semiconductor substrate 1 and then form an opening in the insulating layer to expose the wiring layer 3A. is there.

Patent Document 1 describes a first method shown in FIGS. 12 (a) to 12 (d).
In FIG. 12A, a through hole forming resist 10 is formed in the semiconductor substrate 1, and the through hole 23 is formed in the semiconductor substrate 1.

  In FIG. 12B, the first insulating layer 2 formed on the semiconductor substrate 1 is etched using the resist 10 as a mask to form the opening 24, and the first wiring layer formed on the semiconductor substrate 1. 3 is exposed in the through hole 23.

In FIG. 12C, the resist 10 is removed, and the second insulating layer 7 is formed on the surface of the semiconductor substrate 1, the side wall of the through hole 23, and the opening 24 by the CVD method or the like.
In FIG. 12D, after the second insulating layer 7 is removed only at the bottom of the through hole 23, the second wiring layer 5 is formed by the seed layer formation by sputtering or the plating method to form the through electrode. Reference numeral 15 denotes a filled insulator.

Patent Document 2 describes a second method shown in FIGS. 13 (a) to 13 (h).
In FIG. 13A, a through hole forming resist 10 is formed on the semiconductor substrate 1, and a mortar shape 25 is formed above the through hole by isotropic etching.

In FIG. 13B, the through hole 26 is formed by anisotropic etching using the resist 10 as a mask.
In FIG. 13C, the resist 10 is removed.

In FIG. 13D, a resist 27 is applied to the entire through hole 26 in order to form an opening in the first insulating layer 2 at the bottom of the through hole 26.
In FIG. 13E, patterning is performed by exposure and development.

In FIG. 13F, an opening 28 is formed in the first insulating layer 2 using the resist 27 as a mask.
In FIG. 13G, the resist 27 is removed.

In FIG. 13 (h), a second wiring layer 5 reaching the first wiring layer 3 is formed by a seed layer formation by sputtering or the like, or a plating method, and a through electrode is formed.
JP 2006-128171 A JP 2007-53149 A

  However, in the first method, when the opening 24 is formed in the first insulating layer 2, the underlying first wiring layer 3 is etched, so that the metal particles popping out from the first wiring layer 3 are in the first insulating layer. The first wiring layer 3 and the semiconductor substrate 1 are electrically connected to the side wall of the opening 24 of the layer 2, and as a result, the reliability of the formed through electrode is lowered.

  In the second method, the opening 28 of the first insulating layer 2 is formed in a part of the bottom surface of the through hole 26 formed in the semiconductor substrate 1 in FIGS. As shown in (g), a stepped portion 29 is formed at the connection portion between the through hole 26 and the opening 28, and the semiconductor substrate 1 even if metal particles adhere to the side wall of the opening 28 of the first insulating layer 2. No conduction path is formed.

  However, since the second wiring layer 5 is formed on the first insulating layer 2 in FIG. 13 (h), a film is formed when thermal stress is applied in a subsequent process such as reflow due to the difference in thermal expansion coefficient thereof. As a result, the through-electrode reliability is lowered. Further, since the resist formation and resist removal steps are required twice, the number of processing steps is increased, and the lead time for manufacturing the through electrode is increased. Further, when a through electrode having a high aspect ratio is produced, as shown in FIG. 13E, even if a mortar shape is formed in the opening, light does not easily enter the bottom of the through hole 26, so that exposure is insufficient. In addition, since the through hole 26 is deep and the developer does not enter the bottom of the hole and development is difficult, it is difficult to form a resist when forming the opening 28 in the first insulating layer 2. Yes.

  An object of the present invention is to provide a semiconductor substrate having a highly reliable through electrode, a semiconductor package, and a method for manufacturing the semiconductor substrate.

According to a first aspect of the present invention, there is provided the semiconductor substrate, wherein the first wiring layer is formed on one surface of the semiconductor substrate via the first insulating layer, and the second wiring layer is formed on the inner periphery of the through hole penetrating the semiconductor substrate. A through-hole formed in the semiconductor substrate, wherein the through-hole has a first opening formed from the other surface of the semiconductor substrate toward the first insulating layer, and more than the first opening. A second opening having a small opening area and penetrating from the bottom of the first opening through the first insulating layer to the first wiring layer; and between the inner periphery of the first opening and the second opening. A recess formed on the surface of the first insulating layer located at the side, and a sidewall formed by the first insulating layer existing between the recess and the second opening, and a second wiring layer, wherein the side wall portion contact constituted by the first insulating layer and the inner peripheral surface and the concave portion of the first opening Characterized in that it is electrically connected to said first wiring layer through a fine second opening.

The semiconductor substrate according to claim 2 of the present invention, in claim 1, the second insulating layer is formed over the peripheral surface of the first opening in the said through hole from the circumferential surface of said recess, said second wiring layer The second insulating layer is interposed between the semiconductor substrate and the semiconductor substrate.

  The semiconductor substrate according to claim 3 of the present invention is the semiconductor substrate according to claim 2, wherein the material of the second wiring layer is a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, or a metal such as TiN. It is a compound, or a conductive material containing them, or a Si-based material such as polysilicon, and the second wiring layer is a single layer or a multilayer film of two or more layers.

A semiconductor substrate according to a fourth aspect of the present invention is the semiconductor substrate according to the second aspect, wherein the material of the second insulating layer is a Si compound such as SiN, SiO ₂ , BPSG, or a thermal oxide film, or a metal compound such as Al ₂ O ₃ , Or it is organic compounds, such as a polyimide resin, The said 2nd insulating layer is a single layer or a multilayer film of two or more layers, It is characterized by the above-mentioned.

  According to a fifth aspect of the present invention, there is provided the semiconductor substrate according to the first aspect, wherein the protective film is formed on the second wiring layer so as to expose a part of the surface thereof, and the external circuit is formed on the second wiring layer. And a conductive member for electrical connection.

A semiconductor substrate according to a sixth aspect of the present invention is characterized in that, in the first aspect, an insulating material is filled in a part or the whole of the void formed inside the through hole.
The semiconductor substrate according to claim 7 of the present invention, in claim 1, pore size of the first opening in the other surface 1b of the semiconductor substrate 1 may be greater than the diameter of the bottom of the recess.

  According to an eighth aspect of the present invention, there is provided the semiconductor substrate according to the first aspect, wherein the semiconductor substrate is a silicon-based semiconductor such as silicon or silica gelmanium or a compound semiconductor such as gallium arsenide, gallium nitride, or indium phosphide. Features.

A semiconductor substrate according to a ninth aspect of the present invention is the semiconductor substrate according to the first aspect, wherein a plurality of the second openings are formed in the first insulating layer.
According to a tenth aspect of the present invention, there is provided the semiconductor substrate manufacturing method, wherein the first wiring layer is formed on one surface of the semiconductor substrate via the first insulating layer, and the semiconductor substrate is moved from the one surface to the other surface. When forming a semiconductor substrate having a through electrode in which a second wiring layer is formed on the inner periphery of a through hole penetrating therethrough, a first penetration is made from the other surface of the semiconductor substrate to the first wiring layer through a mask. Forming a hole and a second through hole surrounding the first through hole simultaneously, etching the semiconductor substrate until the first through hole reaches the first insulating layer, and forming the second through hole in the first insulating layer; Etching until a recess is formed in the first opening, the second opening having a smaller opening area than the first opening, and the inner periphery of the first opening and the second opening. A recess in the surface of the first insulating layer located at , In the first side wall portion formed of an insulating layer, is formed, the first insulating layer and the inner peripheral surface and the concave portion of the first opening that exists between said concave second opening A second wiring layer is formed on the first wiring layer through the side wall portion and the second opening portion, and is electrically connected.

  A semiconductor package according to an eleventh aspect of the present invention includes the semiconductor substrate according to any one of the first to ninth aspects.

According to the present invention, a first open mouth, said a first open mouth part second opening mouth opening area is smaller than between the inner peripheral and the second opening in the first open mouth Since the second wiring layer is formed on and electrically connected to the concave portion formed on the surface of the first insulating layer located at the first insulating layer, the semiconductor substrate and the first wiring are formed by the concave portion. The insulation between the layers is improved, the adhesion between the second wiring layer and the first insulating layer is improved, and the reliability of the through electrode can be improved.

Embodiments of the present invention will be described below with reference to FIGS.
(Embodiment 1)
1 to 5 show Embodiment 1 of the present invention.

FIG. 1 shows a semiconductor substrate having through electrodes.
A through electrode in which a first wiring layer 3 is formed on one surface 1 a of the semiconductor substrate 1 via a first insulating layer 2 and a second wiring layer 7 is formed on the inner periphery of a through hole 4 penetrating the semiconductor substrate 1. The through hole 4 formed by dry etching in the thickness direction of the semiconductor substrate 1 has an opening diameter of about 5 μm to 200 μm and a hole depth of about 10 μm to 400 μm.

  The through hole 4 has a large diameter portion 4a as a first opening formed in the semiconductor substrate 1, and a second hole that reaches the first wiring layer 3 through the first insulating layer 2 from the bottom of the large diameter portion 4a. The small-diameter portion 4b is provided as an opening. The non-opening portion of the first insulating layer 2, specifically, the surface of the first insulating layer 2 located between the inner periphery of the large diameter portion 4 a and the small diameter portion 4 b has a width of about 2 to 10 μm and a depth of several μm. The following recesses 6 are formed. Reference numeral 7 denotes a second insulating layer. Reference numeral 8 denotes a protective film, and 9 denotes a conductive member used for connecting the circuit element of the semiconductor package to an external circuit. A circuit element is constructed inside or on the surface of the semiconductor substrate 1.

This penetration electrode is produced by the penetration electrode formation process shown in FIGS.
In FIG. 2A, a photoresist 10 is applied to the semiconductor substrate 1 by spin coating, and openings 11 and 12 are formed by photolithography. The planar shape of the openings 11 and 12 is shown in FIG. The diameter D1 of the opening 11 is about 3 μm to 200 μm, the width D2 of the opening 12 is about 0.5 μm to 10 μm, and D1 is preferably sufficiently larger than D2.

In FIG. 2C, the semiconductor substrate 2 is dry etched using the photoresist 10 as a mask to form a first through hole 13 having a diameter D1 and a ring-shaped second through hole 14 having a width D2. As an etching gas, SF ₆ gas (50 to 500 sccm) is mixed with O ₂ gas of the same degree or less to reduce the partial pressure to SF ₆ , thereby suppressing generation of F radicals acting on semiconductor substrate etching. A highly ionic plasma was generated. Furthermore, by setting the pressure to a high vacuum of 1 to 15 Pa and applying a substrate bias of about 20 to 200 W, the ions can be drawn into the semiconductor substrate, so that the second through hole 14 having a small opening width is formed. can do. At this time, since D1 is sufficiently larger than D2, the formation speed of the first through holes 13 and 14 is such that the amount of ions and radicals drawn into the first through holes 13 of the semiconductor substrate 1 is the first through holes. 13 is higher than the second through hole 14, and the first through hole 13 has a higher etching rate than the second through hole 14. Therefore, the first through hole 13 reaches the first wiring layer 3 first.

  In FIG. 2 (d), etching continues after the first through hole 13 reaches the first insulating layer 2, and when the second through hole 14 reaches the first insulating layer 2, The bottom is over-etched, and the first insulating layer 2 at the bottom of the first through hole 13 is slightly etched.

When the semiconductor substrate 1 remains on the first insulating layer 2 at the bottom of the second through hole 14, current leakage occurs. Therefore, in FIG. 3A, the semiconductor substrate 1 existing at the bottom of the second through-hole 14 is removed as much as possible by overetching more sufficiently. The overetching time at that time is controlled to form the recess 6 on the surface of the first insulating layer 2 at the bottom of the second through hole 14.

  As shown in FIG. 4, the hole diameter D41 of the other surface 1b of the semiconductor substrate 1 of the large diameter portion 4a is preferably larger than the hole diameter D42 of the bottom portion of the recess 6. This also applies to each of the following embodiments. The reason is to improve the coverage when forming an insulating film or a metal film in a later process.

In FIG. 3B, the first insulating layer 2 is etched using the remaining photoresist 10 as a mask to form a small-diameter portion 4b reaching the first wiring layer 6 in the first insulating layer 2 to form the first wiring layer. 3 is exposed to the bottom of the first through hole 13 through the small diameter portion 1b. This is to ensure sufficient conduction between the first wiring layer 3 and the second wiring layer 5 (see FIG. 5C) formed in a later process when the through electrode is finally formed. . When the insulating layer material is SiO ₂ , a mixed gas such as CHF ₃ gas, CF ₄ gas, C ₄ F ₈ gas, Ar gas or the like is used as the etching gas. When the first insulating layer 2 is etched, the first insulating layer 2 at the bottom of the first through hole 13 having a wide opening diameter is formed in the second through hole 14 as in the etching of the semiconductor substrate described with reference to FIG. The etching rate is faster than that of the first insulating layer 2 at the bottom. Therefore, the bottom of the first through hole 13 reaches the first wiring layer 3 first. Further, the depth of the recess 6 is slightly deepened.

As a processing method for forming the small diameter portion 4b in the first insulating layer 2, a wet etching method using hydrofluoric acid or the like may be used in addition to the dry etching method.
Although not shown in the drawings, the method for removing the photoresist 10 after etching the first insulating layer 2 has been described as a method for producing the small-diameter portion 4b. The first insulating layer 2 at the bottom of the first through hole 13 may be etched. In that case, the side wall portion of the first through hole 13 (the semiconductor substrate 1 existing between the first through hole 13 and the second through hole 14) and the semiconductor substrate 2 outside the second through hole 14 are used as masks. 1 The insulating layer 2 is dry-etched again to form the small diameter portion 4b. Further, although the description has been given of using the photoresist 10 as a mask for etching processing, a hard mask such as SiO ₂ or SiN or a metal mask such as Al or Ni may be used as a mask material.

In FIG. 3C, the photoresist 10 is removed by ashing or an organic solvent.
Next, as shown in FIG. 3 (d), the sidewall portion of the first through hole 13 is removed by an isotropic dry etching method to form the large diameter portion 4a. At this time, SF ₆ gas or the like was used as an etching gas. 2 (c) to 2 (d) and FIG. 3 (a), in order to process in the thickness direction of the semiconductor substrate 1, a highly ionic plasma is generated and anisotropic etching is performed. Yes. However, in this step, processing is mainly performed in the plane direction rather than in the thickness direction of the semiconductor substrate 1, so that the pressure is 20 to 50 Pa, and the substrate bias is hardly applied to generate plasma with high radicality, so that it is isotropic. Etching is performed. Of course, since the surface of the semiconductor substrate 1 is also etched, the thickness of the semiconductor substrate 1 is reduced. The side wall portion of the second through hole 14 is naturally etched, but since D1 is larger than D2, ions to the second through hole 14 are the same as in anisotropic dry etching when forming the through hole 1. Since the amount of radical inflow is much smaller than that of the first through hole 13, the etching amount of the side wall portion of the second through hole 14 is small, and the side wall of the first through hole 13 is mainly etched.

The method for removing the side wall portion of the first through-hole 13 may be a wet etching method using KOH, NaOH, NH ₄ OH, or a mixed acid of hydrofluoric acid and nitric acid, in addition to the dry etching method.
Next, as shown in FIG. 5A, the second insulating layer 7 is formed by the CVD method from the other surface 1b of the semiconductor substrate 2 to the inner wall of the large diameter portion 4a and the inside of the concave portion 6 and the small diameter portion 4b. Form. As the insulating film material, Si oxide such as SiN, SiO ₂ , BPSG, and thermal oxide film, metal oxide such as Al ₂ O ₃ , or carbon-based polymer such as polyimide resin may be used. The second insulating layer 7 is a single layer, but may be a multilayer film having two or more layers. As an insulating film forming method, it may be formed by sputtering, thermal oxidation, or sol-gel method.

In FIG. 5B, the film of the second insulating layer 7 formed on the bottom of the recess 6 and on the first insulating layer 2 at the bottom of the large diameter portion 4a and on the bottom of the small diameter portion 4b is dry-etched. Remove by law.
In this case as well, since anisotropic dry etching is used as in the formation of the large-diameter portion 4a, only the upper surface of the second insulating layer 7 inside the large-diameter portion 1a (on the one surface 1a side of the semiconductor substrate 1). The second insulating layer 7 etched and formed on the side walls of the large-diameter portion 4a, the concave portion 6, and the small-diameter portion 4b remains because it is hardly etched.

  In FIG. 5C, the second wiring layer 5 is formed on the second insulating layer 7 on the other surface 1b of the semiconductor substrate 1 and on the second insulating layer 7 on the inner periphery of the large diameter portion 4a. On the second insulating layer 7 on the inner periphery of the recess 6, on the first insulating layer 2 on the bottom of the recess 6, and on the second insulating layer 7 and the first insulating layer 2 on the bottom of the large diameter portion 4a Then, a through electrode reaching the first wiring layer 3 from the other surface 1b side of the semiconductor substrate 2 is formed by sputtering or plating.

  In FIG. 5D, the second wiring layer 5 is patterned, and the insulator 15 is filled into the through hole 4. In order to protect the second wiring layer 5, a protective film 8 is formed on the second wiring layer 5. Thereafter, the protective layer is also patterned to expose a part of the second wiring layer 5, and a conductive member 9 such as a solder ball for electrically connecting to the external circuit is formed in the part, and the state shown in FIG. Become.

  The formation method of the second wiring layer 5 may be a printing method, an inkjet coating method, or the like in addition to a sputtering method or a plating method. In that case, the seed layer may be omitted. The material of the second wiring layer 5 is a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, or Ni, a metal compound such as TiN, or a conductive material containing them, or a Si-based material such as polysilicon. It may be a material. The wiring layer may be a single layer or a multilayer film of two or more layers. Further, a low melting point metal made of tin, an alloy containing tin, indium, or an alloy containing indium may be used.

  A diffusion prevention film (not shown) made of titanium, titanium tungsten, titanium nitride, or tantalum nitride may be formed or formed between the seed layer such as copper and the first insulating layer 2. It does not have to be.

Moreover, although the cross-sectional shape of the 1st through-hole 13 and the 2nd through-hole 14 was a perfect circle, polygons, such as an ellipse and a rectangle, may be sufficient.
According to this configuration, in the through hole 4 formed in the semiconductor substrate 1, the first insulating layer 2 includes the small diameter portion 4b having an area smaller than the area of the bottom of the large diameter portion 4a, and the inner periphery of the large diameter portion 4a. Since the recess 6 is formed on the surface of the first insulating layer 2 located between the small diameter portions 1b, the insulation between the semiconductor substrate 1 and the first wiring layer 3 is improved. Furthermore, the adhesion between the second wiring layer 5 and the first insulating layer 2 is improved, and the reliability of the through electrode and the semiconductor package provided with the through electrode can be improved.

In Embodiment 1, the insulator 15 completely fills the inside of the through hole 4, but it may or may not fill only a part of the inside of the through hole 4.
Furthermore, although the insulator 15 and the protective film 8 are separate, the same material may be used to simultaneously fill the insulator and form the protective layer.

(Embodiment 2)
6, 7 (a), 7 (b), 8 (a) and 8 (b) show a second embodiment of the present invention.
In FIG. 3D of the first embodiment, the single small-diameter portion 4b whose cross-sectional shape is a perfect circle is formed in the semiconductor substrate 1, whereas FIGS. 6A, 6B, 7A, and 7B. In this example, only the difference in the shape of the small diameter portion is different from the first embodiment.

FIG. 6 shows a semiconductor substrate having through electrodes.
FIG. 7A shows a cross-sectional view of the stage where the through hole 4 is formed in the process of forming the through electrode of FIG. 6 in the semiconductor substrate 2, and FIG. 7B shows from the other surface 1 b of the semiconductor substrate 1. The state which looked at the bottom part of the through-hole 4 is shown.

In this embodiment, the through hole 4 is composed of a large diameter portion 4a and two small diameter portions 4b1 and 4b2. The small diameter portions 4b1 and 4b2 have a semicircular cross section.
In the case of the first embodiment, since the small-diameter portion 4b is one place, for example, if particles or the like are deposited on the bottom of the through-hole after forming the through-hole, the adhesion between the first wiring layer 3 and the second wiring layer 5 It is expected that the reliability of the through electrode will be lowered, for example, the wiring resistance will increase and the worst film peeling will occur.

  On the other hand, in the second embodiment, by configuring with two small diameter portions 4b1 and 4b2, even if the above-described problem occurs in one small diameter portion, a conduction path is secured in the other small diameter portions. be able to. Further, since the two small diameter portions 4b1 and 4b2 are formed, the uneven shape of the bottom portion of the through hole 4 becomes more complicated as compared with the case where there is one small diameter portion, so that the first insulating layer 2 and the second wiring layer 5 are formed. Adhesion with is improved. Further, since a plurality of conduction paths between the first wiring layer 3 and the second wiring layer 5 can be ensured, the reliability of the through electrode formed thereafter and the semiconductor package provided with the through electrode can be improved.

FIGS. 8A and 8B show another example.
7A and 7B, the number of the small diameter portions is two and the shape thereof is a semicircular shape. However, in this example, the shape is configured by circular small diameter portions 4b1, 4b2, 4b3, and 4b4. The only difference is that

In the second embodiment, the cross-sectional shape of the plurality of small diameter portions may be a polygon such as an ellipse or a quadrangle. Further, it may be a polygon such as a quadrangle instead of an arc.
(Embodiment 3)
FIG. 9 shows a third embodiment of the present invention.

  In the first embodiment, the insulator 15 is partially or wholly filled inside the through hole 4. However, in this embodiment, a conductive material 16 such as plating is buried inside the through hole 4. The point that the second wiring layer 5 of the first embodiment is formed by the second wiring layer 5 and the conductive material 16 in the whole hole is greatly different. The conductive member 9 is provided on the conductive material 16 embedded inside the through hole 4.

In the third embodiment, two semiconductor substrates 1 are stacked and the upper and lower semiconductor substrates are electrically connected via the conductive material 16.
FIG. 10 shows a semiconductor package in which two semiconductor substrates 1 are built.

  In FIG. 10, the semiconductor substrate 1, 1 having the through electrode as described above is laminated by die bonding material or the like, flip-chip bonded to the substrate 17, and the connection portion is protected by the underfill material 18. A semiconductor package is formed by covering the entire mounting portion of the 17 semiconductor substrates 1 and 1 with a resin 19 and finally mounting a conductive member 20 such as a solder ball.

  Even when an impact is applied to the through electrode when a plurality of semiconductor substrates are stacked or when the stacked substrate is mounted on another circuit board, the through hole 4 has a large diameter portion 4a as a first opening, and a second opening. The second wiring layer 5 and the conductive material 16 are transferred to the first wiring layer 3 through the inner peripheral surface of the large diameter portion 4a, the concave portion 6 and the small diameter portion 4b. Since it is electrically connected, it is possible to disperse and absorb the impact at the time of stacking, so that the destruction of the first wiring layer 3 can be prevented and the reliability of the semiconductor package can be improved. In addition, when resin molds are formed or when this semiconductor package is connected to another printed circuit board by reflow or the like, it is expected that the entire package will be exposed to high temperatures and a large amount of thermal energy will be applied to the through electrode portion. The through electrode formed on the substrate 1 includes a concave portion 6 formed on the surface of the first insulating layer 2 located between the large diameter portion 4a, the small diameter portion 4b, the large diameter portion 4a, and the small diameter portion 4b. Therefore, since the thermal expansion of the first insulating layer 2 and the second wiring layer 5 due to heat can be suppressed, the reliability of the semiconductor package can be improved.

Here, the case of a semiconductor package in which two semiconductor substrates 1 are laminated has been described, but the same applies to the case where a single or a plurality of semiconductor substrates 1 are laid flat on a substrate 17 and resin packaged.
Here, the semiconductor package in which the semiconductor substrate having the through electrode shown in FIG. 9 is stacked and resin packaged is described as an example. However, the semiconductor having the through electrode shown in the first embodiment or the second embodiment is described. The same applies to the case where a single or a plurality of substrates are laid flat or laminated on the substrate 17 and resin packaged.

  In addition, the material of the semiconductor substrate in each of the above embodiments is a silicon semiconductor such as silicon or silica gel, or a compound semiconductor such as gallium arsenide, gallium nitride, or indium phosphide.

  INDUSTRIAL APPLICABILITY The present invention is useful for miniaturization of semiconductor devices using through electrodes and multi-stage chip stacking technology, and can contribute to improving the reliability of various integrated circuits.

Sectional drawing of the semiconductor substrate in which the penetration electrode of Embodiment 1 of the present invention was formed Sectional view and plan view of the manufacturing process of the embodiment Sectional view of the manufacturing process of the embodiment Sectional drawing of the principal part of the manufacturing process of the embodiment Sectional view of the manufacturing process of the embodiment Sectional drawing of the semiconductor substrate in which the penetration electrode of Embodiment 2 of this invention was formed Sectional view and plan view of the manufacturing process of the embodiment Sectional view and plan view of another manufacturing process of the embodiment Sectional drawing of the semiconductor substrate in which the penetration electrode of Embodiment 3 of this invention was formed Sectional drawing of the semiconductor package which laminated and packaged the semiconductor substrate of FIG. Cross-sectional view of a semiconductor package in which a semiconductor substrate having a through electrode is packaged Process drawing of forming through electrode of Patent Document 1 Process drawing of forming through electrode of Patent Document 2

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a One surface of the semiconductor substrate 1 1b The other surface of the semiconductor substrate 1 2 1st insulating layer 3 1st wiring layer 4 Through-hole 4a Large diameter part (1st opening part)
4b Small diameter part (second opening)
4b1, 4b2, 4b3, 4b4 Small diameter portion 5 Second wiring layer 6 Recess 7 Second insulating layer 8 Protective film 9 Conductive member 10 Photoresist 11, 12 Opening portion 13 First through hole 14 Second through hole 15 Insulator 16 Conductive Material 17 Substrate D1 Diameter D2 of opening 11 Width of opening 12

Claims (11)

A semiconductor substrate having a through electrode in which a first wiring layer is formed on one surface of a semiconductor substrate via a first insulating layer, and a second wiring layer is formed on the inner periphery of a through hole penetrating the semiconductor substrate. ,
The through hole is
A first opening formed from the other surface of the semiconductor substrate toward the first insulating layer;
A second opening having a smaller opening area than the first opening and reaching the first wiring layer from the bottom of the first opening through the first insulating layer;
A recess formed in the surface of the first insulating layer located between the inner periphery of the first opening and the second opening;
A side wall formed by the first insulating layer existing between the recess and the second opening;
And the second wiring layer passes through the side wall portion and the second opening portion formed by the inner peripheral surface of the first opening portion, the concave portion, and the first insulating layer , and the first wiring layer. A semiconductor substrate that is electrically connected to the substrate. A second insulating layer is formed from the peripheral surface of the recess to the peripheral surface of the first opening of the through hole,
The semiconductor substrate according to claim 1, wherein the second insulating layer is interposed between the second wiring layer and the semiconductor substrate. The material of the second wiring layer is a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, or a conductive material containing them, Si-based material such as polysilicon 3. The semiconductor substrate according to claim 2, wherein the second wiring layer is a single layer or a multilayer film of two or more layers. The material of the second insulating layer is a Si compound such as SiN, SiO ₂ , BPSG, or a thermal oxide film, a metal compound such as Al ₂ O ₃ , or an organic compound such as polyimide resin. 3. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is a multi-layer film having two or more layers. A protective film formed on the second wiring layer so as to expose a part of the surface thereof;
The semiconductor substrate according to claim 1, further comprising a conductive member electrically connected to an external circuit on the second wiring layer.   The semiconductor substrate according to claim 1, wherein an insulating material is filled in a part or the whole of the gap formed inside the through hole. 2. The semiconductor substrate according to claim 1, wherein the hole diameter of the other surface 1 b of the semiconductor substrate 1 in the first opening is larger than the hole diameter of the bottom of the recess. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a silicon-based semiconductor such as silicon or silica gel-manium, or a compound semiconductor such as gallium arsenide, gallium nitride, or indium phosphide. The semiconductor substrate according to claim 1, wherein a plurality of the second openings are formed in the first insulating layer. A first wiring layer is formed on one surface of the semiconductor substrate via a first insulating layer, and a second wiring layer is formed on the inner periphery of a through hole penetrating the semiconductor substrate from the one surface to the other surface. When creating a semiconductor substrate having a through electrode,
Simultaneously forming a first through hole and a second through hole surrounding the first through hole from the other surface of the semiconductor substrate to the first wiring layer through a mask;
Etching the semiconductor substrate until the first through-hole reaches the first insulating layer and etching the second through-hole until a recess is formed in the first insulating layer. A second opening having a smaller opening area than the first opening; a recess on the surface of the first insulating layer located between the inner periphery of the first opening and the second opening; the recess; A side wall portion formed by the first insulating layer existing between the second opening portion and the side wall portion configured by an inner peripheral surface of the first opening portion, the concave portion, and the first insulating layer. And the manufacturing method of the semiconductor substrate which forms a 2nd wiring layer in the said 1st wiring layer through the said 2nd opening part, and is electrically connected. A semiconductor package incorporating the semiconductor substrate according to claim 1.

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