JP5213394B2 - Image transfer device - Google Patents

Description

  The present invention relates to an image transfer apparatus that performs BITBLT processing of two-dimensional image data.

In two-dimensional graphics rendering processing, BITBLT (Bit Block Transfer) that transfers a rectangular area of an image on a memory to another area is a frequently used function. In some cases, processing such as blend processing or logical operation is performed between transfer source data and transfer destination data at the time of transfer, or an image is synthesized by referring to an image in another area.
When performing BITBLT processing, it is necessary to read image data to be referenced from the memory, perform arithmetic processing, and write to the memory. Conventionally, it has been implemented by software processing by a CPU. However, a method implemented by hardware has been proposed in order to perform processing at high speed (see, for example, Patent Document 1 or Patent Document 2).
In addition, when multiple images with different bits per pixel are read from the memory and combined, a temporary storage memory is provided to temporarily store each image, read from the memory by burst transfer, and stored in the temporary storage memory. A method of synthesizing has also been proposed (see, for example, Patent Document 3).

JP-A-6-004659 JP 2005-190002 A JP 2000-172242 A

In a unified memory architecture used in an embedded system or the like, the main memory used by the CPU and the video memory for drawing are the same memory, so that the transfer source area and the transfer destination area during the BITBLT processing are in the same memory. Will exist. As the memory, SDRAM or DDR-SDRAM is often used.
In this case, for example, in BITBLT processing by a conventional apparatus as shown in Patent Document 1, reading and writing to the memory are repeated for each pixel. For this reason, when the addresses in the transfer source memory and the transfer destination memory are separated from each other, there is a problem that an overhead such as precharge for the memory may occur for each read or write access, resulting in poor efficiency. Further, for example, in the BITBLT process as shown in Patent Document 2, a memory for storing a reference image and a memory for writing are separated, and the BITBLT process in the same memory is not considered. There is a problem that it cannot be applied to BITBLT processing in the same memory.

  Furthermore, for example, the processing by the conventional apparatus as shown in Patent Document 3 assumes that the screen is output to the display device, and the image is written back to the memory or a partial area of the image is stored. Transfer is not considered. Further, in the case of an image with a small number of bits per pixel, there is a problem that the capacity of the temporary storage memory is not effectively used in order to reduce the amount of data read at a time.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an image transfer apparatus that can efficiently access a memory and perform BITBLT processing at high speed.

An image transfer apparatus according to the present invention is provided for each image data to be processed, calculates an address in a memory of image data to be referenced, and reads a plurality of image read units, and a plurality of image read units A plurality of image read units and a control unit for controlling a read request or a write request from the calculation unit. Each read unit has a buffer for temporarily storing the read image data. The read unit reads the reference image data until the buffer is full, and then outputs until the buffer is empty. outputs EMPTY signal indicating whether or not the control unit, EMPTY signal output from the current process and the plurality of images leads and Based, as the next process, to determine the data write from the data read or the arithmetic unit of any of the image read unit in a plurality of image read unit, a memory data write from the data read or computing unit of the plurality of images leads Are controlled so as to be performed continuously.

The image transfer apparatus according to the present invention includes a plurality of image read units that read out the image data for each image data to be processed, and a buffer that temporarily stores the image data read out by these image read units. Read until full, then output until empty, and based on current processing and EMPTY signals from multiple image read units, read data from one of the image read units or data from the arithmetic unit determining the writing, since writing of data from the data read or computing unit of the plurality of images leads to a so that continuously performed with respect to memory, it is possible to effectively utilize the buffer capacity, small buffers This contributes to increasing the capacity, enabling efficient access to the memory, and performing BITBLT processing at high speed.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an image transfer apparatus according to Embodiment 1 of the present invention. Prior to this description, BITBLT processing in the image transfer apparatus of Embodiment 1 will be described.
FIG. 2 is an explanatory diagram of processing contents of the image transfer apparatus according to the first embodiment.
Assume that the illustrated frame buffer 100A, frame buffer 100B, and frame buffer 100C are allocated in the same memory. As an example, it is assumed that the frame buffer 100A and the frame buffer 100C have 32 bits per pixel, and the frame buffer 100B has 16 bits per pixel. As an embodiment, the image transfer apparatus combines the image A in the frame buffer 100A and the image B in the frame buffer 100B under such conditions and transfers them to the area of the image C in the frame buffer 100C while performing blend processing. explain.

Hereinafter, the configuration of the image transfer apparatus according to the first embodiment will be described with reference to FIG.
As illustrated, the image transfer apparatus 10 includes a first image read unit 11, a second image read unit 12, a third image read unit 13, a calculation unit 14, a control unit 15, and a bus IF unit 16. Yes. The image transfer apparatus 10 is connected to the CPU 30 and the memory IF 40 via the bus 20, and the memory 50 is connected to the memory 50. In the figure, broken line arrows indicate control signals, and solid line arrows indicate the flow of data signals.

  The first image read unit 11 is a read unit that reads data of the image A described with reference to FIG. Similarly, the second image read unit 12 is an image read unit that reads out image B data, and the third image read unit 13 is an image read unit that reads out image C data. These image read units 11 to 13 include buffers 11a, 12a, and 13a, respectively, and are configured to temporarily hold images A, B, and C in the buffers 11a, 12a, and 13a.

  The calculation unit 14 performs calculation processing such as synthesis on the data output from the first image read unit 11, the second image read unit 12, and the third image read unit 13. This is a functional unit that outputs to the bus IF unit 16. The control unit 15 is a control unit that controls all of the control in the image transfer apparatus 10, and based on parameters set by the CPU 30, read requests from the first image read unit 11 to the third image read unit 13 and It is determined which process is to be executed among the write requests from the calculation unit 14. The bus IF unit 16 selects one of the read requests from the first image read unit 11 to the third image read unit 13 and the write request from the calculation unit 14 in accordance with an instruction from the control unit 15. And a bus interface for outputting to the bus 20.

The bus 20 is a bus for transferring data between the image transfer apparatus 10 and the memory 50 and transferring control data between the CPU 30 and the image transfer apparatus 10. The CPU 30 is a processor that makes various settings and instructions in the BITBLT process to the image transfer apparatus 10. The memory IF 40 is a memory interface that actually accesses the memory 50. The memory 50 is an external memory that holds image data and is provided with the frame buffers 100A, 100B, and 100C shown in FIG.
Further, as a premise of the present embodiment, the memory IF 40 can perform processing without overhead such as precharge if the row address is the same when performing continuous reading or writing processing on the memory 50. It shall be comprised as follows.

Next, the operation of the first embodiment will be described.
First, at the time of BITBLT processing, the CPU 30 sets necessary parameters such as the size of the image and the contents of calculation processing to the image transfer apparatus 10. Then, when the CPU 30 instructs the image transfer apparatus 10 to start, the image transfer apparatus 10 starts operating.

Hereinafter, the operation of the image transfer apparatus 10 will be described with reference to FIG.
FIG. 3 is a timing chart for explaining the operation of the image transfer apparatus 10.
From the first image lead unit 11 to the control unit 15, a busy signal BUSY1 indicating whether or not the first image lead unit 11 is in operation, the buffer 11a is full, or an image A to be referred to A pulse signal FULL1 for informing that all the data has been read and a signal EMPTY1 indicating whether or not the buffer 11a is empty are output.
Similarly, a busy signal BUSY2 indicating whether or not the second image lead unit 12 is operating, the buffer 12a is full, or the reference is sent from the second image lead unit 12 to the control unit 15. A pulse signal FULL2 for indicating that all the data of the image B to be read has been read and a signal EMPTY2 indicating whether or not the buffer 12a is empty are output.
Similarly, the busy signal BUSY3 indicating whether or not the third image read unit 13 is operating, the buffer 13a is full, or the reference is sent from the third image read unit 13 to the control unit 15. A pulse signal FULL3 for indicating that all data of the image C to be read has been read and a signal EMPTY3 indicating whether or not the buffer 13a is empty are output.

Further, a busy signal BUSY4 indicating whether or not the calculation unit 14 is operating is output from the calculation unit 14 to the control unit 15.
In the initial state, the busy signals BUSY1, BUSY2, BUSY3, and BUSY4 are all “0”, indicating that no operation is in progress. EMPTY1, EMPTY2, and EMPTY3 are all “1”, indicating that the buffer 11a, buffer 12a, and buffer 13a are empty (FIG. 3, T1).

When the image transfer apparatus 1 receives an activation instruction from the CPU 30, the first image read unit 11 starts its operation and sets the busy signal BUSY1 to “1”. Then, from the set parameters (the base address of the frame buffer 100A, the size of the frame buffer 100A, the number of bits per pixel of the frame buffer 100A, the coordinates of the image A, the transfer size, etc.) in the memory 50 of the image A to be referred to The first address is calculated, and the bus IF unit 16 is requested to read the data of the image A.
At the same time, the second image lead unit 12 also starts to operate, and sets the busy signal BUSY2 to “1”. Then, from the set parameters (the base address of the frame buffer B, the size of the frame buffer 100B, the number of bits per pixel of the frame buffer 100B, the coordinates of the image B, the transfer size, etc.) in the memory 50 of the image B to be referred to The first address is calculated, and the bus IF unit 16 is requested to read image B data.
Similarly, the third image read unit 13 also starts to operate, and sets the busy signal BUSY3 to “1”. Then, from the set parameters (the base address of the frame buffer 100C, the size of the frame buffer 100C, the number of bits per pixel of the frame buffer 100C, the coordinates of the image C, the transfer size, etc.) in the memory 50 of the image C to be referenced. The first address is calculated, and the bus IF unit 16 is requested to read image C data.

When the image transfer apparatus 1 receives an activation instruction from the CPU 30, the control unit 15 first instructs the bus IF unit 16 to read the image A. The bus IF unit 16 selects a read request from the first image read unit 11 in accordance with an instruction from the control unit 15 and outputs it to the bus 20. When data read from the memory 50 is received via the memory IF 40, the data is returned to the first image reading unit 11. The first image read unit 11 stores the data received from the bus IF unit 16 in the buffer 11a, and sets a signal EMPTY1 indicating whether or not the buffer 11a is empty to “0”.
When the read request is received by the bus IF unit 16, the first image read unit 11 continuously requests the next data read. Since the bus IF unit 16 is instructed to read the image A from the control unit 15, the bus IF unit 16 subsequently selects a read request from the first image read unit 11 and outputs it to the bus 20. In this way, the image A data is continuously read out, and the image A data is sequentially stored in the buffer 11a (FIG. 3, T2).
During this period, the second image read unit 12 and the third image read unit 13 are in a paused state with the read request being issued because the read request for the image B and the image C is not accepted by the bus IF unit 16. Become.

Eventually, when the buffer 11a of the first image read unit 11 becomes full, the first image read unit 11 outputs a pulse signal FULL1 to the control unit 15 and stops reading data. Then, the data of the image A stored in the buffer 11 a is output to the calculation unit 14.
Even if the data of the image A is output from the first image lead unit 11, the arithmetic unit 14 receives the data of the images B and C from the second image lead unit 12 and the third image lead unit 13 at this time. Since it has not been output, the image A data from the first image lead unit 11 is not received. The first image read unit 11 is in a pause state while outputting the image A data to the calculation unit 14.

  When the pulse signal FULL1 is input from the first image reading unit 11, the control unit 15 determines that a series of reading processing of the image A has been completed, and determines which processing is to be executed next. FIG. 4 shows a determination method in the control unit 15. In this case, since the current process is the reading of the image A and EMPTY2 is “1”, the bus IF unit 16 is instructed to read the image B next.

The bus IF unit 16 selects a read request output from the second image read unit 12 according to an instruction from the control unit 15 and outputs the request to the bus 20. When data read from the memory 50 is received via the memory IF 40, the data is returned to the second image reading unit 12. The second image read unit 12 stores the data received from the bus IF unit 16 in the buffer 12a, and sets a signal EMPTY2 indicating whether or not the buffer 12a is empty to “0”.
When the read request is accepted by the bus IF unit 16, the second image read unit 12 requests the next data to be read continuously. Since the bus IF unit 16 is instructed to read the image B from the control unit 15, the bus IF unit 16 subsequently selects a read request from the second image read unit 12 and outputs it to the bus 20. In this way, the image B data is continuously read, and the image B data is sequentially stored in the buffer 12a (T3 in FIG. 3).

Eventually, when the buffer 12a becomes full, the second image read unit 12 outputs a pulse signal FULL2 to the control unit 15 and stops reading data. Then, the data of the image B stored in the buffer 12a is output to the calculation unit 14.
Even if the image B data is output from the second image read unit 12 in the calculation unit 14, the image C data is not output from the third image read unit 13 at this time. The image B data from the lead unit 12 is not received. The second image read unit 12 is in a pause state while outputting the image B data to the calculation unit 14.

  When the pulse signal FULL2 is input from the second image reading unit 12, the control unit 15 determines that a series of reading processing of the image B has been completed, and determines which processing is to be executed next. In this case, since the current process is the reading of the image B and EMPTY1 is “0” and EMPTY3 is “1”, the bus IF unit 16 is instructed to read the image C next.

The bus IF unit 16 selects a read request output from the third image read unit 13 in accordance with an instruction from the control unit 15 and outputs the request to the bus 20. When data read from the memory 50 is received via the memory IF 40, the data is returned to the third image reading unit 13. The third image read unit 13 stores the data received from the bus IF unit 16 in the buffer 13a, and sets a signal EMPTY3 indicating whether or not the buffer 13a is empty to “0”.
When the read request is accepted by the bus IF unit 16, the third image read unit 13 requests the next data to be read continuously. Since the bus IF unit 16 is instructed to read the image C from the control unit 15, the bus IF unit 16 subsequently selects a read request from the third image read unit 13 and outputs it to the bus 20. In this way, the data of the image C is continuously read out, and the data of the image C is sequentially stored in the buffer 13a (T4 in FIG. 3).
Eventually, when the buffer 13a of the third image read unit 13 becomes full, the third image read unit 13 outputs a pulse signal FULL3 to the control unit 15 and stops reading data. Then, the data of the image C stored in the buffer 13 a is output to the calculation unit 14.

  When the pulse signal FULL 3 is input from the third image reading unit 13, the control unit 15 determines that a series of reading processing of the image C has been completed, and determines which processing is to be executed next. In this case, since the current process is the reading of the image C and EMPTY1 is “0” and EMPTY2 is “0”, the bus IF unit 16 is instructed to write the image C next.

When the data is input from all of the first image read unit 11, the second image read unit 12, and the third image read unit 13, the calculation unit 14 receives the data and starts the operation, and the busy signal BUSY4 Is set to “1”.
The calculation unit 14 performs calculation processing such as composition and blending on the image data according to the set parameters, and outputs a write request to the bus IF unit 16 in order to write the result back to the address of the image C.
The bus IF unit 16 selects the write request output from the calculation unit 14 in accordance with an instruction from the control unit 15 and outputs it to the bus 20. Then, data is written to the memory 50 via the memory IF 40.

When the first image read unit 11, the second image read unit 12, and the third image read unit 13 receive data in the calculation unit 14, the images stored in the buffer 11a, the buffer 12a, and the buffer 13a Data is sequentially output to the calculation unit 14.
The arithmetic unit 14 receives data, performs arithmetic processing, performs processing to output to the bus IF unit 16 by pipeline processing, and continuously outputs write requests to the bus IF unit 16. Since the bus IF unit 16 is instructed to write the image C from the control unit 15, the bus IF unit 16 subsequently selects the write request from the calculation unit 14 and outputs it to the bus 20. In this way, data is continuously written into the image C area (T5 in FIG. 3).

When any of the buffer 11a, the buffer 12a, and the buffer 13a eventually becomes empty, input data to the calculation unit 14 is not prepared, and the calculation unit 14 stops receiving data. The busy signal BUSY4 is set to "0" when all the data received so far is output to the bus IF unit 16.
In this example, since it is assumed that the number of bits per pixel of the image A and the image C is twice that of the image B, the buffer 11a and the buffer 13a are emptied, and half of the data is stored in the buffer 12a. Will remain.

When the buffer 11a becomes empty, the first image read unit 11 sets the signal EMPTY1 indicating whether or not the buffer 11a is empty to “1”, calculates the continuation address of the image A, and calculates the bus IF A read request is output to the unit 16.
Similarly, when the buffer 13a becomes empty, the third image read unit 13 sets the signal EMPTY3 indicating whether or not the buffer 13a is empty to “1”, and calculates the continuation address of the image C. The read request is output to the bus IF unit 16.

  When the busy signal BUSY4 from the calculation unit 14 changes from “1” to “0”, the control unit 15 determines that the series of writing processing of the image C has been completed, and determines which processing is to be executed next. . In this case, since the current process is the writing of the image C and EMPTY1 is “1”, the bus IF unit 16 is instructed to read the image A next. Thereby, the reading process of the image A is continuously performed until the buffer 11a becomes full. (Fig. 3, T6)

  As described above, when reading an image, read continuously until the buffer is full, and when data is complete, write back while continuously calculating until one of the buffers is empty. repeat.

Eventually, when the first image read unit 11 reads the final data of the image A to be referred to, the first image read unit 11 outputs the pulse signal FULL1 to the control unit 15 even if the buffer 11a is not full, and the calculation unit 14 Output the data. The busy signal BUSY1 is set to “0” when all the data has been output to the arithmetic unit 14.
Similarly, when the second image read unit 12 reads the final data of the image B to be referred to, the second image read unit 12 outputs the pulse signal FULL2 to the control unit 15 even if the buffer 12a is not full, and outputs it to the calculation unit 14. In response, data is output. The busy signal BUSY2 is set to “0” when all the data has been output to the arithmetic unit 14.
Similarly, when the third image read unit 13 reads the final data of the image C to be referred to, the third image read unit 13 outputs the pulse signal FULL3 to the control unit 15 even if the buffer 13a is not full, and outputs it to the calculation unit 14. In response, data is output. The busy signal BUSY3 is set to “0” when all the data has been output to the arithmetic unit 14.

  When all the data received by the arithmetic unit 14 is output to the bus IF unit 16 and the busy signal 4 changes from “1” to “0”, if BUSY1, BUSY2, and BUSY3 are all “0”, the image transfer apparatus The operation of 10 ends (FIG. 3, T7).

  As described above, when the image is read, it is continuously read until the buffer is full, and when data is ready, it is written back while continuously performing arithmetic processing until any buffer becomes empty. Thus, reading or writing is continuously performed on the memory 50, overhead during memory access can be reduced, and processing can be performed at high speed.

  In the above embodiment, the number of image lead portions is three, but the number is not limited to three. For example, when realizing a function of combining with reference to another image D, the number of image lead units may be four and the same control may be performed.

  As described above, according to the image transfer apparatus of the first embodiment, in the image transfer apparatus that performs BITBLT processing of image data in the same memory, a memory of image data to be referred to is provided for each image data to be processed. A plurality of image read units for calculating the addresses in the image data, reading the image data, a calculation unit for performing arithmetic processing on the image data read by the plurality of image read units and writing back to the memory, and a plurality of image reads And a control unit that controls a read request or a write request from the calculation unit and the calculation unit, the memory can be accessed efficiently, and the BITBLT process can be performed at high speed.

  Further, according to the image transfer apparatus of the first embodiment, each of the plurality of image reading units includes a buffer that temporarily stores the read image data, reads the image data to be referenced until the buffer is full, and then Since the output is performed until the buffer becomes empty, the buffer capacity can be used effectively, and the buffer capacity can be reduced.

  Further, according to the image transfer apparatus of the first embodiment, the control unit controls the data reading of the plurality of image reading units or the data writing from the calculation unit to be continuously performed on the memory. Therefore, BITBLT processing of image data within the same memory can be performed efficiently, and BITBLT processing can be performed at high speed.

1 is a configuration diagram illustrating an image transfer apparatus according to a first embodiment of the present invention. It is explanatory drawing of the BITBLT process of the image transfer apparatus by Embodiment 1 of this invention. It is a timing diagram which shows operation | movement of the image transfer apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the judgment method in the control part of the image transfer apparatus by Embodiment 1 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Image transfer apparatus, 11 1st image read part, 11a, 12a, 13a buffer, 12 2nd image read part, 13 3rd image read part, 14 calculating part, 15 control part, 16 bus IF part, 20 Bus, 30 CPU, 40 memory IF, 50 memory, 100A, 100B, 100C Frame buffer.

Claims (1)

In an image transfer apparatus that performs BITBLT processing of image data in the same memory,
A plurality of image read units that are provided for each image data to be processed, calculate an address in the memory of the image data to be referenced, and read out the image data;
An arithmetic unit for performing arithmetic processing on the image data read by the plurality of image reading units and writing back to the memory;
A control unit for controlling a read request or a write request from the plurality of image read units and the calculation unit,
Each of the plurality of image read units includes a buffer for temporarily storing the read image data, reads the reference image data until the buffer is full, and then operates to output until the buffer is empty. , Output an EMPTY signal indicating whether or not the buffer is empty ,
Based on the current process and the EMPTY signal output from the plurality of image read units , the control unit reads data from one of the image read units in the plurality of image read units or the arithmetic unit as the next process image transfer apparatus a data write to determine, data writing from the data read or the arithmetic unit of the plurality of image lead portions and controls to be performed continuously to the memory from.

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