Nothing Special   »   [go: up one dir, main page]

JP5271985B2 - 集積回路構造 - Google Patents

集積回路構造 Download PDF

Info

Publication number
JP5271985B2
JP5271985B2 JP2010211576A JP2010211576A JP5271985B2 JP 5271985 B2 JP5271985 B2 JP 5271985B2 JP 2010211576 A JP2010211576 A JP 2010211576A JP 2010211576 A JP2010211576 A JP 2010211576A JP 5271985 B2 JP5271985 B2 JP 5271985B2
Authority
JP
Japan
Prior art keywords
metal
integrated circuit
circuit structure
semiconductor substrate
tsv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010211576A
Other languages
English (en)
Other versions
JP2011071516A (ja
Inventor
明發 陳
文智 邱
曉林 ▲すい▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of JP2011071516A publication Critical patent/JP2011071516A/ja
Application granted granted Critical
Publication of JP5271985B2 publication Critical patent/JP5271985B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05025Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05546Dual damascene structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05547Structure comprising a core and a coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13007Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8136Bonding interfaces of the semiconductor or solid state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

本発明は、集積回路構造に関するものであって、特に、ウェハ背面に形成され、導電ビアであるスルーサブストレートビア(through-substrate via(TSV))に接続される相互接続に関するものである。
各種電子素子(例えば、トランジスタ、ダイオード、レジスタ、キャパシタ等)の集積密度の不断の改善により、集積回路の製造、及び、半導体工業は、急速に成長を続けている。集積密度の改善は、多くが、最小形状寸法の縮小化を重ねてきたことによるもので、与えられたチップ領域内に、より多くの素子を集積することを可能にした。
これらの集積化の改善は、二次元(two-dimensional、2D)上の進歩であり、集積素子が占める体積は、実質上、半導体ウェハの表面上である。リソグラフィの劇的な改善は、既に、二次元の集積回路形成において、大幅な改善をもたらしているが、二次元で達成できる集積密度は、物理的限界がある。これらの限界の一つは、これらの素子の製造に必要な最小寸法があること、並びに、更に多くのデバイスを一チップ内に配置する時に、更に複雑な設計が必要なことである。
もう一つの限界は、デバイス数量の増加に伴い、デバイス間の相互接続(interconnection)の長さや数量も大幅に増加することである。相互接続の長さや数量が増加する場合、回路のRC遅延、及び、電力消耗も増加する。
現在、上述の限界を解決する方法として、通常、3次元の集積回路(three-dimensional integrated circuit 、3D IC)、及び、スタックダイを用いる。3次元の集積回路とスタックダイ中に、スルーサブストレートビア(through-substrate via、TSV)を使用して、ダイを接続する。この例では、TSVを使用して、ダイ上の集積回路を、このダイの背面に接続する。また、TSVは、短い接地経路を提供して、集積回路をこのダイの背面から接地し、接地金属膜により被覆される。
TSVを備えるチップの接合は、TSV間で大きいピッチを必要とするので、TSVの位置は制限される。また、TSV間の距離は、例えば、ソルダーボールを収容するのに十分な空間を必要とする。更に、現行のウェハ背面構造の形成方法において、TSVの電気的接続を、それぞれのTSVから離すのは不可能である。
本発明は、TSVに接続されるウェハ背部の相互接続構造を提供し、上述の問題を改善することを目的とする。
本発明の第1の態様は、集積回路構造であって、正面と背面を有する半導体基板と、半導体基板を貫通する導電ビアと、半導体基板の背面上の金属構造と、を備える。金属構造は、導電ビアを被覆し、接触する金属パッド、及び、導電ビア上の金属線を含む。金属線はデュアルダマシン構造を含む。集積回路構造は、更に、金属線上のバンプを備える。
本発明の第2の態様は、集積回路構造であって、正面と背面を有する半導体基板と、半導体基板中の導電ビアとを備える。また、半導体基板の背面から半導体基板中に延伸し、導電ビアと接触する第一金属構造と、第一金属構造上で、且つ、第一金属構造に電気的に接続するバンプとを備える。
デュアルダマシンプロセスを用いて、背面相互接続構造を形成することにより、マルチ相互接続層がスタックされて、好ましいルーティング能力を有する。基板を凹陥することにより、金属パッドを形成して、TSVと接触し、金属パッドはサイズが大きく、金属パッドをTSVに照準する精度要件が緩和される。更に、金属パッドと底部TSVは、大きい接触領域を有し、接触抵抗が減少する。
第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態に係る集積回路構造の製造工程断面図。 第1実施形態の変形例に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態に係る集積回路構造の製造工程断面図。 第2実施形態の変形例に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態に係る集積回路構造の製造工程断面図。 第3実施形態の変形例に係る集積回路構造の製造工程断面図。
TSVに接続される新規の背面相互接続構造を有する集積回路構造とその形成方法について説明する。以下、本発明の製造工程の一例、及びいくつかの実施態様について説明する。以降の図や説明において、同一要素には同一の符号を用いる。
[実施形態1]
図1を参照すると、基板10と集積回路(図示しない)を含むチップ2が提供される。チップ2はウェハの一部である。基板10は半導体基板、例えば、バルクシリコン基板(bulk silicon substrate)であるが、第III族、第IV族、及び/又は、第V族素子等の別の半導体材料を含んでいてもよい。トランジスタ(ブロック15で示される)等のアクティブ半導体装置が、基板10の前側10f上に形成される。本文中、 "背面" は、基板10がアクティブ半導体装置を有する側と反対側である。金属線とバイアス(図示しない)を含む相互接続構造12が、基板10の前側10fに形成されて、アクティブ半導体装置に接続される。金属線とバイアスは、銅、或いは、銅合金により構成され、公知のダマシンプロセス(damascene processes)により形成される。相互接続構造12は、既知の層間絶縁膜(inter-layer dielectric 、ILD) と 金属間誘電体(inter-metal dielectric 、IMD)を備える。接着パッド14が基板10の前側10fに形成される。
導電ビアであるTSV20が基板10中に形成され、前側10fから基板10中に延伸する。図1で示される第1実施形態においては、TSV20は、ビアファーストアプローチ(via-first approach)にて形成され、相互接続構造12の形成前に形成される。従って、TSV20は、アクティブデバイスを被覆するのに用いられる層間絶縁膜だけに延伸するが、相互接続構造12中の金属間誘電体層には延伸しない。なお、TSV20は、ビアラストアプローチ(via-last approach)にて形成し、相互接続構造12の形成後に形成してもよい。この場合、TSV20は、基板10と相互接続構造12の両方を貫通する。絶縁層22が、TSV20の側壁と端部上に形成され、TSV20と基板10を電気的に絶縁する。絶縁層22は、窒化ケイ素、酸化ケイ素(例えば、オルトけい酸テトラエチル(tetra-ethyl-ortho-silicate 、TEOS)酸化物等の一般の誘電体材料により形成される。チップ2と対応するウェハはキャリア25に接着される。
図2を参照すると、背面研磨が実行されて、TSV20が、基板10の背面10bから露出する。TSV20を停止層として、背面研磨を実施する。その後、図3で示されるように、TSV20が凹陥し、その上表面が基板10の背面10bより低くなる。凹陥深さD1は、約0.5μmより大きく、第1実施形態では、3μmである。凹陥のプロセスにより、開口24が形成される。
図4は、基板10の凹陥プロセスを示し、そのプロセスは、フォトレジスト26をマスクとして用いて実行される。凹陥のプロセスにより、開口24の水平寸法が増加し、TSV20の水平寸法より大きくなる。図4の背面10bの開口24底部28は、TSV20の露出端と同じ高さである。別の実施形態として、底部28は、図4中の点線で示すように、TSV20の露出端より高くしたり、低くしたりしてもよい。開口24の形成と同時に、(トレンチ)開口27も形成される。
図5を参照すると、誘電絶縁層(dielectric isolation layer)30が蒸着される。蒸着方法は、低温CVD(low-temperature chemical vapor deposition 、LTCVD)を含むが、他の常用の方法を使用してもよい。第1実施形態中、誘電絶縁層30は窒化ケイ素(SiNx)で、 数百オングストロームの厚さを有する。次に、図6で示されるように、TSV20の端部を被覆する誘電絶縁層30の一部が、フォトレジスト31の使用とフォトリソグラフィプロセスの実行により、ビア開口33で露出し、形成されたバンプは、TSV20に電気的に接続される。
図7〜図9は、再分配線とパッドの形成を示す図である。図7を参照すると、チタン、窒化チタン、タンタル、窒化タンタル等からなる導電バリア層(conductive barrier layer)32が、例えば、スパッタリングにより形成される。次に、図8で示されるように、銅34がめっきされる。銅34の厚さは、深さD1(図3)に基づく。その後、化学機械研磨(chemical mechanical polish 、CMP)が実行され、第1金属構造である金属構造36(36−1と36−2で示される)を形成する。得られた構造は図9で示される。金属構造36は、金属線36−1を含み、実際は、別のTSV(図示しない)に接続される。従って、金属線36−1は、再分配線として使用される。金属構造36−2は、金属パッドか金属線である。金属パッドは、TSV20より大きい寸法(頂部から見て) で、金属パッドは全水平方向で、TSV20の辺縁を越えて延在される。従って、金属パッド36−2とTSV20は大きい界面面積を有し、よって、接触抵抗が小さい。更に、金属パッド36−2をTSV20に照準する精度要件が緩和される。
図10〜図12Aは、バンプ42の形成プロセスを示す。図10を参照すると、誘電層38がブランケット蒸着(blanket deposited)される。第1実施形態中、誘電層38は窒化ケイ素 (SiNx)で、厚さは、例えば、約0.2μmである。次に、図11で示されるように、フォトレジスト40により、開口が誘電層38中に形成されて、金属パッド36−2が露出する。図12Aは、バンプ42の形成を示し、水平寸法(長さ、或いは、幅)が約30μm以下なので、マイクロバンプ(U-bump) とも称される。バンプ42の形成方法は、電気化学めっき(electrical chemical plating 、ECP)、化学めっき、及び、浸漬(immersion)を含む。得られたバンプ42は、電気ニッケル・無電解金(無電解ニッケル/浸漬金)(electroless nickel immersion gold 、ENIG)構造、無電解ニッケル/無電解パラジウム/無電解金(electroless nickel electroless palladium immersion gold ,ENEPIG)構造、或いは、 ニッケルパラジウム構造としてもよい。図12Aは、バンプ42が、金属パッド36−2の直上にあることを示しているが、バンプ42は、金属パッド36−2の直上になくてもよく、実際は、金属構造36の形成と同時に形成される金属線36−1と同様の再分配線により、金属パッド36−2に接続されていてもよい。
図12Bは、本発明の実施形態1の変形例を示す図である。金属パッド36−2の直上にバンプ42を形成する構成に代えて、追加の再分配線層が形成されている。例えば、付加層60は、エッチ停止層46、誘電層48、第2金属構造であるビア50と金属線52を含み、付加層60は、金属パッド36−2とバンプ42間に挿入される。必要であれば、付加層60上に、更に多くの付加層60と同様の層をスタックし、背面相互接続構造のルーティング可能性(routability)を増加させる。層60の形成方法の詳細は、実質上、図18〜図21で示されるのと同じであり、後述する。
[第2実施形態]
図13〜図23Bを用いて、第2実施形態を説明する。第2実施形態の初期段階は、図1と図2で示したのと同様である。次に、図13を参照すると、基板10が背面からエッチバックされ、TSV20が、基板10の背面を貫通する。第2実施形態においては、エッチバック深さD2は、約0.5μmより大きく、約1μmである。絶縁層22も、TSV20の頂面からエッチバックされ、TSV20の頂面より低く、例えば、約0.5μmである。従って、TSV20の側壁の一部が露出する。
図14を参照すると、誘電層124が基板10の背面に形成され、TSV20を被覆する。第2実施形態において、誘電層124はポリイミドからなり、厚さは約2μmより大きく、例では、約3μmである。他の誘電材料を用いてもよい。
図15〜図17は、金属線の形成プロセスを示す図である。図15を参照すると、例えば、フォトレジスト(図示しない)を用いて、誘電層124をエッチングすることにより開口126が形成される。第2実施形態において、例えば、時間モードを用いて、開口形成プロセスが制御され、TSV20は、開口126の一つにより露出し、誘電層124の底部(層124'で示される)を残して、基板10と開口126を分離する。
図16を参照すると、まず洗浄を行い、導電バリア層128が、例えば、スパッタリングにより蒸着される。導電バリア層128は、チタン、タンタル等からなる。金属素材(metallic material)130がその後、誘電層124の頂面より高くなるまでめっきされる。金属素材130は銅を用いているが、アルミニウム、タングステン等のほかの材料を用いてもよい。その後、図17で示されるように、CMPが実行され、金属線/パッド(金属構造)132(132−1と132−2)が形成される。金属線132−2は、チップ中のTSVの一つに電気的に接続される。従って、金属線132−2は再分配線として用いられる。金属構造132−1は、金属パッド、或いは、金属線である。金属パッドは、TSV20より大きい寸法(上から見て)を有し、上視図で、金属パッド132−1は、全横方向で、TSV20の辺縁を越えて延在している。
図18〜図21は、相互接続の付加層の形成プロセスを示す図である。図18を参照すると、誘電層125が形成される。第2実施形態では、誘電層125はポリイミドで形成され、約2.5μm等、数ミクロンの厚さを有する。その後、フォトレジスト134を用いて、パターン化される。パターン化されたフォトレジスト134により、誘電層125を、金属層132−2が露出するまでエッチングし、ビア開口136を形成する。
図19を参照すると、フォトレジスト134が除去され、付加フォトレジスト140が形成、パターン化される。その後、図20で示されるように、パターン化されたフォトレジスト140が誘電層125を更にエッチングすることにより、トレンチ開口138が形成される。エッチングは、時間モードを用いて実行され、エッチングは、誘電層125の中間で停止される。その後、フォトレジスト140が、例えば、アッシングにより除去される。図18〜図20で示されるステップは、ビアファーストアプローチであり、ビア開口136は、トレンチ開口138が形成される前に形成されることが理解できる。当業者なら、図20で示される構造は、図19と図20に示すステップを図18に示すステップより前に行うトレンチファーストアプローチにより形成してもよいことがわかるであろう。
図21は、金属線144とビア146を含むダマシン構造の形成を示す図であり、導電バリア層148(例えば、Ti層)を蒸着するステップと、銅をめっきするステップと、CMPを実行し、余分な銅を除去するステップと、からなる。図22〜図23Aは、誘電層38とバンプ42の形成を示す図である。形成プロセスは、本質的には、第1実施形態と同じであり、よって、ここで、詳述しない。図23Bは、本発明の第2実施形態の変形例を示す図で、金属線144とビア146は、誘電層124中に形成される。
[第3実施形態]
図24〜図29Bは、第3実施形態を説明するための図である。第3実施形態の初期ステップは、図1と図2と同様である。次に、図24で示されるように、エッチ停止層220が形成される。第3実施形態中、エッチ停止層220は窒化ケイ素で形成され、厚さは、例えば、約750Åである。誘電層222は、エッチ停止層220上に形成される。第3実施形態中、誘電層222は、様々な化学気相蒸着方法(CVD)の一つを用いて形成され、誘電層222は、例えば、酸化物からなる。CVD誘電層222の厚さは、例えば、約8000Åである。別の第3実施形態中、誘電層222は、ポリイミドで形成され、厚さは、CVDを用いて形成するより誘電層の厚さよりも大幅に大きい。ポリイミドで形成される誘電層222の厚さは、約2μmより大きく、第3実施形態では、約5μmである。
図25〜図27は、ビア開口226とトレンチ開口228の形成を示す図である。形成の詳細は、本質的に図18〜図20と同じであり、ここで詳述しない。次に、図28で示されるように、デュアルダマシン構造が形成される。デュアルダマシン構造は、ビア232とビア232を被覆する金属線234と、からなり、金属線234は銅から形成される。導電バリア層236も形成される。
図29Aは、誘電層38とバンプ42の形成プロセスを示す図である。誘電層38とバンプ42の材料と形成プロセスは、実質上、図10〜図12Aと同じである。図29Bは、相互接続の付加層(60)を有する変形例を示す図で、追加のデュアルダマシン構造を含む。必要であれば、更に多くの相互接続が挿入される。
上述の実施形態は、幾つかの優れた特色を有する。デュアルダマシンプロセスを用いて、背面相互接続構造を形成することにより、マルチ相互接続層がスタックされて、好ましいルーティング能力を提供する。TSVを接触させる金属パッド(図10の36−2と図17の132−1)を形成するために基板を凹陥させるので、金属パッドは大きなサイズとすることができる。その結果、TSVに対する金属パッドの配置の精度要求は緩和される。更に、金属パッドとその下のTSVは、大きい接触領域を有し、接触抵抗が減少する。
以上、本発明の好ましい実施形態を例示したが、これらは本発明を限定するものではなく、本発明の趣旨と範囲を逸脱しない限りにおいては、当業者なら行い得る種々の変更や修飾を付加することができる。従って、本発明が請求する保護範囲は、特許請求の範囲を基準とする。
2 チップ
10 基板
10b 背面
10f 前側
12 相互接続構造
14 接着パッド
15 トランジスタ
20 TSV
22 絶縁層
24 開口
25 キャリア
26、31 フォトレジスト
27 (トレンチ)開口
28 底部
30 誘電絶縁層
32、128、148、236 導電バリア層
33、136、226 開口
34 銅
36(36−1と36−2) 金属構造
38、48、222 誘電層
40 フォトレジスト
42 バンプ
46 220 エッチ停止層
50 146 ビア
52 金属線
60 付加層
124 124'誘電層
125 誘電層
126 開口
130 金属素材
132(132−1と132−2) 金属線/パッド
234 金属線
134 フォトレジスト
138 228 トレンチ開口
140 フォトレジスト
144 金属線
232 ビア
D1、D2 深さ

Claims (9)

  1. 集積回路構造であって、
    正面と背面を有する半導体基板と、
    前記半導体基板を貫通する導電ビアと、
    前記半導体基板の背面上にあり、前記導電ビアを被覆し、接触する金属パッド、及び、前記導電ビア上に位置し、デュアルダマシン構造を含む金属線を具備する金属構造と、
    前記金属線上のバンプと、を備えることを特徴とする集積回路構造。
  2. 前記金属パッドは、更に、
    前記導電ビアの頂面と接触する第一底面と、
    前記半導体基板の前記背面より高く、且つ、前記第一底面より低い第二底面と、
    を備えることを特徴とする請求項1に記載の集積回路構造。
  3. 前記デュアルダマシン構造は、前記金属パッドと同じ誘電層中にあることを特徴とする請求項1又は2に記載の集積回路構造。
  4. 前記デュアルダマシン構造は、前記金属パッド上の誘電層中にあることを特徴とする請求項1又は2に記載の集積回路構造。
  5. 前記金属パッドの全水平寸法は、それぞれ、前記導電ビアの水平寸法より大きいことを特徴とする請求項1〜4のいずれか1項に記載の集積回路構造。
  6. 集積回路構造であって、
    正面と背面を有する半導体基板と、
    前記半導体基板中の導電ビアと、
    前記半導体基板の背面から前記半導体基板中に延伸し、前記導電ビアと接触する第一金属構造と、
    前記第一金属構造上で、且つ、前記第一金属構造に電気的に接続するバンプと、
    前記第一金属構造と前記バンプ間に形成され、デュアルダマシン構造を含む第二金属構造と、
    を備えることを特徴とする集積回路構造。
  7. 前記第一金属構造の全水平寸法は、それぞれ、前記導電ビアの水平寸法より大きいことを特徴とする請求項6に記載の集積回路構造。
  8. 前記第一金属構造は、前記半導体基板の前記背面と同じ高さの頂面を有することを特徴とする請求項6又は7に記載の集積回路構造。
  9. 前記第一金属構造は、
    前記導電ビアに接触する導電バリア層と、
    前記導電バリア層上の銅含有金属材料と、
    からなることを特徴とする請求項6〜8のいずれか1項に記載の集積回路構造。
JP2010211576A 2009-09-22 2010-09-22 集積回路構造 Active JP5271985B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US24477309P 2009-09-22 2009-09-22
US61/244,773 2009-09-22
US12/832,019 US8791549B2 (en) 2009-09-22 2010-07-07 Wafer backside interconnect structure connected to TSVs
US12/832,019 2010-07-07

Publications (2)

Publication Number Publication Date
JP2011071516A JP2011071516A (ja) 2011-04-07
JP5271985B2 true JP5271985B2 (ja) 2013-08-21

Family

ID=43755919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010211576A Active JP5271985B2 (ja) 2009-09-22 2010-09-22 集積回路構造

Country Status (5)

Country Link
US (4) US8791549B2 (ja)
JP (1) JP5271985B2 (ja)
KR (1) KR101319701B1 (ja)
CN (1) CN102024781B (ja)
TW (1) TWI453879B (ja)

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8716867B2 (en) 2010-05-12 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interconnect structures using pre-ink-printed sheets
US9190325B2 (en) * 2010-09-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation
KR101697573B1 (ko) * 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20120090417A (ko) * 2011-02-08 2012-08-17 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP2012256679A (ja) * 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置及びその製造方法
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
CN103000571B (zh) * 2011-09-19 2015-07-08 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法
CN103890940B (zh) 2011-10-28 2017-03-01 英特尔公司 包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构
US9449913B2 (en) 2011-10-28 2016-09-20 Intel Corporation 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
KR101931115B1 (ko) 2012-07-05 2018-12-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140023055A (ko) * 2012-08-16 2014-02-26 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
KR102021884B1 (ko) * 2012-09-25 2019-09-18 삼성전자주식회사 후면 본딩 구조체를 갖는 반도체 소자
US8859425B2 (en) * 2012-10-15 2014-10-14 Micron Technology, Inc. Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
KR102018885B1 (ko) * 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US10483132B2 (en) * 2012-12-28 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US9466578B2 (en) * 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US20150179580A1 (en) * 2013-12-24 2015-06-25 United Microelectronics Corp. Hybrid interconnect structure and method for fabricating the same
US9093503B1 (en) * 2014-01-03 2015-07-28 International Business Machines Corporation Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
US9865523B2 (en) * 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
KR102222485B1 (ko) * 2014-09-18 2021-03-04 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
KR102279729B1 (ko) * 2014-12-01 2021-07-21 삼성전자주식회사 Tsv, 전면 범핑 패드 및 후면 범핑 패드를 갖는 반도체 소자
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
US9666523B2 (en) 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US9472490B1 (en) 2015-08-12 2016-10-18 GlobalFoundries, Inc. IC structure with recessed solder bump area and methods of forming same
KR20170023643A (ko) 2015-08-24 2017-03-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10121812B2 (en) * 2015-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked substrate structure with inter-tier interconnection
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
JP6955864B2 (ja) * 2016-12-26 2021-10-27 ラピスセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
WO2018136712A1 (en) * 2017-01-20 2018-07-26 Tokyo Electon Limited Interconnect structure and method of forming the same
KR102406573B1 (ko) * 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10515921B2 (en) * 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US11843020B2 (en) 2017-10-30 2023-12-12 Samsung Electronics Co., Ltd. Image sensor
KR102542614B1 (ko) 2017-10-30 2023-06-15 삼성전자주식회사 이미지 센서
US11521923B2 (en) * 2018-05-24 2022-12-06 Intel Corporation Integrated circuit package supports
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
KR102635832B1 (ko) 2018-09-28 2024-02-15 삼성전자주식회사 반도체 소자 및 그 제조방법
US10727124B2 (en) 2018-10-29 2020-07-28 International Business Machines Corporation Structure and method for forming fully-aligned trench with an up-via integration scheme
JP7353748B2 (ja) * 2018-11-29 2023-10-02 キヤノン株式会社 半導体装置の製造方法および半導体装置
US10770427B1 (en) * 2019-06-27 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US11195810B2 (en) 2019-08-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure and method of forming same
US11398408B2 (en) * 2019-09-24 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate with trace connected to via at a level within a dielectric layer
US11094580B2 (en) * 2019-10-01 2021-08-17 International Business Machines Corporation Structure and method to fabricate fully aligned via with reduced contact resistance
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
US11295978B2 (en) 2020-04-29 2022-04-05 International Business Machines Corporation Interconnects having spacers for improved top via critical dimension and overlay tolerance
KR20210133524A (ko) 2020-04-29 2021-11-08 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
US20220293750A1 (en) * 2021-03-12 2022-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit including backside conductive vias
KR20220129924A (ko) * 2021-03-17 2022-09-26 삼성전자주식회사 인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지
CN113078119B (zh) * 2021-03-26 2022-03-18 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
US12100670B2 (en) 2021-03-26 2024-09-24 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure
KR20220167423A (ko) 2021-06-11 2022-12-21 삼성전자주식회사 관통 전극들을 포함하는 반도체 소자
US20230005869A1 (en) * 2021-07-05 2023-01-05 Changxin Memory Technologies, Inc. Micro bump, method for forming micro bump, chip interconnection structure and chip interconnection method
US12087691B2 (en) 2021-09-21 2024-09-10 International Business Machines Corporation Semiconductor structures with backside gate contacts
KR102681185B1 (ko) * 2021-09-24 2024-07-04 한국기계연구원 마이크로 엘이디 표시모듈 및 이의 제조방법
US12002758B2 (en) 2021-11-04 2024-06-04 International Business Machines Corporation Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer
KR20240019456A (ko) * 2022-08-04 2024-02-14 삼성전자주식회사 반도체 장치

Family Cites Families (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2034900B (en) * 1978-11-17 1982-10-20 Marconi Instruments Ltd Spectrum analyser
US4872750A (en) * 1982-07-14 1989-10-10 Nec Home Electronics Ltd. Image projection apparatus
US4799050A (en) * 1986-10-23 1989-01-17 Litton Systems Canada Limited Full color liquid crystal display
JP2554724B2 (ja) * 1987-12-11 1996-11-13 株式会社リコー レーザーダイオードアレイを用いる光走査光学系
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US5646067A (en) 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US6469683B1 (en) * 1996-01-17 2002-10-22 Nippon Telegraph And Telephone Corporation Liquid crystal optical device
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
KR100377033B1 (ko) 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ic 및 그 제조방법
JPH10163315A (ja) * 1996-11-28 1998-06-19 Nec Ic Microcomput Syst Ltd 半導体回路装置
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3600470B2 (ja) * 1998-06-22 2004-12-15 パイオニア株式会社 プラズマディスプレイパネル
KR100281897B1 (ko) 1998-07-21 2001-03-02 윤종용 도전층을 갖는 반도체 장치의 제조방법
US6706189B2 (en) 1998-10-09 2004-03-16 Zenon Environmental Inc. Cyclic aeration system for submerged membrane modules
WO2000025176A1 (fr) * 1998-10-28 2000-05-04 Dai Nippon Printing Co., Ltd. Afficheur a cristaux liquides
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP3998373B2 (ja) 1999-07-01 2007-10-24 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6785028B1 (en) * 1999-11-24 2004-08-31 Ricoh Company, Ltd. Optical scanning device having a temperature compensation unit
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
US6292285B1 (en) * 1999-12-20 2001-09-18 Xerox Corporation Single rotating polygon mirror with v-shaped facets for a multiple beam ROS
JP3626058B2 (ja) 2000-01-25 2005-03-02 Necエレクトロニクス株式会社 半導体装置の製造方法
JP2001291720A (ja) 2000-04-05 2001-10-19 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US7053465B2 (en) 2000-11-28 2006-05-30 Texas Instruments Incorporated Semiconductor varactor with reduced parasitic resistance
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6696360B2 (en) * 2001-03-15 2004-02-24 Micron Technology, Inc. Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
JP2002296714A (ja) * 2001-03-30 2002-10-09 Fuji Photo Film Co Ltd 放射線画像情報読取方法
US7224063B2 (en) * 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
KR100404479B1 (ko) * 2001-06-21 2003-11-05 주식회사 하이닉스반도체 듀얼 다마신 배선 형성방법
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
CN1215551C (zh) * 2002-04-12 2005-08-17 台湾积体电路制造股份有限公司 阻绝气体释放及凸出结构产生的双镶嵌方法
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP3774715B2 (ja) * 2002-10-21 2006-05-17 キヤノン株式会社 投射型表示装置
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US7354798B2 (en) * 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
JP4072677B2 (ja) 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2004297019A (ja) 2003-03-28 2004-10-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
JP4248928B2 (ja) 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US6897125B2 (en) 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US6878616B1 (en) * 2003-11-21 2005-04-12 International Business Machines Corporation Low-k dielectric material system for IC application
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Necエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4339152B2 (ja) * 2004-03-08 2009-10-07 富士通マイクロエレクトロニクス株式会社 配線構造の形成方法
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Necエレクトロニクス株式会社 半導体装置の製造方法
JP4439976B2 (ja) * 2004-03-31 2010-03-24 Necエレクトロニクス株式会社 半導体装置およびその製造方法
CN102290425B (zh) 2004-08-20 2014-04-02 Kamiyacho知识产权控股公司 具有三维层叠结构的半导体器件的制造方法
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
KR20060054689A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR101052366B1 (ko) 2004-11-16 2011-07-28 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR20060054690A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
JP2006339584A (ja) * 2005-06-06 2006-12-14 Sharp Corp 半導体装置およびその製造方法
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7429529B2 (en) 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20070081239A1 (en) * 2005-10-06 2007-04-12 May Gregory J Optical characteristics of a screen
US7609442B2 (en) * 2005-10-13 2009-10-27 Hewlett-Packard Development Company, L.P. Synchronizing screen
TW200733270A (en) * 2005-10-19 2007-09-01 Koninkl Philips Electronics Nv Redistribution layer for wafer-level chip scale package and method therefor
JP5073946B2 (ja) 2005-12-27 2012-11-14 新光電気工業株式会社 半導体装置および半導体装置の製造方法
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7514775B2 (en) 2006-10-09 2009-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US7544605B2 (en) 2006-11-21 2009-06-09 Freescale Semiconductor, Inc. Method of making a contact on a backside of a die
JP4415984B2 (ja) * 2006-12-06 2010-02-17 ソニー株式会社 半導体装置の製造方法
US8247322B2 (en) * 2007-03-01 2012-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Via/contact and damascene structures and manufacturing methods thereof
US7697183B2 (en) * 2007-04-06 2010-04-13 Prysm, Inc. Post-objective scanning beam systems
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
KR20080101635A (ko) 2007-05-18 2008-11-21 삼성전자주식회사 반도체 패키지, 그 제조 방법, 및 반도체 패키지를 이용한패키지 모듈 및 전자 제품
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20090057909A1 (en) 2007-06-20 2009-03-05 Flipchip International, Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TW200910557A (en) 2007-06-20 2009-03-01 Flipchip Int Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TWI351751B (en) 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
US8556430B2 (en) * 2007-06-27 2013-10-15 Prysm, Inc. Servo feedback control based on designated scanning servo beam in scanning beam display systems with light-emitting screens
US8193092B2 (en) 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
KR101387701B1 (ko) * 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2009055004A (ja) * 2007-08-24 2009-03-12 Honda Motor Co Ltd 貫通配線構造
US20090102052A1 (en) * 2007-10-22 2009-04-23 Sang Wook Ryu Semiconductor Device and Fabricating Method Thereof
JP2009147218A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置とその製造方法
JP5358089B2 (ja) 2007-12-21 2013-12-04 スパンション エルエルシー 半導体装置
US7804119B2 (en) 2008-04-08 2010-09-28 International Business Machines Corporation Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP5324822B2 (ja) * 2008-05-26 2013-10-23 ラピスセミコンダクタ株式会社 半導体装置
US7939449B2 (en) * 2008-06-03 2011-05-10 Micron Technology, Inc. Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
US7800238B2 (en) 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US7869112B2 (en) * 2008-07-25 2011-01-11 Prysm, Inc. Beam scanning based on two-dimensional polygon scanner for display and other applications
US8384224B2 (en) * 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
KR20100021856A (ko) 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
KR20100045857A (ko) * 2008-10-24 2010-05-04 삼성전자주식회사 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법
US7935571B2 (en) * 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US7999320B2 (en) 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US8097964B2 (en) * 2008-12-29 2012-01-17 Texas Instruments Incorporated IC having TSV arrays with reduced TSV induced stress
US7910473B2 (en) 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8399354B2 (en) 2009-01-13 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with low-K dielectric liner
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8531015B2 (en) * 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
JP5019303B2 (ja) * 2010-03-03 2012-09-05 Smc株式会社 電磁弁駆動回路、電磁弁及び電磁弁の駆動方法
US8587121B2 (en) * 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8174124B2 (en) * 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing

Also Published As

Publication number Publication date
US9449875B2 (en) 2016-09-20
US20140322909A1 (en) 2014-10-30
TWI453879B (zh) 2014-09-21
CN102024781B (zh) 2013-04-17
KR20110033022A (ko) 2011-03-30
US20170005069A1 (en) 2017-01-05
US9716074B2 (en) 2017-07-25
TW201112371A (en) 2011-04-01
US9978708B2 (en) 2018-05-22
KR101319701B1 (ko) 2013-10-17
JP2011071516A (ja) 2011-04-07
US20110068466A1 (en) 2011-03-24
CN102024781A (zh) 2011-04-20
US8791549B2 (en) 2014-07-29
US20140312494A1 (en) 2014-10-23

Similar Documents

Publication Publication Date Title
JP5271985B2 (ja) 集積回路構造
US20240170457A1 (en) Stacked integrated circuits with redistribution lines
US20210125900A1 (en) Through-Substrate Vias with Improved Connections
TWI416693B (zh) 半導體裝置及其製造方法
US8034708B2 (en) Structure and process for the formation of TSVs
US8846523B2 (en) Process of forming through-silicon via structure
TWI544597B (zh) 積體電路元件以及半導體製程
US8486823B2 (en) Methods of forming through via
CN101752336B (zh) 半导体装置及其制造方法
TWI429046B (zh) 半導體裝置及其製造方法
US20100244251A1 (en) Semiconductor device and method for fabricating the same
US9437578B2 (en) Stacked IC control through the use of homogenous region
TWI648837B (zh) 半導體結構及其製造方法
TWI829079B (zh) 半導體結構及其形成方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100922

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130329

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130416

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130513

R150 Certificate of patent or registration of utility model

Ref document number: 5271985

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250