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JP5252024B2 - Semiconductor device - Google Patents

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JP5252024B2
JP5252024B2 JP2011088139A JP2011088139A JP5252024B2 JP 5252024 B2 JP5252024 B2 JP 5252024B2 JP 2011088139 A JP2011088139 A JP 2011088139A JP 2011088139 A JP2011088139 A JP 2011088139A JP 5252024 B2 JP5252024 B2 JP 5252024B2
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solder
semiconductor chip
circuit pattern
layer
bonding
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JP2011159994A (en
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良成 池田
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

本発明は、パワー用ＩＧＢＴモジュールなどを対象とする半導体装置に関し、詳しくは絶縁基板の回路パターン上にマウントした半導体チップの接合構造に係わる。   The present invention relates to a semiconductor device intended for a power IGBT module and the like, and more particularly to a bonding structure of a semiconductor chip mounted on a circuit pattern of an insulating substrate.

先ず、頭記のＩＧＢＴモジュールを例に、その組立構造を図４に示す。図において、１は放熱用銅ベース、２はセラミック板２ａの上面，下面に銅回路パターン２ｂ，銅箔２ｃを成層して銅ベース１に搭載した絶縁基板、３，４はＩＧＢＴ，ＦＷＤの半導体チップ、５は銅ベース１と絶縁基板２の裏面銅箔２ｃ，および絶縁基板２の回路パターン２ａと半導体チップ３，４との間を接合した半田接合層、６は銅ベース１の下面にサーマルコンパウンド７で伝熱的に接合し冷却体（ヒートシンク）である。なお、図２では配線リード、モジュールの外囲ケースなどは省略して描かれてない。     First, the assembly structure is shown in FIG. 4 taking the IGBT module mentioned above as an example. In the figure, 1 is a heat-dissipating copper base, 2 is an insulating substrate mounted on the copper base 1 with a copper circuit pattern 2b and a copper foil 2c formed on the upper and lower surfaces of the ceramic plate 2a, and 3 and 4 are semiconductors of IGBT and FWD. The chip 5 is a solder bonding layer that bonds the copper base 1 and the back surface copper foil 2c of the insulating substrate 2 and the circuit pattern 2a of the insulating substrate 2 and the semiconductor chips 3 and 4; It is a cooling body (heat sink) joined by heat transfer with the compound 7. In FIG. 2, the wiring leads, the module enclosing case, etc. are not shown.

ここで、銅ベース１／絶縁基板２の裏面銅箔２ｃ，絶縁基板２の回路パターン２ａ／半導体チップ３，４を接合する半田材にはクリーム半田あるいは板半田を使用し、リフロー工程を経て半田接合層５を形成している。     Here, cream solder or plate solder is used as a solder material for joining the copper base 1 / the back surface copper foil 2c of the insulating substrate 2 and the circuit pattern 2a / semiconductor chips 3 and 4 of the insulating substrate 2, and the solder is passed through a reflow process. A bonding layer 5 is formed.

一方、最近では環境問題からＳｎ−Ｐｂ系半田の代替として鉛成分を含まない鉛フリー半田が採用されるようになっており、前記のＩＧＢＴモジュール（パワーモジュール）に適用する半田材としては、現在知られている各種組成の鉛フリー半田の中でも取りわけ接合性（半田濡れ性），機械的特性，伝熱抵抗などの面で比較的バランスがよく、かつ製品への実績もあるＳｎ−Ａｇ系の鉛フリー半田が多く使われている（例えば、非特許文献１参照）。     On the other hand, recently, lead-free solder containing no lead component has been adopted as an alternative to Sn-Pb solder due to environmental problems. As a solder material applied to the IGBT module (power module), Among the known lead-free solders of various compositions, Sn-Ag series has a relatively good balance in terms of jointability (solder wettability), mechanical properties, heat transfer resistance, etc., and has a track record in products. Lead-free solder is often used (see Non-Patent Document 1, for example).

また、鉛フリー半田として、Ｓｎ，ＡｇのほかにＮｉ，Ｃｕを添加した半田材を適用し、その半田材中に生成した金属間化合物の特性（高温強度）を有効に生かして半導体チップと半導体チップをマウントする放熱基板との間を接合するようにしたものも知られている（例えば、特許文献１参照）。     Moreover, as a lead-free solder, a solder material to which Ni and Cu are added in addition to Sn and Ag is applied, and the characteristics (high-temperature strength) of the intermetallic compound generated in the solder material are effectively utilized to make a semiconductor chip and a semiconductor. There is also known one that joins a heat dissipation substrate on which a chip is mounted (for example, see Patent Document 1).

さらに、最近では半導体デバイスの製造技術分野でも金属ナノ粒子の量子サイズ効果による低温焼結現象および高い表面活性を利用した低温焼成形の導電性ペースト（以下、「ナノ金属ペースト」と称する）が開発，市販されており、このナノ金属ペーストを使って基板上に半導体チップを接合するなどの応用技術が提案されている（例えば、特許文献２）。
両角，他２名，「パワー半導体モジュールにおける信頼性設計技術」，冨士時報，富士電機株式会社，平成１３年２月１０日，第７４巻，第２号，ｐ１４５〜１４８ 特開平１１−３４７７８５号公報 特開２００４−１３０３７１号公報 Furthermore, recently, in the field of semiconductor device manufacturing technology, a low-temperature firing type conductive paste (hereinafter referred to as “nanometal paste”) utilizing the low-temperature sintering phenomenon due to the quantum size effect of metal nanoparticles and high surface activity has been developed. Have been proposed, and application techniques such as bonding a semiconductor chip on a substrate using the nanometal paste have been proposed (for example, Patent Document 2).
Both corners, 2 others, “Reliability design technology in power semiconductor modules”, Fuji time signal, Fuji Electric Co., Ltd., February 10, 2001, Vol. 74, No. 2, p145-148 JP 11-347785 A JP 2004-130371 A

ところて、半導体チップ／絶縁基板の接合材にＳｎ−Ａｇ系の鉛フリー半田を適用した半導体モジュールについて、パワーサイクル試験（モジュールの実動作を模擬した断続通電試験）により半田接合部に発生した亀裂（欠陥）の進展形態を観察したところ、Ｓｎ−Ａｇ系の鉛フリー半田接合層には図５で表すように発熱密度が高い半導体チップ３の中央部下付近を起点としてほぼ同心円状に亀裂（符号Ａで表す）が進展することが認められた。また、この亀裂の特徴は、半田層の厚さ方向に平行な縦割れ，または網目状を呈してＳｎの結晶粒界を選択的に進展しており、このことからＳｎ−Ａｇ系の鉛フリー半田では熱劣化（組織変化）によって亀裂が進行するものと想定される（非特許文献１のｐ１４７参照）。   By the way, for a semiconductor module in which Sn-Ag-based lead-free solder is applied to the bonding material of the semiconductor chip / insulating substrate, a crack occurred in the solder joint portion by a power cycle test (intermittent current test simulating the actual operation of the module). As a result of observing the progress of (defects), the Sn-Ag lead-free solder joint layer was cracked almost concentrically starting from the vicinity of the central portion of the semiconductor chip 3 having a high heat generation density as shown in FIG. (Represented by A) was observed to progress. In addition, the characteristics of this crack are vertical cracks parallel to the thickness direction of the solder layer, or a network, and the Sn crystal grain boundary is selectively propagated. From this, Sn-Ag lead free It is assumed that cracks progress due to thermal degradation (structural change) in solder (see p147 of Non-Patent Document 1).

このように、半導体チップ／絶縁基板の接合にＳｎ−Ａｇ系の鉛フリー半田を適用して接合した半導体装置について、従来の接合構造では半導体チップの中央部下付近の半田接合層に熱劣化（組織変化）が発生して亀裂が生じるために、長期に亘り高い信頼性を確保することが難しい。   As described above, with respect to a semiconductor device bonded by applying Sn-Ag lead-free solder to the semiconductor chip / insulating substrate bonding, the conventional bonding structure causes thermal degradation (structure) near the solder bonding layer near the center of the semiconductor chip. Change) and cracks occur, and it is difficult to ensure high reliability over a long period of time.

かかる点、例えば特許文献２に開示されている鉛フリー半田を適用し、その半田材中に生成した金属間化合物を半田層の全域に成長させて半導体チップ／回路パターン間を金属間化合物だけで接合するようにすれば、前記した半田層の熱劣化（組織変化）に起因して半導体チップの中央部下の接合層に亀裂が発生するのを防止できることが想定される。しかしながら、発明者が実験を通じて得た知見によれば、半導体チップ／絶縁基板の回路パターン間の接合面全域を全て半田材中に生成した金属間化合物で接合すると、半導体チップの中央部下の接合層に亀裂が発生するのを効果的に防止できるものの、外周側のフィレット部を起点として接合層の面方向に加わる剪断応力の作用方向に亀裂が発生，進展するのが認められた。これは、半導体チップ／絶縁基板の熱膨張係数差により熱サイクルで接合層に生じる熱応力（剪断応力）が半導体チップの中央部下よりもチップ外周のフィレット部付近に多く集中するのに対して、金属間化合物は半田層に比べて脆く、延性も低いために金属間化合物の接合層が疲労破壊して亀裂が発生するものと推測される。   In this respect, for example, the lead-free solder disclosed in Patent Document 2 is applied, and an intermetallic compound generated in the solder material is grown over the entire solder layer so that only the intermetallic compound is formed between the semiconductor chip / circuit pattern. By joining, it is assumed that cracks can be prevented from occurring in the joining layer under the central portion of the semiconductor chip due to the above-described thermal deterioration (structural change) of the solder layer. However, according to the knowledge obtained by the inventors through experiments, when the entire bonding surface between the circuit patterns of the semiconductor chip / insulating substrate is bonded with the intermetallic compound generated in the solder material, the bonding layer under the central portion of the semiconductor chip Although it was possible to effectively prevent cracks from occurring, cracks were observed to develop and propagate in the direction of shear stress applied to the surface direction of the bonding layer starting from the fillet portion on the outer peripheral side. This is because the thermal stress (shear stress) generated in the bonding layer in the thermal cycle due to the difference in the thermal expansion coefficient of the semiconductor chip / insulating substrate is concentrated more in the vicinity of the fillet portion of the outer periphery of the chip than under the central portion of the semiconductor chip It is presumed that the intermetallic compound is brittle and has a lower ductility than the solder layer, so that the intermetallic compound bonding layer undergoes fatigue failure and cracks occur.

また、半導体チップ／回路パターン間をナノ金属粒子で接合したパッケージについても、前記の金属間化合物による接合と同様に半導体チップ中央部下の亀裂発生を効果的に防止できるものの、半導体チップの外周縁を起点として接合層の外周部には剪断応力の作用方向に亀裂の発生が認められる。   In addition, as for the package in which the semiconductor chip / circuit pattern is bonded with the nano metal particles, cracking under the center of the semiconductor chip can be effectively prevented as in the bonding with the intermetallic compound, but the outer peripheral edge of the semiconductor chip is As a starting point, the occurrence of cracks in the direction of shear stress is recognized in the outer peripheral portion of the bonding layer.

本発明は上記の点に鑑みなされたものであり、その目的は半導体チップ／絶縁基板間の半田接合部について、半導体チップの中央部下付近の接合層に亀裂が発生するのを抑制し、併せて半導体チップ／絶縁基板間の伝熱性を向上させて高いパワーサイクル耐性と長期信頼性の向上が図れるように接合構造を改良した半導体装置を提供することにある。   The present invention has been made in view of the above points, and the object thereof is to suppress the occurrence of cracks in the bonding layer near the center of the semiconductor chip at the solder bonding portion between the semiconductor chip and the insulating substrate. It is an object of the present invention to provide a semiconductor device having an improved junction structure so as to improve heat transfer between a semiconductor chip and an insulating substrate to improve high power cycle resistance and long-term reliability.

上記目的を達成するために、本発明によれば、絶縁基板の回路パターン上に鉛フリー半田を適用して半導体チップを半田マウントした半導体装置において、
半導体チップと回路パターンとの間の接合面を半導体チップの中央部下に対応する中央面域と、該中央面域を囲む外周面域とに分け、かつ回路パターンには前記中央面域に対応して台形状の凸部を形成した上で、回路パターン上に形成した前記凸部と半導体チップの中央部との間を、半田の代わりにナノ金属ペーストを適用して金属接合し、その外周面域を鉛フリー半田で接合する（請求項１）。 In order to achieve the above object, according to the present invention, in a semiconductor device in which a semiconductor chip is solder mounted by applying lead-free solder on a circuit pattern of an insulating substrate,
The bonding surface between the semiconductor chip and the circuit pattern is divided into a central surface area corresponding to the lower part of the semiconductor chip and an outer peripheral surface area surrounding the central surface area, and the circuit pattern corresponds to the central surface area. After forming a trapezoidal convex part, a metal joint is applied between the convex part formed on the circuit pattern and the central part of the semiconductor chip by applying a nano metal paste instead of solder, and its outer peripheral surface The areas are joined with lead-free solder (claim 1).

上記のように半導体チップ／回路パターン間の半田接合部について、チップ外周部に比べて通電に伴う発熱密度が大で高温となる半導体チップの中央部と向かい合う回路パターン上の部分に凸部を形成した上で、鉛フリー半田を適用して半導体チップ／回路パターン間を接合することにより、半導体チップの中央部下の半田接合層はチップ外周側に比べて厚さが薄く、したがってその部分の伝熱抵抗が小さくなって半導体チップからの放熱性も増す。これにより、半田接合層の中央面域については高温な温度上昇に伴う熱劣化（組織変化）が抑制されて該部分での亀裂発生を抑制できる。一方、熱膨張係数差に起因する剪断応力が集中する半田接合層の外周部には十分に厚い半田層が確保されているので、半田の塑性，延性を生かしてこの部分に作用する剪断応力を吸収緩和でき、その結果として半導体装置のパワーサイクル耐性，長期信頼性が向上する。   As described above, at the solder joint between the semiconductor chip and the circuit pattern, a convex part is formed on the part on the circuit pattern facing the central part of the semiconductor chip where the heat generation density caused by energization is large and high compared to the outer periphery of the chip. In addition, by applying lead-free solder to bond between the semiconductor chip / circuit pattern, the solder bonding layer below the center of the semiconductor chip is thinner than the outer periphery of the chip, so heat transfer in that part The resistance is reduced and the heat dissipation from the semiconductor chip is also increased. Thereby, about the center surface area of a solder joint layer, the thermal degradation (structure change) accompanying a high temperature rise is suppressed, and the crack generation | occurrence | production in this part can be suppressed. On the other hand, since a sufficiently thick solder layer is secured on the outer periphery of the solder joint layer where shear stress due to the difference in thermal expansion coefficient is concentrated, the shear stress acting on this part is utilized by taking advantage of the plasticity and ductility of the solder. Absorption can be relaxed, and as a result, the power cycle resistance and long-term reliability of the semiconductor device are improved.

また、回路パターンの凸部／半導体チップ間の半田接合層の厚さを５μｍ以下に設定してリフローし、半導体チップの中央部と回路パターンの凸部との間をリフロー工程を含む熱履歴により生成した金属間化合物で接合するようにすれば、鉛フリー半田（Ｓｎ−Ａｇ系半田）の適用で従来問題となっていた半導体チップ中央部下の半田層に生じる熱劣化、およびその熱劣化に起因する亀裂の発生を防止しつつ、外周部側では層の厚い半田層が剪断応力に対する応力緩和層として有効に働き、これにより半導体装置の長期信頼性がより一層向上する。   Further, the thickness of the solder bonding layer between the convex part of the circuit pattern / semiconductor chip is set to 5 μm or less and reflow is performed, and the thermal history including the reflow process is performed between the central part of the semiconductor chip and the convex part of the circuit pattern If the generated intermetallic compound is used for joining, the thermal degradation that occurs in the solder layer under the center of the semiconductor chip, which has been a problem in the past by the application of lead-free solder (Sn-Ag solder), and the thermal degradation On the outer peripheral side, the thick solder layer effectively works as a stress relaxation layer against shear stress, thereby further improving the long-term reliability of the semiconductor device.

さらに、半導体チップ／回路パターン間の接合について、回路パターンに形成した凸部と半導体チップ中央部との間の接合面域では、半田の代わりにナノ金属ペーストを適用してナノ金属粒子間，ナノ金属粒子／接合母材間の低温焼結により金属同士で直接接合し、その外周面域には延性の高い鉛フリー半田を適用して層の厚い半田接合層を確保することにより、前記と同様に発熱密度の高い半導体チップの中央部に対してはナノ金属粒子により低熱抵抗，高耐熱性で熱劣化のない金属接合部を確保し、またチップ外周部では層の厚い半田接合層が剪断応力を効果的に吸収緩和して長期信頼性のさらなる向上が図れる。   Furthermore, with regard to the bonding between the semiconductor chip / circuit pattern, in the bonding surface area between the convex portion formed in the circuit pattern and the central portion of the semiconductor chip, a nano metal paste is applied in place of the solder to apply a nano metal paste between the nano metal particles. Similar to the above, by joining directly between metals by low-temperature sintering between metal particles / joining base material and applying a lead-free solder with high ductility to the outer peripheral surface area to ensure a thick solder joint layer At the center of the semiconductor chip, which has a high heat generation density, a metal joint with low thermal resistance, high heat resistance, and no thermal degradation is secured by nano metal particles. Can be effectively absorbed and relaxed to further improve long-term reliability.

以下、本発明の実施の形態を図１，図２，図３に示す各実施例に基づいて説明する。なお、図示実施例の図は半導体チップ３と絶縁基板２の回路パターン２ｂとの半田接合部を模式的に表しており、図中で図５に対応する部材には同じ符号を付している。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on the respective examples shown in FIGS. The drawing of the illustrated embodiment schematically shows a solder joint between the semiconductor chip 3 and the circuit pattern 2b of the insulating substrate 2, and members corresponding to those in FIG. .

図１（ａ），（ｂ）は本発明の請求項１に対応する実施例を示すものであり、半導体チップ３をマウントとする回路パターン２ａには、半導体チップ３の中央部下面と向かい合う面域に台形状の凸部２ｂ−１をエッチング加工，あるいはプレス加工により形成しておく。なお、凸部２ｂ−１の平面形状は図示のように円形とするほか、方形状あるいは多角形であってもよい。   FIGS. 1A and 1B show an embodiment corresponding to claim 1 of the present invention. A circuit pattern 2a having a semiconductor chip 3 as a mount has a surface facing the lower surface of the central portion of the semiconductor chip 3. FIG. A trapezoidal convex portion 2b-1 is formed in the region by etching or pressing. In addition, the planar shape of the convex portion 2b-1 may be a square shape or a polygonal shape in addition to a circular shape as illustrated.

そして、半導体チップ３／回路パターン２ｂ間の半田リフロー工程では、前記凸部２ｂ−１を含む回路パターン２ａ上の接合面域に鉛フリー半田（Ｓｎ−Ａｇ系半田）のクリーム半田を印刷するか、あるいは板半田を載せ、この半田の上に半導体チップ３を重ね合わせた上で、炉内に搬入してリフロー半田付けを行う。   Then, in the solder reflow process between the semiconductor chip 3 and the circuit pattern 2b, is it possible to print a lead-free solder (Sn—Ag solder) cream solder on the bonding surface area on the circuit pattern 2a including the convex portion 2b-1? Alternatively, a plate solder is placed, and the semiconductor chip 3 is overlaid on the solder, and then carried into a furnace to perform reflow soldering.

これにより、半導体チップ３と回路パターン２ｂとの間には、図１（ａ）の断面図で表すように半導体チップ２の中央部下では層の厚さが薄く、外周域では層の厚さが厚い半田接合層５が形成される。   Thereby, between the semiconductor chip 3 and the circuit pattern 2b, as shown in the sectional view of FIG. 1A, the layer thickness is thin under the central portion of the semiconductor chip 2 and the layer thickness is in the outer peripheral area. A thick solder bonding layer 5 is formed.

上記の接合構造によれば、通電に伴う発熱密度の高い半導体チップ３の中央部下では半田接合層５の厚さが薄くて熱抵抗が小さくなり、半導体チップ３から伝熱する熱の放熱性も高まって半田層に生じる熱劣化，および熱劣化に起因する半田接合層５の亀裂（図５参照）の発生が抑制される。一方、半田接合部の外周部では十分な厚さの半田接合層５が確保されているので、熱サイクルに伴いこの外周のフィレット部分に集中する剪断応力は厚い半田接合層５により効果的に吸収緩和される。その結果、半田接合部のパワーサイクル耐性，長期信頼性が向上する。   According to the above bonding structure, the thickness of the solder bonding layer 5 is thin and the thermal resistance is small under the central portion of the semiconductor chip 3 having a high heat generation density due to energization, and the heat dissipation of heat transferred from the semiconductor chip 3 is also achieved. The thermal degradation that occurs in the solder layer and the occurrence of cracks (see FIG. 5) in the solder joint layer 5 due to the thermal degradation are suppressed. On the other hand, since the solder bonding layer 5 having a sufficient thickness is secured at the outer peripheral portion of the solder bonding portion, the shear stress concentrated on the outer fillet portion due to the thermal cycle is effectively absorbed by the thick solder bonding layer 5. Alleviated. As a result, the power cycle resistance and long-term reliability of the solder joint are improved.

次に、先記実施例１をさらに発展させた本発明の請求項２に対応する実施例を図２に示す。この実施例では、先記実施例１で述べた回路パターン２ｂの凸部２ｂ−１／半導体チップ３間を接合する鉛フリー半田（Ｓｎ−Ａｇ系半田）の層厚さｄを５μｍ以下に縮小設定して半田リフローする。このリフロー工程でリフロー温度を約２５０℃，時間を約２分として半田接合を行うと、熱履歴により半導体チップ３（チップ下面はＮｉメッキされている）／半田の接合界面，および回路パターン２ｂ（Ｃｕ）／半田の接合界面に金属間化合物５ａ（Ｓｎ−Ｎｉ，Ｓｎ−Ｃｕ化合物）が生成し、その層厚さは２．５μｍ程度まで成長するようになる。これにより、回路パターン２ｂの凸部上面と半導体チップ３の中央部下面との間の領域が殆ど金属間化合物５ａだけで接合された状態となる。これにより、半導体チップ３の中央部下の半田接合層５に対する熱劣化，亀裂の発生をより効果的に抑制することができる。なお、半田リフローで金属間化合物５ａが十分に成長せずに半田層が残ったとしても、半導体装置の実使用時における熱履歴により金属間化合物５ａの成長が進んで半導体チップ３の中央部下の接合層が全て金属間化合物となる。   Next, FIG. 2 shows an embodiment corresponding to claim 2 of the present invention, which is a further development of the first embodiment. In this embodiment, the layer thickness d of lead-free solder (Sn—Ag solder) that joins between the convex portion 2b-1 / semiconductor chip 3 of the circuit pattern 2b described in the first embodiment is reduced to 5 μm or less. Set and reflow solder. In this reflow process, when solder bonding is performed at a reflow temperature of about 250 ° C. and a time of about 2 minutes, the semiconductor chip 3 (the lower surface of the chip is Ni-plated) / solder bonding interface and the circuit pattern 2b (due to thermal history) The intermetallic compound 5a (Sn—Ni, Sn—Cu compound) is formed at the Cu / solder joint interface, and the layer thickness grows to about 2.5 μm. As a result, the region between the upper surface of the convex portion of the circuit pattern 2b and the lower surface of the central portion of the semiconductor chip 3 is almost joined by the intermetallic compound 5a alone. Thereby, it is possible to more effectively suppress the thermal deterioration and the occurrence of cracks in the solder bonding layer 5 below the central portion of the semiconductor chip 3. Even if the intermetallic compound 5a does not grow sufficiently by the solder reflow and the solder layer remains, the growth of the intermetallic compound 5a progresses due to the thermal history during actual use of the semiconductor device, so that All the bonding layers become intermetallic compounds.

一方、前記凸部２ｂ−１の外周側接合部では、凸部２ｂ−１の上面域に比べて半田層が厚いので金属間化合物５ａの成長は半田接合層５の一部に止まる。したがって、実使用時の温度サイクルに伴い外周部に集中する熱応力（剪断応力）は、金属間化合物５ａに比べて延性の高い半田層で吸収緩和される。   On the other hand, since the solder layer is thicker at the outer peripheral side joint portion of the convex portion 2 b-1 than the upper surface area of the convex portion 2 b-1, the growth of the intermetallic compound 5 a stops at a part of the solder joint layer 5. Therefore, the thermal stress (shear stress) concentrated on the outer peripheral part with the temperature cycle during actual use is absorbed and relaxed by the solder layer having higher ductility than the intermetallic compound 5a.

次に、本発明の請求項３に対応する実施例を図３に示す。この実施例では、回路パターン２ｂに形成した凸部２ｂ−１と半導体チップ３の中央部下面との接合にナノ金属ペーストを適用し、該接合部を囲む外周部の接合には鉛フリー半田を適用して接合している。   Next, an embodiment corresponding to claim 3 of the present invention is shown in FIG. In this embodiment, a nano metal paste is applied to the joint between the convex portion 2b-1 formed on the circuit pattern 2b and the lower surface of the central portion of the semiconductor chip 3, and lead-free solder is used to join the outer peripheral portion surrounding the joint portion. Applied and joined.

ここで、ナノ金属ペーストは、Ａｇ，Ｃｕなどの金属ナノ粒子，金属ナノ粒子が常温で凝集するのを抑制してナノ粒子を独立分散状態に保持する有機分散材（バインダ），加熱により有機分散材と反応して金属ナノ粒子を裸にする分散材捕捉材、および加熱により前記分散材と分散材捕捉材との反応物質を捕捉して揮散する揮発性有機成分（保護膜）を混合した組成であり、ペーストを加熱することによりバインダ−保護膜間で化学反応が進行してナノ金属粒子が裸の状態になり、その表面活性によりナノ金属粒子間，ナノ金属粒子／接合部の母材（回路パターン，半導体チップの金属メタライズ層）間で低温焼結が進行して最終的に金属同士で直接接合される。   Here, the nanometal paste is made of Ag, Cu, or other metal nanoparticles, an organic dispersion material (binder) that keeps the nanoparticles from aggregating at room temperature and maintaining the nanoparticles in an independently dispersed state, and organic dispersion by heating. Composition that mixes dispersion trapping material that reacts with the material to bare metal nanoparticles, and volatile organic component (protective film) that traps and volatilizes the reaction material between the dispersion material and the dispersion trapping material by heating When the paste is heated, the chemical reaction proceeds between the binder and the protective film, and the nano metal particles become bare, and the surface activity between the nano metal particles and the base metal of the nano metal particles / joint part ( The low temperature sintering proceeds between the circuit pattern and the metal metallization layer of the semiconductor chip, and finally the metals are directly joined together.

そして、回路パターン２に半導体チップ３を接合する工程では、回路パターン２ｂの凸部２ｂ−１上面にナノ金属ペーストをスクリ−ン印刷法などにより均一厚さに塗布し、その外周側には鉛フリー半田（Ｓｎ−Ａｇ系半田）を凸部２ｂ−１の段差分を含めた厚さに塗布しておく。次いで、半導体チップ３を重ね合わせた状態で加熱（加熱温度：２００〜２５０℃程度）し、加圧力を加えることにより、図示のように半導体チップ３の中央部下面と回路パターン２ｂの凸部２ｂ−１との間がナノ金属粒子接合層８により、またその外周側が層の厚い半田接合層５で接合されるようになる。   Then, in the step of bonding the semiconductor chip 3 to the circuit pattern 2, a nano metal paste is applied to the upper surface of the convex portion 2b-1 of the circuit pattern 2b to a uniform thickness by a screen printing method or the like, and the outer peripheral side is lead Free solder (Sn—Ag solder) is applied to a thickness including the level difference of the protrusion 2b-1. Next, the semiconductor chip 3 is heated in a superposed state (heating temperature: about 200 to 250 ° C.), and a pressure is applied, so that the lower surface of the central portion of the semiconductor chip 3 and the convex portion 2b of the circuit pattern 2b as shown in the figure. -1 is bonded by the nano metal particle bonding layer 8 and the outer peripheral side thereof is bonded by the thick solder bonding layer 5.

この接合構造によれば、半導体チップ３の中央部と回路パターン２ｂの凸部２ｂ−１との間が伝熱抵抗の小さなナノ金属粒子接合層８を介して金属接合されるので、従来の半田接合構造で問題となっていた半導体チップ３の中央部下の半田接合層における熱劣化，亀裂の発生（図５参照）を防止し、また、その外周側は層厚の厚い半田接合層５で半導体チップ３／回路パターン２ｂ間が接合されるので、先記の実施例１，２と同様に熱サイクルでフィレット部に集中する熱応力（剪断応力）が効果的に吸収緩和される。これにより、半導体装置として長期信頼性がより一層向上する。   According to this bonding structure, the central portion of the semiconductor chip 3 and the convex portion 2b-1 of the circuit pattern 2b are metal bonded via the nano metal particle bonding layer 8 having a small heat transfer resistance. Thermal degradation and cracking (see FIG. 5) in the solder bonding layer under the center of the semiconductor chip 3 which has been a problem in the bonding structure are prevented, and the outer peripheral side is made of a thick solder bonding layer 5 for the semiconductor. Since the chip 3 / circuit pattern 2b is joined, the thermal stress (shear stress) concentrated on the fillet portion in the thermal cycle is effectively absorbed and relaxed as in the first and second embodiments. Thereby, long-term reliability as a semiconductor device is further improved.

本発明の実施例１に対応する半導体チップ／回路パターン間の半田接合部の模式構造図で、（ａ）は断面側視図、（ｂ）は回路パターンの平面図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic structural diagram of a solder joint between a semiconductor chip and a circuit pattern corresponding to Example 1 of the present invention, where (a) is a sectional side view and (b) is a plan view of a circuit pattern. 本発明の実施例２に対応する半導体チップ／回路パターン間の半田接合部の模式構造図Schematic structural diagram of a solder joint between a semiconductor chip / circuit pattern corresponding to Example 2 of the present invention 本発明の実施例３に対応する半導体チップ／回路パターン間の半田接合部の模式構造図Schematic structure diagram of solder joint between semiconductor chip / circuit pattern corresponding to Example 3 of the present invention 本発明の実施対象となるＩＧＢＴモジュールの組立構造図Assembly structure diagram of IGBT module which is an object of the present invention 図４において半導体チップ／回路パターン間を鉛フリー半田で接合した場合に半導体チップの中央部下の発生する半田接合層の熱劣化，亀裂発生の様子を表した模式図Schematic diagram showing the state of thermal degradation and cracking of the solder joint layer generated under the center of the semiconductor chip when the semiconductor chip / circuit pattern is joined with lead-free solder in FIG.

１ 銅ベース
２ 絶縁基板
２ｂ 回路パターン
２ｂ−１ 凸部
３ 半導体チップ
５ 鉛フリー半田の半田接合層
５ａ 金属間化合物
８ ナノ金属粒子接合層 DESCRIPTION OF SYMBOLS 1 Copper base 2 Insulating substrate 2b Circuit pattern 2b-1 Convex part 3 Semiconductor chip 5 Solder joint layer of lead-free solder 5a Intermetallic compound 8 Nano metal particle joint layer

Claims (1)

絶縁基板の回路パターン上に鉛フリー半田を適用して半導体チップを半田マウントした半導体装置において、
半導体チップと回路パターンとの間の接合面を半導体チップの中央部下に対応する中央面域と、該中央面域を囲む外周面域とに分け、かつ回路パターンには前記中央面域に対応して台形状の凸部を形成した上で、該凸部と半導体チップの中央部との間をナノ金属粒子で金属接合し、その外周面域を鉛フリー半田で接合したことを特徴とする半導体装置。 In a semiconductor device in which a lead-free solder is applied onto a circuit pattern of an insulating substrate and a semiconductor chip is solder mounted,
The bonding surface between the semiconductor chip and the circuit pattern is divided into a central surface area corresponding to the lower part of the semiconductor chip and an outer peripheral surface area surrounding the central surface area, and the circuit pattern corresponds to the central surface area. In addition, a semiconductor having a trapezoidal convex portion, a metal joint between the convex portion and the central portion of the semiconductor chip with nano metal particles, and an outer peripheral surface region joined with lead-free solder. apparatus.
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