JP5191074B2 - Multilayer printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer printed wiring board.
[0002]
[Prior art]
A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like, on a resin board reinforced with a glass cloth of about 0.5 to 1.5 mm called a core, and copper It is produced by alternately laminating conductive circuits and interlayer resin insulation layers by the method described above. The connection between the conductor circuits through the interlayer resin insulating layer of the multilayer printed wiring board is made by via holes.
[0003]
Conventionally, a build-up multilayer printed wiring board is manufactured by a method disclosed in, for example, Japanese Patent Laid-Open No. 9-130050.
That is, first, a through hole is formed in a copper clad laminate to which a copper foil is attached, and then a through hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern using a photolithographic technique to form a conductor circuit. Next, a roughened surface is formed on the surface of the formed conductor circuit by electroless plating or etching, and an insulating resin layer is formed on the conductor circuit having the roughened surface, followed by exposure and development. Via hole openings are formed, and then an interlayer resin insulation layer is formed through UV curing and main curing.
[0004]
Further, after roughening the interlayer resin insulation layer with acid, oxidizing agent, etc., a thin electroless plating film is formed, a plating resist is formed on the electroless plating film, and then thickened by electrolytic plating. Etching is performed after the plating resist is peeled off to form a conductor circuit connected to the underlying conductor circuit by a via hole.
After repeating this process, a solder resist layer for protecting the conductor circuit is finally formed, and plating is applied to the exposed portions for connection to electronic components such as IC chips and motherboards, and soldering is performed. After forming the bump forming pads, a solder paste is printed on the electronic component side such as an IC chip to form solder bumps, thereby manufacturing a build-up multilayer printed wiring board. Further, if necessary, solder bumps are also formed on the mother board side.
[0005]
[Problems to be solved by the invention]
In recent years, with the increase in frequency of IC chips, there has been a demand for higher speed and higher density of multilayer printed wiring boards. As a multilayer printed wiring board corresponding to this, a stacked via structure (a via directly above a via hole) is required. A multilayer printed wiring board having via holes having a structure in which holes are formed has been proposed.
In such a multilayer printed wiring board having a via hole having a stacked via structure, since the signal transmission time is shortened, it is easy to cope with the high speed of the multilayer printed wiring board and the degree of freedom in designing the conductor circuit is improved. Therefore, it is easy to cope with higher density of the multilayer printed wiring board.
[0006]
However, in a multilayer printed wiring board having a via hole having such a stacked via structure, a crack may occur in the interlayer resin insulating layer in the vicinity of the via hole. In particular, when a stacked via structure in which three or more via holes are stacked is formed, a crack often occurs in the outermost interlayer resin insulation layer. Further, due to this crack, the outermost layer Separation or disconnection may occur in the conductor circuit around the interlayer resin insulation layer.
[0007]
[Means for Solving the Problems]
Therefore, the present inventors have examined the cause of the occurrence of cracks in the interlayer resin insulating layer (particularly, the outermost interlayer resin insulating layer) in the vicinity of the via hole when a via hole having a stacked via structure is formed.
As a result, via holes with a stacked via structure are usually formed in a field via shape suitable for forming a via hole immediately above each via hole, and the via holes are arranged linearly. Therefore, when stress is generated due to the difference in coefficient of linear expansion between the interlayer resin insulation layer and the via hole, the stress is difficult to be relaxed, especially in the uppermost via hole. In general, it is found that the external connection terminal such as a solder bump is formed on the upper part, and the stress is more easily relieved, and the stress is easily concentrated on this part. It was considered that this was the reason why cracks were likely to occur in the interlayer resin insulation layer (particularly, the outermost interlayer resin insulation layer).
[0008]
Furthermore, the present inventors have found that the above-described problems can be solved by forming a recess on the upper surface of the uppermost via hole in the multilayer printed wiring board in which the via holes of different levels are stacked, The present invention having the following contents has been achieved.
[0009]
That is, in the printed wiring board of the present invention, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes. A multilayer printed wiring board having a solder resist layer formed on the outer layer,
Among the above via holes, via holes of different levels are stacked,
Of the stacked via holes, the uppermost via hole is characterized in that a recess is formed on the upper surface thereof.
[0010]
In the multilayer printed wiring board of the present invention, it is desirable that the stacked via holes are stacked so that the centers of the respective via holes substantially overlap.
In the multilayer printed wiring board, at least one via hole among the stacked via holes is stacked with the other via hole shifted in the center, and the remaining via holes are stacked with the other via holes. It is also desirable that the holes are stacked so that their centers almost overlap.
[0011]
In the multilayer printed wiring board, the depth of the concave portion is preferably 5 to 25 μm.
In the multilayer printed wiring board, it is desirable that at least the outermost interlayer resin insulation layer among the interlayer resin insulation layers has a linear expansion coefficient of 100 ppm / ° C. or less.
[0012]
In the multilayer printed wiring board, it is desirable that at least the outermost interlayer resin insulating layer of the interlayer resin insulating layers is mixed with particles and a rubber component, and the particles include inorganic particles, resin It is desirable that it is at least one of particles and metal particles.
[0013]
In the multilayer printed wiring board, at least the outermost interlayer resin insulating layer among the interlayer resin insulating layers is a thermosetting resin, a photosensitive resin, a resin composite of a thermosetting resin and a thermoplastic resin. And it is desirable to form with the resin composition containing at least 1 sort (s) of the resin composite body of a thermosetting resin and a photosensitive resin.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
In the printed wiring board of the present invention, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, and further, the outermost layer is formed on the outermost layer. A multilayer printed wiring board on which a solder resist layer is formed,
Among the above via holes, via holes of different levels are stacked,
Of the stacked via holes, the uppermost via hole is characterized in that a recess is formed on the upper surface thereof.
[0015]
In the multilayer printed wiring board of the present invention, via holes of different levels are stacked, and among the stacked via holes, the uppermost via hole has a concave portion formed on the upper surface, so the upper surface is flat. It is easier to be deformed than a field-via-shaped via hole that is completely filled inside, and stress generated due to the difference in linear expansion coefficient between the via hole and the interlayer resin insulation layer can be easily relaxed. Therefore, the multilayer printed wiring board of the present invention does not concentrate a large stress in the uppermost via hole, and it is difficult to generate a crack in the interlayer resin insulating layer due to the concentration of the stress. Excellent.
In addition, since the wiring distance is shortened by stacking via holes of different levels, the signal transmission time can be shortened, the degree of freedom in designing the conductor circuit is improved, and high-density wiring is easily handled.
[0016]
The multilayer printed wiring board of the present invention will be described below with reference to the drawings.
1 and 2 are partial cross-sectional views schematically showing a part of an embodiment of the multilayer printed wiring board of the present invention.
[0017]
As shown in FIG. 1, in the multilayer printed wiring board 100, the conductor circuit 105 and the interlayer resin insulation layer 102 are sequentially laminated on the substrate 101, and the conductor circuits 105 via the interlayer resin insulation layer 102 are respectively separated. Connected via via holes. A solder resist layer 114 having solder bumps 117 is formed on the outermost layer.
[0018]
In the multilayer printed wiring board 100, of the stacked via holes 107a to 107d, the uppermost via hole (fourth via hole) 107d has a recess formed on the upper surface thereof.
The uppermost via hole in which the concave portion is formed in this way is easy to relieve stress, and therefore, large stress does not concentrate on the uppermost via hole. Therefore, inconveniences caused by the above-mentioned concentration of stress, that is, cracks occur in the interlayer resin insulation layer near the uppermost via hole, and the conductor circuit around the interlayer resin insulation layer is peeled off or disconnected due to this crack. The inconvenience that occurs is difficult to occur.
[0019]
The depth of the recess formed on the upper surface of the uppermost via hole is not particularly limited, but is preferably 5 to 25 μm.
If the depth of the concave portion is less than 5 μm, the stress relieving effect may not be sufficiently obtained. On the other hand, if the depth exceeds 25 μm, disconnection may occur in the via hole, or via hole and interlayer resin insulation This is because peeling may occur between the layers, leading to a decrease in reliability.
[0020]
In the multilayer printed wiring board 100, the via holes 107a to 107d are stacked such that the centers of the respective via holes substantially overlap.
In the multilayer printed wiring board of the present invention, it is desirable that the via holes in each layer are stacked so that their centers are substantially overlapped. In this case, since the wiring distance is shorter, the signal transmission time is reduced. It can be shortened, and the degree of freedom in designing the conductor circuit is improved.
[0021]
Further, as shown in FIG. 2, the multilayer printed wiring board 200 of the present invention has the via hole 207a to 207d stacked so that the uppermost via hole 207d is shifted to the lower via hole. It may be stacked.
In the multilayer printed wiring board of the present invention, of the stacked via holes, at least one via hole is stacked with the other via hole shifted in the center, and the remaining via holes are the other via holes. It is also desirable that the via holes are stacked so that their centers almost overlap.
[0022]
In this way, when at least one via hole is stacked with its center shifted, it is possible to disperse the stress generated due to the difference in linear expansion coefficient between the via hole and the interlayer resin insulation layer. In addition, since a large stress does not concentrate on a part of the stacked via holes, a crack is hardly generated in the interlayer resin insulating layer due to the concentration of the stress.
[0023]
When stacking at least one via hole on another via hole while shifting the center thereof, the stacked via hole is shaped so that only the uppermost via hole is the lower via hole as in the multilayer printed wiring board 200. The other via holes are not limited to a shape in which the centers are substantially overlapped, and the via holes are stacked in four stages, for example, the uppermost stage The via hole and the third via hole are stacked so that their centers almost overlap, and the lower via hole (second via hole) is stacked with the center shifted, and the first step Alternatively, the second via holes may be stacked so that the centers of the via holes substantially overlap. The via holes in the 2nd to 4th stages may be stacked so that the centers thereof are substantially overlapped, and this may be stacked with the center shifted from the center of the 1st stage via holes. May be stacked with the lower via hole shifted from the center.
Further, the number of via holes to be stacked is not particularly limited, and may be two or three, or five or more.
In the present specification, the center of the via hole refers to the center of the non-land portion of the via hole when the via hole is viewed in plan.
In this specification, the via holes are stacked in the stacked upper and lower via holes in the upper via hole (regardless of the land portion or non-land portion) and the upper via hole. A state where the bottom surface is electrically connected.
[0024]
Further, in this specification, the term “stacked so that the centers substantially overlap” means that the centers of the upper and lower via holes are of course horizontal when the centers of the upper and lower via holes are stacked. The case where the distance is 5 μm or less is included.
Therefore, in this specification, being stacked with the center shifted is the case where the horizontal distance between the centers of the stacked via holes exceeds 5 μm.
[0025]
In the multilayer printed wiring board of the present invention, the via holes stacked with their centers shifted are the outer edge portion (shown as A in FIG. 2) of the non-land portion of the lower via hole and the upper via hole. It is desirable that they are stacked so as not to overlap with the bottom surface (shown as B in FIG. 2).
When the outer edge of the non-land portion of the lower via hole and the bottom surface of the upper via hole are stacked, the stress generated in each via hole causes a part of the stacked via hole (for example, If the stack is made so that the outer edge of the non-land portion of the lower via hole and the bottom surface of the upper via hole do not overlap, The stress is dispersed in the holes, and the stress is less likely to concentrate in a part of the stacked via holes, and inconvenience due to the stress concentration is less likely to occur.
[0026]
The distance between the outer edge of the non-land portion of the lower via hole and the outer edge of the bottom surface of the upper via hole (indicated by L in FIG. 2) is specifically, for example, the non-land of the via hole. When the diameter of the portion is about 40 to 200 μm, the diameter is desirably 5 to 70 μm.
This is because within this range, it is difficult for stress to concentrate on a part of the via holes stacked as described above, and a degree of freedom in design can be ensured.
[0027]
Next, components constituting the multilayer printed wiring board of the present invention will be described.
In the multilayer printed wiring board of the present invention, the conductor circuit and the interlayer resin insulation layer are sequentially laminated on the substrate, the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, and the outermost layer A solder resist layer is formed.
[0028]
Examples of the substrate include insulating substrates such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine substrate, and a fluororesin substrate.
The conductor circuit is made of, for example, Cu, Ni, P, Pd, Co, W, an alloy thereof, or the like, and is formed by plating or the like. A specific method for forming a conductor circuit will be described in detail later.
[0029]
The substrate may be formed with through holes for connecting the conductor circuits formed on both sides thereof. In this case, it is desirable that a resin filler layer is formed in the through holes.
In the multilayer printed wiring board, a via hole may be formed immediately above the through hole. In this case, a resin filler layer is formed in the through hole, and a lid plating is formed on the through hole. It is desirable that a layer is formed. This is because the connection reliability between the via hole and the through hole becomes more excellent by forming the lid plating layer.
[0030]
Furthermore, in the multilayer printed wiring board of the present invention, a through hole penetrating the substrate and the interlayer resin insulating layer may be formed. By forming such a through hole, the conductor circuits sandwiching the substrate and the interlayer resin insulation layer can be electrically connected.
[0031]
The interlayer resin insulation layer is, for example, a thermosetting resin, a photosensitive resin, a thermoplastic resin, a resin composite of a thermosetting resin and a thermoplastic resin, a resin composite of a thermosetting resin and a photosensitive resin, or the like. It is formed by the resin composition containing this.
[0032]
Specific examples of the thermosetting resin include, for example, epoxy resins, phenol resins, polyimide resins, polyester resins, bismaleimide resins, polyolefin resins, polyphenylene ether resins, and the like.
[0033]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0034]
Examples of the polyolefin resin include polyethylene, polystyrene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.
[0035]
As said photosensitive resin, an acrylic resin etc. are mentioned, for example.
Moreover, what provided the photosensitivity to the above-mentioned thermosetting resin can also be used as a photosensitive resin. Specific examples include those obtained by reacting methacrylic acid or acrylic acid with a thermosetting group (for example, epoxy group in an epoxy resin) of a thermosetting resin to give an acrylic group.
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, and polysulfone.
[0036]
Examples of the resin composite of the thermosetting resin and the thermoplastic resin include those containing the above-described thermosetting resin and the above-described thermoplastic resin. Especially, what contains an epoxy resin and / or a phenol resin as a thermosetting resin, and contains a phenoxy resin and / or polyether sulfone (PES) as a thermoplastic resin is desirable.
Moreover, as a composite_body | complex of the said photosensitive resin and a thermoplastic resin, what contains above-described photosensitive resin and above-mentioned thermoplastic resin is mentioned, for example.
[0037]
Examples of the resin composition also include a roughened surface-forming resin composition. Examples of the roughened surface-forming resin composition include, in an uncured heat-resistant resin matrix that is hardly soluble in a roughened liquid consisting of at least one selected from an acid, an alkali, and an oxidizing agent. And a material in which a substance soluble in a roughening liquid comprising at least one selected from oxidizing agents is dispersed.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.
[0038]
The heat resistant resin matrix is preferably one that can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using the roughening liquid, for example, a thermosetting resin, a thermoplastic resin. Examples thereof include resins and composites thereof. Photosensitive resin may also be used. This is because when the via hole opening is formed, the opening can be formed by exposure and development processing.
[0039]
Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. Further, resins obtained by imparting photosensitivity to these thermosetting resins, that is, resins obtained by (meth) acrylation reaction of thermosetting groups using methacrylic acid or acrylic acid may be used. Specifically, (meth) acrylate of an epoxy resin is desirable, and an epoxy resin having two or more epoxy groups in one molecule is more desirable.
[0040]
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like. These may be used alone or in combination of two or more.
[0041]
Examples of the soluble substance include inorganic particles, resin particles, metal particles, rubber particles, liquid phase resins, and liquid phase rubbers. These may be used alone or in combination of two or more.
[0042]
Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide; potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate, and talc. And silicon compounds such as silica and zeolite. These may be used alone or in combination of two or more.
The alumina particles can be dissolved and removed with hydrofluoric acid, and calcium carbonate can be dissolved and removed with hydrochloric acid. Sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.
[0043]
Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the resin particles are immersed in a roughening solution made of at least one selected from an acid, an alkali, and an oxidizing agent, the heat resistance It is not particularly limited as long as it has a faster dissolution rate than the resin matrix. Specifically, for example, amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, Examples include polyphenylene resin, polyolefin resin, fluororesin, and bismaleimide-triazine resin. These may be used alone or in combination of two or more.
The resin particles must be previously cured. If not cured, the resin particles are dissolved in a solvent that dissolves the resin matrix, so they are uniformly mixed, and only the resin particles cannot be selectively dissolved and removed with an acid or an oxidizing agent. is there.
[0044]
Examples of the metal particles include gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead, and the like. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.
[0045]
Moreover, when using the resin composition containing a thermosetting resin as such a resin composition, it is desirable to use a thing with a glass transition temperature of 180 degrees C or less.
This is because, in a resin composition having a glass transition temperature exceeding 180 ° C., the temperature at the time of heat curing exceeds 200 ° C., the substrate may be warped at the time of heating or inconvenience at the time of melting may occur.
[0046]
In the multilayer printed wiring board, at least the outermost interlayer resin insulation layer preferably has a linear expansion coefficient of 100 ppm / ° C. or less, and all the interlayer resin insulation layers have a linear expansion coefficient of 100 ppm / ° C. or less. More desirable.
Thus, when the linear expansion coefficient of the interlayer resin insulation layer is small, stress due to the difference in the linear expansion coefficient is not easily generated between the interlayer resin insulation layer and the via hole, the substrate, or the conductor circuit. Peeling between the insulating layer and the via hole and cracking in the interlayer resin insulating layer are less likely to occur. Therefore, the multilayer printed wiring board on which the interlayer resin insulation layer having the linear expansion coefficient in the above range is formed is more reliable.
[0047]
The linear expansion coefficient of the interlayer resin insulation layer is more preferably 30 to 90 ppm / ° C. When the linear expansion coefficient is less than 30 ppm / ° C., the rigidity is high. For example, when the roughened surface is formed on the surface, the unevenness of the roughened surface may not be retained, whereas the above range is acceptable. This is because it is more excellent in crack resistance and excellent in shape retention of the roughened surface.
[0048]
Further, it is desirable that particles and a rubber component are blended in the interlayer resin insulation layer.
When the particles are blended, the shape retention of the interlayer resin insulation layer is further improved, and when the rubber component is blended, stress is applied to the interlayer resin insulation layer due to the flexibility and rebound resilience of the rubber component. This can absorb or relieve the stress when acting.
[0049]
The particles are preferably at least one of inorganic particles, resin particles, and metal particles.
Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide; potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate, and talc. And those composed of silicon compounds such as silica and zeolite. These may be used alone or in combination of two or more.
[0050]
Examples of the resin particles include amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins, bismaleimide-triazines, and the like. Things. These may be used alone or in combination of two or more.
[0051]
As said metal particle, what consists of gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead etc. is mentioned, for example. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.
[0052]
Examples of the rubber component include acrylonitrile-butadiene rubber, polychloroprene rubber, polyisoprene rubber, acrylic rubber, polysulfur type rigid rubber, fluorine rubber, urethane rubber, silicone rubber, ABS resin, and the like.
Further, polybutadiene rubbers; various modified polybutadiene rubbers such as epoxy modification, urethane modification, (meth) acrylonitrile modification, (meth) acrylonitrile butadiene rubber containing a carboxyl group, and the like can also be used.
[0053]
The blending amount of the particles and the rubber component is not particularly limited, but the blending amount after forming the interlayer resin insulation layer is desirably 1 to 25% by weight for the particles and 5 to 20% by weight for the rubber component. This is because, within this range, it is suitable for matching the thermal expansion coefficient with the substrate and the solder resist layer, and for relieving stress due to curing shrinkage when forming the interlayer resin insulation layer. More desirable amounts are 3 to 18% by weight for the particles and 7 to 18% by weight for the rubber component.
[0054]
The via hole is made of, for example, Cu, Ni, P, Pd, Co, W, alloys thereof, or the like, as in the case of the conductor circuit, and is formed by plating or the like.
Moreover, in the multilayer printed wiring board, among the stacked via holes, the uppermost via hole has a recess formed on the upper surface thereof, but the shape of the other via holes is not particularly limited, and the upper via hole is formed on the upper surface. It may have a shape with a recess or a field via shape.
Here, when the via hole shape other than the uppermost stage is a field via shape, the upper surface is flat, which is suitable for stacking via holes.
In the multilayer printed wiring board of the present invention, via holes of different levels are not stacked, and there may be via holes in which other via holes are not stacked.
Note that a via hole having a recess formed on the upper surface and a via hole having a field via shape, and methods of forming each will be described in detail later.
[0055]
In the stacked via holes, it is desirable that at least one of the via holes has a land diameter different from that of other via holes. When the stacked via holes have such a structure, the via hole having a large land diameter serves as a reinforcing material for the interlayer resin insulation layer, and the mechanical strength of the interlayer resin insulation layer is improved, and the via hole is improved. This is because cracks are less likely to occur in the nearby interlayer resin insulation layer.
[0056]
The solder resist layer is formed using a solder resist composition containing, for example, a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, an epoxy resin, a polyimide resin, or the like.
[0057]
Examples of solder resist compositions other than those described above include (meth) acrylates of novolak epoxy resins, imidazole curing agents, bifunctional (meth) acrylate monomers, and (meth) acrylate esters having a molecular weight of about 500 to 5,000. Examples include a polymer, a thermosetting resin composed of a bisphenol type epoxy resin, a photosensitive monomer such as a polyvalent acrylic monomer, a paste-like fluid containing a glycol ether solvent, and the viscosity is 1 to 25 ° C. It is desirable that the pressure is adjusted to 10 Pa · s.
The solder resist composition may contain an elastomer or an inorganic filler.
Moreover, as a soldering resist composition, a commercially available soldering resist composition can also be used.
[0058]
Next, a method for producing the multilayer printed wiring board of the present invention will be described in the order of steps.
(1) First, a conductive circuit is formed on a substrate using the above-described resin substrate, a copper-clad laminate with copper foil attached to both sides thereof, or the like as a starting material.
Specifically, for example, after forming a solid conductor layer by performing electroless plating treatment on both surfaces of the substrate, an etching resist corresponding to the conductor circuit pattern is formed on the conductor layer, and then etching is performed. What is necessary is just to form by performing.
Moreover, you may use a copper clad laminated board as a board | substrate with which the solid conductor layer was formed.
[0059]
In addition, when forming a through hole for connecting between conductor circuits formed on both sides of a substrate, a through hole is previously formed in the substrate, and an electroless plating process is also applied to the wall surface of the through hole. Thus, a through hole is formed to connect between conductor circuits sandwiching the substrate.
[0060]
Further, after forming the through hole, it is desirable to fill the through hole with a resin filler. At this time, it is desirable to fill the resin filler in the conductor circuit non-formed portion.
Examples of the resin filler include a resin composition containing an epoxy resin, a curing agent, and inorganic particles.
Further, when the resin filler is filled in the through hole or in the conductor circuit non-forming portion, the wall surface of the through hole or the side surface of the conductor circuit may be roughened in advance.
This is because the adhesion between the resin filler and the through-holes is improved.
In addition, as a roughening process method, the method similar to the method used at the process of (2) mentioned later can be used.
[0061]
Moreover, when forming a cover plating layer on the said through hole, this cover plating layer can be formed by passing through the process of the following (a)-(c), for example.
That is, (a) after forming the through hole having the resin filler layer inside through the above-described steps, the surface of the substrate including the exposed surface of the resin filler layer is subjected to electroless plating treatment or sputtering. To form a thin film conductor layer. In addition, when using an electroless-plating process, a catalyst is previously provided to the to-be-plated surface.
[0062]
(B) Next, a plating resist is formed on portions other than on the through holes (including the resin filler layer), and electrolytic plating is performed using the thin film conductor layer as a plating lead.
(C) Next, after the completion of electrolytic plating, the plating resist is peeled off and the thin film conductor layer under the plating resist is removed.
Through the steps (a) to (c), a lid plating layer composed of two layers of a thin film conductor layer and an electrolytic plating layer can be formed.
The steps (a) to (c) from application of the catalyst to removal of the thin film conductor layer are performed using the same method as used in the steps (6) to (8) described later. Can do.
[0063]
In the case of forming a lid plating layer consisting of one layer, for example, after applying a catalyst to the surface of the substrate including the exposed surface of the resin filler layer, a plating resist is formed on portions other than on the through holes, Thereafter, electroless plating treatment and removal of the plating resist may be performed.
[0064]
(2) Next, the surface of the conductor circuit is roughened as necessary. Examples of the roughening treatment method include blackening (oxidation) -reduction treatment, etching treatment using a mixed solution containing an organic acid and a cupric complex, treatment by Cu-Ni-P needle alloy plating, and the like. Can be used. The roughening treatment performed in this step is performed in order to ensure adhesion between the interlayer resin insulating layer formed through a subsequent step, and when the adhesion between the conductor circuit and the interlayer resin insulating layer is high, This step may not be performed.
[0065]
(3) Next, an uncured resin layer made of a thermosetting resin, a photosensitive resin, or a resin composite is formed on the conductor circuit, or a resin layer made of a thermoplastic resin is formed.
The uncured resin layer may be formed by applying uncured resin with a roll coater, curtain coater, or the like, or may be formed by thermocompression bonding of an uncured (semi-cured) resin film. . Furthermore, you may affix the resin film in which metal layers, such as copper foil, were formed in the single side | surface of an uncured resin film.
The resin layer made of a thermoplastic resin is preferably formed by thermocompression bonding a resin molded body formed into a film shape.
[0066]
(4) Next, in the case of forming an interlayer resin insulation layer using a thermosetting resin or a resin composite containing a thermosetting resin as the material, the uncured resin layer is subjected to a curing treatment, Openings for via holes are formed to form interlayer resin insulation layers.
The via hole opening is preferably formed by laser processing. The laser treatment may be performed before the curing treatment or after the curing treatment.
Moreover, when forming the interlayer resin insulation layer which consists of photosensitive resin or the resin composite containing photosensitive resin, you may provide the opening for via holes by performing exposure and image development processing. In this case, the exposure and development processes are performed before the curing process.
[0067]
When an interlayer resin insulation layer using a thermoplastic resin as the material is formed, a via hole opening can be formed in the resin layer made of the thermoplastic resin by laser processing to form an interlayer resin insulation layer. .
[0068]
At this time, examples of the laser to be used include a carbon dioxide laser, an excimer laser, a UV laser, and a YAG laser. These may be used properly in consideration of the shape of the via hole opening to be formed.
[0069]
In the case of forming the via hole openings, a large number of via hole openings can be formed at a time by irradiating laser light with a hologram type excimer laser through a mask.
In addition, when a via hole opening is formed using a short pulse carbon dioxide laser, there is little resin residue in the opening, and damage to the resin at the periphery of the opening is small.
[0070]
When laser light is irradiated through the optical system lens and the mask, a large number of via hole openings can be formed at one time.
This is because laser light having the same intensity and the same irradiation angle can be simultaneously irradiated to a plurality of portions through the optical system lens and the mask.
[0071]
Moreover, the thickness of the interlayer resin insulation layer is not particularly limited, but normally 5 to 50 μm is desirable. Further, the opening diameter of the via hole opening is not particularly limited, but is usually preferably 40 to 200 μm.
[0072]
Further, when forming a through hole for connecting between the conductor circuits sandwiching the substrate and the interlayer resin insulation layer, a through hole penetrating the interlayer resin insulation layer and the substrate is formed in this step. The through hole can be formed using drilling, laser processing, or the like.
[0073]
(5) Next, a roughened surface is formed on the surface of the interlayer resin insulating layer including the inner wall of the opening for the via hole using an acid or an oxidizing agent as necessary.
This roughened surface is formed in order to improve the adhesion between the interlayer resin insulation layer and the thin film conductor layer formed thereon, and provides sufficient adhesion between the interlayer resin insulation layer and the thin film conductor layer. If there is a property, it may not be formed. Moreover, when the through-hole which penetrates a board | substrate and an interlayer resin insulation layer is formed, you may form a roughening surface in the wall surface.
[0074]
Examples of the acid include sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, formic acid, and examples of the oxidizing agent include permanganates such as chromic acid, chromium sulfuric acid, and sodium permanganate.
In addition, after the roughened surface is formed, it is desirable to neutralize the surface of the interlayer resin insulation layer using an aqueous solution such as an alkali or a neutralizing solution. This is because the influence of an acid or an oxidizing agent can be prevented in the next step.
In addition, the roughened surface may be formed using plasma treatment or the like.
[0075]
(6) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulation layer provided with the via hole opening.
The thin film conductor layer can be formed using a method such as electroless plating, sputtering, or vapor deposition. When the roughened surface is not formed on the surface of the interlayer resin insulating layer, the thin film conductor layer is preferably formed by sputtering.
In addition, when forming a thin film conductor layer by electroless plating, the catalyst is previously provided to the to-be-plated surface. Examples of the catalyst include palladium chloride.
[0076]
The thickness of the thin film conductor layer is not particularly limited, but when the thin film conductor layer is formed by electroless plating, 0.6 to 1.2 μm is desirable, and when formed by sputtering, 0.1 to 0.1 μm is preferable. 1.0 μm is desirable.
[0077]
Further, when a through hole penetrating the substrate and the interlayer resin insulating layer is formed in the step (4), a thin film conductor layer is also formed in the through hole to form a through hole. In this case, it is desirable to form a resin filler layer in the through hole, and then a lid plating layer may be formed on the through hole. In particular, when a via hole is formed in a post process on the through hole formed here, it is desirable to form a lid plating layer.
[0078]
The through hole formed in this way connects the conductor circuit between the substrate and the interlayer resin insulation layer, as well as the two layers formed on both surfaces of the two-layer conductor circuit and the substrate. A total of four conductor circuits may be connected to the other conductor circuit.
[0079]
(7) Next, a plating resist is formed on a part of the thin film conductor layer by using a dry film or the like, and then electrolytic plating is performed using the thin film conductor layer as a plating lead. A plating layer is formed.
Here, the plating resist is formed so that a via hole having a desired land diameter can be formed. That is, if a via hole having a large land diameter is to be formed at this level, the width of the plating resist non-forming portion may be increased.
[0080]
Further, in this step, by appropriately selecting the composition of the electroplating solution, it is possible to form an electrolytic plating layer having a recess on its upper surface or an electrolytic plating layer having a flat upper surface. For example, when forming an electrolytic copper plating layer using an electrolytic copper plating solution, an electrolytic copper plating solution containing sulfuric acid, copper sulfate, and additives can be used.
[0081]
In addition, when an electrolytic copper plating solution containing an additive composed of a specific leveling agent and a brightening agent is used among the electrolytic copper plating solutions, an electrolytic copper plating layer having a flat upper surface is formed. Can do.
That is, it contains 50 to 300 g / l of copper sulfate, 30 to 200 g / l of sulfuric acid, 25 to 90 mg / l of chlorine ions, and 1 to 1000 mg / l of an additive comprising at least a leveling agent and a brightener. By using an electrolytic copper plating solution, an electrolytic copper plating layer having a flat upper surface can be formed.
[0082]
The electrolytic copper plating solution having such a composition completely fills the opening for the via hole regardless of the opening diameter of the via hole, the material and thickness of the resin insulating layer, and the presence or absence of the roughened surface of the interlayer resin insulating layer. be able to.
In addition, since the electrolytic copper plating solution contains copper ions at a high concentration, the copper ions are sufficiently supplied to the opening for the via hole, and the opening for the via hole is plated at a plating rate of 40 to 100 μm / hour. It can be plated, leading to faster electroplating process.
[0083]
The electrolytic copper plating solution is 100 to 250 g / l of copper sulfate, 50 to 150 g / l of sulfuric acid, 30 to 70 mg / l of chlorine ions, and 1 to 600 mg / l of at least a leveling agent and a brightener. It is desirable that the composition contains 1 additive.
[0084]
Moreover, in the said electrolytic copper plating solution, the said additive should just consist of a leveling agent and a brightener at least, and may contain the other component.
Here, examples of the leveling agent include polyethylene, gelatin, and derivatives thereof.
Examples of the brightener include sulfur oxides and related compounds, hydrogen sulfide and related compounds, and other sulfur compounds.
[0085]
The blending amount of the leveling agent is desirably 1 to 1000 mg / l, and the blending amount of the brightener is desirably 0.1 to 100 mg / l. Moreover, as for the mixture ratio of both, 2: 1-10: 1 are desirable.
Further, when an electroplating layer having a flat upper surface is formed using such an electrolytic copper plating solution, the shape of a via hole formed through a subsequent process becomes a field via shape.
[0086]
In addition, when forming the electroplating layer which has a recessed part on the upper surface, conventionally well-known electrolytic copper plating solution, ie, 120-250 g / l sulfuric acid, 30-100 g / l copper sulfate, and various additives, for example. An electrolytic copper plating solution containing can be used.
[0087]
Further, in this step, after forming an electrolytic plating layer having a recess on the upper surface, the electrolytic copper plating layer having a flat upper surface may be formed by filling the recess with a conductive paste. After forming an electrolytic plating layer having a recess on its upper surface, the recess is filled with a resin filler, and further, a lid plating layer is formed thereon to form an electrolytic copper plating layer having a flat upper surface. May be.
[0088]
(8) Next, the plating resist is peeled off, and the thin film conductor layer existing under the plating resist is removed by etching to form an independent conductor circuit (including via holes). Examples of the etchant include sulfuric acid-hydrogen peroxide aqueous solution, persulfate aqueous solution such as ammonium persulfate, ferric chloride, cupric chloride, hydrochloric acid and the like. Moreover, you may use the mixed solution containing a cupric complex and an organic acid as etching liquid.
[0089]
Moreover, it may replace with the method described in said (7) and (8), and may form a conductor circuit by using the following method.
That is, after an electrolytic plating layer is formed on the entire surface of the thin film conductor layer, an etching resist is formed on a part of the electrolytic plating layer using a dry film, and then the electrolytic plating layer under the etching resist non-forming portion and The thin-film conductor layer may be removed by etching, and an independent conductor circuit (including a via hole) may be formed by removing the etching resist.
[0090]
(9) Thereafter, the above steps (3) to (8) are repeated once or twice or more to further form an upper interlayer resin insulation layer and a conductor circuit (including via holes). In addition, what is necessary is just to select suitably how many times the said process of (3)-(8) is repeated according to the design of a multilayer printed wiring board.
[0091]
Here, the steps (3) to (8) are repeated so that the via hole is stacked on the lower via hole. Specifically, in the step (4), the formation position of the via hole can be adjusted by adjusting the formation position of the via hole opening.
In addition, by adjusting the formation position of the via hole opening, the upper via hole is stacked so that the center of the lower via hole and the center thereof are almost overlapped, or the upper via hole is shifted to the lower via hole. It can be stacked.
[0092]
Further, in the last repetition step when the steps (3) to (8) are repeated, that is, the step of forming the outermost interlayer resin insulation layer and the uppermost via hole, the step (7) When the electrolytic plating layer is formed, the electrolytic plating layer having a recess on the upper surface is formed. By forming such an electrolytic plating layer, a via hole having a recess formed on the upper surface thereof can be formed.
[0093]
Further, in the steps (7) and (8), when a through hole is formed through the substrate and the interlayer resin insulating layer, a via hole may be formed immediately above the through hole.
[0094]
(10) Next, a solder resist layer having a plurality of solder bump forming openings is formed on the substrate including the uppermost conductor circuit.
Specifically, after applying an uncured solder resist composition with a roll coater or curtain coater, or after crimping a solder resist composition formed into a film, solder bumps are formed by laser processing or exposure development processing. A solder resist layer is formed by forming an opening for use and, if necessary, performing a curing treatment.
[0095]
Further, examples of the laser used when forming the solder bump forming opening include the same lasers as those used when forming the above-described via hole opening.
[0096]
Next, if necessary, solder pads are formed on the surface of the conductor circuit exposed at the bottom surface of the solder bump forming opening.
The solder pad can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, or platinum.
Specifically, it is desirable to form with a metal such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
The solder pad can be formed by using, for example, a method such as plating, vapor deposition, or electrodeposition. Among these, plating is preferable because the uniformity of the coating layer is excellent.
[0097]
(11) Next, the solder bump forming openings are filled with a solder paste and subjected to a reflow process, or after being filled with a solder paste, a conductive pin is attached, and a reflow process is further performed. BGA (Ball Grid Array) and PGA (Pin Grid Array) are formed.
In addition, plasma treatment with oxygen, carbon tetrachloride, or the like may be performed in a timely manner for a character printing process for forming product recognition characters or the like or for modifying the solder resist layer.
The multilayer printed wiring board of the present invention can be manufactured through such steps.
[0098]
【Example】
Hereinafter, the present invention will be described in more detail.
[0099]
Example 1
A. Preparation of photosensitive resin composition A
(i) 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) at a concentration of 80% by weight in diethylene glycol dimethyl ether (DMDG), a photosensitive monomer ( Toa Gosei Co., Ltd., Aronix M315) 3.15 parts by weight, defoamer (Sannopco S-65) 0.5 part by weight and N-methylpyrrolidone (NMP) 3.6 parts by weight are placed in a container and mixed with stirring. A mixed composition was prepared.
[0100]
(ii) 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 1.0 μm and an average particle size of 0.5 μm 09 parts by weight was put in another container and stirred and mixed, and then 30 parts by weight of NMP was further added and stirred and mixed by a bead mill to prepare another mixed composition.
[0101]
(iii) Imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) 2 parts by weight, photopolymerization initiator (Ciba Specialty Chemicals Co., Ltd., Irgacure I-907) 2 parts by weight, photosensitizer (Nippon Kasei) A mixed composition was prepared by further taking 0.2 parts by weight of DETX-S (manufactured by Yakuhin Co., Ltd.) and 1.5 parts by weight of NMP in another container and stirring and mixing them.
And the photosensitive resin composition A was obtained by mixing the mixed composition prepared by (i), (ii), and (iii).
[0102]
B. Preparation of photosensitive resin composition B
(i) 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) at a concentration of 80% by weight in diethylene glycol dimethyl ether (DMDG), a photosensitive monomer ( Toa Gosei Co., Ltd., Aronix M315) 4 parts by weight, antifoaming agent (Sannopco S-65) 0.5 part by weight and N-methylpyrrolidone (NMP) 3.6 parts by weight are put into a container and mixed by stirring. A mixed composition was prepared.
[0103]
(ii) 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 0.5 μm were put in another container and stirred and mixed. Thereafter, 30 parts by weight of NMP was further added and stirred and mixed with a bead mill to prepare another mixed composition.
[0104]
(iii) Imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) 2 parts by weight, photopolymerization initiator (Ciba Specialty Chemicals Co., Ltd., Irgacure I-907) 2 parts by weight, photosensitizer (Nippon Kasei) A mixed composition was prepared by further taking 0.2 parts by weight of DETX-S (manufactured by Yakuhin Co., Ltd.) and 1.5 parts by weight of NMP in another container and stirring and mixing them.
Then, the photosensitive resin composition B was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).
[0105]
C. Preparation of resin filler
100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), SiO having an average particle diameter of 1.6 μm and a maximum particle diameter of 15 μm or less coated with a silane coupling agent on the surface₂By taking 72 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) in a container, the viscosity is 30 to 25 ° C. at 25 ± 1 ° C. An 80 Pa · s resin filler was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
[0106]
D. Manufacturing method of multilayer printed wiring board
(1) A copper-clad laminate in which 18 μm copper foil 8 is laminated on both surfaces of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material (FIG. 3 ( a)). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern to form the lower conductor circuit 4 and the through hole 9 on both surfaces of the substrate 1 (FIG. 3 (b) )reference).
[0107]
(2) The substrate on which the through hole 9 and the lower conductor circuit 4 are formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reducing bath was performed, and a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 4 including the through holes 9.
[0108]
(3) Next, after preparing the resin filler described in C above, within 24 hours after adjustment by the following method, the conductor circuit non-formed portion of the substrate 1 and the lower conductor circuit 4 within the through hole 9 A layer 10 ′ of resin filler was formed on the outer edge of each.
That is, first, a resin filler was pushed into a through hole using a squeegee, and then dried under conditions of 100 ° C. and 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-forming portion is placed on the substrate, and a resin filler layer 10 'is formed on the conductor circuit non-forming portion, which is a recess, using a squeegee. The film was dried at 20 ° C. for 20 minutes (see FIG. 3C).
[0109]
(4) One side of the substrate after the processing of (3) above is applied to the surface of the lower conductor circuit 4 or the land surface of the through hole 9 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that the resin filler did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, a heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to form the resin filler layer 10.
[0110]
In this way, the surface layer portion of the resin filler layer 10 and the surface of the lower conductor circuit 4 formed in the through hole 9 and the conductor circuit non-forming portion are flattened, and the side surface 4a of the resin filler layer 10 and the lower conductor circuit 4 is flattened. And an insulative substrate in which the inner wall surface 9a of the through hole 9 and the resin filler layer 10 are firmly adhered through the roughened surface (FIG. 3D). )reference). That is, by this step, the surface of the resin filler layer 10 and the surface of the lower conductor circuit 4 are flush.
[0111]
(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surface of the lower conductor circuit 4 and the land surface of the through hole 9. Thus, a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 4. As an etchant, an etchant (MEC Etch Bond, manufactured by MEC Co., Ltd.) comprising 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.
[0112]
(6) Next, the photosensitive resin composition B prepared in B above (viscosity: 1.5 Pa · s) was applied to both sides of the substrate using a roll coater within 24 hours after preparation, and 20 in a horizontal state. After standing for a minute, drying (prebaking) was performed at 60 ° C. for 30 minutes. Next, the photosensitive resin composition A prepared in A above (viscosity: 7 Pa · s) was applied using a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes in the same manner, and then at 60 ° C. Drying (prebaking) for 30 minutes was performed to form two-layered resin layers 2a and 2b in a semi-cured state (see FIG. 3 (e)).
[0113]
(7) Next, a photomask film on which a black circle having a diameter of 80 μm is printed is adhered to both surfaces of the substrate on which the semi-cured resin layers 2a and 2b are formed, and 500 mJ / cm using an ultrahigh pressure mercury lamp.²And then developed with a DMDG solution. Thereafter, this substrate was further 3,000 mJ / cm with an ultra-high pressure mercury lamp.²Exposed at 100 ° C., heat-treated at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 at 3 hours, and has a via hole opening 6 with a diameter of 80 μm that is excellent in dimensional accuracy equivalent to a photomask film. An interlayer resin insulation layer 2 composed of two layers was formed (see FIG. 4A).
[0114]
(8) Furthermore, the substrate on which the via hole opening 6 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve the epoxy resin particles present on the surface of the interlayer resin insulation layer 2 By removing the surface, the surface of the interlayer resin insulating layer 2 including the inner wall of the via-hole opening 6 was made rough (not shown).
[0115]
(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, a palladium catalyst (manufactured by Atotech Co., Ltd.) is applied to the surface of the roughened substrate (roughening depth: 3 μm), whereby a catalyst is formed on the surface of the interlayer resin insulation layer 2 and the inner wall surface of the via hole opening 6. Nuclei were attached.
[0116]
(10) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a thin-film conductor layer 12 having a thickness of 0.6 to 3.0 μm over the entire rough surface (FIG. 4B). reference).
[Electroless plating aqueous solution]
NiSO₄                 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0117]
(11) Next, a commercially available photosensitive dry film is affixed to the thin film conductor layer 12, and a mask is placed thereon, and 100 mJ / cm.²Then, a plating resist 3 was provided by developing with a 0.8% aqueous sodium carbonate solution (see FIG. 4C).
[0118]
(12) Next, the substrate is washed with 50 ° C. water, degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. It formed (refer FIG.4 (d)).
(Electrolytic plating aqueous solution)
CuSO₄・ 5H₂O 210g / l
Sulfuric acid 150g / l
Cl⁻                          40 mg / l
Polyethylene glycol 300mg / l
Bisdisulfide 100mg / l
[Electrolytic plating conditions]
Current density 1.0A / dm²
60 minutes
Temperature 25 ℃
[0119]
(13) Subsequently, the plating resist 3 was peeled and removed in a 40 g / l NaOH aqueous solution at 50 ° C. Thereafter, the substrate is heated at 150 ° C. for 1 hour, and the thin film conductor layer existing under the plating resist is removed by using an etching solution containing sulfuric acid-hydrogen peroxide aqueous solution. A via hole 7 having a shape was formed (see FIG. 5A).
[0120]
(14) By repeating the steps (5) to (13), a conductor circuit 5 independent of the upper interlayer resin insulation layer 2 and a via-hole 7 having a filled via shape are formed (FIG. 5B). To FIG. 6 (a)).
Here, the second-stage via hole is formed so that the center of the first-stage via hole and the center thereof are substantially overlapped by adjusting the formation position of the via-hole opening.
[0121]
(15) Further, by repeating the steps (5) to (11) above, an upper interlayer resin insulation layer 2 and a thin film conductor layer 12 are further formed, and then the plating resist 3 is formed on the thin film conductor layer 12. Provided (see FIG. 6B).
[0122]
(16) Next, the substrate on which the plating resist 3 is formed is washed and degreased with water at 50 ° C., washed with water at 25 ° C. and further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. The electrolytic copper plating layer 13 was formed (see FIG. 6C). An electrolytic plating layer 13a having a recess on the upper surface was formed in the opening for the via hole.
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1.0 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0123]
(17) Next, in the same manner as in the above step (13), the plating resist 3 is removed and the thin film conductor layer 12 is etched, and an independent conductor circuit and a via hole 7a having a recess on its upper surface Was formed (see FIG. 7A). Here, by adjusting the formation position of the via hole opening, the uppermost via hole is formed so that the second via hole and the center thereof are substantially overlapped.
[0124]
(18) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 15.0 parts by weight, imidazole curing agent (Shikoku 1.6 parts by weight manufactured by Kasei Co., Ltd., trade name: 2E4MZ-CN), 3.0 parts by weight of polyvalent acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604), which is a photosensitive monomer, Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoam (San Nopco, S-65) 0.7 Part by weight is placed in a container, and a mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator and Michler's ketone as a photosensitizer are mixed with this mixture composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. The viscosity is measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) for 60 minutes.^-1(Rpm), rotor No. 4, 6 min^-1(Rpm), rotor No. 3 according.
[0125]
(19) Next, the solder resist composition is applied to both surfaces of the multilayer wiring board to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the solder pad A photomask with a thickness of 5 mm on which a pattern of 10 mm was drawn was brought into close contact with the solder resist layer and 1000 mJ / cm²Were exposed to UV light and developed with DMTG solution to form an opening having a diameter of 80 μm.
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. Then, a solder resist layer 14 having a thickness of 20 μm was formed.
[0126]
(20) Next, the substrate on which the solder resist layer 14 is formed is immersed in an etching solution containing sodium persulfate as a main component for 1 minute, and a roughened surface having an average roughness (Ra) of 1 μm or less on the surface of the conductor circuit. (Not shown) was formed.
Further, this substrate was made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 15 having a thickness of 5 μm was formed in the opening by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (.1.7 × 10^-1mol / l) is immersed in an electroless gold plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm-thick gold plating layer 16 on the nickel plating layer 15 as a solder pad. .
[0127]
(21) Thereafter, a mask was placed on the solder resist layer 14, and a solder paste was printed on the solder bump forming openings using a piston-type press-fitting printer. Thereafter, the solder paste was reflowed at 250 ° C. and further flux cleaning was performed to obtain a multilayer printed wiring board provided with solder bumps (see FIG. 7B).
The linear expansion coefficient of the interlayer resin insulation layer formed in this example is 70 ppm / ° C.
[0128]
(Example 2)
A. Preparation of resin film for interlayer resin insulation layer
30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy Co., Ltd.), 40 parts by weight of cresol novolac type epoxy resin (epoxy equivalent 215, Epiklon N-673 manufactured by Dainippon Ink and Chemicals, Inc.), triazine 30 parts by weight of a structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 manufactured by Dainippon Ink & Chemicals, Inc.) was dissolved in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha with stirring. Thereto, terminal epoxidized polybutadiene rubber (Nagase Kasei Kogyo Denarex R-45EPT) 12 parts by weight, 2-phenyl-4,5-bis (hydroxymethyl) imidazole pulverized product 1.5 parts by weight, finely pulverized silica 4 parts by weight , Silicon Added to prepare an epoxy resin composition agent 0.5 parts by weight.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.
[0129]
B. Preparation of resin filler
A resin filler was prepared in the same manner as in Example 1.
C. Manufacture of multilayer printed wiring boards
(1) A copper-clad laminate in which 18 μm copper foil 28 is laminated on both surfaces of an insulating substrate 21 made of glass epoxy resin or BT resin having a thickness of 0.8 mm was used as a starting material (see FIG. 8A). ). First, this copper-clad laminate was etched into a lower conductor circuit pattern to form lower conductor circuits 24 on both surfaces of the substrate (see FIG. 8B).
[0130]
(2) The substrate 21 on which the lower conductor circuit 24 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface (not shown) on the surface of the lower conductor circuit 24.
[0131]
(3) Next, the resin film for an interlayer resin insulation layer produced in A is laminated by vacuum pressure bonding at 0.5 MPa while raising the temperature to 50 to 150 ° C. to form an interlayer resin insulation layer 22 (See FIG. 8C). Further, a through hole 39 having a diameter of 300 μm was formed by drilling in the substrate 21 on which the interlayer resin insulating layer 22 was formed.
[0132]
(4) Next, a mask on which a through hole having a thickness of 1.2 mm is formed is placed on the interlayer resin insulation layer 22, and CO with a wavelength of 10.4 μm is placed.₂Via hole with a gas laser diameter of 4.0 mm, top hat mode, pulse width 8.0 μsec, mask through-hole diameter 1.0 mm, and interlayer resin insulation layer 22 with a diameter of 80 μm under conditions of one shot. 26 was formed (see FIG. 8D).
[0133]
(5) Next, the substrate on which the via hole opening 26 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes, and the wall surface of the through-hole 39 is subjected to desmear treatment and an interlayer resin. By dissolving and removing the epoxy resin particles present on the surface of the insulating layer 22, a roughened surface (not shown) was formed on the surface including the inner wall surface of the via hole opening 26.
[0134]
(6) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Furthermore, the surface of the interlayer resin insulating layer 22 (including the inner wall surface of the via hole opening 26) is provided by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth 3 μm), and Catalyst nuclei were attached to the wall surface of the through hole 39 (not shown). That is, the substrate is made of palladium chloride (PdCl₂) And stannous chloride (SnCl)₂The catalyst was imparted by immersing it in a catalyst solution containing) and depositing palladium metal.
[0135]
(7) Next, the substrate is immersed in an electroless copper plating aqueous solution at 34 ° C. for 40 minutes, the surface of the interlayer resin insulation layer 22 (including the inner wall surface of the via hole opening 26), and the wall surface of the through hole 39 A thin film conductor layer 32 having a thickness of 0.6 to 3.0 μm was formed (see FIG. 8E). In addition, as an electroless copper plating aqueous solution, the aqueous solution similar to the electroless copper plating aqueous solution used at the process of (1) of Example 1 was used.
[0136]
(8) Next, a commercially available photosensitive dry film is attached to the substrate on which the thin film conductor layer 32 is formed, and a mask is placed thereon, and 100 mJ / cm.²Then, a plating resist 23 was provided by developing with a 0.8% aqueous sodium carbonate solution (see FIG. 9A).
[0137]
(9) Next, the substrate is washed with 50 ° C. water for degreasing, washed with 25 ° C. water and further washed with sulfuric acid, and then electroplated under the same conditions as in the step (12) of Example 1. Then, an electrolytic copper plating film 33 was formed on the portion where the plating resist 23 was not formed (see FIG. 9B).
[0138]
(10) Further, after removing the plating resist 23 with 5% KOH, the thin film conductor layer under the plating resist 23 is etched using an etching solution containing sulfuric acid and hydrogen peroxide, and through holes 29, and The conductor circuit 25 (including the via hole 27) was used.
[0139]
(11) Next, the substrate 30 on which the through hole 29 and the like are formed is immersed in an etching solution, and a roughened surface (not shown) is formed on the surface of the through hole 29 and the conductor circuit 25 (including the via hole 27). Formed. As an etchant, MEC Etch Bond manufactured by MEC was used.
[0140]
(12) Next, after preparing the resin filler described in B above, using the same method as in step (3) of Example 1, within 24 hours after preparation, A layer of resin filler was formed on the conductor circuit non-formation portion on the interlayer resin insulation layer 22 and the outer edge portion of the conductor circuit 25.
[0141]
Subsequently, in the same manner as in the step (4) of Example 1, the surface layer portion of the resin filler layer formed in the through hole or in the conductor circuit non-forming portion and the surface of the conductor circuit 25 are further flattened. By performing the heat treatment, a resin filler layer 30 having a surface flush with the surface of the conductor circuit 25 was formed (see FIG. 9C).
[0142]
(13) Next, a palladium catalyst (not shown) was applied to the surface of the interlayer resin insulation layer 22 and the exposed surface of the resin filler layer 30 by performing the same treatment as in the above (6). Next, an electroless plating process was performed under the same conditions as in (7) above, and a thin film conductor layer 32 was formed on the exposed surface of the resin filler layer 30 and the upper surface of the conductor circuit 25.
[0143]
(14) Next, the plating resist 23 was provided on the thin-film conductor layer 32 using the method similar to said (8) (refer FIG.9 (d)).
Subsequently, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water, and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions. A copper plating film 33 was formed (see FIG. 10A).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 + 2 ° C
[0144]
(15) Next, after removing the plating resist 33 with 5% KOH, the thin film conductor layer under the plating resist 33 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. 31 (see FIG. 10B).
(16) Next, a roughened surface (not shown) was formed on the surface of the lid plating layer 31 using an etching solution (MEC Etch Bond, manufactured by MEC).
[0145]
(17) Next, the steps (3) to (11) are repeated twice to further form an upper interlayer resin insulation layer 22, a conductor circuit 25, and a field via-shaped via hole 27 (FIG. 10 ( c) to FIG. 13 (a)). Here, the formation position of the via hole opening is adjusted, and in the first repetition process, a via hole is formed immediately above the lid plating layer 31, and in the second repetition process, the lower via hole and its center are formed. A second via hole was formed so as to substantially overlap. In this step, no through hole was formed.
[0146]
(18) Further, by repeating the steps (3) to (8) above, an upper interlayer resin insulation layer 22 and a thin film conductor layer 32 are formed, and then a plating resist 23 is formed on the thin film conductor layer 32. It formed (refer FIG.13 (b)).
[0147]
(19) Next, the substrate on which the plating resist 23 is formed is washed and degreased with water at 50 ° C., washed with water at 25 ° C. and further washed with sulfuric acid, and then the step of (16) of Example 1 is performed. Under the same conditions as in the process, electrolytic plating was performed to form an electrolytic copper plating layer. In the via hole opening, an electrolytic copper plating layer having a concave portion on the upper surface was formed.
[0148]
(20) Next, in the same manner as in the above step (10), the plating resist 23 is removed and the thin film conductor layer 32 is etched to form an independent conductor circuit 25 and a via hole 27a having a recess on its upper surface. (See FIG. 14A). Further, a roughened surface (not shown) was formed on the surfaces of the conductor circuit 25 and the via hole 27a in the same manner as in the step (11).
[0149]
(21) Next, a multilayer printed wiring board provided with solder bumps 37 was obtained in the same manner as in the steps (18) to (21) of Example 1 (see FIG. 14B).
The linear expansion coefficient of the interlayer resin insulation layer formed in this example is 60 ppm / ° C.
[0150]
(Example 3)
A. Preparation of photosensitive resin compositions A and B
Photosensitive resin compositions A and B were prepared in the same manner as in Example 1.
[0151]
B. Preparation of resin filler
A resin filler was prepared in the same manner as in Example 1.
[0152]
C. Manufacturing method of multilayer printed wiring board
(1) A copper-clad laminate in which 18 μm copper foil 48 is laminated on both surfaces of a substrate 41 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material (FIG. 15 ( a)). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern to form lower layer conductor circuits 44 and through holes 49 on both sides of the substrate 41 (FIG. 15B). )reference).
[0153]
(2) The substrate on which the through hole 49 and the lower conductor circuit 44 are formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reducing bath was performed, and a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 44 including the through holes 49.
[0154]
(3) Next, after preparing the resin filler described in B above, using the same method as in step (3) of Example 1, within 24 hours after adjustment, A resin filler layer 50 ′ was formed on the conductor circuit non-formed portion of the substrate 41 and the outer edge portion of the lower conductor circuit 44 (see FIG. 15C).
[0155]
(4) Subsequently, in the same manner as in the step (4) of Example 1, the surface portion of the layer of the resin filler formed in the through hole or in the conductor circuit non-formed portion and the surface of the lower conductor circuit 44 are flattened. Furthermore, by performing heat treatment, the resin filler layer 50 whose surface is flush with the surface of the lower conductor circuit 44 is formed (see FIG. 15D).
[0156]
(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surface of the lower conductor circuit 44 and the land surface of the through hole 49. Thus, a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 44. As an etchant, MEC Etch Bond manufactured by MEC was used.
[0157]
(6) Next, the photosensitive resin composition B prepared in A above (viscosity: 1.5 Pa · s) was applied to both sides of the substrate using a roll coater within 24 hours after preparation, and 20 in a horizontal state. After standing for a minute, drying (prebaking) was performed at 60 ° C. for 30 minutes. Next, the photosensitive resin composition A prepared in A above (viscosity: 7 Pa · s) was applied using a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes in the same manner, and then at 60 ° C. Drying (pre-baking) for 30 minutes was performed to form two layers of semi-cured resin layers 42a and 42b (see FIG. 15E).
[0158]
(7) Next, a photomask film on which a black circle having a diameter of 80 μm is printed is brought into close contact with both surfaces of the substrate on which the semi-cured resin layers 42a and 42b are formed, and 500 mJ / cm by an ultrahigh pressure mercury lamp.²And then developed with a DMDG solution. Thereafter, this substrate was further 3,000 mJ / cm with an ultra-high pressure mercury lamp.²Exposure at 100 ° C., heat treatment at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and has a via hole opening 46 with a diameter of 80 μm excellent in dimensional accuracy equivalent to a photomask film. An interlayer resin insulating layer 42 composed of two layers was formed (see FIG. 16A).
[0159]
(8) Further, the substrate on which the via hole opening 46 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve the epoxy resin particles present on the surface of the interlayer resin insulating layer 42. By removing the surface, the surface of the interlayer resin insulating layer 42 including the inner wall of the via hole opening 46 was made a rough surface (not shown).
[0160]
(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, by applying a palladium catalyst (manufactured by Atotech Co., Ltd.) to the surface of the roughened substrate (roughening depth 3 μm), a catalyst is formed on the surface of the interlayer resin insulating layer 42 and the inner wall surface of the via hole opening 46. Nuclei were attached.
[0161]
(10) Next, an electroless plating process was performed under the same conditions as in step (10) of Example 1 to form a thin film conductor layer 52 having a thickness of 0.6 to 3.0 μm over the entire rough surface (FIG. 16 (b)).
[0162]
(11) Next, a commercially available photosensitive dry film is affixed to the thin film conductor layer 52, and a mask is placed thereon, and 100 mJ / cm.²The plating resist 43 was provided by exposing and developing with 0.8% sodium carbonate aqueous solution (see FIG. 16C).
[0163]
(12) Next, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic copper under the same conditions as in the step (12) of Example 1. Plating was performed to form an electrolytic copper plating layer 53 (see FIG. 16D).
[0164]
(13) Subsequently, the plating resist 43 was peeled and removed in a 40 g / l NaOH aqueous solution at 50 ° C. Thereafter, the substrate is heated at 150 ° C. for 1 hour, and the thin film conductor layer existing under the plating resist is removed using an etching solution containing sulfuric acid-hydrogen peroxide aqueous solution. A via hole 47 having a shape was formed (see FIG. 17A).
[0165]
(14) Next, by repeating the above steps (5) to (13), an upper interlayer resin insulation layer 42 and independent conductor circuits 45 and field via-shaped via holes 47 were formed ( FIG. 17B to FIG. 18A). Here, by adjusting the formation position of the via hole opening, the second via hole is formed so that the lower via hole and the center thereof are substantially overlapped.
[0166]
(15) Further, by repeating the steps (5) to (13) above, an upper interlayer resin insulation layer 42 and independent conductor circuits 45 and field via-shaped via holes 47 are formed (FIG. 18 (b)).
Here, by adjusting the formation position of the via-hole opening, the third-stage via hole was stacked while being shifted from the center of the second-stage via hole. The distance between the outer edge of the bottom surface of the via hole (third via hole) formed in this step and the outer edge of the non-land portion of the lower via hole (second via hole) is 5 μm. It is.
[0167]
(16) Further, by repeating the above steps (5) to (11) again, an upper interlayer resin insulation layer 42 and a thin film conductor layer 52 are formed, and then a plating resist 43 is formed on the thin film conductor layer 52. Formed.
[0168]
(17) Next, the substrate on which the plating resist 43 is formed is washed and degreased with water at 50 ° C., washed with water at 25 ° C. and further washed with sulfuric acid, and then the step of (16) of Example 1 is performed. Electrolytic copper plating was performed under the same conditions as those used in the process to form an electrolytic copper plating layer 53 (see FIG. 18C). An electrolytic plating layer 53a having a recess on the upper surface thereof was formed in the opening for the via hole.
Thereafter, the plating resist 43 was removed and the thin film conductor layer was etched in the same manner as in the above step (13) to form an independent conductor circuit and a via hole 47a having a recess on its upper surface (FIG. 19). (See (a)). Here, the uppermost via hole is formed so that the lower via hole (third via hole) and the center thereof are substantially overlapped.
[0169]
(18) Next, a multilayer printed wiring board provided with solder bumps 57 was obtained in the same manner as in the steps (18) to (21) of Example 1 (see FIG. 19B). The linear expansion coefficient of the interlayer resin insulation layer formed in this example is 70 ppm / ° C.
[0170]
Example 4
A. Preparation of resin film for interlayer resin insulation layer
A resin film for an interlayer resin insulation layer was produced in the same manner as in Example 2.
[0171]
B. Preparation of resin filler
A resin filler was prepared in the same manner as in Example 1.
C. Manufacture of multilayer printed wiring boards
(1) A copper-clad laminate in which 18 μm copper foil 68 is laminated on both surfaces of an insulating substrate 61 made of glass epoxy resin or BT resin having a thickness of 0.8 mm was used as a starting material (see FIG. 20A). ). First, the copper-clad laminate was etched into a lower conductor circuit pattern to form lower conductor circuits 64 on both sides of the substrate (see FIG. 20B).
[0172]
(2) The substrate 61 on which the lower conductor circuit 64 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface (not shown) on the surface of the lower conductor circuit 64.
[0173]
(3) Next, the resin film for the interlayer resin insulation layer produced in A is laminated by vacuum pressure bonding at 0.5 MPa while raising the temperature to 50 to 150 ° C., and the interlayer resin insulation layer 62 is formed. (See FIG. 20 (c)).
Further, a through hole 79 having a diameter of 300 μm was formed by drilling in the substrate 61 on which the interlayer resin insulating layer 62 was formed.
[0174]
(4) Next, a mask in which a through hole having a thickness of 1.2 mm is formed is placed on the interlayer resin insulation layer 62, and CO with a wavelength of 10.4 μm₂With a gas laser, a via hole opening with a diameter of 80 μm in the interlayer resin insulation layer 62 under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a mask through hole diameter of 1.0 mm, and one shot 66 was formed (see FIG. 20D).
[0175]
(5) Next, the substrate on which the via hole opening 66 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes, and the wall surface of the through-hole 79 is subjected to desmear treatment, and an interlayer resin By dissolving and removing the epoxy resin particles present on the surface of the insulating layer 62, a roughened surface (not shown) was formed on the surface including the inner wall surface of the opening 66 for the via hole.
[0176]
(6) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Furthermore, the surface of the interlayer resin insulation layer 62 (including the inner wall surface of the via hole opening 66) is provided by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth 3 μm), and Catalyst nuclei were attached to the wall surface of the through hole 79 (not shown). That is, the substrate is made of palladium chloride (PdCl₂) And stannous chloride (SnCl)₂The catalyst was imparted by immersing it in a catalyst solution containing) and depositing palladium metal.
[0177]
(7) Next, the substrate is immersed in an electroless copper plating aqueous solution at 34 ° C. for 40 minutes, and the surface of the interlayer resin insulation layer 62 (including the inner wall surface of the via hole opening 66) and the wall surface of the through hole 79 A thin film conductor layer 72 having a thickness of 0.6 to 3.0 μm was formed (see FIG. 20E). In addition, as an electroless copper plating aqueous solution, the aqueous solution similar to the electroless copper plating aqueous solution used at the process of (1) of Example 1 was used.
[0178]
(8) Next, a commercially available photosensitive dry film is attached to the substrate on which the thin-film conductor layer 72 is formed, and a mask is placed thereon, and 100 mJ / cm.²Then, a plating resist 63 was provided by developing with a 0.8% sodium carbonate aqueous solution (see FIG. 21A).
[0179]
(9) Next, the substrate is washed with 50 ° C. water for degreasing, washed with 25 ° C. water and further washed with sulfuric acid, and then electroplated under the same conditions as in the step (12) of Example 1. Then, an electrolytic copper plating film 73 was formed on the portion where the plating resist 63 was not formed (see FIG. 21B).
[0180]
(10) Further, after removing the plating resist 63 with 5% KOH, the thin film conductor layer under the plating resist 63 is etched using an etching solution containing sulfuric acid and hydrogen peroxide, and through holes 69, and The conductor circuit 65 (including the via hole 67) was used.
[0181]
(11) Next, the substrate on which through holes 69 and the like are formed is dipped in an etching solution, and a roughened surface (not shown) is formed on the surfaces of through holes 69 and conductor circuits 65 (including via holes 67). did. As an etchant, MEC Etch Bond manufactured by MEC was used.
[0182]
(12) Next, after preparing the resin filler described in B above, using the same method as in step (3) of Example 1, within 24 hours after preparation, A resin filler layer was formed on the conductor circuit non-formed portion on the interlayer resin insulation layer 62 and the outer edge portion of the conductor circuit 65.
[0183]
Subsequently, in the same manner as in the step (4) of Example 1, the surface layer portion of the resin filler layer formed in the through hole or in the conductor circuit non-forming portion and the surface of the conductor circuit 65 are planarized, By performing the heat treatment, a resin filler layer 70 having a surface flush with the surface of the conductor circuit 65 was formed (see FIG. 21C).
[0184]
(13) Next, a palladium catalyst (not shown) was applied to the surface of the interlayer resin insulation layer 62 and the exposed surface of the resin filler layer 70 by performing the same treatment as in the above (6). Next, an electroless plating process was performed under the same conditions as in (7) above, and a thin film conductor layer 72 was formed on the exposed surface of the resin filler layer 70 and the upper surface of the conductor circuit 65.
[0185]
(14) Next, a plating resist 63 was provided on the thin-film conductor layer 62 using the same method as in (8) above (see FIG. 21D).
Subsequently, the substrate was washed with water at 50 ° C. to degrease, washed with water at 25 ° C. and further washed with sulfuric acid, and then subjected to electrolytic plating under the same conditions as in the step (14) of Example 2. Then, an electrolytic copper plating film 73 was formed on the portion where the plating resist 63 was not formed (see FIG. 22A).
[0186]
(15) Next, after removing the plating resist 73 with 5% KOH, the thin film conductor layer under the plating resist 73 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the lid plating layer 71 (see FIG. 22B).
(16) Next, a roughened surface (not shown) was formed on the surface of the lid plating layer 71 using an etching solution (MEC Etch Bond, manufactured by MEC).
[0187]
(17) Next, by repeating the steps (3) to (11), an upper interlayer resin insulation layer 62, a conductor circuit 65, and a field via-shaped via hole 67 are formed (FIG. 22C). To FIG. 23 (c)). Here, the via hole was formed immediately above the lid plating layer 71 by adjusting the formation position of the via hole opening. In this step, no through hole was formed.
[0188]
(18) Next, by repeating the steps (3) to (11) twice, an upper interlayer resin insulating layer 62, a conductor circuit 65, and a field via-shaped via hole 67 are formed (FIG. 24 ( a) to FIG. 25 (a)). Here, by adjusting the formation position of the via hole opening, the via hole was stacked so that the center of the lower via hole substantially overlaps the center thereof.
In this step, no through hole was formed.
[0189]
(19) Further, by repeating the above steps (3) to (8) again, an upper interlayer resin insulation layer 62 and a thin film conductor layer 72 are formed, and then a plating resist is formed on the thin film conductor layer 72. 63 was formed (see FIG. 25B).
[0190]
(20) Next, the substrate on which the plating resist 63 is formed is washed and degreased with water at 50 ° C., washed with water at 25 ° C. and further washed with sulfuric acid, and then the step of (16) of Example 1 is performed. Electrolytic plating was performed under the same conditions as in the process to form an electrolytic plating layer. An electrolytic plating layer having a recess on the upper surface was formed in the opening for via hole.
[0191]
(21) Thereafter, the plating resist 63 is peeled off and the thin film conductor layer 72 is etched in the same manner as in the above step (10), so that an independent conductor circuit 65 and a via hole 67a having a recess on the upper surface thereof. (See FIG. 26 (a)). Further, a roughened surface was formed on the surfaces of the conductor circuit 65 and the via hole 67a in the same manner as in the step (11).
In the series of steps (19) to (21), the via holes were stacked while being shifted from the center of the lower via hole by adjusting the formation position of the via hole opening. The distance between the outer edge of the bottom of the uppermost via hole (fourth via hole) formed in this step and the outer edge of the non-land portion of the lower via hole (third via hole) Is 8 μm.
[0192]
(22) Next, a multilayer printed wiring board provided with solder bumps 77 was obtained in the same manner as in steps (18) to (21) of Example 1 (see FIG. 26B).
In addition, the linear expansion coefficient of the interlayer resin insulation layer in the multilayer printed wiring board produced in this example is 60 ppm / ° C.
[0193]
(Example 5)
In the step (15) of Example 3, the distance between the outer edge of the bottom surface of the third via hole and the outer edge of the non-land portion of the lower via hole (second via hole) is 20 μm. A multilayer printed wiring board was produced in the same manner as in Example 3 except that the via holes were stacked.
[0194]
(Example 6)
In the step (21) of Embodiment 4, the outer edge of the bottom surface of the uppermost via hole (fourth via hole) and the outer edge of the non-land portion of the lower via hole (third via hole) A multilayer printed wiring board was produced in the same manner as in Example 4 except that the via holes were stacked so that the distance to the part was 40 μm.
[0195]
(Example 7)
In the step (15) of Example 3, the distance between the outer edge of the bottom surface of the third via hole and the outer edge of the non-land portion of the lower via hole (second via hole) is 70 μm. A multilayer printed wiring board was produced in the same manner as in Example 3 except that the via holes were stacked.
[0196]
(Example 8)
In the step (15) of the third embodiment, the via hole is adjusted so that the horizontal distance between the center of the third via hole and the center of the lower via hole (second via hole) is 70 μm. A multilayer printed wiring board was produced in the same manner as in Example 3 except that was stacked.
[0197]
Example 9
In the step (21) of Example 4, the horizontal distance between the center of the uppermost via hole (fourth via hole) and the center of the lower via hole (third via hole) is A multilayer printed wiring board was produced in the same manner as in Example 4 except that via holes were stacked so as to have a thickness of 70 μm.
[0198]
About the multilayer printed wiring board manufactured in Examples 1-9, the heat cycle test was done, the shape observation of the interlayer resin insulation layer and the via hole before and behind that, and the conduction test were done.
[0199]
Evaluation method
(1) Heat cycle test
The cycle of leaving at -65 ° C for 3 minutes and 130 ° C for 3 minutes was repeated 1000 cycles.
[0200]
(2) Shape observation
After producing the multilayer printed wiring board, before and after the heat cycle test, the multilayer printed wiring board is cut so as to pass through a via hole having a concave portion on the upper surface, and the cross section is obtained using an optical microscope with a magnification of 100 to 400 times. Observed.
[0201]
(3) Continuity test
After the multilayer printed wiring board was manufactured, a continuity test was performed using a checker before and after the heat cycle test, and the continuity state was evaluated from the results displayed on the monitor.
[0202]
As a result, in the multilayer printed wiring boards of Examples 1 to 9, cracks occurred in all interlayer resin insulation layers including the interlayer resin insulation layer around the uppermost via hole in the cross-sectional shape observation before and after the heat cycle test. In addition, the occurrence of peeling between the interlayer resin insulation layer and the via hole was not observed. In addition, before and after the heat cycle test, no short circuit or disconnection occurred, and the conduction state was good.
[0203]
【Effect of the invention】
As described above, the multilayer printed wiring board of the present invention is the multilayer printed wiring board of the present invention, the via holes of different layers are stacked, among the stacked via holes, Since the recess is formed on the upper surface, the stress generated due to the difference in the coefficient of linear expansion between the via hole and the interlayer resin insulation layer can be relieved, and a large stress is concentrated in the uppermost via hole. Therefore, cracks are hardly generated in the interlayer resin insulation layer due to the concentration of the stress, and the reliability is excellent.
In the multilayer printed wiring board of the present invention, via holes of different levels are stacked, so that the wiring distance is short, the signal transmission time can be shortened, and the degree of freedom in designing the conductor circuit is improved. Easy to handle high density wiring.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view schematically showing an embodiment of a multilayer printed wiring board according to the present invention.
FIG. 2 is a partial cross-sectional view schematically showing another embodiment of the multilayer printed wiring board of the present invention.
FIGS. 3A to 3E are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 4A to 4D are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 5A to 5C are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 6A to 6C are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
FIGS. 7A and 7B are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention. FIGS.
FIGS. 8A to 8E are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention.
FIGS. 9A to 9D are cross-sectional views schematically showing a part of the process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
FIGS. 10A to 10D are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 11A to 11C are cross-sectional views schematically showing a part of the process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
FIGS. 12A to 12C are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board of the present invention.
FIGS. 13A and 13B are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention. FIGS.
FIGS. 14A and 14B are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 15A to 15E are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 16A to 16D are cross-sectional views schematically showing a part of a process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
FIGS. 17A to 17C are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention. FIGS.
18 (a) to 18 (c) are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
FIGS. 19A and 19B are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
20 (a) to 20 (e) are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
FIGS. 21A to 21D are cross-sectional views schematically showing a part of the process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
22 (a) to 22 (d) are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
FIGS. 23A to 23C are cross-sectional views schematically showing a part of the process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
24 (a) to 24 (c) are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
FIGS. 25A and 25B are cross-sectional views schematically showing a part of the process for manufacturing the multilayer printed wiring board of the present invention. FIGS.
26 (a) and 26 (b) are cross-sectional views schematically showing a part of the process for producing the multilayer printed wiring board of the present invention.
[Explanation of symbols]
1, 21, 41, 61 substrate
2, 22, 42, 62 Interlayer resin insulation layer
3, 23, 43, 63 Plating resist
4, 24, 44, 64 Underlayer conductor circuit
5, 25, 45, 65 Conductor circuit
6, 26, 46, 66 Via hole opening
7, 27, 47, 67 Via hole
8, 28, 48, 68 Copper foil
9, 29, 49, 69 Through hole
10, 30, 50, 70 Resin filler layer
12, 32, 52, 72 Thin film conductor layer
13, 33, 53, 73 Electrolytic plating film
14, 34, 54, 74 Solder resist layer
17, 37, 57, 77 Solder bump
31, 71 Lid plating layer

Claims (7)

A multilayer in which a conductor circuit and an interlayer resin insulating layer are sequentially laminated on a substrate, the conductor circuits sandwiching the interlayer resin insulating layer are connected via via holes, and a solder resist layer is formed on the outermost layer A printed wiring board,
Among the via holes, via holes of different levels are stacked,
Of the stacked via holes, the bottom via hole is stacked with the other via hole shifted in the center, and the remaining via holes are stacked so that their centers almost overlap each other. Or
The two-stage via holes including the bottom are stacked so that the centers thereof are substantially overlapped, and the remaining via holes are also stacked so that the centers are substantially overlapped. The via hole and the remaining via hole are stacked with their centers shifted.
The uppermost via hole has a recess formed on the upper surface thereof, and the via hole other than the uppermost layer includes an electroless plating film formed on the surface of the interlayer resin insulating layer, and the electroless plating film. A multilayer printed wiring board comprising an electrolytic plating film formed on the interlayer resin insulating layer and filling the opening of the interlayer resin insulating layer.   The multilayer printed wiring board according to claim 1, wherein the depth of the recess is 5 to 25 μm.   3. The multilayer printed wiring board according to claim 1, wherein at least an outermost interlayer resin insulating layer among the interlayer resin insulating layers has a linear expansion coefficient of 100 ppm / ° C. or less.   The multilayer printed wiring board according to any one of claims 1 to 3, wherein particles and a rubber component are blended in at least the outermost interlayer resin insulating layer among the interlayer resin insulating layers.   The multilayer printed wiring board according to claim 4, wherein the particles are at least one of inorganic particles, resin particles, and metal particles.   Among the interlayer resin insulation layers, at least the outermost interlayer resin insulation layer includes a thermosetting resin, a photosensitive resin, a resin composite of a thermosetting resin and a thermoplastic resin, and a thermosetting resin and a photosensitive resin. The multilayer printed wiring board in any one of Claims 1-5 currently formed with the resin composition containing at least 1 sort (s) of the resin complex with resin.   The multilayer printed wiring board according to any one of claims 1 to 6, which is a multilayer build-up wiring board manufactured by a semi-additive method.

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