JP5167024B2 - Phase synchronization circuit, control method therefor, and communication device - Google Patents

Description

  The present invention relates to a phase synchronization circuit used in an electronic device, a control method thereof, and a communication device.

  2. Description of the Related Art A phase locked loop (hereinafter referred to as a sample / hold type PLL (Phase Locked Loop), or simply referred to as a PLL circuit) that generates a clock in synchronization with a reference signal that is intermittently input in a burst form is known. Yes.

  FIG. 9 is a diagram showing a configuration of a conventional sample / hold type PLL circuit. A reference signal is intermittently input as an input signal to the sample / hold type PLL circuit. When an input signal is input, the sample / hold type PLL circuit compares the phase of the input signal with the clock obtained by dividing the output of the VCO 6 by N by the 1 / N frequency dividing circuit 7 in the phase comparator 1. . After this comparison, in the LPF 2 that is a low-pass filter, the phase error voltage is removed from the output of the phase comparator 1, and the signal after the removal is a sample / hold circuit (hereinafter sometimes abbreviated as S / H). 12 is input. The S / H 12 is controlled by the pulse generator 9 and performs a sampling operation during a period in which a reference signal is input, and performs a hold operation during a period in which there is no reference signal. The output of the S / H 12 is input to the VCO 6 as a control voltage for the VCO 6. The output from the VCO 6 is N-divided by the 1 / N frequency divider 7 and phase-compared with the reference signal. Therefore, the VCO 6 outputs a signal having a frequency N times that is synchronized with the reference signal. By using such a sample / hold type PLL circuit, it is possible to obtain a continuous signal synchronized with a reference signal that exists only intermittently.

  If noise is superimposed on the reference signal input during the sampling period, or if the reference signal cannot secure a sufficient level, the burst period may end with the PLL circuit being out of synchronization. . In this case, after the synchronization is lost, the synchronization is not achieved until the synchronization is achieved in the next burst period, and a stable PLL operation cannot be performed.

Conventionally, when the reference signal input during the sampling period cannot maintain a normal signal state due to, for example, the dropout of the playback device, the sample / hold circuit is set to the hold state and the voltage immediately before the abnormality is held. The technique to do is known (refer patent document 1).
JP-A-62-292018

  However, the conventional configuration has various problems. For example, in the conventional configuration, synchronization is lost unless an abnormality in the input signal is detected and switched to the hold state before the VCO control voltage is affected.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a phase synchronization circuit, a control method thereof, and a communication device that can output an output signal having a stable frequency.

In order to achieve the above object, a phase locked loop circuit according to one embodiment of the present invention includes a voltage-controlled oscillation circuit that outputs a signal having a frequency corresponding to an input control voltage as an output signal, an input signal, and the voltage-controlled oscillation circuit. A comparison unit that compares phases with the output signal, two or more sample / hold circuits that hold voltages based on phase comparisons by the comparison unit at different timings, and two or more sample / hold circuits. Switching means for selecting any one of them and inputting the output from the selected sample / hold circuit as the control voltage to the voltage-controlled oscillation circuit; and an abnormality detection means for detecting an abnormality of the input signal, switching means, when an abnormality is detected in the input signal by the abnormality detecting means, the sample / hold circuit selected at the time It selects the output of the sample / hold circuit comprising, characterized in that.

Another embodiment of the present invention is a method for controlling a phase locked loop, wherein an output step of outputting a signal according to a control voltage as an output signal in a voltage controlled oscillation circuit, an input signal, and the voltage controlled oscillation circuit A comparison step for comparing the phase with the output signal, a holding step for holding voltages based on the phase comparison in the comparison step in two or more sample / hold circuits at different timings, and the two or more samples / A switching step of selecting one of the hold circuits and inputting the output from the selected sample / hold circuit as the control voltage to the voltage-controlled oscillation circuit, and an abnormality detection step of detecting an abnormality of the input signal. , and in the higher switching換工, when an abnormality in the input signal in the abnormality detecting process is detected, the sample / hold circuit selected at the time It selects the output of the sample / hold circuit comprising, characterized in that.

  According to the present invention, an output signal having a stable frequency can be output.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of a phase synchronization circuit, a control method therefor, and a communication device according to the invention will be described in detail with reference to the accompanying drawings. The phase synchronization circuit is built in, for example, a communication device and used for communication.

(Embodiment 1)
FIG. 1 is a block diagram illustrating an example of a configuration of a PLL circuit according to the first embodiment.

  The PLL circuit is a phase synchronization circuit that outputs an output signal having a frequency synchronized with an input signal by phase synchronization control. Here, the PLL circuit includes the phase comparator 1, LPF 2, S / Ha 3, S / Hb 4, changeover switch 5, VCO 6, 1 / N frequency divider circuit 7, noise detection circuit 8, pulse And a generator 9.

  The phase comparator 1 compares the phases of the input signal and the output signal of the VCO 6. Here, the output signal of the VCO 6 to be compared has a frequency (clock) divided by N by the 1 / N frequency dividing circuit 7. An LPF (Low Pass Filter) 2 is a low-pass filter that removes the high-frequency and passes only the low-frequency, and removes the phase error voltage from the output of the phase comparator 1. S / Ha3 functions as a first sample / hold circuit, and S / Hb4 functions as a second sample / hold circuit. The changeover switch 5 selects either S / Ha3 or S / Hb4. By this selection, an output from one of the sample / hold circuits (hereinafter sometimes abbreviated as S / H) is input to the VCO 6 as a control voltage. A VCO (Voltage Controlled Oscillator) 6 is a voltage controlled oscillation circuit, generates a signal having a frequency corresponding to the control voltage from the S / H circuit input via the changeover switch 5, and outputs it as an output signal. . The 1 / N frequency dividing circuit 7 divides the frequency from the VCO 6. The noise detection circuit 8 functions as an abnormality detection means for detecting an abnormal state. Specifically, the noise detection circuit 8 detects noise or the like (including a decrease in signal level) of the input signal and outputs the detection result to the pulse generator 9. . The pulse generator 9 generates a control signal and controls each part constituting the PLL circuit. The above is the description of the configuration of the PLL circuit according to the first embodiment.

  Here, it is assumed that, for example, a reference signal is intermittently input as an input signal to the PLL circuit. In the PLL circuit, the phase comparator 1 compares the phase of this input signal with the output signal (clock) obtained by dividing the output of the VCO 6 by N by the 1 / N divider circuit 7. After this comparison, the PLL circuit removes the phase error voltage from the output of the phase comparator 1 in LPF 2 and inputs the signal after the removal to S / Ha 3 and S / Hb 4. S / Ha3 and S / Hb4 are controlled by the pulse generator 9 and perform a sampling operation during a period in which a reference signal is input, and hold operation in a period in which there is no reference signal. In the changeover switch 5, either S / Ha3 or S / Hb4 output is selected, and the output from the selected S / H circuit is input to the VCO 6 as a control voltage. The output from the VCO 6 is N-divided by the 1 / N frequency divider 7 and phase-compared with the reference signal. Therefore, the VCO 6 outputs a signal having a frequency N times that is synchronized with the reference signal. When the noise detection circuit 8 detects noise of the input signal, the detection signal is output from the noise detection circuit 8 to the pulse generator 9.

  Next, the processing flow of the PLL circuit shown in FIG. 1 will be described with reference to FIGS. 2 and 3 are flowcharts showing an example of the operation of the PLL circuit shown in FIG. 1, and FIG. 4 is a diagram showing an example of various signals used at that time.

  Here, the flowcharts shown in FIGS. 2 and 3 will be described in order with reference to the table shown in FIG. When the power is turned on, this process is started (step S101). In the PLL circuit, first, the system is reset, SW (sample hold circuit switching signal), which is a signal for controlling the changeover switch 5, is in the S / Ha3 selection state, and NOISE (noise detection signal) is initially in a noise-free state. It is set (step S102). Thereafter, the PLL circuit waits until a burst period indicating a period in which the reference signal is actually input is reached in the intermittent reference signal input (NO in step S103).

  Here, when the burst period is reached (YES in step S103), signals (SHa = 1, SHb = 1) instructing S / Ha3 and S / Hb4 to shift to the sampling mode are input from the pulse generator 9. The Thereby, S / Ha3 and S / Hb4 start a sampling operation (step S104). This sampling operation is continued until the burst period ends (YES in step S105). During the sampling operation, the PLL circuit is in a closed loop, and is a period during which the PLL operation (processing related to phase synchronization control) is actually performed.

  When the burst period ends (NO in step S105), the PLL circuit shifts from the sampling operation to the hold operation. Along with the shift to the hold operation, the signal for determining the S / Ha3 control mode output from the pulse generator 9 is set to the sampling mode (SHA = 1). The signal for determining the S / Hb4 control mode output from the pulse generator 9 is set to the hold mode (SHb = 0) (step S106).

  The PLL circuit maintains the hold operation until the next burst period (NO in step S107). In the hold operation period, the PLL circuit is in an open loop, the PLL operation is not performed, and the VCO 6 is controlled by the voltage held in the S / H circuit to generate a clock. When the next burst period is reached and the SH signal is in the sampling state (SH = 1) (YES in step S107), S / Ha3 is sampled and S / Hb4 is held in accordance with the SHa and SHb signals from the pulse generator 9. To do.

  When the burst period ends (NO in step S108), the process moves to FIG. 3, and the PLL circuit confirms NOISE (noise detection signal) from the noise detection circuit 8 in the pulse generator 9. This process is performed in order to confirm that the PLL operation is not normally performed when noise is generated during the burst period. As a result, if the generation of noise is not confirmed (YES in step S109), the PLL circuit switches the signal of each of the SHa signal and SHb signal from the current state in the pulse generator 9, and S / Ha3 and S / Hb4. Each mode is switched (step S110). Further, the PLL circuit controls the SW signal in the pulse generator 9 and switches the changeover switch 5 to the S / H circuit on the sampling mode side (step S111). Thereafter, the PLL circuit returns to the process of step S107.

  On the other hand, if the generation of noise is confirmed in the determination in step S109 (NO in step S109), the PLL circuit controls the SW signal in the pulse generator 9 and sets the changeover switch 5 to the S / S on the hold mode side. Switch to the H circuit (step S112). Thereafter, the PLL circuit waits until the burst period is reached (NO in step S113). When the burst period is reached (YES in step S113), the PLL circuit controls the SW signal in the pulse generator 9, and switches the changeover switch 5 to the S / H circuit on the sampling mode side (step S114). The PLL circuit continues the sampling operation during the burst period (YES in step S115).

  Here, when the burst period ends (NO in step S115) and noise is generated during the burst period (NO in step S116), the PLL circuit returns to the process of step S112 again. On the other hand, when the sampling operation is completed without generating noise (YES in step S116), the PLL circuit switches the signals of the SHa signal and the SHb signal to the current state in the pulse generator 9. Then, the respective modes of S / Ha3 and S / Hb4 are switched (step S117). Further, the SW signal is controlled and the changeover switch 5 is switched to the S / H circuit on the sampling mode side (step S118), and then the processing returns to step S107.

  As described above, according to the first embodiment, the sample / hold type PLL operation is performed using the two sample / hold circuits. At this time, the two sample / hold circuits perform sampling operations at different timings. Therefore, when noise occurs during the sampling operation, the output is switched to the output on the sample / hold circuit side that holds a stable voltage, and the clock is generated during the holding operation. This makes it possible to generate a stable clock even when there is a possibility that the control voltage of the VCO deviates from an appropriate voltage due to disturbance.

(Embodiment 2)
Next, Embodiment 2 will be described. FIG. 5 is a block diagram illustrating an example of a configuration of a PLL circuit according to the second embodiment. In addition, about the structure same as FIG. 1 which demonstrated Embodiment 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted. Here, differences will be described. The difference is that a synchronization detection circuit a10 as a first synchronization detection circuit and a synchronization detection circuit b11 as a second synchronization detection circuit are provided as new configurations.

  Here, it is assumed that, for example, a reference signal is intermittently input as an input signal to the PLL circuit. In the PLL circuit, the phase comparator 1 compares the phase of this input signal with the output signal (clock) obtained by dividing the output of the VCO 6 by N by the 1 / N divider circuit 7. After this comparison, the PLL circuit removes the phase error voltage from the output of the phase comparator 1 in LPF 2 and inputs the signal after the removal to S / Ha 3 and S / Hb 4. S / Ha3 and S / Hb4 are controlled by the pulse generator 9 and perform a sampling operation during a period in which a reference signal is input, and hold operation in a period in which there is no reference signal. In the changeover switch 5, either S / Ha3 or S / Hb4 output is selected, and the output from the selected S / H circuit is input to the VCO 6 as a control voltage. The output from the VCO 6 is N-divided by the 1 / N frequency divider 7 and phase-compared with the reference signal. Therefore, the VCO 6 outputs a signal having a frequency N times that is synchronized with the reference signal. When the noise detection circuit 8 detects noise of the input signal, the detection signal is output from the noise detection circuit 8 to the pulse generator 9. Furthermore, when the first synchronization detection circuit a or the synchronization detection circuit b detects that the PLL is synchronized, a detection signal is output from the synchronization detection circuit to the pulse generator 9.

  Next, the processing flow of the PLL circuit shown in FIG. 5 will be described with reference to FIGS. 6 and 7 are flowcharts showing an example of the operation of the PLL circuit shown in FIG. 5, and FIG. 8 is a diagram showing an example of various signals used at that time.

  Here, the flowcharts shown in FIGS. 6 and 7 will be described in order with reference to the table shown in FIG. When the power is turned on, this process is started (step S201). In the PLL circuit, first, the system is reset, SW (sample hold circuit switching signal), which is a signal for controlling the changeover switch 5, is in the S / Ha3 selection state, and NOISE (noise detection signal) is initially in a noise-free state. Is set. At this time, LOCK (PLL lock detection signal) is also initialized to an asynchronous state (step S202). Thereafter, the PLL circuit waits until the burst period indicating the period in which the reference signal is actually input is reached in the intermittent reference signal input (NO in step S203).

  Here, when the burst period is reached (YES in step S203), signals (SHa = 1, SHb = 1) instructing S / Ha3 and S / Hb4 to shift to the sampling mode are input from the pulse generator 9. The Thereby, S / Ha3 and S / Hb4 start a sampling operation (step S204). This sampling operation is continued until the burst period ends (YES in step S205). During the sampling operation, the PLL circuit is in a closed loop, and is a period during which the PLL operation is actually performed.

  When the burst period ends (NO in step S205), the PLL circuit shifts from the sampling operation to the hold operation, and the pulse detector 9 determines the value of LOCK (PLL lock detection signal) from the synchronization detection circuits 10 and 11. To do. As a result, if it is in the synchronous detection state (LOCK = 1) (YES in step S206), the signal for determining the S / Ha3 control mode output from the pulse generator 9 is set to the sampling mode (SHA = 1). Is done. The signal for determining the S / Hb4 control mode output from the pulse generator 9 is set to the hold mode (SHb = 0). At this time, LOCK (PLL lock detection signal) is turned OFF (LOCK = 0) (step S207). On the other hand, if LOCK (PLL lock detection signal) is in an asynchronous state (LOCK = 0) (NO in step S206), the PLL circuit returns to the process in step S203 and repeats the PLL operation until synchronization is achieved.

  The PLL circuit maintains the hold operation until the next burst period (NO in step S208). In the hold operation period, the PLL circuit is in an open loop, the PLL operation is not performed, and the VCO 6 is controlled by the voltage held in the S / H circuit to generate a clock. When the next burst period is reached and the SH signal is in the sampling state (SH = 1) (YES in step S208), S / Ha3 is sampled and S / Hb4 is held in accordance with the SHa and SHb signals from the pulse generator 9. To do. When the burst period ends (NO in step S209), the process proceeds to FIG. 7 and the PLL circuit confirms NOISE (PLL lock detection signal) from the synchronization detection circuits 10 and 11 in the pulse generator 9. This process is performed to confirm whether the PLL circuit is out of synchronization during the burst period. As a result, if it can be confirmed that synchronization has been achieved (YES in step S210), then the PLL circuit confirms NOISE (noise detection signal) from the noise detection circuit 8 in the pulse generator 9. If the generation of noise is not confirmed (YES in step S211), the PLL circuit switches the signal of each of the SHa signal and SHb signal from the current state in the pulse generator 9, and each mode of S / Ha3 and S / Hb4 Are replaced (step S212). Further, the PLL circuit controls the SW signal in the pulse generator 9 and switches the changeover switch 5 to the S / H circuit on the sampling mode side (step S213). Thereafter, the PLL circuit returns to the process of step S208.

  On the other hand, when generation of noise is confirmed in the determination in step S211 (NO in step S211), or in the determination in step S210 that it is asynchronous (NO in step S210), the PLL circuit The process proceeds to step S214. That is, the PLL circuit controls the SW signal in the pulse generator 9 and switches the changeover switch 5 to the S / H circuit on the hold mode side (step S214). Thereafter, the PLL circuit waits until the burst period is reached (NO in step S215). When the burst period is reached (YES in step S215), the PLL circuit controls the SW signal in the pulse generator 9, and switches the changeover switch 5 to the S / H circuit on the sampling mode side (step S216). The PLL circuit continues the sampling operation during the burst period (YES in step S217).

  Here, if synchronization is not achieved or noise is generated during this burst period (NO in step S218 or NO in step S219), the PLL circuit returns to the process of step S214 again. On the other hand, if the synchronization is achieved during the burst period and the sampling operation in the burst period is completed without generating noise (YES in step S218, then YES in step S219), the PLL circuit performs step S220. Proceed to the process. Then, in the pulse generator 9, the PLL circuit switches the signal of each of the SHa signal and the SHb signal to the current state, and switches the mode of each of the S / Ha3 and S / Hb4 (step S220). Further, the SW signal is controlled and the changeover switch 5 is switched to the S / H circuit on the sampling mode side (step S221), and then the process returns to step S208.

  As described above, according to the second embodiment, in addition to the configuration of the first embodiment, the synchronization state by the PLL operation is detected, and the VCO is controlled by the synchronized VCO control signal (control voltage). As a result, a more stable PLL operation is possible.

  The above is an example of a typical embodiment of the present invention, but the present invention is not limited to the embodiment described above and shown in the drawings, and can be appropriately modified and implemented without departing from the scope of the present invention. .

  For example, the PLL circuit described above may be built in a communication device (not shown) and used for communication. That is, the present invention can also be applied to a communication device.

  In the first and second embodiments described above, the case where two sample / hold circuits are provided has been described. However, the present invention is not limited to this, and three or more circuits may be provided. In that case, the synchronization detection circuit described in the second embodiment may be added correspondingly.

1 is a block diagram illustrating an example of a configuration of a PLL circuit according to a first embodiment. 3 is a first flowchart showing an example of the operation of the PLL circuit shown in FIG. 4 is a second flowchart showing an example of the operation of the PLL circuit shown in FIG. 1. It is a figure which shows an example of the various signals used with the PLL circuit shown in FIG. 6 is a block diagram illustrating an example of a configuration of a PLL circuit according to a second embodiment. FIG. 6 is a first flowchart showing an example of the operation of the PLL circuit shown in FIG. 5. 6 is a second flowchart showing an example of the operation of the PLL circuit shown in FIG. 5. It is a figure which shows an example of the various signals used with the PLL circuit shown in FIG. It is a figure which shows a prior art example.

Explanation of symbols

1 Phase comparator 2 LPF
3 S / Ha
4 S / Hb
5 selector switch 6 VCO
7 1 / N frequency dividing circuit 8 Noise detection circuit 9 Pulse generator 10 Synchronization detection circuit a
11 Synchronization detection circuit b

Claims (7)

A voltage controlled oscillation circuit that outputs a signal having a frequency according to the input control voltage as an output signal;
Comparison means for comparing the phase of the input signal and the output signal of the voltage controlled oscillation circuit;
Two or more sample / hold circuits respectively holding voltages based on phase comparisons by the comparison means at different timings;
Switching means for selecting one of the two or more sample / hold circuits and inputting an output from the selected sample / hold circuit to the voltage controlled oscillation circuit as the control voltage;
An abnormality detecting means for detecting an abnormality of the input signal,
The switching means is
When an abnormality is detected in the input signal by the abnormality detection means, an output of a sample / hold circuit different from the sample / hold circuit selected at that time is selected.
A phase synchronization circuit characterized by that.   The two or more sample / hold circuits maintain the state for a predetermined period when the voltage is sampled when the abnormality detection unit detects the abnormality.
  The phase-locked loop according to claim 1. Synchronization detection means for detecting the synchronization state of the process related to the phase synchronization control,
The switching means is
When an abnormality is detected in the input signal by the abnormality detection means, or when the processing related to the phase synchronization control is not synchronized by the synchronization detection means, the sample / The phase synchronization circuit according to claim 1 or 2, wherein an output of a sample / hold circuit different from the hold circuit is selected. A low-pass filter that removes high-frequency frequencies;
The two or more sample / hold circuits are:
4. The phase synchronization circuit according to claim 1, wherein a voltage based on a phase comparison by the comparison unit that has passed through the low-pass filter is held. 5. The abnormality detection means includes
The phase synchronization circuit according to any one of claims 1 to 4, wherein noise included in the input signal is detected as the abnormality. A method for controlling a phase synchronization circuit, comprising:
An output step of outputting a signal according to the control voltage as an output signal in the voltage controlled oscillation circuit;
A comparison step of comparing the phase of the input signal and the output signal of the voltage controlled oscillator circuit;
A holding step of holding two or more sample / hold circuits at different timings based on the phase comparison in the comparison step;
A switching step of selecting one of the two or more sample / hold circuits and inputting an output from the selected sample / hold circuit to the voltage controlled oscillation circuit as the control voltage;
An abnormality detection step of detecting an abnormality of the input signal,
In the switching step,
When an abnormality is detected in the input signal in the abnormality detection step, the output of the sample / hold circuit different from the sample / hold circuit selected at that time is selected.
A control method for a phase locked loop circuit.   A communication device including the phase synchronization circuit according to claim 1.

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