JP5049688B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device, and more particularly to a technique effective when applied to a scan driver circuit that operates by connecting two output terminals per Y electrode of a plasma display panel.

  According to a study by the present inventor, regarding a plasma display device, for example, in a scan driver circuit that operates by connecting two output terminals per Y electrode of a plasma display panel, two adjacent output terminals are connected. The two output terminals are operated at the same timing while being connected to one Y electrode. The reason for this operation is to reduce the thermal and electrical load of the scan driver circuit.

  By the way, in the scan driver circuit of the plasma display apparatus as described above, when the two output terminals are connected, when the control signal malfunctions due to noise or the like, the two output terminals move at different timings. A through current may flow between the two terminals, which may result in destruction of the scan driver circuit.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a plasma display device capable of preventing a through operation between two output terminals in a scan driver circuit that operates by connecting two output terminals per Y electrode of a plasma display panel. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the present invention, in the plasma display device, two adjacent circuit wirings are connected to each other so that the two output terminals do not move at different timings in the circuit wiring inside the scan driver circuit. Specifically, the two output terminals of the scan driver circuit are operated using one operation signal, thereby preventing a through operation between the two output terminals.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, a penetrating operation between two output terminals can be prevented in a scan driver circuit that operates by connecting two output terminals per Y electrode of a plasma display panel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A plasma display device according to Embodiment 1 of the present invention will be described with reference to FIGS.

  FIG. 1 is a diagram showing an example of the configuration of a plasma display panel mounted on the plasma display device of the present embodiment.

  The plasma display panel includes a front plate 1 and a back plate 2.

  On the front plate 1, X electrodes 11 and Y electrodes 12 that repeatedly discharge are arranged in parallel at a predetermined interval. Each of the X and Y electrodes 11 and 12 discharges in pairs with electrodes adjacent to one side, but there is also a structure in which discharge is performed with electrodes adjacent to both sides. Further, although the X and Y electrodes 11 and 12 are alternately arranged, there is a structure in which the X electrodes 11 or the Y electrodes 12 are adjacently arranged on the side where no discharge is performed. The electrode groups of the X and Y electrodes 11 and 12 are covered with a dielectric layer 13, and the surface thereof is further covered with a protective layer 14 such as MgO.

  An address electrode 15 is disposed on the back plate 2 in a direction substantially perpendicular to the X electrode 11 and the Y electrode 12, and is covered with a dielectric layer 16. Partitions 17 are arranged on both sides of the address electrode 15 to partition the cells in the column direction. Further, on the side surfaces of the dielectric layer 16 and the partition wall 17 on the address electrode 15, phosphors 18, 19, and 20 that are excited by ultraviolet rays and generate visible light of red (R), green (G), and blue (B). It has been applied.

  The front plate 1 and the back plate 2 are bonded together so that the protective layer 14 and the partition wall 17 are in contact with each other, and a discharge gas such as Ne—Xe is sealed therein to constitute a plasma display panel. There is also a structure having partition walls that divide cells in the row direction.

  FIG. 2 is a diagram illustrating an example of the configuration of the plasma display device according to the present embodiment.

  The plasma display device includes a plasma display panel 3 formed by bonding the front plate 1 and the back plate 2, the X electrode drive circuit 4, the Y electrode drive circuit 5, the address electrode drive circuit 6, the control circuit 7, and the scan. The driver circuit 8 is configured.

  The plasma display panel 3 includes the above-described electrode groups of the X electrode 11, the Y electrode 12, and the address electrode 15, and a line is formed by a pair of the adjacent X electrode 11 and Y electrode 12, and the address electrode 15 intersects. A cell is configured corresponding to the region divided by the partition wall 17. A pixel is composed of a set of R, G, and B cells.

  The X electrode drive circuit 4 is connected to an electrode group including a plurality of X electrodes 11 of the plasma display panel 3 and is driven by applying a drive signal in common to these electrode groups.

  The scan driver circuit 8 is connected to an electrode group composed of a plurality of Y electrodes 12 of the plasma display panel 3, and is driven by applying a scan pulse to each of these electrode groups in order during an address period.

  The Y electrode drive circuit 5 is connected to an electrode group composed of a plurality of Y electrodes 12 of the plasma display panel 3 and is driven by applying a drive signal to these electrode groups in a reset period and a sustain period in common.

  The address electrode drive circuit 6 is connected to an electrode group composed of a plurality of address electrodes 15 of the plasma display panel 3, and is driven by applying an address pulse to each of these electrode groups in synchronization with a scan pulse during an address period. It is. The address electrode drive circuit 6 may be disposed on both the upper and lower sides of the plasma display panel 3.

  The control circuit 7 is connected to the X electrode drive circuit 4, the Y electrode drive circuit 5, and the address electrode drive circuit 6 to control the X electrode drive circuit 4, the Y electrode drive circuit 5, and the address electrode drive circuit 6, respectively. Yes. The control circuit 7 includes a display data control unit, a scan driver control unit, a display / power control unit, and the like, and is supplied with display data, a clock signal, a vertical synchronization signal, and the like from outside. The control circuit 7 includes a CPU, and each of the above parts is realized by hardware or software by the CPU.

  FIG. 3 is a diagram illustrating an example of the configuration of one field. FIG. 3 shows a driving method for displaying an image of one image (one field: 1/60 sec), and is an example of an address / display separation method.

  One field is composed of a plurality of (10 subfields 21 to 30 in this example) subfields. Each subfield includes a reset period 31, an address period 32, and a sustain period 33. In the reset period 31, the charge in the cell is controlled for the purpose of assisting the discharge in the subsequent address period 32, and in the address period 32, the discharge for determining the cell to emit light is performed. In the subsequent sustain period 33, discharge is repeatedly performed to cause the cell to emit light.

  FIG. 4 is a diagram illustrating an example of a basic configuration of a driver IC applied to the scan driver circuit described above.

  The driver IC 41 includes a logic unit of a low voltage power source and a driver unit of a high voltage power source of 100 V or higher in order to generate a high voltage scan pulse by an external control signal. In the following description, it is assumed that a 68-bit scan driver IC is used as an example.

  The driver IC 41 includes a 68-bit shift register SR that sequentially shifts the input data DA according to the clock signal CLK, a 68-bit latch circuit LT that latches the output of the shift register SR according to the latch control signal LAT, and 68 bits. It consists of 68 driver units DV that output drive signals in accordance with the corresponding 68 outputs. Each driver portion DV is composed of a transistor pair, and a diode is connected between each output of the driver portion DV and the high withstand voltage power sources VH and GND. Each output DVO1 to DVO68 of each driver unit DV is connected to each output terminal (OUT1 to OUT68) of the driver IC 41.

  In FIG. 4, OC is an output control signal for the driver unit DV, CLR is a reset signal for the shift resist SR, A / (/ B) is a data shift direction input control signal for the shift resist SR, DB is a data signal, and VDD is Each low-voltage power supply is shown.

  In the driver IC 41, in the logic unit of the low-voltage power supply, the data DA serially input from the image signal processing LSI is shifted bit by bit by the 68-bit shift register SR in synchronization with the clock signal CLK. The 68-channel output bits from the shift register SR are connected to the driver unit DV of the high voltage power supply through the latch circuit LT, and are output as scan pulses from the respective channel outputs in accordance with the shift operation of the shift resist SR. To do.

  FIG. 5 is a diagram illustrating an example of the drive waveform (a) in the address period and the sustain period and the operation (b) and (c) of the driver unit at the timing of the drive waveform. The operation of the driver unit is controlled using the output control signal OC.

  At the start of the address period, the output control signal OC is turned on, the H side transistor of the driver section DV is turned on, the L side transistor is turned off, and a high withstand voltage (VH) is inputted to all outputs ((1) State). During the address period, most driver sections DV are at VH, but only one channel driver section is in GND (state (2)) and outputs a scan pulse. After the scan pulse is generated, VH is output until the end of the address period (state (3)). Here, the scan lines are sequentially shifted, and one scan pulse is output for each channel.

  At the end of the address period, the H-side transistor of the driver section DV is turned off, the L-side transistor is turned on, VH is turned off, and GND is output.

  Outside the address period, the output control signal OC is cut off, the H-side transistor of the driver section DV is turned off, and the L-side transistor is turned on. In the sustain period, positive and negative sustain voltages are supplied from the power supply circuit connected to the GND terminal of the driver unit DV, and a sustain pulse is output through the diode (states (4) and (5)).

  FIG. 6 is a diagram illustrating an example of a connection configuration between the output terminal of the driver IC and the Y electrode described above.

  The driver IC 41 is configured to operate by connecting two output terminals per Y electrode of the plasma display panel 3. That is, two output terminals OUT1 and OUT2 of the driver IC 41 are connected to Y1 of one Y electrode. Similarly, OUT3 and OUT4 are connected to Y2,..., OUT67 and OUT68 are connected to Y34.

  FIG. 7 is a diagram for explaining the prior art, and is a diagram illustrating an example of a penetrating operation in an address period in the driver unit.

  In the driver IC of the scan driver circuit 8, with two output terminals connected, during normal operation, the two output terminals move at the same timing, the H side transistor of the output terminal OUT1 is OFF, and the L side transistor is OFF. In the case of ON, similarly for the output terminal OUT2, the H-side transistor is OFF and the L-side transistor is ON. Conversely, if the H-side transistor of the output terminal OUT1 is ON and the L-side transistor is OFF, the same applies to the H-side and L-side transistors of the output terminal OUT2.

  However, when the control signal malfunctions due to noise or the like, the two output terminals may move at different timings. For example, due to a malfunction, as shown in FIG. 7, the H-side transistor of the output terminal OUT1 is turned OFF, the L-side transistor is turned ON, the H-side transistor of the output terminal OUT2 is turned ON, and the L-side transistor is turned OFF. In this case, a through current flows from the high-voltage power supply VH through the H-side transistor of the output terminal OUT2 and the L-side transistor of the output terminal OUT1 along the path to GND. As described above, when a through current flows between the output terminals OUT1 and OUT2, the through operation is performed between the two output terminals, and the scan driver circuit 8 may be destroyed.

  Therefore, in the present embodiment, in the scan driver circuit 8 that operates by connecting two output terminals per Y electrode, the two output terminals are arranged so as to prevent a through operation between the two output terminals. It is configured to operate using a single operation signal.

  FIG. 8 is a diagram illustrating an example of a configuration of a driver IC of a scan driver circuit that can prevent a through operation between two output terminals.

  As described above (FIG. 4), the driver IC 41 includes a shift register SR that sequentially shifts input data according to a clock signal, a latch circuit LT that latches an output of the shift register SR according to a latch control signal LAT, A driver unit DV that outputs a drive signal in accordance with each output of the circuit LT and output terminals OUT1 to OUT68 that output a drive signal from the driver unit DV are configured.

  In this driver IC 41, in particular, two adjacent circuit wirings are connected between the latch circuit LT and the driver unit DV, and the two output terminals are operated using one operation signal. . That is, in the connection between the outputs LTO1 and LTO2 of the latch circuit LT and the inputs DVI1 and DVI2 of the driver unit DV, the circuit wiring of the output LTO1 is cut and the circuit wiring of the output LTO2 is connected to the inputs DVI1 and DVI2. Similarly, the circuit wiring of the output LTO3 is cut and the circuit wiring of the output LTO4 is connected to the inputs DVI3 and DVI4,..., And the circuit wiring of the output LTO67 is cut and the circuit wiring of the output LTO68 is connected to the inputs DVI67 and DVI68. To do.

  Thus, in the driver section DV, when the H side transistor of the output terminal OUT1 is ON and the L side transistor is OFF, the H side transistor of the output terminal OUT2 is ON and the L side transistor is OFF, In this case, when the H side transistor of the output terminal OUT1 is OFF and the L side transistor is ON, the H side transistor of the output terminal OUT2 is OFF and the L side transistor is ON. No through current flows between the transistor and the transistor at the output terminal OUT2. Similarly, no through current flows between the other output terminals OUT3 and OUT4, and between the output terminals OUT67 and OUT68.

  Therefore, according to the present embodiment, the circuit wiring inside the scan driver circuit 8 is adjacent between the latch circuit LT and the driver unit DV so that the two output terminals do not move at different timings. By connecting two circuit wirings and operating two output terminals using one operation signal, a through operation between the two output terminals can be prevented.

(Embodiment 2)
A plasma display apparatus according to Embodiment 2 of the present invention will be described with reference to FIG.

  In the plasma display device of the present embodiment, the configuration of the plasma display panel, the configuration of the plasma display device, the configuration of one field, the basic configuration of the driver IC, the terminal configuration, and the like are the same as those in FIGS. Since it is the same, description here is abbreviate | omitted. In the present embodiment, the configuration of a driver IC of a scan driver circuit different from that of the first embodiment will be described below.

  FIG. 9 is a diagram showing an example of the configuration of the driver IC of the scan driver circuit in the plasma display device of the present embodiment.

  The driver IC 41 includes a shift register SR, a latch circuit LT, a driver unit DV, and output terminals OUT1 to OUT68. In this embodiment, in particular, the latch circuit LT of the first embodiment and the driver unit DV are connected to each other. Instead, two adjacent circuit wirings are connected between the shift register SR and the latch circuit LT, and the two output terminals are operated using one operation signal.

  That is, in connecting the outputs SRO1 and SRO2 of the shift register SR and the inputs LTI1 and LTI2 of the latch circuit LT, the circuit wiring of the output SRO1 is cut and the circuit wiring of the output SRO2 is connected to the inputs LTI1 and LTI2. Thereafter, similarly, the circuit wiring of the output SRO3 is cut and the circuit wiring of the output SRO4 is connected to the inputs LTI3 and LTI4,... To do.

  Therefore, according to the present embodiment, two adjacent circuit wirings are connected between the shift register SR and the latch circuit LT, and the two output terminals are operated using one operation signal. Thus, as in the first embodiment, since no through current flows between the transistors in the driver portion DV of the driver IC 41, the through operation between the two output terminals can be prevented.

(Embodiment 3)
A plasma display device according to Embodiment 3 of the present invention will be described with reference to FIG.

  Also in the plasma display device of the present embodiment, the configuration of the plasma display panel, the configuration of the plasma display device, the configuration of one field, the basic configuration of the driver IC, the terminal configuration, and the like are shown in FIGS. The description here is omitted. Also in the present embodiment, the configuration of the driver IC of the scan driver circuit different from the first embodiment will be described below.

  FIG. 10 is a diagram showing an example of the configuration of the driver IC of the scan driver circuit in the plasma display device of the present embodiment.

  The driver IC 41 includes a shift register SR, a latch circuit LT, a driver unit DV, and output terminals OUT1 to OUT68. In this embodiment, in particular, the latch circuit LT of the first embodiment and the driver unit DV are connected to each other. Instead, two adjacent circuit wirings are connected between the driver portion DV and the output terminals OUT1 to OUT68, and the two output terminals are operated using one operation signal.

  That is, in the connection between the outputs DVO1 and DVO2 of the driver unit DV and the output terminals OUT1 and OUT2, the circuit wiring of the output DVO1 is cut and the circuit wiring of the output DVO2 is connected to the output terminals OUT1 and OUT2. Thereafter, similarly, the circuit wiring of the output DVO3 is cut and the circuit wiring of the output DVO4 is cut to the output terminals OUT3 and OUT4,... Connect to.

  Therefore, according to the present embodiment, two adjacent circuit wirings are connected between the driver unit DV and the output terminals OUT1 to OUT68, and two output terminals are used using one operation signal. By operating, the through current does not flow between the transistors in the driver portion DV of the driver IC 41 as in the first embodiment, so that the through operation between the two output terminals can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third embodiments, the example in which the odd-numbered circuit wiring is cut and connected to the even-numbered circuit wiring among the two adjacent circuit wirings has been described. It is also possible to cut the circuit wiring of the signal and connect the circuit wiring of the odd signal.

  Further, in the present invention, it is also possible not to form the circuit wiring for the portion where the circuit wiring is cut from the beginning. Furthermore, it is possible not to mount the circuit component for cutting the circuit wiring from the beginning. In this case, the driver IC of the scan driver circuit can be downsized.

  In addition, the present invention is not limited to the case where the circuit wiring is cut or the circuit wiring of the portion is not formed from the beginning, but between the latch circuit and the driver unit, between the shift register and the latch circuit, or A selection means such as a switch is provided between the driver unit and the output terminal, and one of the two adjacent circuit wirings is selected by the selection means, and one output signal is used for the two output terminals. It is also possible to operate.

  The present invention relates to a plasma display device, and is particularly applicable to a scan driver circuit that operates by connecting two output terminals per Y electrode of a plasma display panel.

It is a figure which shows an example of a structure of the plasma display panel mounted in the plasma display apparatus of Embodiment 1 of this invention. It is a figure which shows an example of a structure of the plasma display apparatus of Embodiment 1 of this invention. It is a figure which shows an example of a structure of 1 field in the plasma display apparatus of Embodiment 1 of this invention. In the plasma display apparatus of Embodiment 1 of this invention, it is a figure which shows an example of the basic composition of the driver IC applied to the scan driver circuit. In the plasma display device according to the first embodiment of the present invention, (a) to (c) are diagrams showing an example of drive waveforms in the address period and the sustain period and the operation of the driver unit at the timing of the drive waveforms. In the plasma display apparatus of Embodiment 1 of this invention, it is a figure which shows an example of the connection structure of the output terminal of driver IC, and a Y electrode. It is a figure which shows an example of the penetration operation | movement of the address period in a driver part in the plasma display apparatus of a prior art. In the plasma display apparatus of Embodiment 1 of this invention, it is a figure which shows an example of a structure of driver IC of a scan driver circuit which can prevent the penetration operation between two output terminals. In the plasma display apparatus of Embodiment 2 of this invention, it is a figure which shows an example of a structure of driver IC of a scan driver circuit which can prevent the penetration operation between two output terminals. It is a figure which shows an example of a structure of driver IC of a scan driver circuit which can prevent the penetration operation between two output terminals in the plasma display apparatus of Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Front plate, 2 ... Back plate, 3 ... Plasma display panel, 4 ... X electrode drive circuit, 5 ... Y electrode drive circuit, 6 ... Address electrode drive circuit, 7 ... Control circuit, 8 ... Scan driver circuit,
DESCRIPTION OF SYMBOLS 11 ... X electrode, 12 ... Y electrode, 13 ... Dielectric layer, 14 ... Protective layer, 15 ... Address electrode, 16 ... Dielectric layer, 17 ... Partition, 18-20 ... Phosphor,
21-30 ... subfield, 31 ... reset period, 32 ... address period, 33 ... sustain period,
41 ... Driver IC,
SR: shift register, LT: latch circuit, DV: driver unit, OUT1 to OUT68: output terminal.

Claims (2)

A scan pulse is sequentially applied to each of the plasma display panel, an X electrode driving circuit that is driven by applying a driving signal in common to the plurality of X electrodes of the plasma display panel, and each of the plurality of Y electrodes of the plasma display panel. A scan driver circuit that is driven by application, a Y electrode drive circuit that is driven by applying a drive signal during a reset period and a sustain period in common to a plurality of Y electrodes of the plasma display panel, and a plurality of addresses of the plasma display panel Each of the electrodes has an address electrode drive circuit that is driven by applying an address pulse in synchronization with the scan pulse in an address period,
The scan driver circuit includes a shift register that sequentially shifts input data according to a clock signal, a latch circuit that latches an output of the shift register according to a latch control signal, and a drive signal according to each output of the latch circuit A driver unit that outputs the output signal, and an output terminal that outputs a drive signal from the driver unit,
Connecting two adjacent wirings on the input side of the latch circuit;
Connecting the two connected wirings on the input side and one of the two adjacent output wirings from the shift register;
Each of the two output-side wires from the latch circuit corresponding to the two input-side wires of the latch circuit is connected to two adjacent input-side wires of the driver section. ,
The two adjacent output terminals of the driver unit corresponding to the two input-side wirings of the driver unit are connected to one of the Y electrodes of the plasma display panel. A plasma display device. The plasma display device according to claim 1, wherein
The driver unit has a plurality of driving units corresponding to the number of wirings on the output side from the latch circuit,
Each of the plurality of driving units includes first and second switching elements connected in series, a first diode connected in parallel with the first switching element, and parallel to the second switching element. A second diode connected to
A plasma display apparatus, wherein a connection node between a low potential side terminal of the first switching element and a high potential side terminal of the second switching element is connected to the output terminal .

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