JP4936574B2 - Encoding apparatus and control method thereof - Google Patents

Description

  The present invention relates to a technique for arithmetically encoding a binary symbol sequence generated from digital information such as image data.

  In recent years, with the advancement of digital signal processing technology, it has become possible to perform high-efficiency encoding of a large amount of digital information such as moving images, still images, and voices, and to perform recording on a small recording medium or transmission via a communication medium. By applying such technology, video encoding devices capable of converting TV broadcast and video camera images into streams have been developed. Among video coding methods for moving images, the standard H.264 established by ITU-T, among others. H.264 (also known as MPEG4 Part 10 / AVC) has attracted attention. In recent years, the compression effect of high-efficiency coding is largely due to entropy coding, and arithmetic coding can be cited as a particularly efficient entropy coding method. Also in H.264.

  H. H.264 employs arithmetic coding called Context-based Adaptive Binary Arithmetic Coding (hereinafter referred to as CABAC) and variable-length coding called Context-based Adaptive Variable length Coding (hereinafter referred to as CAVLC).

  Patent Document 1 has been proposed as a prior example focusing on the CABAC and CAVLC. The “image information encoding method and image information decoding method” disclosed in Patent Document 1 discloses an invention intended to limit the amount of input / output data to / from CABAC and guarantee the processing time of the decoder. Yes.

JP 2004-135251 A

  FIG. 5 is a flowchart showing a processing procedure of a conventional arithmetic coding method. This processing procedure is described in ITU-T H.264. It is defined by the H.264 standard and is known. H. The arithmetic coding in H.264, ie CABAC, corresponds to the input of binary symbols.

  In FIG. 5, it is determined whether or not the input of the symbol is completed in step S900. If it is determined that the input is not complete, the symbol is input in step S901. The symbol input here is a binary symbol of 0 or 1. Next, step S902 divides the section. The section is expressed by a lower end and a length in an integer area from 0 to 1023. The division of the section is to divide the section into two according to the ratio of occurrence probability of binary symbols. For example, when the occurrence probability of the symbol “0” is 75% and the occurrence probability of the symbol “1” is 25%, the section is divided at a ratio of 75:25 (in this case, the symbol “0” is the dominant symbol, the symbol “1” is called the inferior symbol). In subsequent step S903, one of the divided sections is selected in accordance with the input symbol.

  For example, as shown in FIG. 6, it is assumed that the current section is represented by a lower end value of 21 and a length of 320. Assume that the occurrence probability of 0 and 1 is 75% and 25%. If the input symbol is “1”, the section “1” is selected. As a result, the new lower end is 261 and the length is 80.

  In step S904, it is determined whether the length of the new section is less than 256. If the length of the section is 256 or more, the process returns to step S900. If the section length is 80 as in the example described with reference to FIG. 6 and is less than 256, the process branches to step S905.

  In step S905, it is determined whether the lower end value of the section is less than 256. If the lower end of the section is less than 256, the process branches to step S906, where “0” is output as a code string, and step S907 outputs a number “1” corresponding to the number of reserved bits described later as a code string. The reserved bit number is reset to zero here. Step S908 normalizes the section. Normalization is a process of enlarging the length of a section less than 256 and ensuring the accuracy of subsequent processing. In step S908, the lower end value and the section length are each doubled.

  If it is determined in step S905 that the lower end is 256 or more, the process branches to step S909, and it is determined whether the lower end of the section is less than 512. If the lower end of the section is less than 512, the process branches to step S910. If it is 512 or more, the process branches to step S912.

  In step S912, “1” is output as a code string, and in step S913, “0” corresponding to the number of reserved bits described later is output as a subsequent code string. The number of reserved bits is again reset to zero. In step S914, the section is normalized. In normalization by this step, the value obtained by subtracting 512 from the lower end and doubling it is used as the new lower end, and the length of the section is doubled.

  In step S909, if the lower end is less than 512, the process branches to step S910 to increase the number of reserved bits by one. In step S911, the section is normalized. In the normalization in step S911, 256 is subtracted from the lower end, and the section is also doubled. For example, in the example of FIG. 6, the lower end is 10 (= (261-256) × 2), and the length of the section is 160 (= 80 × 2). Further, the reserved bit is also increased to “1”. After each step of these normalization processes, the process returns to step S904 again, and the normalization process is repeated in the same manner until the length of the section becomes 256 or more.

  For example, in the example of FIG. 6, since the length of the section after normalization is 160, the process proceeds from step S904 to step S905 again. Since the lower end is 10, the process proceeds to step S906, where “0” is output, and since the number of reserved bits has been increased to 1 earlier, one “1” is output (step S907). That is, the code string “01” is output. Further, in the normalization step S908, the lower end is doubled to 20 and the section length is also doubled to 320. Here, since the length of the section is 256 or more, the process returns from step S904 to S900. In step S900, the end of the input symbol is detected, and the above processing is repeated until the process branches to the end processing step of step S915.

  The present inventor considered that the above conventional arithmetic coding method has two problems. First, the number of steps for processing one input symbol is very large by the loop from step S904 to step S914. This causes an increase in processing time by software and an increase in circuit scale by hardware. Second, when the increase in the number of reserved bits in step S910 is repeated, the memory required for holding the value increases, and the number of times of processing in steps S907 and S913, which is a process for eliminating the reserved bits, also increases. It is.

  The present invention has been made in view of such a problem, and if arithmetic coding is applied to hardware, the circuit can be simplified and power consumption can be reduced, and if applied to software, It is an object of the present invention to provide a technology that enables reduction of memory consumption and high-speed processing due to simplification of processing.

In order to solve this problem, for example, the encoding apparatus of the present invention has the following configuration. That is,
Encoding using arithmetic coding that sequentially inputs binary symbols to be encoded, generates binary data indicating a decimal point value of 0 or more and less than 1 as encoded data, and outputs the generated encoded data A device,
Each time a binary symbol is input, a section on a number line expressed with finite precision is divided into two according to the ratio of the probability of occurrence of the dominant symbol and the inferior symbol, and is divided according to the value of the input binary symbol. and the district between the selection means to repeat the selection of the section,
Based on the length of the selection period selected in said section between selection means, and the normalized count determining means for determining the number of normalization processing for expanding the length of the selected segment,
Based on prior Symbol selection section, a calculating means for calculating the number of output bits that can be output as encoded data,
If the calculated output number of output bits calculated in unit is greater than 0, the encoded data having the output bits minutes, generated based on the value of the upper or lower end of the front Symbol selection period, and outputs, the number of pending bit An encoded data output means for outputting the number of bits corresponding to the number of reserved bits when non-zero, and clearing the number of reserved bits to zero,
A reserved bit update unit that adds a result obtained by subtracting a value indicated by the number of output bits calculated by the calculation unit from the value indicating the number of times determined by the normalization number determination unit to the reserved bit number;
Normalization means for normalizing the selected section by the number of times of normalization determined by the normalization frequency determination means.

  According to the present invention, the number of times of increasing the number of reserved bits can be reduced as compared with the conventional technology. Therefore, when applied to hardware, the circuit can be simplified and the power consumption can be reduced. Become. Further, if applied to software, it is possible to reduce the memory consumption accompanying the simplification of processing and to further speed up the processing.

It is a flowchart which shows the process sequence of the arithmetic coding part in 1st Embodiment. It is a Venn diagram which shows the classification | category of the area during the arithmetic coding process in the 1st embodiment. It is a flowchart which shows the process sequence of the arithmetic coding part in 2nd Embodiment. It is a figure which shows the example of the area in the arithmetic coding in 2nd Embodiment. It is a flowchart which shows the conventional arithmetic coding process sequence. It is a figure for demonstrating a normalization process. It is a block block diagram of the encoding part in the apparatus which embodiment applies. It is a specific block block diagram of the arithmetic coding part in 1st Embodiment. It is a specific block block diagram of the arithmetic coding part in 2nd Embodiment.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 7 is a block diagram illustrating a configuration example of the apparatus according to the present embodiment. 101 is a video input unit, 102 is a conversion unit, 103 is a quantization unit, 104 is a CAVLC coding unit, 105 is a CABAC coding unit, 106 is a binarization unit, 107 is an arithmetic coding unit, 108 is a selection unit, Reference numeral 109 denotes a stream output unit. The encoding apparatus in this embodiment is an H.264 standard. Based on the H.264 standard, high-efficiency encoding processing is performed in the following procedure. Note that this encoding apparatus is applicable to an imaging apparatus (video camera) and a video recording / reproducing apparatus.

  The digital video signal input from the video input unit 101 is supplied to the conversion unit 102. The conversion unit 102 divides the image data represented by the input digital video signal into blocks composed of, for example, 16 × 16 pixels, and converts each block into a coefficient string. The conversion unit 102 reduces the visual redundancy of the information amount in the block by motion prediction processing, motion compensation processing, orthogonal transform processing (frequency conversion), and the like.

  The coefficient sequence obtained by the conversion process of the conversion unit 102 is supplied to the quantization unit 103. The quantization unit 103 quantizes the input coefficient sequence according to a preset quantization parameter.

  The information amount of the coefficient sequence is reduced according to the size of the quantization parameter in the quantization unit 103. The quantized coefficient sequence is supplied to the CAVLC encoding unit 104 and the CABAC encoding unit 105. Since the CAVLC encoding unit 104 is not directly related to the present invention, a detailed description thereof will be omitted, and the CABAC encoding unit 105 will be described.

  The binarizing unit 106 in the CABAC encoding unit 105 converts the input coefficient sequence into 0 and 1 binary symbol sequences.

  The arithmetic encoding unit 107 inputs the sequence of the binary symbol sequence binarized by the binarizing unit 106, and generates a compressed arithmetic encoded data sequence by performing processing according to the procedure described later. Output. At this time, since the binarization unit 106 can convert each coefficient into a binary symbol string on a one-to-one basis using a table, the processing can be executed in units of one coefficient. On the other hand, the arithmetic encoding unit 107 needs to perform processing for each binary symbol.

  The code sequence generated by the CAVLC encoding unit 104 and the code sequence generated by the CABAC encoding unit 105 that has undergone arithmetic encoding are respectively supplied to the selection unit 108, and the selection unit 108 selects one of the code sequences ( Stream) is selected as output. Thereafter, the selected stream is output from the stream output unit 109.

  The feature of this embodiment is the arithmetic coding unit 107 in FIG. Therefore, the arithmetic encoding unit 107 will be described in more detail.

  As described above, arithmetic coding is such that division and selection are repeated according to the value of an input symbol, and a decimal point value of 0 or more and less than 1 is used as an encoding result. Since the decimal point value of 0 or more and less than 1 is in the format of “0.xxx... (X is 0 or 1)”, “xxx...” Excluding the integer part and the decimal point is the encoded data. The bit at the first decimal point indicates “0.5” in decimal, and the bit at the second decimal point indicates “0.25”. That is, the value represented by the i-th digit of the decimal point can be said to be half of the value represented by the (i-1) -th bit of the decimal point. For example, a decimal number “0.75” can be expressed as a binary number “0.11”.

  Further, since processing is performed by an electronic circuit or a computer program, the lower end, upper end, and section length of the section must be expressed by a register having a limited number of bits. However, as the number of digits after each decimal point is obtained, the length of the section is gradually reduced accordingly. That is, the difference between the register values defining the lower end and the upper end of the interval is gradually reduced, and the accuracy when the interval is divided by the ratio of the occurrence probability of symbols is lowered. Therefore, in order to effectively function the number of bits to be used, when the length of the section becomes less than a certain threshold value, it is necessary to expand the length of the section. The process of enlarging the length of this section is called normalization.

  FIG. 1 is a flowchart showing an arithmetic coding processing procedure in the arithmetic coding unit 107 in the present embodiment. The processing contents of the arithmetic encoding unit 107 will be described below according to this flowchart.

  First, in step S100, it is determined whether or not input of symbols to be encoded has been completed. This determination may be made by counting the number of input symbols and determining whether the number has reached the number of symbols that is a predetermined coding unit.

  If it is determined that the encoding process is incomplete, the process proceeds to step S101, and one symbol is input. The encoding target symbol in this embodiment is a binary symbol of 0 or 1 output from the binarization unit 106.

  Next, in step S102, the section is divided. The interval at the start of encoding ranges from 0 to 1023. That is, the lower end is 0, the section length is 1024, the lower end is defined as 0, and the upper end 1023 is defined as an integer “1”, and the interval between them is defined to represent the decimal point. In this case, the lower end and the upper end may each be stored and held in a 10-bit register.

  The division processing of the section in step S102 is to divide the section into two according to the ratio of the occurrence probability of the input binary symbols. For example, if the occurrence probability of 0 is 75% and the occurrence probability of 1 is 25%, the section is divided at a ratio of 75:25.

  In subsequent step S103, one of the divided sections is selected according to the input symbol. For example, as shown in FIG. 6, it is assumed that the lower end of the current section is “21”, the length of the section is “320”, and the occurrence probabilities of symbols 0 and 1 are 75% and 25%. If the input symbol is “1”, one section is selected, the new lower end is “261”, and the length of the section is “80”.

  In step S104, the length of the new section is compared with the threshold “256”. When the length of the section is “256” or more, the process returns to step S100.

  As shown in FIG. 6, when the length of the section is “80” and is less than “256”, the process branches to step S105.

  In step S105, the value at the lower end of the section is determined. If the value at the lower end is less than “512”, the process branches to step S106. In this step S106, it is determined whether or not the value at the upper end of the section is less than “512”.

  If it is determined in step S106 that the upper end value is less than “512”, the process proceeds to step S107.

  The process proceeds to step S107 when both the upper and lower values of the selected section are “512” or less. Accordingly, in step S107, “0” is output as the encoded bit. In step S108, “1” is output by the number indicated by the number of reserved bits at that time, and then the number of reserved bits is reset to “0”. If the number of reserved bits immediately after the processing proceeds to step S108 is “0”, nothing is done. In step S109, the section is normalized. The normalization process in step S109 is a process of enlarging a section that is less than “256” and ensuring the accuracy of the subsequent encoding process. In this step S109, the value obtained by doubling the lower end value is set as the lower end value of the updated section. In addition, the length of the section is doubled, and the result is set as the length of the updated section. Then, the process returns to step S104.

  On the other hand, if it is determined in step S105 that the value of the lower end of the selected section is “512” or more, the process branches to step S112. That is, both the upper and lower values of the current section are “512” or more. In step S112, “1” is output as the value of the target digit as a bit after encoding. In the subsequent step S113, the number of reserved bits “0” is output, and then the number of reserved bits is reset to “0”. In step S114, the section is normalized. The normalization process in step S114 is a process of enlarging a section that is less than “256” and ensuring the accuracy of the subsequent encoding process. In this step S114, 512 is subtracted from the lower end value, and the value obtained by doubling the subtraction result is set to the updated lower end value. Further, the result of doubling the length of the section is set as the length of the updated section. Thereafter, the process returns to step S104.

  If it is determined in step S106 that the value at the upper end of the section is “512” or more, the process proceeds to step S110. The process proceeds to step S110 when the lower end value of the section is less than “512” and the upper end value of the section is “512” or more. That is, whether the bit of the target digit is “0” or “1” indicates that it is not determined at this time. Therefore, in step S110, the number of reserved bits is increased by one. Subsequently, in step S111, the section is normalized. In the normalization in step S111, “256” is subtracted from the value at the lower end of the section, and the value obtained by doubling the subtraction result is set as the updated lower end value. In addition, a process of setting the result of doubling the length of the section to the length of the updated section is performed. Thereafter, the process returns to step S104.

  Thus, when the processes of steps S100 to S114 are completed for all symbols to be encoded, the end process of step S115 is performed. In this end processing, one convenient value is determined in binary notation between the upper and lower ends of the section determined in the previous processing, and a bit of an unoutput digit is output according to the determined value. The process to do is performed. For example, it is assumed that the value at the upper end of the interval is equal to the value at the lower end of the interval (the length of the interval is 0), and the encoded bits and reserved bits at that time are output.

  The processing contents of the arithmetic encoding unit 107 of this embodiment have been described above. The processing of this embodiment can halve the number of executions of the step of increasing the number of reserved bits, compared to the above-described conventional method of FIG. 5 described above.

  For example, in the example of FIG. 6, the value of the lower end of the new section obtained by section selection is “261”. In the conventional method, the process proceeds to step S910 in which the number of reserved bits is increased by branching from steps S905 and S909.

  On the other hand, according to the present embodiment, the value at the lower end of the section is “261” and the value at the upper end of the section is “341” (= 261 + 80). Then, the processing after step S107 is performed. That is, in the above case, according to the present embodiment, the process of increasing the reserved bit is not performed.

  In step S107, bit “0” is output as encoded data. Thereafter, the process proceeds to step S108. In the case of FIG. 6, the number of reserved bits remains zero. Accordingly, this step S108 is not processed. In the normalization in step S109, the value of the lower end of the current section and the length of the section are each doubled. That is, the value at the lower end of the section is “522” and the length of the section is “160”. Thereafter, the process returns to step S104. Since the section length “160” is less than the threshold value “256”, the process proceeds to step S112 after the branch process in steps S104 and S105. In step S112, “1” is output, and step S113 is not processed. As a result of the normalization process in step S114, the value of the lower end of the section is “20” (= (522-512) × 2), and the length of the section is “320” (= 160 × 2).

  As a result, the encoded data to be output is “01”, the value at the lower end of the section is “20”, and the length of the section is “320”. What should be noted here is that, in the case of this embodiment, the same output and the same section state as the conventional method shown in FIG.

  Here, the difference between the processing of the prior art and the present embodiment will be described with reference to FIG. FIG. 2 is a Venn diagram in which sections before normalization are classified by the range of the upper end and the lower end.

  In the conventional method, the length of the section is less than “256”, and the bit “0” is output as encoded data only in the area 201 whose lower end value is less than “256”. That is, the remaining areas 202 and 203 must be processed to increase the reserved bits.

  On the other hand, in the method according to the present embodiment, when the length of the section is less than “256”, when the section satisfies the conditions of the areas 201 and 202, the bit “0” is output as encoded data. The reserved bit is increased only when the value at the upper end of the region 203, that is, the section is “512” or more and the value at the lower end of the section is less than “512”.

  In this way, as shown in this embodiment, the classification is refined by incorporating the upper end, and when the section is in the area 202 that originally does not need to be reserved, “0” is output as encoded data. The number of bit increase processes can be reduced to half that of the prior art. Incidentally, in the area 204 where the value at the lower end of the section indicates “512” or more, “1” is output as the bit of the encoded data. Therefore, the processing of the present embodiment in the region 204 where the lower end value of the section indicates “512” or more is consistent with the conventional technique and the method.

  FIG. 8 is a block diagram showing a specific internal configuration of the arithmetic coding unit 107 in the embodiment.

  As shown in the figure, the arithmetic coding unit 107 of the present embodiment includes an input unit 801, a control unit 802, an end processing unit 803, an output switching unit 804, an interval update unit 805, a normalization unit 806, an output bit generation unit 807, a hold The bit processing unit 808 is configured. The operation in this configuration will be described again in association with the flowchart of FIG.

  The input unit 801 sequentially inputs binary symbols from the binarization unit 106 in step S101. When the input unit 801 detects that the number of input symbols has reached a preset number of coding units, the input unit 801 outputs an end determination signal to the control unit 802.

  The section update unit 805 performs section division in step S102 and section selection in step S103, and supplies signals indicating the values of the upper and lower ends of the selected section to the control unit 802 and the normalization unit 806.

  The control unit 802 supplies a control signal to each block based on a signal supplied from each block.

  The termination processing unit 803 performs termination processing in step S <b> 115 according to the trigger signal from the control unit, and supplies the termination bit string to the output switching unit 804.

  The output bit generation unit 807 supplies “0” or “1” to the output switching unit 804 in accordance with the control signal from the control unit 802. This process corresponds to step S107 or step S112 in FIG.

  The reserved bit processing unit 808 supplies the reserved bit string in step S108, step S110, and step S113 to the output switching unit 804 in accordance with the control signal from the control unit 802.

  The output switching unit 804 selects and outputs one of the bit strings supplied from the end processing unit 803, the output bit generation unit 807, and the reserved bit processing unit 808 in accordance with the control signal from the control unit 802.

  The normalization unit 806 receives a control signal from the control unit 802 and a signal representing the upper and lower end values from the section update unit, normalizes the section, and supplies the upper and lower ends of the new section to the section update unit 805. . This process corresponds to steps S109, S111, and S114 of FIG. 1, but which process is performed is determined by a control signal from the control unit 802. The values of the upper end and the lower end changed by normalization are supplied to the control unit 802 via the section update unit 805.

  The control unit 802 generates a signal for controlling each of these blocks depending on the determinations of steps S100, S104, S105, and S106, which are branch processes in the flowchart of FIG.

  As described above, according to the present embodiment, when a binary symbol sequence is encoded, the number of times of increasing the number of reserved bits can be reduced to half that of the previous number, and the number of generated bits can be reduced. It is also possible to guarantee the compatibility of encoded data. Therefore, it is possible to prevent an increase in circuit scale due to hardware.

  Further, it has an input device (video camera, image scanner, or storage device for storing uncompressed image data) for inputting image data to be encoded, and the other components shown in FIG. Of course, it is also possible to use a high-level control unit such as a RAM and a RAM storing a program executed by the control unit. Further, only the arithmetic coding unit 107 in FIG. 7 may be realized by a microcomputer and software executed by the microcomputer.

<Second Embodiment>
A second embodiment according to the present invention will be described. FIG. 3 is a flowchart showing a processing procedure of the arithmetic coding unit 107 in the second embodiment. Except for the arithmetic coding unit 107, the second embodiment is the same as the first embodiment, and a description thereof will be omitted.

  Hereinafter, the processing procedure of the arithmetic encoding unit 107 will be described with reference to the flowchart of FIG.

  First, in step S300, it is determined whether or not input of symbols to be encoded has been completed. This determination may be made by counting the number of input symbols and determining whether the number has reached the number of symbols that is a predetermined coding unit.

  If it is determined that the encoding process is incomplete, the process proceeds to step S301, and one symbol is input. The encoding target symbol in this embodiment is a binary symbol of 0 or 1 output from the binarization unit 106.

  Next, in step S302, the section is divided. At the start of encoding, the lower end of the section is 0 and the length of the section is 1024.

  The division processing of the section in step S302 is to divide the section into two according to the ratio of the occurrence probability of the input binary symbols. For example, if the occurrence probability of 0 is 75% and the occurrence probability of 1 is 25%, the section is divided at a ratio of 75:25. In step S303, one of the divided sections is selected according to the input symbol. For example, as shown in FIG. 6, it is assumed that the section is represented by the lower end 21 and the length 320, and the occurrence probabilities of the symbols “0” and “1” are 75% and 25%. In this case, when the input symbol is “1”, one section is selected, the lower end of the new section is “261”, and the length is “80”.

  In step S304, the number of times of normalization is calculated based on the length of the new section selected in step S303. As already described, the normalization process is a process that occurs when the length of the section is less than 256 and doubles the length of the section. Then, the normalization process is repeated until the length of the section becomes 256 or more.

That is, the relationship between the section length and the number of normalizations is as follows.
・ If the section length is 128 or more and less than 256, the normalization count is 1
・ If the section length is 64 or more and less than 128, the normalization count is 2
・ If the section length is 32 or more and less than 64, the number of normalization is 3 times,
・ If the section length is 16 or more and less than 32, the normalization count is 4 times.
・ If the section length is 8 or more and less than 16, the number of normalization is 5 times.
・ If the section length is 4 or more and less than 8, the number of normalization is 6 times.

  Considering the above, when the length of the section is expressed in binary form with 9 bits, the number of normalizations coincides with the number of consecutive zeros from the most significant bit (MSB) to the least significant bit (LSB). Accordingly, in step S304, the number of consecutive zeros is counted from the MSB, and the counted value is obtained as the number of normalizations. The method for obtaining the number of normalizations is not limited to the above. For example, the logarithm of the length of the interval in which 2 is low is obtained, and the decimal part of the logarithm is rounded down. A value obtained by subtracting the rounded down logarithm from 8 may be used as the normalization count. However, the former can be realized by a simple process or a simple circuit configuration.

  In step S305, the number of code bits to be determined and output is calculated. If there is no processing for increasing the reserved bits, the number of normalizations and the number of determined output bits match.

  For example, each of the sections 401, 402, and 403 in FIG. 4 indicates that the length of the section is “128” or more and less than “256”. Therefore, the number of normalizations for the sections 401, 402, and 403 is one. Since the upper end of the section 401 is less than “512”, “0” is output as a bit of encoded data. Since the lower end of the section 402 is “512” or more, “1” is output.

  On the other hand, since the lower end of the section 403 is less than “512” and the upper end is “512” or more, only the reserved bit is increased by 1, and the bit of the encoded data at this point is not output. That is, when the threshold value “512” exists between the upper end and the lower end of a certain section, the reserved bit is increased by “1” and the encoded data is not output.

  The above is examined in more detail as follows.

  Assume that the upper and lower ends of the section are represented by 10 bits. When the upper end and the lower end of a certain section are both less than “512”, the most significant bits (MSB) of the upper end and the lower end are both “0”. When both the upper end and the lower end of a certain section are “512” or more, the MSBs of the upper end and the lower end are both “1”. When the section spans “512”, that is, when the lower end <512 ≦ the upper end, the MSBs of the upper end and the lower end do not match.

  Therefore, when the upper and lower MSBs match, one of the output bits is determined. If the MSBs at the upper end and the lower end do not match, the reserved bit should be increased by “1”. The same can be considered for the case of multiple times of normalization.

Again, pay attention to FIG. The section 404 in FIG. 4 indicates that the lower end is “270”, the upper end is “389”, and the length of the section is “119” (= 389-270).
According to the procedure of the first embodiment described above, a 2-bit code “01” is output as a result of the two times of normalization. The number of output bits is “2” after the first normalization after the upper and lower ends of the section after the first normalization do not cross “512” and the upper and lower ends are doubled. This is because this section does not cross "512". In other words, if the section after the first normalization does not cross “256”, it can be said that the section after the second normalization that is doubled does not cross “512”. That is, if the upper and lower ends of the section do not cross “512”, the number of output bits is 1, and if the section does not cross “256”, the number of output bits is 2, and if “128” does not cross The number of output bits is determined as 3. After all, when the upper end and lower end of the section are expressed in binary with 10 bits, the number of coincidence bits from the most significant bit of both is equal to the number of output bits. However, since the number of output bits does not exceed the allowable number of normalizations, the number of output bits is clipped with the allowable number of normalizations as an upper limit.

  Returning to the description of FIG. The number of output bits calculated as described above is determined. In step S306, it is determined whether or not the number of output bits is “1” or more. When it is determined that the number of output bits is “1” or more, the processing from step S307 to step S309 is executed.

  In steps S307 to S309, the bit string is output as a code. At this time, the output bit string is the matching bit string itself at the upper end and the lower end of the section.

  For example, in the case of the section 404 in FIG. 4, the upper end is “389” and the lower end is “270”. When this is expressed in binary, the upper end is “0110000101” and the lower end is “0100001110”. Therefore, since both two bits “01” match from the most significant bit, a matching bit string “01” is output.

  In step S310, the number of reserved bits is updated. A value obtained by subtracting the number of output bits from the number of normalizations is added to the number of reserved bits. Thereafter, in step S311, the section is normalized. The process of removing the output bit string from the lower end (making it zero) and doubling it by the number of times of normalization is repeated. Similarly, the length of the section is repeated twice as much as the number of times of normalization. Here, repeating N times N times is the same even if it is replaced with N-bit left shift calculation.

  In the step of outputting the bit string in steps S307 to S309, if the number of reserved bits is 1 or more, first in step S307, only the first bit of the output bit string is output. In step S308, the inverted bits of the first bit are output by the number of reserved bits. In step S309, the remaining output bit strings are output.

  For example, assume that the reserved bit count is “3” when the section 404 in FIG. 4 is reached. In this case, the first bit “0” of the output bit string “01” is output first, and then “1” obtained by inverting “0” is output as three reserved bits, that is, “111”. The remaining bit string “1” (the second bit of “01”) is output in step S309. Therefore, the encoded data output in this step is “01111”. The number of reserved bits is reset to zero here.

  Thereafter, returning to step S300, the processes of steps S301 to S311 are repeated until the end of the input symbol is determined. When the end of the input symbol is determined, the end process of step S315 is performed.

  As can be seen from the flowchart of FIG. 3, since the number of normalizations and the number of output bits are calculated and processed collectively, it can be seen that the loop structure is remarkably reduced compared to the conventional method. . It can also be seen that one input symbol can be processed in a single loop.

  FIG. 9 is an internal block configuration diagram of the arithmetic coding unit 107 in the second embodiment for performing the above-described processing. The arithmetic encoding unit 107 according to the second embodiment includes an input unit 901, a control unit 902, an end processing unit 903, an output switching unit 904, an interval update unit 905, a normalization unit 906, an output bit generation unit 907, and reserved bit processing. A unit 908, a coincidence bit detection unit 909, and a section length calculation unit 910. The operation of each processing unit will be described below in association with the flowchart of FIG.

  In step S301, the input unit 901 sequentially inputs the binary symbols from the binarization unit 106. In addition, when the input unit 801 detects that the number of input symbols has reached a preset number that is an encoding unit, the input unit 801 outputs an end determination signal to the control unit 902.

  The section update unit 905 performs section division processing in step S302 and section selection processing in step S303. Then, the section update unit 905 supplies signals indicating the values of the upper and lower ends of the selected section to the coincidence bit detection unit 909, the section length calculation unit 910, and the normalization unit 906.

  The coincidence bit detection unit 909 compares the values of the upper end and the lower end supplied from the interval update unit 905, and counts the number of bits that continuously match from the most significant bit in the binary representation. This process corresponds to step S305, and supplies the number of matched bits to the control unit 902.

  The section length calculation unit 910 performs a process of calculating the length of the section by subtracting the lower end value from the upper end value supplied from the section update unit 905 (corresponding to step S304), and a signal indicating the length of the section Is supplied to the control unit 902.

  The control unit 902 calculates the required number of normalizations from the length of the section input from the section length calculation unit 910 and supplies the number of normalizations to the normalization unit 906.

  The normalization unit 906 normalizes the values of the upper end and the lower end supplied from the section update unit according to the number of normalizations supplied from the control unit 902, and supplies the upper end and the lower end of the new section to the section update unit 905. This process corresponds to step S311, and normalization for the number of times is processed in a single step without performing a loop process.

  Further, the control unit 902 supplies a control signal to each block based on a signal supplied from each block.

  The control unit 902 outputs a trigger signal to the end processing unit 903 when receiving the end determination signal from the input unit 901. In response to the trigger signal from the control unit 902, the end processing unit 903 performs end processing corresponding to step S315, and outputs an end bit string to the output switching unit 904.

  The output bit generation unit 907 supplies “0” or “1” to the output switching unit 904 according to the control signal from the control unit 902. This process corresponds to steps S307 and S309 in the flowchart of FIG. 3, and generates a number of output bits corresponding to the number of coincidence bits detected by the coincidence bit detection unit 909.

  The reserved bit processing unit 908 supplies the reserved bit string in step S308 and step S310 to the output switching unit 904 in accordance with the control signal from the control unit 902.

  The output switching unit 904 selects and outputs one of the bit strings supplied from the end processing unit 903, the output bit generation unit 907, and the reserved bit processing unit 908 according to the control signal from the control unit 902.

  Note that the control unit 902 performs processing corresponding to the branch determination processing corresponding to steps S300 and S306 in the flowchart of FIG. 3, and issues a control signal for each block.

  As described above, according to the second embodiment, it is possible to reduce the loop processing of arithmetic coding processing and to suppress an increase in the number of reserved bits as compared with the conventional case. As a result, it is possible to provide an arithmetic coding apparatus that can process with a smaller circuit scale and power consumption.

  7 has an input device for inputting image data to be encoded (an imaging device such as a video camera, an image scanner or a video camera, or a storage device for storing uncompressed image data). It is of course possible to configure each component shown by an advanced control unit such as a microcomputer and a RAM that stores a program executed by the control unit. Further, only the arithmetic coding unit 107 in FIG. 7 may be realized by a memory storing a microcomputer and software executed by the microcomputer.

  Further, in the first and second embodiments, the example applied to the imaging apparatus (video camera) and the video recording / reproducing apparatus has been described. However, any apparatus having a configuration for generating a binary symbol as encoding target information may be used. Since the present invention can be applied, the present invention is not limited by the above embodiment.

  In general, software, that is, a computer program is stored in a computer-readable storage medium such as a CD-ROM. Then, the computer readable storage medium is set in a computer reading device (for example, a CD-ROM drive) and copied or installed in the system, so that the computer can execute the corresponding computer program. Therefore, it is obvious that such a computer readable storage medium falls within the scope of the present invention.

Claims (7)

Encoding using arithmetic coding that sequentially inputs binary symbols to be encoded, generates binary data indicating a decimal point value of 0 or more and less than 1 as encoded data, and outputs the generated encoded data A device,
Each time a binary symbol is input, a section on a number line expressed with finite precision is divided into two according to the ratio of the probability of occurrence of the dominant symbol and the inferior symbol, and is divided according to the value of the input binary symbol. and the district between the selection means to repeat the selection of the section,
Based on the length of the selection period selected in said section between selection means, and the normalized count determining means for determining the number of normalization processing for expanding the length of the selected segment,
Based on prior Symbol selection section, a calculating means for calculating the number of output bits that can be output as encoded data,
If the calculated output number of output bits calculated in unit is greater than 0, the encoded data having the output bits minutes, generated based on the value of the upper or lower end of the front Symbol selection period, and outputs, the number of pending bit An encoded data output means for outputting the number of bits corresponding to the number of reserved bits when non-zero, and clearing the number of reserved bits to zero,
A reserved bit update unit that adds a result obtained by subtracting a value indicated by the number of output bits calculated by the calculation unit from the value indicating the number of times determined by the normalization number determination unit to the reserved bit number;
An encoding apparatus comprising: normalization means for normalizing the selected section by the number of normalization times determined by the normalization number determination means. The normalization number determination means includes means for counting the number of 0s from the most significant bit indicating the length of the selected section to the lower order, and the counted value is used as the number of normalizations. encoding apparatus according to 1.   The calculation means includes means for comparing the value at the upper end of the selected section with a value indicating the lower end, and calculating the number of consecutive common bits from the most significant bit toward the lower order. The encoding apparatus according to claim 1, wherein the number of output bits is determined from: Furthermore, image data input means for inputting image data;
A frequency conversion means for converting the frequency of the input image data;
A quantization means for quantizing coefficient data obtained by frequency conversion;
The encoding according to any one of claims 1 to 3 , further comprising: binarizing means that binarizes coefficient data quantized by the quantizing means and outputs the binarized symbol data. apparatus. Encoding using arithmetic coding that sequentially inputs binary symbols to be encoded, generates binary data indicating a decimal point value of 0 or more and less than 1 as encoded data, and outputs the generated encoded data An apparatus control method comprising:
Each time a binary symbol is input, a section on a number line expressed with finite precision is divided into two according to the ratio of the probability of occurrence of the dominant symbol and the inferior symbol, and is divided according to the value of the input binary symbol. and the district between the selection process is repeated to select the interval,
Based on the length of the selection period selected in about compartment between election択工, normalized count determination step of determining the number of normalization processing for expanding the length of the selected segment,
Based on prior Symbol selection section, a calculation step of calculating the number of output bits that can be output as encoded data,
If the calculated output number of output bits calculated in step is larger than 0, the encoded data having the output bits minutes, generated based on the value of the upper or lower end of the front Symbol selection period, and outputs, the number of pending bit An encoded data output step of outputting data of the number of bits corresponding to the number of reserved bits when non-zero, and clearing the number of reserved bits to zero;
A reserved bit update step of adding a result obtained by subtracting a value indicated by the number of output bits calculated in the calculation step from the value indicating the number of times determined in the normalization number determination step to the reserved bit number;
And a normalization step of normalizing the selected section by the number of times of normalization determined in the normalization frequency determination step. A computer program that causes the computer to function as each unit according to any one of claims 1 to 4 when the computer reads and executes the computer program. A computer-readable storage medium storing the computer program according to claim 6 .

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