JP4906140B2 - Substrate processing system - Google Patents

Description

  The present invention relates to a substrate processing system suitable for a technique for performing patterning a plurality of times on a film to be processed of a substrate such as a semiconductor wafer.

  In the manufacture of semiconductor devices, a photolithography technique is used to form a circuit pattern on a semiconductor wafer (hereinafter simply referred to as a wafer) that is a substrate to be processed. Circuit pattern formation using photolithography involves applying a resist solution on a wafer to form a resist film, irradiating the resist film with light and exposing the resist film so as to correspond to the circuit pattern. Is carried out by a procedure such as developing.

  In recent years, semiconductor devices tend to be highly integrated from the viewpoint of improving the operation speed, and so in the photolithography technology, miniaturization of circuit patterns formed on a wafer is required. For this reason, the wavelength of light used for exposure has been conventionally shortened, but the current situation is that it cannot sufficiently cope with ultrafine semiconductor devices of 45 nm node and beyond.

  Therefore, as a patterning technique capable of dealing with ultrafine semiconductor devices of 45 nm node and beyond, a technique of performing patterning a plurality of times when forming a pattern of one layer has been proposed (for example, Patent Document 1). Among these, the technique of performing patterning twice is called double patterning.

  In double patterning, two exposures are performed with different exposure patterns in order to form a single layer pattern. Therefore, when a conventional apparatus is applied, it is necessary to repeat photolithography and etching twice. However, this method has a problem in terms of productivity because the cost for forming a single layer pattern is doubled and the process becomes longer. In order to solve such a problem, a method of performing etching after repeating photolithography twice with different exposure patterns has been studied.

  However, the present situation is that a system or method for efficiently performing double patterning by such a method has not been established.

JP-A-7-147219

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a substrate processing system capable of performing patterning a single layer a plurality of times with high efficiency.

In order to solve the above problems, in the first aspect of the present invention, a carrier block that carries in and out a carrier that stores a plurality of substrates;
A processing unit for performing a coating process for forming a coating film including a photosensitive material film on a substrate carried one by one from a carrier block, and a developing process for developing the photosensitive material film exposed to a predetermined exposure pattern;
An interface block that delivers a substrate between the processing unit and an exposure apparatus that exposes the photosensitive material film in a predetermined exposure pattern;
A substrate processing system comprising a substrate transport mechanism for transporting a substrate between them, and capable of supporting an exposure apparatus that performs exposure at least twice on one substrate,
The processing unit includes a first coating processing unit that performs a first coating process corresponding to a first exposure, a first development processing unit that performs a first development process, and a second time corresponding to a second exposure. A second application processing unit for performing an application process and a second development processing unit for performing a second development process;
A first stacked body in which the first coating processing section is stacked on the second development processing section, and a second stacked body in which the second coating processing section is stacked on the first development processing section. And a substrate processing system characterized by being juxtaposed.

  In the first aspect, the interface block may include a buffer unit that buffers a plurality of substrates.

In the second aspect of the present invention, a carrier block that carries in and out a carrier that stores a plurality of substrates,
A processing unit for performing a coating process for forming a coating film including a photosensitive material film on a substrate carried one by one from a carrier block, and a developing process for developing the photosensitive material film exposed to a predetermined exposure pattern;
An interface block that delivers a substrate between the processing unit and an exposure apparatus that exposes the photosensitive material film in a predetermined exposure pattern;
A substrate processing system comprising a substrate transport mechanism for transporting a substrate between them, and capable of supporting an exposure apparatus that performs exposure at least twice on one substrate,
The processing unit includes a first coating processing unit that performs a first coating process corresponding to a first exposure, a first development processing unit that performs a first development process, and a second time corresponding to a second exposure. A second application processing unit for performing an application process and a second development processing unit for performing a second development process;
A first stacked body in which the first coating processing section is stacked on the second development processing section, and a second stacked body in which the second coating processing section is stacked on the first development processing section. And juxtaposed,
The interface block has a buffer unit for buffering a plurality of substrates,
Provided is a substrate processing system characterized in that the buffering of the substrate is performed by the buffer unit so that the throughput is half the throughput of the exposure apparatus.

  In the first and second aspects, the buffer section may include a loading buffer cassette that performs buffering when the substrate is loaded into the exposure apparatus. The buffer section may further include a carry-out buffer cassette for buffering the substrate carried out from the exposure apparatus. Further, it is preferable that the carry-in buffer cassette or the carry-in and carry-out buffer cassette has a first exposure and a second exposure.

  Further, the apparatus further includes a conveyance control mechanism that controls conveyance of the substrate by the substrate conveyance mechanism, and the conveyance control mechanism conveys the substrate from the carrier of the carrier block to the first coating processing unit of the processing unit, After completion of the coating process in the first coating processing unit, the substrate is transported to the exposure apparatus via the interface block, and after the first exposure in the exposure apparatus, the substrate is transferred to the exposure block via the interface block. The processing unit is transported to the first development processing unit, and after the development processing in the first development processing unit is completed, the substrate is transported to the second coating processing unit, and the coating processing in the second coating processing unit is completed. After that, the substrate is transported to the exposure apparatus through the interface block, and after the second exposure in the exposure apparatus, the substrate is moved forward through the interface block. The transport mechanism is controlled so as to be transported to the second development processing section of the processing section, and after the development processing in the second development processing section is completed, the substrate is stored in the carrier of the carrier block. Is preferred.

  The first coating processing unit and the second coating processing unit include a photosensitive material film coating processing layer in which units for coating a photosensitive material film are integrated, and the first development processing unit and the second development processing unit. The processing unit has a development processing layer in which units for performing the development processing are integrated, and the transport mechanism transports the substrate to each unit in the photosensitive material film coating processing layer and in the development processing layer, respectively. It is preferable to have a main transfer device to be performed and a delivery mechanism for connecting each processing layer in the vertical direction to each of the first laminate and the second laminate.

  In addition to the photosensitive material film coating processing layer, the first coating processing section includes a lower antireflection film coating processing layer in which units for forming an antireflection film are formed below the photosensitive material film, and the photosensitive material. It is possible to have at least one of an upper antireflection film coating treatment layer in which units for forming the antireflection film are integrated on the top of the film. In addition to the photosensitive material film coating processing layer, the second coating processing section includes a cleaning unit in which units for performing at least one of cleaning processing and surface processing of the coating film formed by coating processing in the first coating processing section are integrated. / A surface treatment layer can be provided. In this case, the cleaning / surface treatment layer may be cured as a surface treatment. In addition, the second coating processing unit includes an upper antireflection film coating processing layer in which units for forming an antireflection film are formed on the photosensitive material film, in addition to the photosensitive material film coating processing layer. can do.

According to the present invention, it is possible to correspond to an exposure apparatus that performs at least two exposures on a single substrate, and as a processing unit, a first coating processing unit that performs a first coating process corresponding to the first exposure. A first development processing unit that performs the first development processing, a second coating processing unit that performs the second coating processing corresponding to the second exposure, and a second development processing unit that performs the second development processing. Therefore, the patterning can be continuously performed a plurality of times without taking out the wafer W to the outside. For this reason, multiple times of patterning can be performed with extremely high efficiency.
In addition, the buffer block is provided in the interface block so that the throughput of the substrate processing system is half that of the exposure apparatus, so it is not necessary to follow the high throughput of the exposure apparatus, and the load on the substrate processing system can be reduced. Can do.

1 is a schematic perspective view showing a substrate processing system according to an embodiment of the present invention. FIG. 2 is a schematic horizontal sectional view showing a DEV layer portion of the substrate processing system of FIG. 1. The schematic side view of the substrate processing system of FIG. The perspective view which shows the layout of a DEV layer. The perspective view which shows the developing unit of a DEV layer. The longitudinal cross-sectional view which shows the heating unit and main arm of a DEV layer. Sectional drawing which shows the cure unit in a C / S layer. Sectional drawing which shows a conveyance layer. The perspective view which shows an interface arm typically. The figure which shows the control system which controls the substrate processing system which concerns on this embodiment. The figure for demonstrating the procedure of the double patterning of the type which repeats the patterning by photolithography twice. The figure which shows typically the processing operation in the substrate processing system and exposure apparatus of this embodiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. 1 is a schematic perspective view showing a substrate processing system according to an embodiment of the present invention, FIG. 2 is a schematic horizontal sectional view showing a DEV layer portion of the substrate processing system of FIG. 1, and FIG. 3 is a diagram of the substrate processing system of FIG. It is a schematic side view.

  The substrate processing system 100 is configured to perform a coating process of a coating film containing a photoresist on a wafer and a development process after exposure, and corresponds to double patterning in which patterning is performed twice. It is installed in a clean room in an atmosphere. The substrate processing system 100 forms a carrier block S1 for carrying in and out a carrier 20 in which a plurality of wafers W to be processed are stored, and a coating film including a photoresist film as a photosensitive material with respect to the wafer W. And a processing block S2 for performing a developing process for developing a photoresist film exposed to a predetermined exposure pattern, and an interface block S3, and used in a state where the exposure apparatus 200 is connected to the interface block S3. Is done.

  As shown in FIG. 1, a controller 10 that controls the entire substrate processing apparatus 100 is provided below the carrier block S1. Details of the control unit 10 will be described later. The exposure apparatus 200 is also provided with a control unit (not shown).

  1 to 3, the width direction of the substrate processing system 100 is the X direction, the arrangement direction of the carrier block S1, the processing block S2, and the interface block S3 orthogonal thereto is the Y direction, and the vertical direction is the Z direction.

  In the carrier block S 1, a mounting table 21 on which a plurality of carriers 20 can be mounted, an opening / closing part 22 provided on a front wall as viewed from the mounting table 21, and a wafer W from the carrier 20 via the opening / closing part 22. A transfer arm C for taking out is provided. The transfer arm C is configured to be movable forward and backward, freely movable up and down, rotatable around a vertical axis, and movable in the arrangement direction of the carriers 20.

  The processing block S2 is surrounded by the casing 24 and is connected to the carrier block S1. The processing block S2 includes first and second sub-blocks SB1 and SB2 formed by laminating a plurality of processing layers, and these are juxtaposed in the Y direction.

  In the first sub-block SB1, a second development processing unit 42 that performs the second development processing is disposed on the lower side, and a first coating processing unit 31 that performs the first coating processing is disposed thereon. . The second development processing unit 42 is configured with two development processing layers (DEV layers) B1 having the same structure stacked one above the other. The first application processing unit 31 is a lower antireflection film application processing layer (BCT layer) B2 for applying a lower antireflection film formed on the lower layer side of the resist film, and a resist solution application process. A structure in which a resist coating treatment layer (COT layer) B3 and an upper antireflection coating coating layer (TCT layer) B4 for performing coating treatment of an antireflection coating formed on the upper side of the resist film are laminated in order from the bottom. Have. The first sub-block SB1 has the first transport layer M1 between the second development processing unit 42 and the first coating processing unit 31, and has the second transport layer M2 at the lowest level.

  In the second sub-block SB2, the first development processing unit 41 that performs the first development processing is disposed on the lower side, and the second coating processing unit 32 that performs the second coating processing is disposed thereon. . The first development processing unit is configured with two development processing layers (DEV layers) B5 having the same structure stacked one above the other. The DEV layer B5 has the same structure as the DEV layer B1. When the second coating process unit 32 performs the second coating process on the upper antireflection film, which is the uppermost layer in the first coating process, the second coating process unit 32 performs the coating process with particles attached to the surface. Cleaning / surface treatment layer (C / S layer) B6 for applying surface treatment such as cleaning treatment and / or curing treatment of the upper antireflection film provided from the viewpoint of preventing leaching, etc., application of resist solution A resist coating layer (COT layer) B7 for performing processing and an upper antireflection coating layer (TCT layer) B8 for performing coating processing of an antireflection film formed on the upper layer side of the resist film are laminated in order from the bottom. Have a structure. The second sub-block SB2 includes a third transport layer M3 between the first development processing unit 41 and the second coating processing unit 32, and includes a fourth transport layer M4 at the lowest level. Note that the interlayers of the first and second sub-blocks SB1 and SB2 are partitioned by a partition plate (base body).

  In addition, the processing block S2 is a first transport shelf unit configured by stacking a plurality of delivery stages in the vertical direction along the processing layers B1 to B4 and the transport layers M1 and M2 on the carrier block S1 side portion. T1 and in the portion between the first sub-block SB1 and the second sub-block SB2, the processing layers B1 to B4 and the transport layers M1 and M2, and the processing layers B5 to B8 and the transport layer M3 , A second transfer shelf unit T2 configured by stacking a plurality of delivery stages in the vertical direction along M4, and the processing layers B5 to B8 and the transfer layer M3 on the interface block S3 side portion, There is a third transfer shelf unit T3 configured by stacking a plurality of delivery stages in the vertical direction along M4.

Next, the configuration of the processing layers B1 to B8 and the transport layers M1 to M4 will be described.
In the present embodiment, these processing layers B1 to B8 include many common portions, and each processing layer has a substantially similar layout. Therefore, the DEV layer B1 will be described as a representative example with reference to FIG. A transfer path R1 in which a main transfer arm (main arm) A1 for transferring the wafer W along the Y direction moves is formed at the center of the DEV layer B1.

  On one side of the transport path R1, a developing unit 3 including a plurality of coating units for performing a coating process of a developer as a liquid processing unit is provided along the transport path R1. On the other side of the transfer passage R1, four shelf units U1, U2, U3, U4 and an exhaust unit 5 in which heating / cooling heat treatment units are multi-staged are provided along the transfer passage R1. ing. Therefore, the developing unit 3 and the shelf units U1 to U4 are arranged to face each other with the conveyance path R1 interposed therebetween.

  As shown in FIGS. 5A and 5B, the developing unit 3 has a housing 30, in which three spin chucks 31 as wafer holding units are arranged, and each spin chuck 31 is The drive unit 32 is configured to be rotatable about the vertical axis and to be movable up and down. A cup 33 is provided around the spin chuck 31, and a drainage unit (not shown) including an exhaust pipe and a drain pipe is provided on the bottom surface of the cup 33. In the figure, reference numeral 34 denotes a chemical liquid supply nozzle. The chemical liquid supply nozzle 34 is provided so as to be movable up and down, and is configured to be movable in the Y direction along the guide 36 by a drive unit 35.

  In the developing unit 3, the wafer W is loaded into the housing 30 by the main arm A 1 through the transfer port 37 provided facing the transfer path R 1 and is transferred to the spin chuck 31. The conveyance port 37 can be opened and closed by a shutter 38. By closing the conveyance port 37 with the shutter 38, inflow of particles into the housing 30 can be prevented. Then, a developing solution is supplied from the supply nozzle 34 to the surface of the wafer W, a liquid film of the developing solution is formed on the surface of the wafer W, and then the developing solution on the surface of the wafer W is washed away by a cleaning solution from a cleaning solution supply mechanism (not shown). Thereafter, the development process is completed by rotating the wafer W and drying it.

  In the shelf units U1 to U4, thermal processing units for performing pre-processing and post-processing of processing performed in the developing unit 3 are stacked in two stages, and an exhaust unit is disposed below the shelf units U1 to U4. 5 is provided. In the thermal processing unit, for example, the heating unit 4 that heats the wafer W after exposure, or heats the wafer W after development processing to dry, and the processing in the heating unit 4 Thereafter, a cooling unit or the like for adjusting the wafer W to a predetermined temperature is included. Specifically, the shelf units U1, U2, and U3 in the DEV layer B1 have heating units 4 stacked in two stages, and the shelf unit U4 has stacked cooling units in two stages.

  As shown in FIG. 6, the heating unit 4 has a housing 40, and a base 41 is installed therein. A transfer port 42 for the wafer W is formed in a portion of the housing 40 facing the transfer path R1. In the housing 40, a cooling plate 43 for removing rough heat and a heating plate 44 are provided. The cooling plate 43 is configured to be movable between a cooling position shown in the drawing and a transfer position on the hot plate 44. In the figure, 45 is a plate for rectification. The wafer W is transferred to the cooling plate 43 by the lift pins 47, and the wafer W is transferred to the hot plate 44 by the lift pins 48 and the wafer W is transferred from the cooling plate 43 to the hot plate 44.

  Although a detailed description of the cooling unit constituting the shelf unit U4 is omitted, a casing having a transfer port 42 opened toward the transfer path R1 is provided in the same manner as the heating unit 4, and the inside of the casing is, for example, a water-cooling type cooling unit. An apparatus having a configuration including a plate is used.

  As shown in FIG. 6, the exhaust unit 5 includes a suction port 51 that opens in the housing 50 so as to face the transfer passage R1, and an exhaust pipe 54 that sucks and exhausts the inside of the exhaust chamber 53 inside the housing. The exhaust chamber 53 is evacuated to a negative pressure, thereby sucking the gas in the transfer passage R1 and removing particles.

  The main arm A1 transfers the wafer W between the processing units of the shelf units U1 to U4, the developing unit 3, the transfer stage of the first transfer shelf unit T1, and the transfer stage of the second transfer shelf unit T2. Is configured to do. As shown in FIG. 6, the main arm A <b> 1 includes, for example, two arm bodies 61 and 62 for supporting the peripheral area on the back surface side of the wafer W. The arm bodies 61 and 62 are arranged on the transfer base 63. It is configured to move forward and backward independently of each other. The transport base 63 is provided on the elevating base 64 so as to be rotatable around the vertical axis. The elevating base 64 can be moved up and down along the elevating guide rail 67. Guide rails 65 are horizontally arranged on the front surfaces of the four exhaust units 5 of the shelf units U1 to U4, and the main arm A1 can move in the horizontal direction along the guide rails 65 via the lifting guide rails 67. It has become. The elevating guide rail 65 is provided with a hole 66 at a position corresponding to the suction port 51, and the conveyance path R <b> 1 is exhausted through the hole 66. The lower end portion of the elevating guide rail 67 reaches the inside of the exhaust chamber 5 across the lower end of the guide rail 65 and is locked to a drive belt 55 for moving the elevating guide rail 67 along the guide rail 65.

Next, other processing layers will be briefly described.
As described above, the DEV layer B5 is configured in exactly the same way as the DEV layer B1, and the wafer W is transferred by the main arm A5 having the same configuration as the main arm A1. Further, the BCT layer B2, the COT layers B3 and B7, and the TCT layers B4 and B8 are coated with a chemical solution for antireflection film or a chemical solution for forming a resist film (resist solution) instead of the developing unit 3 of the DEV layer B1. The difference is that a coating unit is used. The basic structure of these coating units is almost the same as that of the developing unit 3, but unlike the developing unit 3, a coating chemical is dropped on the center of the wafer while rotating the spin chuck and spread by centrifugal force to form a coating film. Form. Further, these coating processing units B2 to B4, B7, and B8 are partially different from the DEV layer B1 in the units constituting the shelf units U1 to U4. That is, a heating unit and a cooling unit similar to the shelf units U1 to U4 of the DEV layer B1 are included, and a peripheral exposure unit that exposes the peripheral portion of the wafer W is provided on any one of the processing layers. The shelf units U1 to U4 of the layers B3 and B7 include units that perform a hydrophobic treatment on the wafer W. The processing layers B2, B3, B4, B7, and B8 are provided with main arms A2, A3, A4, A7, and A8 having the same configuration as the main arm A1, and the wafer W is transferred by these main arms. It has become.

  The cleaning / surface treatment layer (C / S layer) B6 is different in that a cleaning unit is used instead of the development unit 3 of the DEV layer B1. The basic structure of the cleaning unit is the same as that of the developing unit 3 except that a cup is arranged around the spin chuck. Unlike the developing unit 3, pure water or cleaning chemicals are supplied to the wafer while rotating the spin chuck. The surface of the wafer W is washed by being dropped at the center of the wafer and spread by centrifugal force. The cleaning / surface treatment layer (C / S layer) B6 is partially different from the DEV layer B1 in the units constituting the shelf units U1 to U4. That is, in addition to the heating unit and the cooling unit similar to the shelf units U1 to U4 of the DEV layer B1, a cure unit is provided. As shown in FIG. 7, the cure unit 8 has a configuration in which a wafer support 82 is provided in a housing 81 and an ultraviolet lamp 83 is disposed above the wafer W supported on the wafer support 82. The uppermost layer is cured by irradiating the wafer W with ultraviolet rays. In the C / S layer B6, the wafer W is transferred by the main arm A6 having the same configuration as the main arm A1.

  As described above, the first transfer layer M1 is provided between the DEV layer B1 and the BCT layer B2 on the upper side of the first sub-block SB1, and the wafer W is placed on the first transfer shelf adjacent to the carrier block S1. The wafer W is transferred directly from the unit T1 to the intermediate second transfer shelf unit T2. As shown in FIG. 8, the first transport layer M1 includes a transport region P1 partitioned by a partition plate 7a from the transport path R1 of the DEV layer B1, and a shuttle arm 7 as a direct transport means. The shuttle arm 7 includes an arm body 71 for supporting the peripheral area on the back surface side of the wafer W, and the arm body 71 is configured to be movable back and forth on the transfer base 72. The transport base 72 is provided on the moving base 73 so as to be rotatable about the vertical axis. On the back side of the shuttle arm 7, a housing 70 is provided horizontally along the transfer area P1. Inside the housing 70, the exhaust chamber 70 a includes a drive unit (not shown) for moving the shuttle arm 7. A guide rail 74 for guiding the shuttle arm 7 in the horizontal direction is provided on the front surface of the housing 70 so as to extend in the horizontal direction along the front surface of the housing 70.

  The housing 70 is provided with a suction port 75 opened to face the transport region P1, and the guide rail 74 is provided with holes 74a spaced in the lateral direction so as to overlap the suction port 75. . A plurality of exhaust ports 77 are opened at intervals in the lateral direction on the side opposite to the transfer region P1 of the exhaust chamber 70a. The exhaust port 77 has exhaust pipes 78 for sucking and exhausting the inside of the exhaust chamber 70a. It is connected. The exhaust chamber 70a is made negative pressure through the exhaust pipe 78, so that the gas in the transport region P1 flows into the exhaust chamber 70a. In the transfer area P1, for example, a gas introduction part 79 is provided in the lateral direction so as to cover the entire transfer area P1. The gas introduction part 79 is provided with gas introduction ports (not shown) at regular intervals, so that clean gas is supplied to the transport region P1. In this way, particles in the transport region P1 are removed by exhausting the transport region P1 through the exhaust chamber 70a while supplying clean gas to the transport region P1. At this time, by adjusting the supply and exhaust of the clean gas, the pressure in the transfer area P1 is controlled to be slightly more positive than the pressure in the clean room, so that the inflow of particles from the outside to the transfer area P1 can be prevented. Can be suppressed.

  The second transport layer M2 is provided at the lowermost stage of the first sub-block SB1, and transports the wafer W by going straight from the first transport shelf unit T2 to the first transport shelf unit T1. Is configured in exactly the same way as the first transport layer M1. The third transport layer M3 is provided between the DEV layer B5 and the C / S layer B6 on the upper side of the second sub-block SB2, and is adjacent to the interface block S3 from the intermediate second transport shelf unit T2. The configuration is the same as that of the first transfer layer M1, except that the wafer W is transferred to the third transfer shelf unit T3. The fourth transport layer M4 is provided at the lowermost stage of the second sub-block SB2, and transports wafers from the third transport shelf unit T3 to the second transport shelf unit T2. It is configured in exactly the same way as the transport layer M1.

  A region adjacent to the carrier block S1 in the transport path R1 of the processing layers B1 to B4 of the first sub-block SB1 and the transport region P1 of the transport layers M1 and M2 is a first wafer transfer region R2, and A first transport shelf unit T1 is provided in the delivery region R2. In the transfer area R2, a transfer arm D1, which is a lifting and lowering transfer means for transferring the wafer W to the transfer shelf unit T1, is provided.

  The first transfer shelf unit T1 has a transfer stage TRSB at a position corresponding to the second transfer layer M2, and has a transfer stage TRS1 at a position corresponding to each DEV layer B1, and is attached to the first transfer layer M1. It has a delivery stage TRSA at a corresponding position, has two delivery stages TRS2 at a position corresponding to the BCT layer B2, has two delivery stages TRS3 at a position corresponding to the COT layer B3, and corresponds to the TCT layer B4 Two delivery stages TRS4 are provided at the positions to be operated.

  The transfer arm C is accessible from the transfer stage TRSB corresponding to the lowermost second transfer layer M2 of the first transfer shelf unit T1 to the transfer stage TRS2 corresponding to the BCT layer B2. The delivery arm D1 is accessible from the lowermost delivery stage TRSB to the uppermost delivery stage TRS4 corresponding to the TCT layer B4.

  The transfer arm D1 moves from the lowermost second transport layer M2 to the uppermost TCT layer B4 so that the wafer W can be transferred to the transfer stages TRSB to TRS4 provided in the respective layers. In addition, it is configured to be able to advance and retreat and to move up and down.

  The shuttle arm 7 is accessible to the transfer stages TRSA and TRSB corresponding to the first and second transport layers M1 and M2, and the DEV layer B1, BCT layer B2, COT layer B3, and TCT layer B4 are respectively accessible. The main arms A1 to A4 of each processing layer can access the corresponding delivery stages TRS1 to TRS4, respectively.

  The transport path R1 and transport layers M1 and M2 of the processing layers B1 to B4 of the first sub-block SB1, the transport path R1 and transport layer M3 of the processing layers B5 to B8 of the second sub-block SB2, A region between the transfer region P1 of M4 is a second wafer transfer region R3, and the first transfer shelf unit T2 is provided in the transfer region R3. In the transfer area R3, a transfer arm D2, which is a lifting and lowering transfer means for transferring the wafer W to the transfer shelf unit T2, is provided.

  The transport shelf unit T2 has a transfer stage TRSD at a position corresponding to the fourth transport layer M4, has a transfer stage TRS5 at a position corresponding to each DEV layer B5, and a position corresponding to the third transport layer M3. Has a delivery stage TRSC, has two delivery stages TRS6 at a position corresponding to the C / S layer B6, has two delivery stages TRS7 at a position corresponding to the COT layer B7, and corresponds to the TCT layer B8. Two delivery stages TRS8 are provided at the position.

  The second delivery arm D2 is accessible from the lowermost delivery stage TRSD to the uppermost delivery stage TRS8 corresponding to the TCT layer B8. Therefore, the second transfer arm D2 moves from the lowermost fourth transfer layer M4 to the uppermost TCT layer B8 and transfers the wafer W to the transfer stages TRSC to TRS8 provided in the respective layers. It is configured to be able to advance and retreat and ascend and descend so that it can be performed.

  The shuttle arm 7 is accessible to the transfer stages TRSC and TRSD corresponding to the third and fourth transport layers M3 and M4, and the DEV layer B5, C / S layer B6, COT layer B7, TCT layer B8. The main arms A5 to A8 of each processing layer are accessible to the transfer stages TRS5 to TRS8 respectively corresponding to.

  The area adjacent to the interface block S3 in the transfer path R1 of the DEV layer B5 and the transfer area P1 of the third and fourth transfer layers M3 and M4 is a third wafer transfer area R4, as shown in FIG. In addition, the third transfer shelf unit T3 is provided in the region R4.

  The third transfer shelf unit T3 has a transfer stage TRSF at a position corresponding to the fourth transfer layer M4, has a transfer stage TRS9 at a position corresponding to each DEV layer B1, and is provided on the third transfer layer M3. A delivery stage TRSE is provided at a corresponding position.

  The shuttle arm 7 can access the transfer stages TRSE and TRSF corresponding to the third and fourth transport layers M3 and M4, and the main arm A5 can access the transfer stage TRS7 corresponding to the DEV layer B5. It is possible.

  The delivery stages TRS1 to TRS9 and TRSA to TRSF all have the same structure. For example, the delivery stages TRS1 to TRS9 and TRSA to TRSF have a rectangular parallelepiped enclosure, and a stage on which the wafer W is placed is provided. A free pin is provided and configured. The stage also has a mechanism for adjusting the temperature of the wafer W to a predetermined temperature. Each arm enters the case through a transfer port provided on a side surface facing each arm of the case, and each arm can hold and transfer the back surface of the wafer W floating from the stage via the pin. In addition, the wafer W can be placed on the plate by delivering the wafer W onto the pins protruding from the arms and lowering the pins.

  In this embodiment, two delivery stages are provided in each of the processing layers B2 to B4 and B6 to B8, and one is provided in each of the DEV layers B1 and B5 and the transport layers M1 to M4. The number of delivery stages may be determined as appropriate according to the scheduled transfer sequence.

The interface block S3 includes a buffer unit 9 that can temporarily wait for a plurality of wafers W when the wafer W is loaded into the exposure apparatus 200 and when the wafer W is unloaded from the exposure apparatus 200. The buffer unit 9 includes a first loading buffer cassette (Bu _IN 1) 91 that stores a wafer W to be loaded into the exposure apparatus 200 during the first exposure, and the wafer W after the first exposure is completed from the exposure apparatus 200. second input buffer cassette containing the wafers W to be carried into the exposure apparatus 200 during the first unloading buffer cassette _(Bu OUT 1) 92,2 th exposure that houses the paid out wafer W _(Bu iN 2) 93 It has a second carry-out buffer cassette (Bu _OUT 2) 94 for storing the wafer W that has been discharged from the exposure apparatus 200 after the second exposure has been completed. Bu _IN 2) 93, first carry buffer cassette _(Bu IN 1) 91, the first carry-out buffer cassette _(Bu OUT 1) 92, a second carry-out buffer cassette (B _OUT 2) 94 is arranged (see FIG. 3).

  Further, on the processing block S 2 side of the buffer unit 9, the wafer W is unloaded from the loading interface arm E 1 and the unloading buffer cassette 92 or 94 for loading the coated wafer W into the loading buffer cassette 91 or 93. An unloading interface arm E2 is provided. These interface arms E1 and E2 can also access the transfer stages TRS9, TRSE, and TRSF of the transfer shelf unit T3. When the wafer W is transferred into the transfer buffer cassette 91 or 93, the third transfer is performed. When the wafer W is transferred to the transfer stage TRSE by the shuttle arm 7 of the layer M3 and then transferred by the transfer interface arm E1 and returned from the transfer buffer cassette 92 or 94, the transfer interface arm E2 returns the wafer W. Transfer to the transfer stage TRS9 or TRSF.

  Also, a first exposure interface arm E3 for transporting a first exposure wafer W between the buffer unit 9 and the exposure apparatus 200, and a second exposure wafer between the buffer unit 9 and the exposure apparatus 200. A second-exposure interface arm E4 is provided.

  These interface arms E1 to E4 have the same structure. For example, as shown in FIG. 9, one arm 111 for supporting the central region on the back surface side of the wafer W can be moved forward and backward along the base 112. Is provided. The base 112 is attached to a lift 113 by a rotation mechanism 114 so as to be rotatable about a vertical axis, and is provided so as to be movable up and down along a lift rail 115. As a result, the arm 111 is configured to be able to advance and retreat, move up and down, and rotate about the vertical axis. The delivery arms D1 and D2 are configured in the same manner as the interface arms E1 to E4 except that they do not rotate around the vertical axis.

Next, the control unit 10 will be described. FIG. 10 is a block diagram showing the main part of the control unit 10.
The control unit 10 includes a wafer transfer system such as a main arm A1 to A8, a shuttle arm 7, a transfer arm C, a transfer arm D1 and D2, and an interface arm E1 to E4 of the substrate processing system 100, a carrier block S1, a processing block S2, A controller 11 having a microprocessor (MPU) for controlling each component such as each unit of the interface block S3, and a keyboard for an operator to input commands to manage each component of the substrate processing system 100; The user interface 12 includes a display that visualizes and displays the operating status of each component of the substrate processing system 100, and the storage unit 13 that stores information such as recipes necessary for processing.

  The storage unit 13 is a program that gives a control program for realizing various processes executed by the substrate processing system 100 under the control of the controller 11, a processing procedure of the substrate processing system 100, a wafer W transfer schedule, and the like, that is, a recipe Etc. are stored. The recipe of the transfer schedule specifies the transfer path of the wafer W (order of modules such as a delivery stage and a unit on which the wafer W is placed) according to the processing type, and is a recipe that the operator executes from a plurality of recipes Is supposed to be selected. Control programs such as recipes are stored in a storage medium in the storage unit 13. The storage medium may be a fixed one such as a hard disk or a portable one such as a CDROM, DVD, or flash memory. Moreover, you may make it transmit a recipe suitably from another apparatus via a dedicated line, for example.

Next, the processing operation of the wafer W by the substrate processing system 100 configured as described above will be described.
First, double patterning for forming a fine pattern on a predetermined film of the wafer W, which is performed in the substrate processing system 100 of this embodiment, will be described with reference to FIG. Here, for the sake of simplicity, only the substrate, the film to be etched, and the resist film are drawn, but in the actual pattern, an antireflection film, a base film, a hard mask layer, an etching stop layer, and the like are appropriately arranged. .

  First, as shown in FIG. 11A, a first resist coating process is performed on an etching target film 302 formed on a semiconductor substrate (wafer) 301 to form a resist film 303 (first coating). .

  Next, as shown in FIG. 11B, a first resist pattern having a pattern portion 304 is formed by performing a first exposure and a first development process (first patterning).

  Next, as shown in FIG. 11 (c), the pattern portion 304 and the resist in the subsequent second application are not subjected to leaching or the like so that the pattern portion 304 is adversely affected. Surface treatment (cure, coating, etc.) is performed on 304 to form a surface treated portion 305 (pattern surface treatment).

  Next, as shown in FIG. 11D, a resist film 306 is formed by performing a second resist coating process on the first resist pattern (second coating).

  Next, as shown in FIG. 11E, a second exposure and a second development process are performed to form a pattern portion 307 between adjacent ones of the first pattern portion 304, A fine pattern is obtained (second patterning).

  Thereafter, the wafer that has been subjected to the second patterning is etched by an etching apparatus provided separately to form a fine etching pattern as shown in FIG. 11F (etching).

In the substrate processing system 100, patterning twice as illustrated in FIG. 11 is performed by the following processing operation.
FIG. 12 is a diagram schematically showing processing operations in the substrate processing system 100 and the exposure apparatus 200 of the present embodiment. In FIG. 12, a black arrow indicates a process for the first patterning, and a white arrow indicates a process for the second patterning. In the present embodiment, as shown in FIG. 12, the carrier 20 containing the plurality of wafers W of the first lot is set in the carrier block S1, the wafers W are taken out one by one from the carrier, and the first coating process is performed. The first resist film or the like is formed in the section 31 and then sequentially loaded into the first loading buffer cassette (Bu _IN 1) 91 of the buffer section 9 of the interface block S3. When the wafers W for one lot are accumulated in the first carry-in buffer cassette (Bu _IN 1) 91, the wafers W are sequentially transferred to the stage 201 of the exposure apparatus 200, and the first exposure process is started.

Subsequently, the carrier 20 loaded with the second lot of wafers W is set in the carrier block S1, the wafers W are taken out one by one, and the first resist film is formed in the same manner, and the first carry-in buffer cassette (Bu _IN 1) When the wafers W are sequentially loaded into 91 and the wafers W for one lot are accumulated in the first carry-in buffer cassette (Bu _IN 1) 91, the wafers W are sequentially transferred to the stage 201 of the exposure apparatus 200 and similarly. The first exposure process is started.

On the other hand, the wafers W of the first lot that have been transferred to the stage 201 after the completion of the first exposure are sequentially loaded into the first carry-out buffer cassette (Bu _OUT 1) 92. Then, the wafers W are sequentially taken out from the first carry-out buffer cassette (Bu _OUT 1) 92, and the first development processing unit 41 performs the first development processing. Thereafter, the second coating processing unit 32 subsequently forms a second resist film or the like on the wafer W after the first development processing, and then the second loading buffer cassette (in the buffer unit 9 of the interface block S3). Bu _IN 2) sequentially carry into 93.

At this time, in the exposure apparatus 200, when the first exposure of the wafers W of the second lot is completed, the reticle is replaced with one corresponding to the second exposure. After the work is completed, when the wafers W of the first lot are accumulated in the second carry-in buffer cassette (Bu _IN 2) 93, the wafers are sequentially transferred to the stage 201 of the exposure apparatus 200 and the second exposure process is started.

  Processing of the wafers W of the third lot and the fourth lot is started at an appropriate time during the processing.

After the second exposure is completed, the wafers W of the first lot unloaded onto the stage 201 are sequentially loaded into the second unloading buffer cassette (Bu _OUT 2) 94. Then, the wafers W are sequentially taken out from the second carry-out buffer cassette (Bu _OUT 2) 94, and the second development processing unit 42 performs the second development process. The wafer W that has undergone the second development process is transferred to the carrier 20. Returned. Similarly, the second lot of wafers W are also subjected to the first development processing in the first development processing section 41 and the second resist film formation processing in the second coating processing section 32 after the first exposure, After the second exposure, the second development process is performed and the carrier 20 is returned.

  The above processing is continuously performed on a large number of lots of wafers W. As described above, in the substrate processing system 100 of the present embodiment, the first coating / developing processing and the second coating / developing processing are performed. Since these are performed in separate processing units, the patterning can be performed twice without taking out the wafer W to the outside. For this reason, double patterning can be performed with extremely high efficiency. Further, the substrate processing system 100 performs the first application / development process and the second application / development process in separate processing units for the two exposure operations in the exposure apparatus 200 as described above. Accordingly, in the steady state, the overall wafer processing throughput in the substrate processing system 100 may be half of the throughput in the exposure apparatus 200, and it is not necessary to follow the increase in throughput of the exposure apparatus. Can reduce the load. That is, in the double patterning process, the throughput of the exposure apparatus is required to be 200 to 300 sheets / hour, and when a conventional coating / development system is used, the current 100 to 100 in accordance with the throughput of the exposure apparatus. 150 sheets / hour must be 200 to 300 sheets / hour, and the burden on the apparatus becomes extremely large. By using the substrate processing system 100 of this embodiment, the throughput is reduced to the current 100 to 150 sheets / hour. The apparatus burden can be reduced.

  However, when devices having different throughputs are connected in this way and wafers are transferred between them, wafer buffering is indispensable at the connecting part. Therefore, in the present embodiment, the buffer unit 9 is provided to buffer the wafer W. Specifically, when the wafer W is transferred from the substrate processing system 100 with a low throughput to the exposure apparatus 200 with a high throughput, if there is no buffer, the throughput is locally doubled at that portion, and exposure is performed with a normal transfer arm. The supply of the wafer W to the apparatus 200 cannot catch up, and since the reticle needs to be replaced in the first exposure and the second exposure in the exposure apparatus 200, the operation for each lot is indispensable. Therefore, in the case of this embodiment, the carry-in buffer is essential. On the other hand, when the wafer W is unloaded from the exposure apparatus 200, it can be handled as long as the performance of the transfer arm corresponds to the throughput of the exposure apparatus 200. Therefore, the unloading buffer is not essential. Considering the difference, an unloading buffer is actually necessary.

  In the present embodiment, the first coating processing unit 31, the second coating processing unit 32, the first development processing unit 41, and the second development processing unit 42 are provided in a stacked manner, so that application of resist or the like is performed twice. Although it is a system that performs processing and development processing separately, its footprint can be reduced. In particular, a stacked body in which the first coating processing unit 31 is provided on the second development processing unit 42 and a stacked body in which the second coating processing unit 32 is provided on the first development processing unit 41 are juxtaposed. As a result, efficient wafer transfer is possible.

  Furthermore, since the sections for performing each process are combined as a single processing layer and stacked, the footprint of the system can be reduced from this point of view.

  Furthermore, since each processing layer is arranged so that it can be efficiently transported in one stroke by performing application processing and development processing of resist or the like twice, the processing efficiency can be further improved.

Next, a more specific processing operation will be described.
A carrier 20 storing a plurality of wafers from the outside is carried into the carrier block S1, and one wafer W is taken out from the carrier 20 by the transfer arm C and carried into the processing block S. First, the first coating process is performed in the first coating processing unit 31 of the first sub-block SB1. Specifically, first, the wafer W is transferred from the transfer arm C to the transfer stage TRS2 of the first transfer shelf unit T1, and the wafer W on the transfer stage TRS2 is received by the main arm A2 of the BCT layer B2, and the wafer W Is transferred in the order of cooling unit → antireflection film forming unit (unit corresponding to developing unit 3 in FIG. 5) → heating unit, and a predetermined antireflection film (BARC) is formed by sequentially performing predetermined processing. Thereafter, the wafer W is delivered and returned to the stage TRS2.

  Subsequently, the wafer W of the transfer stage TRS2 is transferred to the transfer stage TRS3 of the COT layer B3 by the transfer arm D1, and the wafer W on the transfer stage TRS3 is received by the main arm A3 of the COT layer B3, and the wafer W is cooled by the cooling unit. → Resist coating unit (unit corresponding to developing unit 3 in FIG. 5) → Heating unit is transported in this order, and predetermined processing is sequentially performed to form a resist film on the lower antireflection film. Then, the wafer W is transferred to the peripheral exposure unit to perform peripheral edge exposure processing, and then returned to the delivery stage TRS3.

Next, the wafer W of the transfer stage TRS3 is transferred to the transfer stage TRS4 of the TCT layer B4 by the transfer arm D1, and the main arm A4 of the TCT layer B4 receives the wafer W on the transfer stage TRS4, and the wafer W is cooled by the cooling unit. → Second antireflection film forming unit (unit corresponding to developing unit 3 in FIG. 5) → Heating unit is transported in this order to form an upper antireflection film (TARC) on the upper layer of the resist film. Thereafter, the wafer W is delivered and returned to the stage TRS4.
Thus, the first coating process is completed.

Thereafter, the wafer W of the transfer stage TRS4 is transferred to the transfer stage TRSA by the transfer arm D1. Next, the shuttle arm 7 of the first transfer layer M1 receives the wafer W on the transfer stage TRSA, changes the direction to the second transfer shelf unit T2, moves to the second transfer shelf unit T2, and moves to the wafer. W is transferred to the delivery stage TRSC of the second transfer shelf unit T2. The wafer W on the stage TRSC is received by the shuttle arm 7 of the third transfer layer M3 belonging to the second sub-block SB2, and turned to the third transfer shelf unit T3 side, so that the third transfer shelf unit The wafer W moves to the T3 side, and the wafer W is transferred to the transfer stage TRSE of the third transfer shelf unit T3. The wafer W on the transfer stage TRSE is loaded into the first loading buffer cassette (Bu _IN 1) 91 of the buffer unit 9 by the loading interface arm E1 of the interface block S3.

When one lot of wafers W is collected in the first carry-in buffer cassette (Bu _IN 1) 91, the wafers W therein are transferred to the exposure apparatus 200 by the first exposure interface arm E3. Then, the first exposure is performed on the wafer W transferred to the exposure apparatus 200.

The wafer W for which the first exposure has been completed is carried out to the interface block S3. Specifically, it is carried into the first carry-out buffer cassette (Bu _OUT 1) 92 by the interface arm E3 for the first exposure.

Thereafter, the wafer W of the first unloading buffer cassette (Bu _OUT 1) 92 is loaded into the processing block S2, and the first developing process is performed by the first developing unit 41 of the second sub-block SB2. Specifically, the wafer W of the first carry-out buffer cassette (Bu _OUT 1) 92 is taken out by the carry-out interface arm E2, and the delivery stage TRS9 corresponding to any DEV layer B5 of the third carrying shelf unit T3. Transport to. Then, the main arm A5 of the DEV layer B5 receives the wafer W on the transfer stage TRS9, and the heating unit 4 → cooling unit → developing unit 3 → heating unit 4 included in the shelf units U1 to U4 in the DEV layer B5. → The cooling unit is transported in the order, and predetermined processes such as post-exposure baking, development, and post-baking are performed. The wafer W thus developed is transferred to the transfer stage TRS5 of the second transfer shelf unit T2. Thus, the first development process is completed.

  Thereafter, the second coating process is continuously performed by the second coating processing unit 32 of the second sub-block SB2. Specifically, first, the wafer W on the transfer stage TRS5 is transferred to the transfer stage TRS6 by the transfer arm D2, and the wafer W on the transfer stage TRS6 is received by the main arm A6 of the C / S layer B6 to clean the wafer. For example, cleaning and surface treatment of a pattern formed in the first coating / exposure / development process by transporting in the order of unit (unit corresponding to the development unit 3 in FIG. 5) → heating unit → cooling unit → cure unit 8 Cure treatment by ultraviolet irradiation. This prevents particles from adhering or causing leaching during the second coating process. Thereafter, the wafer W is delivered and returned to the stage TRS6.

  Subsequently, the wafer W of the transfer stage TRS6 is transferred to the transfer stage TRS7 of the COT layer B7 by the transfer arm D2, and the wafer W on the transfer stage TRS7 is received by the main arm A7 of the COT layer B7, and the wafer W is cooled by the cooling unit. → Resist coating unit (unit corresponding to developing unit 3 in FIG. 5) → Transfer in order of heating unit and sequentially carry out predetermined processing, thereby resist on the upper layer of the upper antireflection film in the first coating process A film is formed. Then, the wafer W is transferred to the peripheral exposure unit to perform peripheral edge exposure processing, and then returned to the delivery stage TRS7.

Next, the wafer W of the transfer stage TRS7 is transferred to the transfer stage TRS8 of the TCT layer B8 by the transfer arm D2, and the wafer W on the transfer stage TRS8 is received by the main arm A8 of the TCT layer B8. → Second antireflection film forming unit (unit corresponding to developing unit 3 in FIG. 5) → Heating unit is transported in this order to form an upper antireflection film (TARC) on the upper layer of the resist film. Thereafter, the wafer W is delivered and returned to the stage TRS8.
Thus, the second coating process is completed.

Thereafter, the wafer W of the transfer stage TRS8 is transferred to the transfer stage TRSC of the second transfer shelf unit T2 by the transfer arm D2. The wafer W on the stage TRSC is received by the shuttle arm 7 of the third transfer layer M3 belonging to the second sub-block SB2, and turned to the third transfer shelf unit T3 side, so that the third transfer shelf unit The wafer W moves to the T3 side, and the wafer W is transferred to the transfer stage TRSE of the third transfer shelf unit T3. The wafer W on the transfer stage TRSE is loaded into the second loading buffer cassette (Bu _IN 2) 93 of the buffer unit 9 by the loading interface arm E1 of the interface block S3.

When one lot of wafers W accumulates in the second carry-in buffer cassette (Bu _IN 2) 93, the wafers W therein are transferred to the exposure apparatus 200 by the second exposure interface arm E4. Then, the wafer W transferred to the exposure apparatus 200 is subjected to the second exposure.

The wafer W for which the second exposure has been completed is carried out to the interface block S3. Specifically, it is carried into the second carry-out buffer cassette (Bu _OUT 2) 94 by the second exposure interface arm E4.

Thereafter, the wafer W of the second carry-out buffer cassette (Bu _OUT 2) 94 is carried into the processing block S2, and the second development processing is performed by the second development processing unit 42 of the first sub-block SB1. Specifically, the wafer W of the second unloading buffer cassette (Bu _OUT 2) 94 is taken out by the unloading interface arm E2, and is transferred to the transfer unit TRSF corresponding to the fourth transfer layer M4 of the third transfer shelf unit T3. Transport. Next, the shuttle arm 7 of the fourth transfer layer M4 receives the wafer W on the transfer stage TRSF, changes the direction to the second transfer shelf unit T2, moves to the second transfer shelf unit T2, and moves the wafer. W is transferred to the transfer stage TRS5 corresponding to any DEV layer B1 belonging to the second development processing section 42 of the first sub-block SB1 of the second transfer shelf unit T2. Then, the main arm A1 of the DEV layer B1 receives the wafer W on the delivery stage TRS5, and the heating unit 4 → cooling unit → developing unit 3 → heating unit 4 included in the shelf units U1 to U4 in the DEV layer B1. → The cooling unit is transported in the order, and predetermined processes such as post-exposure baking, development, and post-baking are performed. The wafer W thus developed is transferred to the delivery stage TRS1 of the first transfer shelf unit T1. Thus, the second development process is completed. In such a transport sequence, it is not necessary to use the second transport layer M2, but it can be used as a bypass means in the event of some trouble in the system, or transport on another route when processing is complicated. It can be used as a means.

  The wafer W on the transfer stage TRS1 for which the second development process has been completed is stored in the carrier 20 by the transfer arm C. Such processing is continuously performed on the wafers W of a plurality of lots.

  In such a transfer sequence, a predetermined process is performed while the wafer is transferred to each unit by the main arm in each processing layer, and the wafer is transferred to the other stacked processing layers by a vertical transfer mechanism. Since it can be bypassed using the shuttle arm of a conveyance layer, very efficient conveyance can be performed.

  The above is a typical embodiment of the present invention, but the present invention is not limited to the above embodiment and can be variously modified. For example, in the above embodiment, the substrate processing system has a structure in which each processing layer is stacked. However, if the first coating process, the first developing process, the second coating process, and the second developing process can be performed, It is not restricted to such a structure.

  In the above embodiment, as the first coating process, the lower antireflection film, the resist film, and the upper antireflection film are formed. However, only one of the lower antireflection film and the upper antireflection film may be used. It is good also as a resist film only without providing. Further, as the second coating process, a curing process as a cleaning process and a surface process is performed, and then a resist film and an upper antireflection film are formed. However, either the cleaning process or the surface process may be performed. Further, although the curing treatment by ultraviolet irradiation is performed as the surface treatment, another energy ray or heat may be used, or another surface treatment such as coating may be performed instead of the curing treatment.

  Furthermore, although the case where a semiconductor wafer is used as the object to be processed has been described in the above embodiment, the present invention is naturally applicable to a processing system such as a substrate other than the semiconductor wafer, for example, an LCD glass substrate.

3; developing unit 4; heating unit 7; shuttle arm 9; buffer unit 10; control unit 31; first coating processing unit 32; second coating processing unit 41; first development processing unit 42; 93; loading buffer 92, 94; unloading buffer 100; substrate processing system 200; exposure apparatus S2; processing block S3; interface blocks A1 to A8; main arms E1 to E4; interface arm C; DEV layer B2; BCT layers B3 and B7; COT layers B4 and B8; TCT layer B6; C / S layers M1 to M4; transport layers U1 to U4; shelf units T1 to T3; ~ TRS9, TRSA ~ TRSF; Delivery stage

Claims (13)

A carrier block for carrying in and out a carrier for storing a plurality of substrates;
A processing unit for performing a coating process for forming a coating film including a photosensitive material film on a substrate carried one by one from a carrier block, and a developing process for developing the photosensitive material film exposed to a predetermined exposure pattern;
An interface block that delivers a substrate between the processing unit and an exposure apparatus that exposes the photosensitive material film in a predetermined exposure pattern;
A substrate processing system comprising a substrate transport mechanism for transporting a substrate between them, and capable of supporting an exposure apparatus that performs exposure at least twice on one substrate,
The processing unit includes a first coating processing unit that performs a first coating process corresponding to a first exposure, a first development processing unit that performs a first development process, and a second time corresponding to a second exposure. A second application processing unit for performing an application process and a second development processing unit for performing a second development process;
A first stacked body in which the first coating processing section is stacked on the second development processing section, and a second stacked body in which the second coating processing section is stacked on the first development processing section. Are juxtaposed with each other.   The substrate processing system according to claim 1, wherein the interface block includes a buffer unit that buffers a plurality of substrates. A carrier block for carrying in and out a carrier for storing a plurality of substrates;
A processing unit for performing a coating process for forming a coating film including a photosensitive material film on a substrate carried one by one from a carrier block, and a developing process for developing the photosensitive material film exposed to a predetermined exposure pattern;
An interface block that delivers a substrate between the processing unit and an exposure apparatus that exposes the photosensitive material film in a predetermined exposure pattern;
A substrate processing system comprising a substrate transport mechanism for transporting a substrate between them, and capable of supporting an exposure apparatus that performs exposure at least twice on one substrate,
The processing unit includes a first coating processing unit that performs a first coating process corresponding to a first exposure, a first development processing unit that performs a first development process, and a second time corresponding to a second exposure. A second application processing unit for performing an application process and a second development processing unit for performing a second development process;
A first stacked body in which the first coating processing section is stacked on the second development processing section, and a second stacked body in which the second coating processing section is stacked on the first development processing section. And juxtaposed,
The interface block has a buffer unit for buffering a plurality of substrates,
A substrate processing system characterized in that the buffering of the substrate is performed by the buffer unit so that the throughput is half the throughput of the exposure apparatus.   4. The substrate processing system according to claim 2, wherein the buffer unit includes a loading buffer cassette that performs buffering when the substrate is loaded into the exposure apparatus.   5. The substrate processing system according to claim 4, wherein the buffer unit further includes an unloading buffer cassette for buffering the substrate unloaded from the exposure apparatus.   6. The substrate processing system according to claim 4, wherein the carry-in buffer cassette or the carry-in and carry-out buffer cassette has a first exposure and a second exposure. A transport control mechanism for controlling transport of the substrate by the substrate transport mechanism;
The transport control mechanism transports the substrate from the carrier of the carrier block to the first coating processing unit of the processing unit, and after the coating processing in the first coating processing unit is completed, the substrate is transferred via the interface block. After the first exposure in the exposure apparatus, the substrate is transported to the first development processing section of the processing section via the interface block, and the first development processing section After completion of the development processing, the substrate is transferred to the second coating processing section, and after the coating processing in the second coating processing section is completed, the substrate is transferred to the exposure apparatus via the interface block, and the exposure apparatus After the second exposure, the substrate is transferred to the second development processing section of the processing section through the interface block, and after the development processing in the second development processing section is completed, The substrate processing system according to any one of claims 6 claims 3 to the substrate to accommodate the carrier in the carrier block, and controls the transport mechanism.   2. The first coating processing unit, the first development processing unit, the second coating processing unit, and the second development processing unit are configured to be stacked one above the other. The substrate processing system according to claim 7. The first coating processing unit and the second coating processing unit have a photosensitive material film coating processing layer in which units for coating a photosensitive material film are integrated,
The first development processing unit and the second development processing unit have a development processing layer in which units for performing development processing are integrated,
The transport mechanism includes a main transport device that transports a substrate to each unit in the photosensitive material film coating processing layer and the development processing layer, and each of the first stacked body and the second stacked body. The substrate processing system according to claim 1, further comprising a transfer mechanism that connects the processing layers in a vertical direction.   In addition to the photosensitive material film coating processing layer, the first coating processing unit includes a lower antireflection film coating processing layer in which units for forming an antireflection film are formed below the photosensitive material film, and the photosensitive material film. 10. The substrate processing system according to claim 9, further comprising at least one of an upper antireflection film coating treatment layer on which units for forming an antireflection film are integrated.   The second coating processing unit includes a cleaning / surface in which units for performing at least one of cleaning processing and surface processing of the coating film formed by coating processing in the first coating processing unit are integrated in addition to the photosensitive material film coating processing layer. The substrate processing system according to claim 8, further comprising a processing layer.   The substrate processing system according to claim 11, wherein the cleaning / surface treatment layer performs a curing treatment as a surface treatment.   The second coating processing unit includes an upper antireflection film coating treatment layer in which units for forming an antireflection film are formed on the photosensitive material film in addition to the photosensitive material film coating treatment layer. The substrate processing system according to any one of claims 9 to 12.

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