JP4895420B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a capacitor electrode and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, a DRAM (Dynamic Random Access Memory) is known as one of semiconductor devices. FIG. 9 is a schematic cross-sectional view showing a conventional semiconductor device. A conventional semiconductor device will be described with reference to FIG.
[0003]
Referring to FIG. 9, the semiconductor device is a DRAM, and includes a field effect transistor and a capacitor formed on semiconductor substrate 101. The capacitor stores a charge as a memory signal. The field effect transistor also functions as a switching element that controls charge accumulation in the capacitor. Conductive regions 102 a to 102 e are formed on the main surface of the semiconductor substrate 101 at intervals. The conductive regions 102a to 102d serve as the source and drain regions of the field effect transistor. Gate insulating films 103a to 103c are formed over the semiconductor substrate 101 over channel regions located between the conductive regions 102a to 102d. Gate electrodes 104a to 104c are formed on the gate insulating films 103a to 103c. Sidewall insulating films 105a to 105f are formed on the side walls of the gate electrodes 104a to 104c. Covering insulating films 106a to 106c are formed on the gate electrodes 104a to 104c. A field effect transistor is constituted by the gate electrode 104a, the gate insulating film 103a, and the conductive regions 102a and 102b as the source and drain regions. Another field effect transistor is constituted by the gate electrode 104b, the gate insulating film 103b, and the conductive regions 102b and 102c as the source and drain regions. Another field effect transistor is composed of the gate electrode 104c, the gate insulating film 103c, and the conductive regions 102c and 102d as the source and drain regions.
[0004]
A first interlayer insulating film 107 is formed on the covering insulating films 106 a to 106 c, the sidewall insulating films 105 a to 105 f, and the main surface of the semiconductor substrate 101. In the first interlayer insulating film 107, contact holes 108a and 108b are formed in regions located on the conductive regions 102b and 102c. The contact holes 108a and 108b are filled with conductor films 109a and 109b such as doped polysilicon films. A second interlayer insulating film 110 is formed on the first interlayer insulating film 107. A contact hole 111a is formed in the second interlayer insulating film 110 in a region located on the conductor film 109b. In the region located on the conductive region 102e on the main surface of the semiconductor substrate 101, a contact hole 111b is formed by removing a part of the first and second interlayer insulating films 107 and 110. The contact holes 111a and 111b are filled with conductor films 115a and 115b such as tungsten films, respectively. First wiring layers 112a and 112b are formed on the conductor films 115a and 115b.
[0005]
A third interlayer insulating film 113 is formed on the first wiring layers 112 a and 112 b and the second interlayer insulating film 110. In a region located on the conductor film 109a, a contact hole 114 is formed by removing a part of the second and third interlayer insulating films 110 and 113. The contact hole 114 is filled with a conductor film 116.
[0006]
A fourth interlayer insulating film 117 is formed on the third interlayer insulating film 113. In a region located on the first wiring layer 112b, a contact hole 150 is formed by removing a part of the third and fourth interlayer insulating films 113 and 117. The contact hole 150 is filled with a conductor film 151.
[0007]
A fifth interlayer insulating film 118 is formed on the fourth interlayer insulating film 117. In a region located on the conductor film 116, an opening 119 is formed by removing a part of the fourth and fifth interlayer insulating films 117 and 118. A capacitor lower electrode 120 connected to the conductor film 116 is formed inside the opening 119. A dielectric film 121 is formed so as to extend from above the capacitor lower electrode 120 to the upper surface of the fifth interlayer insulating film 118. A capacitor upper electrode 122 is formed on the dielectric film 121 so as to fill the inside of the opening 119 and to extend to the upper surface of the fifth interlayer insulating film 118. A capacitor is composed of the capacitor lower electrode 120, the dielectric film 121, and the capacitor upper electrode 122.
[0008]
A sixth interlayer insulating film 123 is formed on the capacitor upper electrode 122 and the fifth interlayer insulating film 118. A contact hole 152 a is formed in the sixth interlayer insulating film 123 in a region located on the capacitor upper electrode 122. Further, in a region located on the conductor film 150, a contact hole 152b is formed by removing a part of the fifth and sixth interlayer insulating films 118 and 123. The contact holes 152a and 152b are filled with conductor films 153a and 153b such as tungsten films. The conductor film 153 a is connected to the capacitor upper electrode 122. The conductor film 153b is connected to the conductor film 151. On the conductor films 152a and 152b, second wiring layers 154a and 154b made of aluminum or the like are formed. The second wiring layer 154a is used to fix the potential of the capacitor upper electrode 122. In a semiconductor device such as a DRAM, as shown in FIG. 9, a plurality of memory cells including capacitors are arranged on a substrate 101 in a matrix. An interlayer insulating film (not shown) is formed on the second wiring layers 154a and 154b.
[0009]
[Problems to be solved by the invention]
In semiconductor devices typified by DRAM, there is an increasing demand for miniaturization and higher integration. Therefore, the size of the DRAM memory cell as shown in FIG. 9 is becoming smaller. However, a certain amount of charge needs to be stored in a capacitor that stores charge in the memory cell. Therefore, in order to secure the capacity of the capacitor while reducing the size of the memory cell, a capacitor structure having a shape extending in the height direction, such as a cylindrical capacitor or a thick film capacitor as illustrated, is employed. . On the other hand, the first wiring 112b and the second wiring layer 154b connected to the conductive region 102e for the purpose of supplying a signal to the conductive region 102e located below the capacitor upper electrode 122 or fixing the potential. Need to be connected through contact holes 152b and 150. At this time, the contact hole 152a located above the capacitor upper electrode 122 and the contact hole 152b located below the second wiring layer 154b have different depths due to the structure of the capacitor. Therefore, when the contact holes 152a and 152b are formed by one etching process, it is necessary to continue etching until the contact hole 152b reaches a predetermined depth. At this time, the capacitor upper electrode 122 is excessively etched at the bottom of the contact hole 152a. As a result, there arises a problem that the capacitor upper electrode 122 is damaged or the contact hole 152a penetrates the capacitor upper electrode 122. For this reason, conventionally, an etching process for forming the contact hole 152a and an etching process for forming the contact hole 152b have been performed separately. As a result, the number of manufacturing steps of the semiconductor device increases, which increases the manufacturing cost of the semiconductor device.
[0010]
Further, the second wiring layers 154a and 154b may be caused by mask overlay error or the like in the photoengraving process for forming the second wiring layers 154a and 154b or the photoengraving process for forming the contact holes 152a and 152b. And the contact holes 152a and 152b may be misaligned. In this case, the second wiring layer 154a and the capacitor upper electrode 122 are not connected, and a defect has occurred in the semiconductor device.
[0011]
Further, as the semiconductor device is miniaturized, it is necessary to reduce the wiring width and wiring height (wiring cross-sectional area) of the second wiring layers 154a and 154b and the interval between the wirings. However, when the cross-sectional area of the wiring becomes smaller in this way, the wiring resistance of the second wiring layers 154a and 154b increases. Such an increase in wiring resistance causes wiring delay. As a result, necessary characteristics such as operation speed cannot be realized in the semiconductor device, and defective products may occur.
[0012]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can prevent the occurrence of defects and reduce the manufacturing cost. Is to provide.
[0013]
[Means for Solving the Problems]
  A semiconductor device according to one aspect of the present invention includes a conductive region, a first insulating film, a capacitor electrode, a second insulating film, and first and second wiring layers. The conductive region is formed on the semiconductor substrate. The first insulating film is formed on the conductive region. The capacitor electrode is formed on the first insulating film. The second insulating film is formed on the capacitor electrode, has a first groove exposing a part of the capacitor electrode, and has an upper surface. The first wiring layer is filled in the first groove, has an upper surface, and is connected to the capacitor electrode. Contact holes reaching the conductive regions are formed in the first and second insulating films.Formed,In the second insulating film,Second connected to the contact holeGrooveIs formed. The second wiring layer is filled in the second groove and the contact hole. The upper surface of the first wiring layer, the upper surface of the second wiring layer, and the upper surface of the second insulating film are located on substantially the same plane.The first and second wiring layers contain copper.
[0014]
In this way, since the wiring connected to the capacitor electrode can have a so-called damascene wiring structure, the manufacturing process of the semiconductor device can be simplified as compared with the prior art.
[0015]
Conventionally, a capacitor electrode and a wiring layer made of aluminum or the like are connected via a conductor film such as a tungsten plug formed in the contact hole. For this reason, the bonding interface between the wiring layer and the conductor film becomes a bonding interface of different materials, and the interfacial resistance is increased, so that the electromigration resistance is lowered. However, in the present invention, since the wiring layer has a damascene wiring structure and a part of the capacitor electrode is exposed in the groove, the lower surface of the wiring layer is directly connected to the capacitor electrode. For this reason, it is not necessary to form a tungsten plug. For this reason, it can prevent that the electromigration tolerance of a wiring layer falls.
[0016]
Also, by forming a groove in the insulating film and filling the inside of the groove with a conductor film, the formation of the wiring layer and the connection between the wiring layer and the capacitor electrode can be realized simultaneously. There is no problem of misalignment with the wiring layer to be formed on the contact hole. Therefore, it is possible to prevent the occurrence of defects due to such positional deviation.
[0017]
Further, since the upper surface of the wiring layer and the upper surface of the insulating film are located on substantially the same plane, there is no step due to the wiring layer on the upper surface of the wiring layer. Therefore, when another insulating film or the like is formed on the insulating film, no step is formed on the upper surface of the other insulating film due to the step on the upper surface of the wiring layer. Therefore, when an upper wiring layer or the like is formed on another insulating film, it is possible to prevent a failure such as disconnection of the upper wiring layer due to the step.
[0018]
In addition, for the purpose of supplying a signal to a conductive region located below the capacitor electrode, another conductive layer formed in the same layer as the wiring layer may be connected to the conductive region. At this time, in a region that does not overlap the capacitor electrode in a plan view, another contact hole that reaches the conductive region to the insulating film, a conductor film that fills the other contact hole, and a conductor film It is necessary to form another connected wiring layer. On the other hand, conventionally, a contact hole is formed for connection between the capacitor electrode and the wiring layer. And since this contact hole and the said other contact hole differed in depth, it had to be formed by a separate etching process, respectively. This is because the semiconductor device is miniaturized so that the capacitor extends in the height direction, and the difference in depth between the contact hole and the other contact hole becomes larger. However, in the present invention, no contact hole is formed on the capacitor electrode, and the lower surface of the wiring layer is directly in contact with the capacitor electrode. That is, even if the semiconductor device is miniaturized, it is not necessary to form a plurality of contact holes having different depths as in the conventional case, and thus the manufacturing process of the semiconductor device can be further simplified.
[0020]
  AlsoFormed on the insulating filmSecondThe wiring layer is inside the contact hole andSecondIt can be formed by a so-called dual damascene process in which the inside of the groove is filled with a conductor film. And, as explained in the manufacturing process described later, the aboveSecondThe wiring layer is locatedSecondGroove andFirstThe wiring layer is locatedFirstIf the groove is formed in the same etching process, as described aboveSecondWhen the wiring layer is formed, an increase in the number of manufacturing steps can be minimized. For this reason, it can suppress that the manufacturing cost of a semiconductor device increases.
[0021]
  In the semiconductor device according to the above aspect 1,SecondInsulating filmFirstGroove andSecondThe groove may be formed to extend substantially in parallel.Yes.
[0022]
  in this case,FirstExtends parallel to the wiring layer, and the lower surface contacts the capacitor electrodeSecondA wiring layer can be formed. Therefore, the capacitor electrode andFirstSince the contact area with the wiring layer can be increased, the capacitor electrode andFirstElectrical connection with the wiring layer can be performed more reliably.
[0027]
In this case, copper has a lower electrical resistance value than aluminum which has been conventionally used as a material for the wiring layer. Therefore, if copper is used as the material of the wiring layer, the wiring resistance can be reduced as compared with the conventional case. For this reason, occurrence of wiring delay can be prevented.
[0028]
In the semiconductor device according to the first aspect, it is preferable that a barrier metal layer is formed on the inner wall of the groove.
[0029]
In this case, the barrier metal layer can prevent the material such as copper constituting the wiring layer from diffusing into the insulating film or the capacitor electrode.
[0030]
  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device on a semiconductor substrate.A conductive region is formed. A first insulating film is formed over the conductive region. On the first insulating filmA capacitor electrode is formed. On top of the capacitor electrode has an upper surfaceSecondAn insulating film is formed.Contact holes reaching the conductive regions are formed in the first and second insulating films. SecondIn the insulating film, so that part of the capacitor electrode is exposedFirstForming a grooveAt the same time, a second groove is formed in the second insulating film in the region located on the contact hole..Firstgroove, Contact hole and second grooveFilling the interior of andSecondA conductor film is formed so as to extend onto the upper surface of the insulating film.SecondWhile removing the conductor film located on the upper surface of the insulating film,SecondInsulating filmFirstgrooveAnd the second grooveBy removing a part of the conductor film located above,FirstgrooveAnd the second grooveConsisting of a conductor film filling the interior ofSecondHaving an upper surface that is substantially coplanar with the upper surface of the insulating filmFirst and secondForm a wiring layerThe
[0031]
Here, in the conventional manufacturing process of the wiring layer connected to the capacitor electrode, a step of forming a contact hole in the insulating film, a step of forming a conductor film inside the contact hole, and a position on the upper surface of the insulating film A step of removing the excess conductor film, a step of forming a conductor film to be a wiring layer on the contact hole, and a wiring layer by partially removing the conductor film by etching using the resist film as a mask The process to do was carried out. That is, in the conventional manufacturing process of a semiconductor device, the etching process and the film forming process are performed twice. However, as in the present invention, the wiring layer electrically connected to the capacitor electrode has a so-called damascene wiring structure, thereby forming a groove in the insulating film, and a conductor film that becomes a wiring layer inside the groove. The wiring layer is formed with a smaller number of processes than in the past, such as a process of removing the conductive film located on the upper surface of the insulating film using a chemical mechanical polishing (CMP) method. it can. As a result, the manufacturing process of the semiconductor device can be simplified. Further, in this way, the semiconductor device according to the present invention can be easily manufactured.
[0033]
  AlsoLocated above the contact holeSecondThe process of forming the trench and reaching the capacitor electrodeFirstThe step of forming the groove can be performed simultaneously. AndFirstFormed inside the grooveFirstSince the wiring layer is directly connected to the capacitor electrode,FirstIt is not necessary to form a contact hole for filling a tungsten plug or the like separately from the wiring layer. For this reason, the manufacturing process of a semiconductor device can be simplified compared with the past.
[0034]
  Also,SecondIt is formed in the insulating film by one etching processFirstGroove andSecondThe groove depth ofSecondIf the distance from the upper surface of the insulating film to the upper surface of the capacitor electrode is set approximately equal,FirstIt is possible to prevent the capacitor electrode from being excessively etched at the bottom of the groove. For this reason, it is possible to prevent the capacitor electrode from being damaged by excessive etching.
[0035]
  In the method of manufacturing a semiconductor device in the other aspect,SecondThe step of forming the grooveFirstTo extend almost parallel to the grooveSecondMay include forming groovesYes.
[0036]
  in this case,SecondExtending parallel to the wiring layer of the capacitor, the lower surface contacts the upper surface of the capacitor electrodeFirstA wiring layer can be formed. Therefore, the capacitor electrode andFirstThe contact area with the wiring layer can be increased. As a result, the capacitor electrode andFirstElectrical connection with the wiring layer can be reliably performed.
[0039]
  In the method for manufacturing a semiconductor device in the other aspect described above, the conductor film preferably contains copper.Yes.
[0040]
In this case, copper having a lower electrical resistance value than that of conventionally used aluminum can be used as the wiring layer material.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0042]
(Embodiment 1)
FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a schematic diagram showing a cross section taken along line II-II in FIG. The semiconductor device will be described with reference to FIGS.
[0043]
1 and 2, the semiconductor device is a DRAM, and includes a field effect transistor and a capacitor formed on semiconductor substrate 1. The capacitor stores a charge as a memory signal. The field effect transistor also functions as a switching element that controls charge accumulation in the capacitor. Conductive regions 2a to 2e are formed on the main surface of the semiconductor substrate 1 at intervals. Conductive regions 2a to 2d serve as source and drain regions of the field effect transistor. Gate insulating films 3 a to 3 c are formed on the semiconductor substrate 1 on the channel region located between the conductive regions 2 a to 2 d. Gate electrodes 4a to 4c are formed on the gate insulating films 3a to 3c. Sidewall insulating films 5a-5f are formed on the side walls of gate electrodes 4a-4c. Over the gate electrodes 4a to 4c, coating insulating films 6a to 6c made of a silicon nitride film are formed. A field effect transistor is constituted by the gate electrode 4a, the gate insulating film 3a, and the conductive regions 2a and 2b as the source and drain regions. Another field effect transistor is constituted by the gate electrode 4b, the gate insulating film 3b, and the conductive regions 2b and 2c as the source and drain regions. Another field effect transistor is composed of the gate electrode 4c, the gate insulating film 3c, and the conductive regions 2c and 2d as the source and drain regions.
[0044]
A first interlayer insulating film 7 is formed on the covering insulating films 6 a to 6 c, the sidewall insulating films 5 a to 5 f and the main surface of the semiconductor substrate 1. In the first interlayer insulating film 7, contact holes 8a and 8b are formed in regions located on the conductive regions 2b and 2c. The contact holes 8a and 8b are filled with conductor films 9a and 9b such as a doped polysilicon film. A second interlayer insulating film 10 is formed on the first interlayer insulating film 7. A contact hole 11a is formed in the second interlayer insulating film 10 in a region located on the conductor film 9b. Further, in a region located on the conductive region 2e on the main surface of the semiconductor substrate 1, contact holes 11b are formed by removing a part of the first and second interlayer insulating films 7 and 10 by etching. The contact holes 11a and 11b are filled with conductor films 15a and 15b such as a tungsten film and a doped polysilicon film, respectively. A first wiring layer 12a made of doped polysilicon is formed on the conductor film 15a. Further, a first wiring layer 12b as a conductive region made of doped polysilicon is formed on the conductor film 15b.
[0045]
A third interlayer insulating film 13 is formed on the first wiring layers 12 a and 12 b and the second interlayer insulating film 10. In a region located on the conductor film 9a, a contact hole 14 is formed by removing a part of the second and third interlayer insulating films 10 and 13. The contact hole 14 is filled with a conductor film 16.
[0046]
A fourth interlayer insulating film 17 is formed on the third interlayer insulating film 13. A fifth interlayer insulating film 18 is formed on the fourth interlayer insulating film 17. In a region located on the conductor film 16, an opening 19 is formed by removing a part of the fourth and fifth interlayer insulating films 17 and 18. A capacitor lower electrode 20 connected to the conductor film 16 is formed inside the opening 19. Dielectric film 21 is formed so as to extend from above capacitor lower electrode 20 to the upper surface of fifth interlayer insulating film 18. On the dielectric film 21, a capacitor upper electrode 22 is formed as a capacitor electrode so as to fill the inside of the opening 19 and extend to the upper surface of the fifth interlayer insulating film 18. A capacitor is composed of the capacitor lower electrode 20, the dielectric film 21 and the capacitor electrode 22.
[0047]
A sixth interlayer insulating film 23 as an insulating film is formed on the capacitor upper electrode 22 and the fifth interlayer insulating film 18. In a region located on the capacitor upper electrode 22, a damascene wiring groove 25 a as a groove is formed in the sixth interlayer insulating film 23 so as to expose a part of the upper surface of the capacitor upper electrode 22. In the region located on the first wiring layer 12b, contact holes 24 are formed in the third to sixth interlayer insulating films 13, 17, 18 and 23. In a region located on the contact hole 24, a damascene wiring groove 25b as another groove is formed in the sixth interlayer insulating film 23. The damascene wiring grooves 25a and 25b are formed so as to extend substantially parallel to each other. A part of the upper surface of the capacitor upper electrode 22 is exposed at the bottom surface of the damascene wiring groove 25a. Therefore, the contact area between the capacitor upper electrode 22 and the barrier metal layer 34a formed inside the damascene wiring groove 25a can be increased. Therefore, electrical connection between the capacitor upper electrode 22 and the conductor film 26a as the damascene wiring layer can be reliably performed through the barrier metal layer 34a.
[0048]
Barrier metal layers 34 a and 34 b are formed inside the damascene wiring trenches 25 a and 25 b and the contact hole 24. A conductor film 26a as a wiring layer is formed on the barrier metal layer 34a so as to fill the inside of the damascene wiring groove 25a. Further, a conductor film 26b as another wiring layer is formed on the barrier metal layer 34b so as to fill the inside of the damascene wiring trench 25b and the contact hole 24. The conductor films 26a and 26b are so-called damascene wiring. The upper surfaces of the conductor films 26a and 26b and the upper surface of the sixth interlayer insulating film 23 are located on substantially the same plane. As the conductor films 26a and 26b, for example, copper can be used.
[0049]
Thus, when copper is used as the material of the conductor films 26a and 26b as the wiring layers, copper has a lower electrical resistance value than aluminum, which is a conventional wiring material, so that the wiring resistance can be reduced. For this reason, occurrence of wiring delay can be prevented. Further, since the barrier metal layers 34a and 34b are formed, it is possible to prevent the material such as copper constituting the conductor films 26a and 26b from diffusing into the sixth interlayer insulating film 23 and the like.
[0050]
The conductor film 26 a is used to fix the potential of the capacitor upper electrode 22. In the semiconductor device according to the present invention, a plurality of memory cells each including a capacitor and a field effect transistor as shown in FIG.
[0051]
Here, in the manufacturing process of the wiring layer 154a connected to the conventional capacitor upper electrode 122 as shown in FIG. 9, the process of forming the contact hole 152a in the sixth interlayer insulating film 123, and the inside of the contact hole 152a A step of forming a conductor film, an extra conductor film located on the upper surface of the sixth interlayer insulating film 123 is removed, and a conductor film 153a such as a tungsten plug filled in the contact hole 152a is formed. Forming the wiring layer 154a over the contact hole 152a, and forming the wiring layer 154a by partially removing the conductive film by etching using the resist film as a mask. It was carried out. That is, in the conventional manufacturing process of a semiconductor device, the etching process and the film forming process are performed twice.
[0052]
However, referring to FIG. 1, the wiring layer made of the conductor film 26a electrically connected to the capacitor upper electrode 22 as in the present invention has a so-called damascene wiring structure, so that it will be shown by a manufacturing method described later. In addition, a step of forming a damascene wiring groove 25a in the sixth interlayer insulating film 23, a conductive layer serving as a wiring layer so as to extend from the inside of the damascene wiring groove 25a to the upper surface of the sixth interlayer insulating film 23. A step of forming a body film, and then a step of forming the conductor film 26a by removing the conductor film located on the upper surface of the sixth interlayer insulating film 23 by using a CMP method or the like. The wiring layer can be formed with As a result, the manufacturing process of the semiconductor device can be simplified.
[0053]
In the semiconductor device according to the present invention shown in FIG. 1, the damascene wiring including the conductor film 26a is used as the wiring layer connected to the capacitor upper electrode 22, and the lower surface of the damascene wiring is connected to the capacitor via the barrier metal layer 34a. It is in a state of being connected to the upper electrode 22. Therefore, it is not necessary to form the contact hole 152a (see FIG. 9) and the conductor film 153a (see FIG. 9) such as a tungsten plug as in the prior art. For this reason, the heterogeneous interface formed between the wiring layer 154a and the conductor film 153a such as a tungsten plug in the conventional semiconductor device does not exist in the semiconductor device according to the present invention. Therefore, it is possible to prevent the electromigration resistance of the wiring layer connected to the capacitor upper electrode 22 from being lowered.
[0054]
Further, in the semiconductor device shown in FIG. 1, a damascene wiring groove 25a is formed in the sixth interlayer insulating film 23, and a conductor film is filled in the damascene wiring groove 25a to form a conductor as a wiring layer. The formation of the film 26a and the connection between the conductor film 26a and the capacitor upper electrode 22 are realized at the same time. For this reason, the problem of positional displacement between the contact hole 152a (see FIG. 9) and the wiring layer 154a (see FIG. 9) due to an error in the photolithography process is not caused as in the prior art. Therefore, it is possible to prevent the occurrence of defects due to such positional deviation.
[0055]
Further, since the upper surface of the conductor film 26a and the upper surface of the sixth interlayer insulating film 23 are located on substantially the same plane, the upper surface of the sixth interlayer insulating film 23 is caused by the conductor film 26a. No step is formed. For this reason, when another insulating film or the like is formed on the sixth interlayer insulating film 23, the flatness of the upper surface of the other insulating film is caused by a step in the upper surface of the sixth interlayer insulating film 23. Deterioration can be prevented. Accordingly, when an upper wiring layer or the like is formed on another insulating film, it is possible to prevent a failure such as disconnection of the upper wiring layer due to deterioration of flatness on the upper surface of the other insulating film.
[0056]
Next, the manufacturing process of the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 6 are schematic cross-sectional views for explaining the first to fourth steps of the manufacturing process of the semiconductor device shown in FIGS.
[0057]
First, insulating films to be gate insulating films 3a to 3c (see FIG. 3) are formed on the main surface of a semiconductor substrate 1 (see FIG. 3) such as a silicon wafer. A conductor film to be the gate electrodes 4a to 4c (see FIG. 3) is formed on the insulating film. A resist film having a gate electrode pattern is formed on the conductor film. Using this resist film as a mask, the conductor film and the insulating film are partially removed to form gate electrodes 4a to 4c and gate insulating films 3a to 3c. Next, conductive regions 2a to 2e (see FIG. 3) are formed by implanting conductive impurities into the main surface of the semiconductor substrate 1 using the gate electrodes 4a to 4c as a mask. Conductive region 2e may be formed in advance by injecting conductive impurities into the main surface of semiconductor substrate 1 using a resist film or the like as a mask.
[0058]
Sidewall insulating films 5a-5f and covering insulating films 6a-6c are formed on the sidewalls and upper surfaces of gate electrodes 4a-4c. A first interlayer insulating film 7 (see FIG. 3) is formed on the covering insulating films 6a to 6c and the sidewall insulating films 5a to 5f by using a CVD method (Chemical Vapor Deposition method) or the like. A resist film (not shown) having a hole pattern is formed on the first interlayer insulating film 7. Using this resist film as a mask, a part of the first interlayer insulating film 7 is partially removed by etching. Thereafter, the resist film is removed. In this way, contact holes 8a and 8b (see FIG. 3) are formed. A conductor film is formed so as to fill the inside of the contact holes 8 a and 8 b and to extend onto the upper surface of the first interlayer insulating film 7. Conductor films 9a and 9b (see FIG. 3) are formed by removing the conductor film located on the upper surface of the first interlayer insulating film 7 by etching or the like.
[0059]
A second interlayer insulating film 10 (see FIG. 3) is deposited on the first interlayer insulating film 7 using a CVD method or the like. A resist film having a hole pattern is formed on the second interlayer insulating film 10. Contact holes 11a and 11b (see FIG. 3) are formed by partially removing the second interlayer insulating film using the resist film as a mask. At the bottom of the contact hole 11a, the upper surface of the conductor film 9a is exposed. In addition, the conductive region 2e is exposed at the bottom of the contact hole 11b. Thereafter, the resist film is removed. A conductor film filling the inside of the contact holes 11a and 11b and extending to the upper surface of the second interlayer insulating film 10 is formed by sputtering or the like. As a material of the conductor film, for example, tungsten can be used. The portion of the conductor film located on the upper surface of the second interlayer insulating film 10 is removed. In this way, conductor films 15a and 15b are formed.
[0060]
Thereafter, a conductor film is formed on the second interlayer insulating film 10. A resist film having a wiring pattern is formed on the conductor film. First wiring layers 12a and 12b (see FIG. 3) are formed by partially removing the conductor film by etching using the resist film as a mask. Thereafter, the resist film is removed. A third interlayer insulating film 13 is formed on the first wiring layers 12a and 12b using a CVD method or the like. A resist film having a hole pattern is formed on the third interlayer insulating film 13. Using the resist film as a mask, the second and third interlayer insulating films 10 and 13 are partially removed by etching or the like to form contact holes 14 (see FIG. 3). Thereafter, the resist film is removed. Next, a conductor film filling the inside of the contact hole 14 and extending to the upper surface of the third interlayer insulating film 13 is formed. The conductor film 16 is formed by removing the conductor film located on the upper surface of the third interlayer insulating film 13.
[0061]
A fourth interlayer insulating film 17 is formed on the third interlayer insulating film 13 using a CVD method or the like. A fifth interlayer insulating film 18 is formed on the fourth interlayer insulating film 17 by CVD or the like. A resist film (not shown) having a hole pattern is formed on the fifth interlayer insulating film 18. The opening 19 is formed by partially removing the fourth and fifth interlayer insulating films 17 and 18 by etching using the resist film as a mask. The conductor film 16 is exposed at the bottom of the opening 19. Thereafter, the resist film is removed.
[0062]
A conductor film to be a capacitor lower electrode is formed so as to extend from the inside of the opening 19 to the upper surface of the fifth interlayer insulating film 18. Next, a resist film (not shown) is formed on the conductor film so as to fill the inside of the opening 19 in a region located inside the opening 19. Thereafter, the conductor film located on the upper surface of the fifth interlayer insulating film 18 is removed by dry etching. Note that the CMP method may be used in the step of removing the conductor film. Thereafter, the resist film is removed. In this way, the capacitor lower electrode 20 made of a conductive film is formed inside the opening 19.
[0063]
Next, a dielectric film is formed so as to extend from above the capacitor lower electrode 20 inside the opening 19 to the upper surface of the fifth interlayer insulating film 18. A conductor film to be a capacitor upper electrode is formed on the dielectric film. A resist film having a mask pattern is formed on the conductor film. Using the resist film as a mask, the conductor film and the dielectric film are partially removed to form the dielectric film 21 and the capacitor upper electrode 22 constituting the capacitor. In addition, as a material of the capacitor lower electrode 20 and the capacitor upper electrode 22, polysilicon, amorphous silicon, or the like can be used. When a high dielectric film such as BST or PZT is used as the material of the dielectric film 21, a metal such as platinum or ruthenium or a high melting point metal such as titanium is used as the material of the capacitor lower electrode 20 and the capacitor upper electrode 22. Alternatively, titanium nitride, or a film formed of a plurality of these layers may be used.
[0064]
Next, a sixth interlayer insulating film 23 is formed on the capacitor upper electrode 22. A resist film 27 having a hole pattern is formed on the sixth interlayer insulating film 23. In this way, a structure as shown in FIG. 3 is obtained.
[0065]
Next, as shown in FIG. 4, using the resist film 27 as a mask, the third to sixth interlayer insulating films 13, 17, 18, and 23 are partially removed by etching to form contact holes 24. Next, as shown in FIG. Thereafter, the resist film 27 is removed.
[0066]
Next, as shown in FIG. 5, a resist film 28 having a pattern for damascene wiring trenches is formed on the sixth interlayer insulating film 23.
[0067]
Next, as shown in FIG. 6, by using the resist film 28 as a mask, the sixth interlayer insulating film 23 is partially removed by etching to form damascene wiring grooves 25a and 25b. At the bottom of the damascene wiring trench 25a, the upper surface of the capacitor upper electrode 22 is exposed. Thereafter, the resist film 28 is removed.
[0068]
Thus, by exposing the capacitor upper electrode 22 by etching to form the damascene wiring grooves 25a and 25b, the capacitor upper electrode 22 is electrically connected without forming a separate contact hole as in the prior art. A damascene wiring layer made of the conductive film 26a can be formed. Therefore, the manufacturing process of the semiconductor device can be simplified as compared with the prior art.
[0069]
Conventionally, the contact hole 152a (see FIG. 9) located on the capacitor upper electrode 22 and the other contact hole 152b located in another region and having different depths are formed by separate etching processes. In the present invention, a wiring layer composed of the conductor film 26b located inside the contact hole 24 and the damascene wiring trench 25b is formed by a so-called dual damascene process, and further for the wiring layer connected to the capacitor upper electrode. By forming the damascene wiring trench 25a and the damascene wiring trench 25b connected to the contact hole 24 by the same etching process, the manufacturing process of the semiconductor device can be simplified. For this reason, the manufacturing cost of the semiconductor device can be reduced.
[0070]
Further, by making the depth of the damascene wiring trenches 25a and 25b substantially equal to the depth from the upper surface of the sixth interlayer insulating film 23 to the upper surface of the capacitor upper electrode 22, the capacitor upper electrode 22 is excessively etched. Can be prevented. Further, since the upper surface of the capacitor upper electrode 22 is exposed at the bottom of the damascene wiring groove 25a, the barrier metal layer 34a and the capacitor upper electrode 22 can be reliably brought into contact as will be described later. Therefore, the capacitor upper electrode 22 and the entire lower surface of the conductor film 26 as the damascene wiring layer can be connected via the barrier metal layer 34a via the barrier metal layer 34a. As a result, electrical connection between the capacitor upper electrode 22 and the conductor film 26 as the damascene wiring layer can be reliably performed.
[0071]
Following the process shown in FIG. 6, a barrier metal layer is formed inside the damascene wiring grooves 25 a and 25 b and the contact hole 24. A conductor film made of copper or the like is formed on the barrier metal layer so as to fill the interiors of the damascene wiring trenches 25a and 25b and the contact hole 24 and to extend to the upper surface of the sixth interlayer insulating film 23. To do. Then, the barrier metal layer and the conductor film located on the upper surface of the sixth interlayer insulating film 23 are removed using a CMP method or the like. In this way, barrier metal layers 34a and 34b and conductor films 26a and 26b to be damascene wirings are formed.
[0072]
In this way, the semiconductor device shown in FIGS. 1 and 2 can be obtained.
(Embodiment 2)
FIG. 7 is a schematic cross-sectional view showing a second embodiment of the semiconductor device according to the present invention. FIG. 8 is a schematic diagram showing a cross section taken along line VIII-VIII in FIG. A second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.
[0073]
Referring to FIGS. 7 and 8, the semiconductor device is a DRAM, and basically has the same structure as that of the first embodiment of the semiconductor device according to the present invention shown in FIGS. However, in the semiconductor device shown in FIGS. 7 and 8, a plurality of contact holes 32 are formed on the capacitor upper electrode 22 instead of the damascene wiring trench. The depth of the contact hole 32 is set to be substantially equal to the depth of the damascene wiring groove 25b. Inside the contact hole 32, a barrier metal layer 34a is formed in the same manner as the damascene wiring trench 25a shown in FIG. A conductor film 26a containing copper or the like is formed on the barrier metal layer 34a so as to fill the contact hole 32.
[0074]
A seventh interlayer insulating film 29 is formed on the sixth interlayer insulating film. A contact hole 30 a is formed on the contact hole 32 in the seventh interlayer insulating film 29. A damascene wiring trench 31 is formed on the contact hole 30a. A barrier metal layer 35 a is formed inside the contact hole 30 a and the damascene wiring groove 31. On the barrier metal layer 35a, a conductor film 33 such as copper is formed so as to fill the inside of the contact hole 30a and the damascene wiring trench 31. The damascene wiring groove 31 is formed to extend in a direction substantially perpendicular to the paper surface. The conductor film 33 is connected to each of the conductor films 26a located inside the plurality of contact holes 32 formed so as to be aligned in a direction perpendicular to the paper surface via the contact holes 30a.
[0075]
A contact hole 30b is formed in a region located on the conductor film 26b. A barrier metal layer 35b is formed inside the contact hole 30b. On the barrier metal layer 35b, a conductor film 33 such as copper is formed so as to fill the inside of the contact hole 30b.
[0076]
Here, by changing the planar shape of the contact hole 32, the contact area between the conductor film 26a and the capacitor upper electrode 22 can be changed.
[0077]
The semiconductor device shown in FIGS. 7 and 8 can be manufactured basically in the same process as the manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIGS. That is, after the steps shown in FIGS. 3 and 4 are performed, in the step shown in FIG. 5, in the resist film 28, the region located on the capacitor upper electrode 22 is not a pattern for the damascene wiring trench, but a contact hole. A hole pattern for forming 32 is formed. Thereafter, the process shown in FIG. 6 is performed. Then, by forming the seventh interlayer insulating film 29, the contact holes 30a and 30b, and the conductor film 33, the semiconductor device shown in FIGS. 7 and 8 can be obtained.
[0078]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
[0079]
【The invention's effect】
As described above, according to the present invention, by using the damascene wiring layer as the wiring layer connected to the capacitor electrode, it is possible to prevent the occurrence of defects and reduce the manufacturing cost and the manufacturing thereof. You can get the method.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
2 is a schematic diagram showing a cross section taken along line II-II in FIG. 1; FIG.
3 is a schematic cross-sectional view for illustrating a first step in the manufacturing process of the semiconductor device shown in FIG. 1. FIG.
4 is a schematic cross-sectional view for explaining a second step of the manufacturing process of the semiconductor device shown in FIG. 1. FIG.
FIG. 5 is a schematic cross-sectional view for explaining a third step of the manufacturing process of the semiconductor device shown in FIG.
6 is a schematic cross-sectional view for explaining a fourth step of the manufacturing process of the semiconductor device shown in FIG. 1. FIG.
FIG. 7 is a schematic cross-sectional view showing a second embodiment of a semiconductor device according to the present invention.
8 is a schematic diagram showing a cross section taken along line VIII-VIII in FIG. 7;
FIG. 9 is a schematic cross-sectional view showing a DRAM as a conventional semiconductor device.
[Explanation of symbols]
1 substrate, 2a to 2e conductive region, 3a to 3c gate insulating film, 4a to 4c gate electrode, 5a to 5f side wall insulating film, 6a to 6c covering insulating film, 7, 10, 13, 17, 18, 23, 29 Interlayer insulating film, 8a, 8b, 11a, 11b, 14, 24, 30a, 30b, 32 contact hole, 9a, 9b, 15a, 15b, 16, 26a, 26b, 33 Conductor film, 12a, 12b First wiring Layer, 19 opening, 20 capacitor lower electrode, 21 dielectric film, 22 capacitor upper electrode, 25a, 25b, 31 damascene wiring trench, 27, 28 resist film, 34a, 34b, 35a, 35b barrier metal layer.

Claims (5)

A conductive region formed on a semiconductor substrate;
A first insulating film formed on the conductive region;
A capacitor electrode formed on the first insulating film;
A second insulating film formed on the capacitor electrode, having a first groove exposing a part of the capacitor electrode, and having an upper surface;
A first wiring layer filled in the first groove, having an upper surface, and connected to the capacitor electrode;
A contact hole reaching the conductive region is formed in the first and second insulating films, a second groove connected to the contact hole is formed in the second insulating film, and
A second wiring layer filled in the second groove and the contact hole;
The upper surface of the first wiring layer, the upper surface of the second wiring layer, and the upper surface of the second insulating film are located on substantially the same plane ,
The semiconductor device, wherein the first and second wiring layers contain copper .   The semiconductor device according to claim 1, wherein the first groove and the second groove of the second insulating film are formed so as to extend substantially in parallel. Forming a conductive region on a semiconductor substrate;
Forming a first insulating film on the conductive region;
Forming a capacitor electrode on the first insulating film;
Forming a second insulating film having an upper surface on the capacitor electrode;
Forming a contact hole reaching the conductive region in the first and second insulating films;
In the second insulating film, a first groove is formed so as to expose a part of the capacitor electrode, and a second groove is formed in the second insulating film in a region located on the contact hole. And a process of
Forming a conductor film so as to fill the inside of the first groove, the contact hole, and the second groove and to extend to the upper surface of the second insulating film;
The conductor film located on the upper surface of the second insulating film is removed and the conductor film located on the first groove and the second groove of the second insulating film By removing a part of the conductive film, the conductive film fills the inside of the first groove and the second groove, and is located substantially on the same plane as the upper surface of the second insulating film. Forming a first wiring layer and a second wiring layer having an upper surface. The method of manufacturing a semiconductor device according to claim 3 , wherein the step of forming the second groove includes forming the second groove so as to extend substantially in parallel with the first groove. It said conductive film comprises copper, a method of manufacturing a semiconductor device according to claim 3 or 4.

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