JP4592889B2 - Multilayer circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer circuit board in which a core substrate is multi-layered. In particular, the multi-layer core substrate is formed by laminating a plurality of single-sided or double-sided circuit boards with filled via holes, and batch heating press through an adhesive. The electrical connection between the conductor circuit in the multi-layer core substrate and the build-up wiring layer formed on the multi-layer core substrate is made by the via hole formed in the multi-layer core substrate and the build-up wiring formed immediately above Conductive bumps that can be secured via via holes in the layer, and can be directly connected to the outermost conductor circuit of the build-up wiring layer to electronic components including the semiconductor chip such as LSI and the motherboard, conductive We propose a multilayer circuit board that is advantageous for ultra-high-density wiring with pins or conductive balls.
[0002]
[Prior art]
In recent years, package substrates for mounting electronic components including semiconductor chips such as LSIs are required to have high density and high reliability with fine patterns in response to miniaturization or speeding-up of electronic equipment accompanying the advancement of the electronics industry. It has been. As such a package substrate, “Surface mounting technology” in the January issue of 1997 discloses one in which build-up multilayer wiring layers are formed on both surfaces of a multilayer core substrate.
[0003]
However, in the package substrate according to the above-described prior art, the inner layer pad wired from the through hole is provided on the surface of the multilayer core substrate for connection between the conductor layer and the build-up wiring layer in the multilayer core substrate. It was done by connecting via holes. For this reason, the land shape of the through hole becomes a dharma shape or an iron array shape, and the area of the inner layer pad hinders improvement in the arrangement density of the through holes, and the number of through holes formed has a certain limit. Therefore, when the core substrate is multilayered in order to increase the wiring density, the outer build-up wiring layer cannot secure sufficient electrical connection with the conductor layers in the multilayer core substrate. It was.
[0004]
Note that this problem is the present inventors Raha destination and proposes the improved method as Japanese Patent Application No. 10-15346 (Japanese Patent Laid-Open No. 11-214846). A multilayer circuit board based on such an improvement proposal is a build-up wiring in which an interlayer resin insulation layer and a conductor layer are alternately laminated on a multilayer core board having a conductor layer as an inner layer, and each conductor layer is connected by a via hole. In the multilayer circuit board in which a layer is formed, a through-hole is formed in the multilayer core board, and the through-hole is filled with a filler and covers the exposed surface of the filler from the through-hole. Is formed, and via holes are connected to the conductor layer, thereby improving the arrangement density of the through holes, and connecting with the conductor circuit in the multilayered core substrate through the increased through holes Can be secured.
[0005]
[Problems to be solved by the invention]
However, the through hole in the multilayer circuit board having such a structure is formed by drilling a through-hole with a drill or the like in the multilayered core board and subjecting the wall surface of the through-hole and the substrate surface to electroless plating. In consideration of performance and economy, the lower limit of the through hole opening diameter that can be formed is about 300 μm, and in order to realize ultra-high density wiring that satisfies the demands of the current electronic industry, it is about 50 to 250 μm. Development of technology for obtaining a smaller opening diameter and narrower through-hole land pitch is desired.
[0006]
Therefore, the present inventors have a plurality of circuit boards each having a conductor circuit on one or both sides of a core material made of a hard material and filled via holes reaching the conductor circuit through the core material from the one surface. If the multi-layer core substrate is formed by laminating each other and collectively heat-pressing through an adhesive, the conductor circuits in the multi-layer core substrate and the multi-layer core substrate can be formed without providing a through hole in the multi-layer core substrate. Electrical connection between the internal conductor circuit and the build-up wiring layer formed on the multilayer core board is sufficient via the filled via hole formed in the multilayer core board and the via hole in the build-up wiring layer formed immediately above it. Knowing that
Further, a conductive bump for forming a part of a conductor circuit located on the outermost side of one build-up wiring layer on a solder pad and connecting an electronic component including a semiconductor chip such as an LSI to the solder pad. A conductive pin or a conductive ball that can be directly connected to the motherboard with respect to the solder pad by forming a part of the conductor circuit located on the outermost side of the other build-up wiring layer on the solder pad. It was found that high-density wiring and high-density mounting of electronic parts can be realized by arranging the wiring.
An object of the present invention is to provide a multilayer circuit board that is advantageous for such high-density wiring and high-density mounting of electronic components.
[0007]
[Means for Solving the Problems]
As a result of intensive research aimed at realizing the above object, the inventors have come up with an invention having the following contents as a gist. That is,
(1) The multilayer circuit board of the present invention comprises:
An interlayer resin insulation layer and a conductor layer formed by a semi-additive method are alternately laminated on a multilayer core substrate having a conductor circuit in the inner layer, and a build-up wiring layer in which each conductor layer is connected by a via hole is formed. In the multilayer circuit board
The multilayer core substrate has a conductor circuit on one or both sides of an insulating hard base formed from a hard resin material that has been completely cured, and the holes reach the conductor circuit through the insulating hard base. In addition, a plurality of circuit boards having via holes filled with a conductive material are laminated via an adhesive layer, and are formed by being collectively heat-pressed ,
Each circuit board constituting the multilayer core substrate is a projection that is electrically connected to the via hole of the hole of the insulating hard base and protrudes from the hole, penetrates the adhesive layer by a hot press and is thermally deformed. It has a conductor .
[0008]
(2) Moreover, the multilayer circuit board of the present invention comprises:
A build-up wiring layer in which an interlayer resin insulation layer and a conductor layer formed by a semi-additive method are alternately laminated on both surfaces of a multilayer core substrate having a conductor circuit in an inner layer, and each conductor layer is connected by a via hole In the multilayer circuit board formed,
The multilayer core substrate has a conductor circuit on one or both sides of an insulating hard base formed from a hard resin material that has been completely cured, and the holes reach the conductor circuit through the insulating hard base. In addition, a plurality of circuit boards having via holes filled with a conductive material are laminated via an adhesive layer, and are formed by being collectively heated and pressed,
Solder bumps are provided on the surface of the outermost conductor layer constituting one of the buildup wiring layers, and conductive pins are provided on the surface of the outermost conductor layer constituting the other of the buildup wiring layer. Or conductive balls are arranged ,
Each circuit board constituting the multilayer core substrate is a projection that is electrically connected to the via hole of the hole of the insulating hard base and protrudes from the hole, penetrates the adhesive layer by a hot press and is thermally deformed. It has a conductor .
[0009]
The conductive material filled in the via hole of each circuit board constituting the multilayer core substrate of (1) or (2) is preferably formed from metal plating or conductive paste formed by electrolytic plating. The plating is more preferably electrolytic copper plating, and the conductive paste is more preferably composed of metal particles and a thermosetting or thermoplastic resin.
[0010]
Further, in the above-mentioned multilayer circuit board, each circuit board constituting the multilayer core substrate, corresponding to the via hole position, protrudes from the electrically connected Rutotomoni the hole in the via hole, the adhesive layer by heat pressing are projecting conductors to thermal deformation formed with penetrating, the projecting conductors are desirably formed from conductive paste.
It is desirable that a part of the via hole of the build-up wiring layer is located immediately above the via hole formed in the multilayer core substrate and directly connected to the via hole.
[0011]
In the multilayer circuit board, the insulating base material of each circuit board constituting the multilayer core board is a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy It is desirable to form from the hard base material chosen from the resin base material and an aramid nonwoven fabric-polyimide resin base material.
[0012]
The insulating base material of each circuit board constituting the multilayer core substrate is preferably formed of a glass cloth epoxy resin base material having a thickness of 20 to 600 μm, and the filling via hole diameter is preferably 50 to 250 μm.
[0013]
Further, the filled via hole is formed with respect to the opening of the carbon dioxide laser under the conditions of pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50. It is desirable to be a thing.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The multilayer circuit board of the present invention is a multilayer circuit board in which a build-up wiring layer is formed on a multilayer core board. The multilayer circuit board has a conductor circuit on one side or both sides of an insulating hard base. A plurality of circuit boards each having a conductive material such as electrolytic plating or conductive paste filled in through holes reaching the conductor circuit through the conductive hard base material are stacked on each other via an adhesive layer, and collectively Then, it is characterized in that it is formed by hot pressing.
[0015]
According to such a configuration, since it is not necessary to provide a through hole in the core substrate, the degree of freedom in arranging pads such as lands is improved. As a result, filled via holes can be provided with high density, and the build-up wiring layer of the outer layer can ensure sufficient connection with the conductor circuit in the multilayer core substrate through the via holes thus densified. Thus, high-density wiring can be achieved. Further, it is possible to further increase the density of the wiring in the multilayer core substrate.
[0016]
Furthermore, the multilayer circuit board of the present invention is a multilayer core board formed by laminating a plurality of circuit boards having conductor circuits on one side or both sides of a hard insulating base material through an adhesive and collectively forming by a heat press. Solder bumps are provided on the surface of the outermost conductor layer constituting one of the buildup wiring layers formed on the front surface and the back surface, and the surface of the outermost conductor layer constituting the other of the buildup wiring layers Further, a conductive pin or a conductive ball is provided.
[0017]
According to such a configuration, via holes are provided in the build-up wiring layer with high density, and thus exposed from the opening formed in the outermost solder resist layer among the conductor layers having the densified via holes. Since conductive bumps, conductive pins, or conductive balls are disposed on the conductive pads to be built, the build-up wiring layer in the multilayer circuit board is provided with such conductive bumps, conductive pins, or conductive balls. In this way, it is connected to an electronic component including a semiconductor chip such as an LSI or a mother board with the shortest wiring length, thereby enabling high-density wiring and high-density mounting of the electronic component.
[0018]
In the present invention, each circuit board which constitutes the multilayer core substrate is formed from a conventional such semi-cured and not in the form of prepreg, the insulating resin base material of the fully cured rigid formed from a hard resin material .
[0019]
Examples of such insulating base materials include glass cloth epoxy resin base materials, glass cloth bismaleimide triazine resin base materials, glass cloth polyphenylene ether resin base materials, aramid non-woven fabric-epoxy resin base materials, aramid non-woven fabric-polyimide resin base materials. A rigid (hard) laminate substrate is used, with a glass cloth epoxy resin substrate being most desirable.
[0020]
When a conductor circuit is formed on the insulating base material, the final thickness variation of the insulating base material due to the pressing pressure is eliminated in the step of pressing the copper foil on the insulating base material by a hot press. The positional deviation of the via holes can be minimized, the via land diameter can be reduced, and as a result, the wiring pitch can be reduced and the wiring density can be improved.
[0021]
Moreover, since the cured resin base material is used as the insulating base material, the thickness of the base material can be kept substantially constant, and as a result, it is easy to set the laser processing conditions when forming the opening for forming the via hole. Become.
[0022]
As for the thickness of the said insulating base material, 20-600 micrometers is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength decreases and handling becomes difficult, and the reliability with respect to electrical insulation becomes low. If the thickness exceeds 600 μm, it becomes difficult to form a fine via hole formation and the substrate itself is thick. It is to become.
[0023]
The via hole forming opening formed on the glass epoxy substrate having the thickness in the above range has a pulse energy of 0.5 to 100 mJ, a pulse width of 1 to 100 μs, a pulse interval of 0.5 ms or more, and a shot number. It is preferably formed by a carbon dioxide laser irradiated under conditions of 3 to 50, and the opening diameter is desirably in the range of 50 to 250 μm. The reason is that if it is less than 50 μm, it becomes difficult to fill the opening with a conductive material and the connection reliability is lowered, and if it exceeds 250 μm, it is difficult to increase the density.
[0024]
Prior to the opening formation with such a carbon dioxide laser, a resin film is adhered to the surface of the insulating substrate opposite to the conductor circuit forming surface, or, if necessary, through a semi-cured resin adhesive layer. It is desirable to adhere the resin film and perform laser irradiation from the resin film.
In the former method, a non-through hole is formed by irradiating a laser beam from the side opposite to the copper foil on an insulating base having a copper foil previously bonded on one side, and the copper foil is electrolyzed as a plating lead in the non-through hole. When a single-sided circuit board is manufactured by etching after filling the plating layer, or a non-through hole is provided by laser irradiation on an insulating substrate on which a conductor circuit is pre-formed by etching a single-sided copper-clad laminate. The non-through hole is used when a single-sided circuit board is manufactured by filling an electroplating layer with copper foil as a plating lead. The latter is provided with a through hole in advance by laser irradiation on an insulating substrate. This method is used when a double-sided circuit board is manufactured by filling a through-hole with a conductive paste, and then attaching a copper foil to both sides of an insulating base material and etching.
This resin adhesive is for adhering the copper foil to the surface of the insulating substrate, and is formed of, for example, a bisphenol A type epoxy resin, and the thickness is preferably in the range of 10 to 50 μm.
[0025]
The resin film pasted on the insulating base material or on the resin adhesive layer formed on the insulating base material is used when the via hole is formed by filling electrolytic plating in the opening for forming the via hole. As a protective film or when a conductive paste is filled in the opening to form a via hole and a protruding conductor, or a conductive paste is filled on the electrolytic plating layer and the protruding conductor ( It functions as a mask for printing when forming a (bump), and has a pressure-sensitive adhesive layer that can be peeled off from an insulating substrate or an adhesive layer after filling with a conductive substance.
This resin film is preferably formed from a PET film having a pressure-sensitive adhesive layer thickness of 1 to 20 μm and a film thickness of 10 to 50 μm, for example.
[0026]
The reason is that, depending on the thickness of the PET film, the height of the protruding conductor described later is determined. Therefore, when the thickness is less than 10 μm, the protruding conductor is too low to easily cause a connection failure, and conversely, it exceeds 50 μm. This is because, with the thickness, the protrusion-shaped conductor spreads too much at the connection interface, so that a fine pattern cannot be formed.
[0027]
As the conductive material filled in the opening formed in the insulating substrate, metal plating or conductive paste formed by electrolytic plating is preferable. The conductive paste is preferable in terms of simplifying the process, reducing manufacturing costs, and improving yield, but metal plating is more preferable from the viewpoint of connection reliability.
As the conductive paste, a conductive paste made of at least one metal particle selected from silver, copper, gold, nickel, and solder can be used.
[0028]
As said metal particle, what coated the different metal on the surface of the metal particle can also be used. Specifically, the metal particle which coat | covered the noble metal chosen from gold | metal | money and silver on the surface of a copper particle can be used.
As such a conductive paste, an organic conductive paste in which a thermosetting resin such as an epoxy resin or a phenol resin and a thermoplastic resin such as polyphenylene sulfide (PPS) are added to metal particles is desirable.
[0029]
The conductor circuit formed on one side or both sides of the insulating substrate is subjected to an appropriate etching process after hot pressing a copper foil having a thickness of 5 to 18 μm through a resin adhesive layer held in a semi-cured state. It is preferable to be formed. Such hot pressing is performed under an appropriate temperature and pressure. More preferably, conducted under reduced pressure, by curing only the resin adhesive layer in a semi-cured state, since the copper foil can be securely bonded to the insulating substrate, the circuit board using conventional prepreg Compared with the manufacturing time, the manufacturing time is shortened.
[0030]
A circuit board in which such a conductor circuit is formed on both surfaces of a hard insulating substrate is suitable as a core of a multilayer core board, but a part of the conductor circuit is formed on the board surface corresponding to each via hole. The via land (pad) is preferably formed in a diameter of 50 to 250 μm.
[0031]
In addition, a circuit board in which a conductor circuit is formed on one side of a hard insulating base material can be a multilayer board by sequentially superimposing a plurality of them, and a double-sided circuit board as a core, It is suitable as a laminated circuit board laminated on both sides thereof, and it is preferable that a protruding conductor is formed immediately above the position of the conductive material filled in the via hole.
[0032]
The protruding conductor is preferably formed from a conductive paste or a low-melting metal, and the conductive paste or the low-melting metal is thermally deformed in the process of laminating each circuit board and collectively heating and pressing. Therefore, it is possible to absorb the variation in the height of the conductive material filled in the via hole, and thus it is possible to obtain a multi-layer core substrate excellent in connection reliability by preventing connection failure.
Further, such a protruding conductor can be formed of the same material as that of the conductive paste filled in the via hole and by the same filling process.
[0033]
Furthermore, when the build-up wiring layer formed on the multilayer core substrate is formed by resin application and curing as described later, a roughened layer is formed on the surface of the conductor circuit provided on the multilayer core substrate surface. It is advantageous that
The reason is that the adhesion to the interlayer resin insulation layer and via hole in the build-up wiring layer laminated on the multilayer core substrate can be improved.
In particular, when a roughened layer is formed on the side surface of the conductor circuit, cracks generated toward the interlayer resin insulating layer starting from these interfaces due to insufficient adhesion between the side surface of the conductor circuit and the interlayer resin insulating layer are suppressed. be able to.
[0034]
On the other hand, when the build-up wiring layer is formed by laminating resin films and curing by heating and pressing as described later, the formation of the roughened layer is not necessarily required.
[0035]
The thickness of the roughened layer formed on the surface of such a conductor circuit is preferably 0.1 to 10 μm. This is because if it is too thick, it will cause a short circuit between layers, and if it is too thin, the adhesion to the adherend will be low. The roughened layer is preferably formed by treating with a mixed aqueous solution of an organic acid and a cupric complex, or formed by plating a copper-nickel-phosphorous needle-like alloy.
[0036]
Among these roughening treatments, the treatment using a mixed aqueous solution of an organic acid-cupric copper complex acts as follows under oxygen coexistence conditions such as spraying and bubbling, and is a metal foil such as copper which is a conductor circuit. Dissolve.
Cu + Cu (II) A _n → 2Cu (I) A _{n / 2}
2Cu (I) A _{n / 2} + n / 4O ₂ + nAH (aeration)
→ 2Cu (II) A _n + n / 2H ₂ O
A is a complexing agent (acting as a chelating agent), and n is a coordination number.
[0037]
The cupric complex used in this treatment is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As azoles, diazole, triazole, and tetrazole are preferable. Of these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable.
The content of the cupric complex of the azole is preferably 1 to 15% by weight. It is because it is excellent in solubility and stability if it is within this range.
[0038]
The organic acid is added to dissolve the copper oxide.
Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple Any one selected from acids and sulfamic acids is preferable.
The content of the organic acid is preferably 0.1 to 30% by weight. This is to maintain the solubility of oxidized copper and to ensure dissolution stability.
In addition, the generated cuprous complex is dissolved by the action of an acid and combined with oxygen to form a cupric complex, which again contributes to the oxidation of copper.
In addition to organic acids, inorganic acids such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.
[0039]
In order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions such as fluorine ions, chlorine ions and bromine ions may be added to the etching solution comprising the organic acid-cupric complex. This halogen ion can be supplied by adding hydrochloric acid, sodium chloride or the like.
The amount of halogen ions is preferably 0.01 to 20% by weight. This is because, if it is within this range, the formed roughened layer has excellent adhesion to the interlayer resin insulating layer.
The etching solution comprising this organic acid-cupric complex is prepared by dissolving a cupric complex of an azole and an organic acid (halogen ions as required) in water.
[0040]
Moreover, in the plating treatment of the needle-like alloy composed of copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphorous acid It is desirable to use a plating bath having a liquid composition comprising 10 to 100 g / l of salt, 10 to 40 g / l of boric acid, and 001 to 10 g / l of a surfactant.
[0041]
In the present invention, the multi-layer core substrate is formed by laminating a plurality of circuit boards having conductor circuits on one or both sides and collectively heating and pressing them. As the interlayer resin insulating layer constituting the build-up wiring layer to be formed, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used.
[0042]
As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE), or the like can be used.
Thermoplastic resins include phenoxy resins, fluororesins such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether Sulphone (PES), polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoroethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polyolefin resin and the like can be used.
As a composite of a thermosetting resin and a thermoplastic resin, epoxy resin-PES, epoxy resin-PSF, epoxy resin-PPS, epoxy resin-PPES, epoxy resin-phenoxy resin, phenol resin-phenoxy resin, and the like can be used.
[0043]
In the present invention, the interlayer resin insulation layer constituting the build-up wiring layer can be formed by laminating a desired number of resin films such as polyolefin resin, heat-pressing, and then thermosetting and integrating them. .
The thickness of the polyolefin resin layer is preferably in the range of 5 to 200 μm. The reason is that if the thickness is less than 5 μm, it is difficult to ensure interlayer insulation, and if it exceeds 200 μm, it is difficult to form an opening by laser processing.
[0044]
Moreover, in this invention, the adhesive agent for electroless plating can be used as an interlayer resin insulation layer which comprises a buildup wiring layer.
As the electroless plating adhesive, heat-resistant resin particles that are soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin that becomes insoluble in an acid or oxidizing agent by the curing treatment. What is best. This is because the heat-resistant resin particles are dissolved and removed by treatment with an acid or an oxidizing agent, and a roughened surface made of crucible-like anchors can be formed on the surface.
The depth of the roughened surface is preferably 0.1 to 20 μm. This is to ensure adhesion. Moreover, 0.1-5 micrometers is good in a semi-additive process. This is because the electroless plating film can be removed while ensuring adhesion.
[0045]
In the above electroless plating adhesive, the heat-resistant resin particles that are particularly cured include (1) a heat-resistant resin powder having an average particle size of 10 μm or less, and (2) a heat-resistant resin having an average particle size of 2 μm or less. Agglomerated particles obtained by agglomerating powder, (3) a mixture of heat-resistant resin powder having an average particle diameter of 2 to 10 μm and heat-resistant resin powder having an average particle diameter of 2 μm or less, and (4) an average particle diameter of 2 to 10 μm Pseudo particles formed by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle size of 2 μm or less to the surface of the heat-resistant resin powder, (5) an average particle size of 0.1 to 0.8 μm At least one selected from a mixture of a heat-resistant resin powder and a heat-resistant resin powder having an average particle size of more than 0.8 μm and less than 2 μm, and (6) a heat-resistant resin powder having an average particle size of 0.1 to 10 μm It is desirable to use seeds.
Further, metal particles or inorganic particles may be used in place of the resin particles, and a plurality of these types may be mixed as appropriate. This is because more complex anchors can be formed.
As the heat-resistant resin used in the above electroless plating adhesive, the aforementioned thermosetting resin, thermoplastic resin, or a composite of thermosetting resin and thermoplastic resin can be used.
[0046]
In the present invention, the electrical connection between the conductor circuit formed on the multilayer core substrate and the conductor circuit in the build-up wiring layer can be made by a via hole formed in the interlayer resin insulation layer. In this case, the via hole may be filled with a plating film or a filler.
[0047]
Hereinafter, an example of manufacturing the multilayer circuit board of the present invention will be specifically described with reference to the accompanying drawings. In the method described below, the build-up wiring layer is formed on the multilayer core substrate by a semi-additive method .
[0048]
(A) Formation of multilayer core substrate
(1) In manufacturing a multilayer circuit board according to the present invention, the circuit board constituting the multilayer core board as a base has a copper foil 12 attached to one side of an insulating base 10 as an insulating hard base . Is used as starting material.
The insulating base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid non-woven fabric-epoxy resin base material, an aramid non-woven fabric-polyimide resin base material. Although a chosen hard laminate substrate can be used, a glass cloth epoxy resin substrate is most preferred.
[0049]
As for the thickness of the said insulating base material 10, 20-600 micrometers is desirable. The reason is that when the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to the electrical insulation is reduced. When the thickness exceeds 600 μm, formation of fine via holes and filling of conductive paste are performed. This is because the thickness of the substrate itself is increased.
[0050]
Moreover, as for the thickness of the copper foil 12, 5-18 micrometers is desirable. The reason for this is that when forming an opening for forming a via hole (non-through hole) in an insulating base material using laser processing as described later, if it is too thin, it penetrates, and conversely it is too thick. This is because it is difficult to form a conductor circuit pattern having a fine line width by etching.
[0051]
As the insulating base material 10 and the copper foil 12, in particular, a single-sided copper-clad laminate obtained by laminating an epoxy resin into a glass cloth to form a B stage and laminating a copper foil and heating and pressing. It is preferable to use a plate. The reason is that the position of the wiring pattern and the via hole is not shifted during handling after the copper foil 12 is etched as will be described later, and the positional accuracy is excellent.
[0052]
(2) First, when manufacturing a circuit board having conductor circuits formed on both sides, a protective film 14 is provided on the surface opposite to the surface of the insulating base material 10 on which the copper foil 12 is attached. Affix (see Fig. 1 (a)).
[0053]
This protective film 14 is used as a mask for printing a conductive paste for forming a protruding conductor described later. For example, a polyethylene terephthalate (PET) film having an adhesive layer on the surface can be used.
The PET film 14 is such that the pressure-sensitive adhesive layer has a thickness of 1 to 20 μm and the film itself has a thickness of 10 to 50 μm.
[0054]
(3) Next, carbon dioxide laser irradiation is performed from above the PET film 14 affixed on the insulating base material 10, penetrating the PET film 14, and opening 16 reaching the copper foil 12 from the surface of the insulating base material 10. (See FIG. 1B).
This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions are pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 3. It is desirable to be within the range of 50.
The via diameter that can be formed under such processing conditions is preferably 50 to 250 μm.
[0055]
(4) A desmear process is performed in order to remove the resin residue remaining on the side surface and the bottom surface of the opening 16 formed in the step (3).
This desmear treatment is performed by oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, excimer laser treatment, or the like. In particular, it is desirable to perform desmear treatment by irradiating an ultraviolet laser or excimer laser into the opening from the viewpoint of securing connection reliability.
[0056]
The laser irradiation conditions when this desmear treatment is performed by, for example, ultraviolet laser irradiation using the YAG third harmonic are as follows: the transmission frequency is 3 to 15 KHz, the pulse energy is 0.1 to 5 mJ, and the number of shots is 10 to 30 A range is desirable.
[0057]
(5) Next, an electrolytic copper plating treatment using the copper foil 12 as a plating lead is performed on the desmeared substrate under the following conditions, and the electrolytic copper plating 18 is filled in the opening 16; A filled via hole 20 is formed (see FIG. 1C). By this plating treatment, the electrolytic copper plating 18 is filled in the upper portion of the opening 16 leaving a slight gap enough to fill the conductive paste 22 as will be described later.
[Electrolytic copper plating aqueous solution]
Copper sulfate pentahydrate: 65 g / l
Leveling agent (manufactured by Atotech, HL): 20 ml / l
Sulfuric acid: 220 g / l
Brightener (Atotech, UV): 0.5ml / l
Chlorine ion: 40ppm
[Electrolytic plating conditions]
Bubbling: 3.0 l / min Current density: 0.5 A / dm ²
Set current value: 0.18 A
Plating time: 130 minutes [0058]
(6) After filling the conductive paste 22 with the protective film 14 as a printing mask against the slight gap or dent above the opening 18 that was not filled with the electrolytic copper plating 20 in (5) above, the insulating paste 22 A conductor portion 24 (hereinafter referred to as “protruding conductor”) protruding from the surface of the substrate 10 by an amount corresponding to the thickness of the protective film 14 is formed (see FIG. 1D).
[0059]
(7) Next, after the protective film 14 is peeled off, an adhesive layer 26 is formed on the surface of the insulating substrate 10 including the protruding conductors 24 (see FIG. 1E). This adhesive 26 is a semi-cured state, that is, a B-stage adhesive, and is used for adhering a copper foil on which a conductor circuit pattern is to be formed. For example, an epoxy resin varnish is used, and its layer thickness is 10 A range of ˜50 μm is preferred.
[0060]
(8) A copper foil 28 is pressure-bonded to the surface of the insulating base material 10 provided with the adhesive layer 26 in the step (7) by a hot press to cure the adhesive layer 26 (FIG. 1 (f) reference).
At that time, the copper foil 28 is bonded to the insulating substrate 10 through the cured adhesive layer 26, and the protruding conductor 24 penetrates the adhesive layer 26 and is electrically connected to the copper foil 28. As for the thickness of this copper foil 28, 5-18 micrometers is desirable.
[0061]
(9) Next, on each of the copper foils 12 and 28 attached to both surfaces of the insulating base material 10, an etching protective film is attached, and after an unmasking with a predetermined circuit pattern mask, an etching process is performed. Conductor circuits 30 and 32 (including via lands) are formed (see FIG. 1 (g)).
[0062]
In this processing step, a photosensitive dry film resist is first applied to the surfaces of the copper foils 12 and 28, and then an etching resist is formed by exposing and developing along a predetermined circuit pattern. The metal layer is etched to form conductor circuit patterns 30 and 32 including via lands.
The etching solution is preferably at least one aqueous solution selected from an aqueous solution of sulfuric acid monohydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
[0063]
As a pretreatment for forming the conductor circuits 30 and 32 by etching the copper foils 12 and 28, in order to facilitate the formation of a fine pattern, the entire surface of the copper foil is etched in advance to a thickness of 1 to 10 μm. Preferably, the thickness can be reduced to about 2 to 8 μm.
The via land as a part of the conductor circuit has an inner diameter that is substantially the same as the via hole diameter, but the outer diameter is preferably in the range of 50 to 250 μm.
[0064]
(10) Next, the surfaces of the conductor circuits 30 and 32 formed in the step (8) are roughened as necessary (the display of the roughened layer is omitted) to form the double-sided circuit board 34. To do.
This roughening treatment is to improve adhesion with the adhesive layer and prevent peeling (delamination) when multilayering.
Examples of the roughening treatment method include soft etching treatment, blackening (oxidation) one-reduction treatment, formation of needle-like alloy plating made of copper-nickel-phosphorus (made by Sugawara Eugleite: trade name Interplate), manufactured by MEC There is surface roughening with an etchant named “MEC Etch Bond”.
[0065]
In this embodiment, the roughening layer is preferably formed using an etching solution. For example, the surface of the conductor circuit is etched using an etching solution from a mixed aqueous solution of a cupric complex and an organic acid. It can be formed by processing. Such an etching solution can dissolve the copper conductor circuit pattern under oxygen coexistence conditions such as spraying and bubbling, and the reaction is assumed to proceed as follows.
Cu + Cu (II) A _n → 2Cu (I) A _{n / 2}
2Cu (I) A _{n / 2} + n / 4O ₂ + nAH (aeration)
→ 2Cu (II) A _n + n / 2H ₂ O
In the formula, A represents a complexing agent (acts as a chelating agent), and n represents a coordination number.
[0066]
As shown in the above formula, the generated cuprous complex is dissolved by the action of an acid, is combined with oxygen to form a cupric complex, and again contributes to the oxidation of copper. The cupric complex used in the present invention is preferably an azole cupric complex. The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ions as required) in water.
Such an etching solution is formed, for example, from an aqueous solution in which 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride are mixed.
The double-sided circuit board constituting the multilayer board serving as the base of the multilayer circuit board according to the present invention is manufactured according to the steps (1) to (10).
[0067]
(11) Next, a single-sided circuit board that is laminated on the front and back surfaces of such a double-sided circuit board is manufactured.
First, processing according to the steps (1) to (6) for manufacturing the double-sided circuit board 34 is performed, and laser irradiation is performed from the surface opposite to the copper foil 12 attached to one surface of the insulating base material 10. After forming a non-through hole and filling the non-through hole with the electrolytic copper plating layer 18 to form the via hole 20, the conductive paste 22 is filled into a slight gap above the via hole to form the protruding conductor 44 ( FIG. 2 (a) to FIG. 2 (d)).
[0068]
The protruding height of the protruding conductor 44 from the surface of the insulating base material 10 is substantially equal to the thickness of the protective film 14 and is preferably in the range of 5 to 30 μm.
The reason is that if the thickness is less than 5 μm, poor connection is likely to occur, and if the thickness exceeds 30 μm, the resistance value becomes high, and when the protruding conductor 44 is thermally deformed in the hot press process, it expands too much along the surface of the insulating substrate. This is because a fine pattern cannot be formed.
The protruding conductor 44 is preferably precure.
The reason is that the protruding conductor 44 is hard even in a semi-cured state, and can be in electrical contact with conductor circuits (conductor pads) of other circuit boards to be laminated before the adhesive layer is cured at the stage of the lamination press. Because it becomes.
Such protruding conductors 44 are deformed at the time of hot pressing to increase the contact area, so that the conduction resistance can be lowered and the variation in the height of the protruding conductors 44 is corrected.
[0069]
(12) Next, the protective film 14 opened by laser irradiation is covered, and after the etching protective film 25 is pasted, it is shown with a mask having a predetermined circuit pattern, and then an etching process is performed, so that the conductor circuit 40 (via land is formed). (See FIG. 2 (e)).
In this processing step, first, a photosensitive dry film resist is applied to the surface of the copper foil 12, and then exposed and developed along a predetermined circuit pattern to form an etching resist. The layer is etched to form a conductor circuit pattern 40 including via lands.
[0070]
The etching solution is preferably at least one aqueous solution selected from an aqueous solution of sulfuric acid monohydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
As a pretreatment for forming the conductor circuit 40 by etching the copper foil 12, the entire surface of the copper foil is etched in advance to have a thickness of 1 to 10 μm, more preferably 2 to 2 to facilitate the formation of a fine pattern. The thickness can be reduced to about 8 μm.
[0071]
(13) After the conductor circuit 40 is formed on one side of the insulating base material 10, the protective film 14 and the etching protective film 25 are peeled off to expose the protruding conductor 44, whereby the single-sided circuit board 50 can be obtained. Further, an adhesive layer 46 is formed so as to cover the protruding conductors 44 exposed from the surface of the insulating substrate 10 (see FIG. 2 (f)).
Such a resin adhesive can be applied not only to the entire surface of the insulating substrate 10 including the protruding conductors 44 but also to a surface that does not include the protruding conductors 44 . It is formed as an adhesive layer 46 made of uncured resin. The adhesive layer 46 is preferably precured for easy handling, and the thickness is preferably in the range of 5 to 50 μm.
[0072]
The adhesive layer 46 is preferably made of an organic adhesive. Examples of the organic adhesive include epoxy resin, polyimide resin, thermosetting polyphenolene ether (PPE), and a composite of epoxy resin and thermoplastic resin. It is desirable to be at least one resin selected from a resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
Curtain coaters, spin coaters, roll coaters, spray coats, screen printing, and the like can be used as a method for applying an uncured resin that is an organic adhesive. The adhesive layer can also be formed by laminating an adhesive sheet.
[0073]
The single-sided circuit board 50 formed according to the above steps (11) to (13) has a conductor circuit 40 on one surface of the insulating base material 10 and is electrically conductive on the other surface immediately above the filled via hole 20. The protrusions 44 are formed by exposing a part of the paste, and the adhesive base layer 46 is formed on the surface of the insulating substrate 10 including the protrusions 44. Are laminated and bonded to each other or a double-sided circuit board 34 manufactured in advance to form a multilayered substrate. The resin adhesive 46 is preferably used in such a lamination step. .
[0074]
(B) Multi-layer circuit board for stacking As shown in FIG. 3, three single-sided circuit boards 50, 52 and 54 are stacked on both sides of the double-sided circuit board 34 manufactured in accordance with the processing step (1). The resulting four-layer substrate is integrated by a single press molding under the conditions of a heating temperature of 150 to 200 ° C. and a pressing force of 1 M to 4 MPa (see FIG. 4).
Under the above-described conditions, by heating simultaneously with pressurization, the protruding conductor 44 penetrates the adhesive layer 46 of each single-sided circuit board and is electrically connected to the conductor circuit 40 of the adjacent single-sided circuit board. While being connected, the adhesive layer 46 is cured, and strong adhesion is performed between the adjacent single-sided circuit boards. Note that a vacuum hot press is preferably used as the hot press.
In the embodiment described above, a double-sided circuit board having one layer and a single-sided circuit board having three layers are used to form a multi-layered structure with four layers.
[0075]
(C) Formation of build-up wiring layer Build-up wiring layers are formed on both surfaces of the multilayer core substrate 60 formed by the steps (1) and (2). In FIG. 5, the illustration of the double-sided and single-sided circuit boards constituting the multilayer core substrate 60 is omitted for the sake of simplicity (see FIG. 5A).
[0076]
(1) First, a roughened layer 62 made of copper-nickel-phosphorus is formed on the surface of the conductor circuit 52 on the surface of the multilayer core substrate 60 (see FIG. 5B).
The roughened layer 62 is formed by electroless plating. The liquid composition of this electroless plating aqueous solution has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 ^{−2 to} 4.1 × 10 ⁻² mol / l and 2.2 ×, respectively. It is desirable that they are 10 ^{−3 to} 4.1 × 10 ⁻³ mol / l, 0.20 to 0.25 mol / l.
This is because the crystal structure of the coating deposited in this range becomes a needle-like structure, and thus the anchor effect is excellent. In addition to the above compounds, complexing agents and additives may be added to the electroless plating aqueous solution.
As a method for forming the roughened layer, as described above, the roughened surface is formed by the treatment by copper-nickel-phosphorus needle alloy plating, the oxidation-reduction treatment, and the treatment of etching the copper surface along the grain boundary. There are methods.
[0077]
(2) Next, an interlayer resin insulating layer 64 is formed on the multilayer core substrate 60 having the roughened layer produced in (1) (FIG. 5C).
In particular, in the present invention, it is desirable to use an electroless plating adhesive having a resin matrix made of a composite of a thermosetting resin and a thermoplastic resin as an interlayer resin insulating material for forming a via hole 70 described later.
[0078]
(3) After the electroless plating adhesive layer formed in (2) is dried, an opening 65 for forming a via hole is provided (FIG. 5D).
In the case of a photosensitive resin, it is exposed and developed and then thermally cured. In the case of a thermosetting resin, the adhesive layer 64 is formed with an opening for forming a via hole by thermal curing and laser processing. A portion 65 is provided.
[0079]
(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer 64 are removed by decomposition or dissolution with an acid or an oxidizing agent, and the surface of the adhesive layer is subjected to a roughening treatment to be roughened surface 66. ( FIG. 5 (e)).
Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid. It is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.
On the other hand, as the oxidizing agent, it is desirable to use chromic acid or permanganate (such as potassium permanganate).
[0080]
(5) Next, catalyst nuclei are imparted to the roughened surface 66 on the surface of the adhesive layer 64.
For imparting the catalyst nucleus, it is desirable to use a noble metal ion or a noble metal colloid. Generally, palladium chloride or a palladium colloid is used. It is desirable to perform heat treatment to fix the catalyst core. Palladium is preferable as such a catalyst nucleus.
[0081]
(6) Further, electroless plating is performed on the surface of the adhesive layer 64 (for electroless plating), and an electroless plating film 67 is formed so as to follow the entire roughened surface (FIG. 5F).
At this time, the thickness of the electroless plating film 67 is preferably in the range of 0.1 to 5 μm, and more preferably 0.5 to 3 μm.
Next, a plating resist 68 is formed on the electroless plating film 67 (FIG. 6A). As the plating resist composition, a composition comprising an acrylate of a cresol novolac type epoxy resin or a phenol novolac type epoxy resin and an imidazole curing agent is particularly preferable, but a commercially available dry film can also be used.
[0082]
(7) Further, the plating resist non-formed portion on the electroless plating film 67 is electroplated to provide a conductor layer for forming the upper conductor circuit 72 and fill the opening 65 with the electroplating film 69 to fill the via hole. 70 is formed (FIG. 6B).
At this time, the thickness of the electrolytic plating film 9 exposed to the outside of the opening 5 is desirably 5 to 30 μm. Here, it is desirable to use copper plating as the electrolytic plating.
[0083]
(8) Further, after removing the plating resist 68, the electroless plating film under the plating resist is dissolved and removed with an etching solution such as a mixture of sulfuric acid and hydrogen peroxide or sodium persulfate or ammonium persulfate, and an independent upper layer is removed. The conductor circuit 72 and the filled via hole 70 are used.
[0084]
(9) Next, a roughened layer 74 is formed on the surface of the upper conductor circuit 72.
As a method for forming the roughened layer 74, there are an etching process, a polishing process, an oxidation-reduction process, and a plating process.
Among these treatments, the oxidation-reduction treatment is performed using NaOH (20 g / l), NaClO ₂ (50 g / l), and NaPO ₄ (15.0 g / l) as an oxidation bath (blackening bath), and NaOH (2.7 g). / L), NaBH ₄ (1.0 g / l) is used as the reducing bath.
Moreover, the roughening layer which consists of a copper-nickel-phosphorus alloy layer is formed by precipitation by an electroless-plating process.
[0085]
As an electroless plating solution of this alloy, copper sulfate 1 to 40 g / l, nickel sulfate 0.1 to 6.0 g / l, citric acid 10 to 20 g / l, hypophosphite 10 to 100 g / l, boron It is desirable to use a plating bath having a liquid composition comprising 10 to 40 g / l of acid and 0.01 to 10 g / l of a surfactant.
Further, the surface of the roughened layer 74 is covered with a metal or noble metal layer having an ionization tendency larger than copper and equal to or less than titanium.
In the case of tin, tin borofluoride-thiourea or tin chloride-thiourea solution is used. At this time, an Sn layer of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. In the case of a noble metal, a method such as sputtering or vapor deposition can be employed.
[0086]
(10) Next, an electroless plating adhesive layer 76 is formed on the substrate as an interlayer resin insulation layer.
(11) Further, by repeating the steps (3) to (9), another via hole 80 is provided immediately above the via hole 70, and the upper layer conductor circuit 82 and the roughened layer 84 are further outside the upper layer conductor circuit 72. (See FIG. 6C). The surface of the via hole 80 is formed as a conductor pad that functions as a solder pad.
[0087]
(12) Next, the solder resist composition 90 was applied to the outer surface of the wiring board thus obtained, and the coating film was dried. Then, a photomask film having openings drawn thereon was placed on the coating film. By performing exposure and development processing, an opening 91 exposing the solder pad (including the conductor pad and via hole) portion of the conductor layer is formed (see FIG. 7A).
Here, the diameter of the exposed opening can be made larger than the diameter of the solder pad, and the solder pad may be completely exposed. On the contrary, the opening diameter of the opening can be made smaller than the diameter of the solder pad, and the periphery of the solder pad can be covered with the solder resist layer 90. In this case, the solder pad can be suppressed by the solder resist layer 90, and peeling of the solder pad can be prevented.
[0088]
(13) Further, a metal layer made of “nickel-gold” is formed on the solder pad portion exposed from the opening 91 of the solder resist layer 90.
The nickel plating layer 92 is desirably 1 to 7 μm, and the gold plating layer is preferably 0.01 to 0.06 μm. This is because if the nickel plating layer 92 is too thick, the resistance value increases, and if it is too thin, it is easy to peel off. On the other hand, if the gold plating layer 94 is too thick, the cost increases, and if it is too thin, the adhesion effect with the solder body decreases.
[0089]
(14) Further, the solder pad portion exposed from the opening 91 (opening located above) formed in one of the solder resist layers located on the outermost side of the build-up wiring layer formed on both surfaces of the multilayer core substrate. On the gold plating layer 94, a solder body is supplied to form a solder bump 96, and an opening 91 (an opening located below) is formed on the other side of the solder resist layer located on the outermost side of the buildup wiring layer. A multilayered circuit board is manufactured by supplying a solder body also on the gold plating layer 94 of the solder pad portion exposed from () to form T pins 98 or solder balls 100 (see FIG. 7B). ).
[0090]
As a method for supplying the solder body, a solder transfer method or a printing method can be used.
Here, in the solder transfer method, a solder foil is bonded to a prepreg, and this solder foil is etched leaving only a portion corresponding to the opening portion, thereby forming a solder pattern to form a solder carrier film. In this method, the film is laminated so that the solder pattern comes into contact with the pads after the flux is applied to the solder resist opening portion of the substrate, and this is heated and transferred. On the other hand, the printing method is a method in which a printing mask (metal mask) provided with a through hole at a position corresponding to a pad is placed on a substrate, a solder paste is printed, and heat treatment is performed. As the solder, tin-silver, tin-indium, tin-zinc, tin-bismuth, or the like can be used.
[0091]
As the solder body for forming the conductive bumps 62, tin / lead solder (melting point 183 ° C.) or tin / silver solder (melting point 220 ° C.) having a relatively low melting point is used. As the solder body for connecting 66, it is preferable to use tin / antimony solder, tin / silver solder, or tin / silver / copper solder having a relatively high melting point of 230 ° C. to 270 ° C.
[0092]
【Example】
Example 1
(1) A double-sided circuit board is manufactured using a single-sided copper-clad laminate obtained by laminating an epoxy resin in a glass cloth and forming a B-stage and copper foil, followed by heat pressing. To do. The insulating substrate 10 had a thickness of 75 μm, and the copper foil 12 had a thickness of 12 μm.
A PET film 14 having a pressure-sensitive adhesive layer having a thickness of 10 μm and a thickness of 12 μm is laminated on the surface opposite to the copper foil forming surface of the laminate.
[0093]
(2) Next, a non-through hole 16 for forming a via hole reaching the copper foil 12 is formed by irradiating a pulse oscillation type carbon dioxide laser on the PET film 14 and further subjected to electrolytic copper plating using the copper foil 12 as a plating lead. Then, leaving a slight gap above the non-through hole 16, the non-through hole is filled with electrolytic copper plating 18 to form a filled via hole 20.
In this example, a high peak short pulse oscillation type carbon dioxide gas laser processing machine manufactured by Mitsubishi Electric was used to form a non-through hole for forming a via hole, and a PET film having a thickness of 22 μm as a whole was laminated on the resin surface. An opening for forming a 150 μmφ via hole was formed on a glass cloth epoxy resin substrate having a substrate thickness of 75 μm by laser beam irradiation from the PET film side by a mask image method at a speed of 100 holes / second.
[0094]
(3) Using the PET film 14 as a printing mask, the conductive paste 22 was filled into the gap left above the filled via hole 20 from the opening formed by laser irradiation.
[0095]
(4) When the PET film 14 is peeled from the surface of the insulating substrate 10, the protruding conductor 24 is formed on the surface of the insulating substrate 10 on the via hole 20 side, directly above the via hole 20. Further, an epoxy resin adhesive is applied to the entire surface on the protruding conductor side, dried at 100 ° C. for 30 minutes to form an adhesive layer 26 having a thickness of 20 μm, and then a copper foil 28 having a thickness of 12 μm is heated. Heat pressing is performed on the adhesive layer 26 under the conditions of a temperature of 180 ° C., a heating time of 70 minutes, a pressure of 2 MPa, and a degree of vacuum of 2.5 × 10 ³ Pa.
[0096]
(5) Thereafter, the copper foils 12 and 28 on both sides of the substrate were appropriately etched to form the conductor circuits 30 and 32 (including via lands), thereby producing the core double-sided circuit board 34.
[0097]
(6) Next, a single-sided circuit board for stacking is produced. Similar to the double-sided circuit board, this circuit board uses a single-sided copper-clad laminate as the substrate. The insulating substrate 10 has a thickness of 75 μm, and the copper foil 12 has a thickness of 12 μm.
A PET film 14 having a pressure-sensitive adhesive layer having a thickness of 10 μm and a thickness of 12 μm is laminated on the surface opposite to the copper foil forming surface of the laminate.
[0098]
(7) Next, the process according to the above steps (2) and (3) is performed, and the conductive paste 22 is filled into the slight gap of the filled via hole 20 to form the protruding conductor 44.
[0099]
(8) Covering the PET film 14 and pasting a 22 μm thick PET film 25 as an etching protective film, then suitable for the copper foil 12 pasted on the surface of the insulating substrate 10 opposite to the filled via hole 20 The conductor circuit 40 is formed by performing an appropriate etching process.
[0100]
(9) Thereafter, when all of the PET films 14 and 25 are peeled from the insulating base material 10, the protruding conductor 44 is formed on the surface of the insulating base material 10 on the via hole 20 side, directly above the via hole 20. Further, an epoxy resin adhesive is applied to the entire surface on the protruding conductor side and precured to form an adhesive layer 46 for multilayering. Three such single-sided circuit boards for lamination are produced.
[0101]
(10) The single-sided double-sided circuit board 34 formed by the processes (1) to (9) is used as a core, and the three-layered single-sided circuit boards 50, 52, and 54 are placed at predetermined positions on both sides. Stacked (see FIG. 3) and laminated and pressed at a temperature of 180 ° C. using a vacuum hot press, a multilayer core substrate 60 having all layers having an IVH structure was produced (see FIG. 4).
In the multilayer core substrate 60 thus manufactured, L / S = 75 μm / 75 μm, the land diameter was 250 μm, the via hole diameter was 150 μm, the conductor layer thickness was 12 μm, and the insulating layer thickness was 75 μm.
[0102]
(11) Next, a multilayer core substrate 60 (see FIG. 5 (a)) on which the conductor circuit 40 is formed on both surfaces is made of copper sulfate 8g / l, nickel sulfate 0.6g, citric acid 15g / l, hypophosphorous acid. It is immersed in an electroless plating solution having a pH of 9 consisting of 29 g / l of sodium, 31 g / l of boric acid, and 0.1 g / l of a surfactant. From the copper-nickel-phosphorus having a thickness of 3 μm on the surface of the conductor circuit 40 The resulting roughened layer 62 was formed.
Next, the substrate was washed with water, immersed in an electroless tin displacement plating bath made of 0.1 mol / l tin borofluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour, and the surface of the roughened layer 63 Was provided with a 0.3 μm tin layer (see FIG. 5B, but the tin layer is not shown).
[0103]
(12) The compositions obtained in the following (1) to (3) were mixed and stirred to prepare an electroless plating adhesive.
(1) 35 parts by weight (solid content 80%) of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500), 4 parts by weight of photosensitive monomer (Toa Gosei, Aronix M315), antifoaming 0.5 parts by weight of an agent (manufactured by San Nopco, S-65) and 3.6 parts by weight of NMP were mixed with stirring.
(2) After mixing 8 parts by weight of polyethersulfone (PES) and 7.245 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP were further mixed. Added and mixed with stirring.
(3) Imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 2 parts, Photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts, Photosensitizer (Nippon Kayaku, DETX-S) 0 2 parts by weight and 1.5 parts by weight of NMP were mixed with stirring.
[0104]
(13) The electroless plating adhesive prepared in (12) above was applied to the substrate 60 that had been treated in (11) above (see FIG. 5 (c)) and dried to form an adhesive layer. A photomask film on which a black circle of 85 μmφ was printed was adhered to both surfaces of the substrate 60 and exposed at 500 mJ / cm ² with an ultrahigh pressure mercury lamp. This was spray-developed with a DMDG (diethylene glycol dimethyl ether) solution to form an opening 65 serving as a via hole of 85 μmφ in the adhesive layer.
Further, the substrate is exposed at 3000 mJ / cm ² with an ultra-high pressure mercury lamp and subjected to heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours, so that an opening excellent in dimensional accuracy corresponding to a photomask film is obtained. An interlayer insulating material layer 64 (adhesive layer) having a thickness of 35 μm was formed (see FIG. 5D). Note that the tin plating layer was partially exposed in the opening 65 serving as a via hole.
[0105]
(14) The substrate on which the opening 65 for forming the via hole is formed is immersed in chromic acid for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer. A roughened surface 66 was formed by roughening at a depth of about 5 μm, and then immersed in a neutralized solution (manufactured by Shipley Co., Ltd.) and washed with water.
[0106]
(15) A palladium catalyst (manufactured by Atotech) is applied to the roughening layer 66 (roughening depth: 3.5 μm) on the surface of the adhesive layer, whereby a catalyst is formed on the surface of the adhesive layer 64 and the via hole forming opening 65. Added a nucleus.
[0107]
(16) The substrate is immersed in an electroless copper plating bath having the following composition, and the entire roughened surface has a thickness of 0.6.
An electroless copper plating film 67 of μm was formed (see FIG. 5F).
At this time, since the electroless plating film 67 was thin, irregularities following the roughened surface 66 of the adhesive layer 64 were observed on the film surface.
[Electroless plating aqueous solution]
NiSO ₄ : 0.003 mol / l
Tartaric acid: 0.20 mol / l
Copper sulfate: 0.03 mol / l
HCHO: 0.05 mol / l
NaOH: 0.10 mol / l
α, α′-bipyridyl: 40 mg / l
Polyethylene glycol (PEG): 0.1 g / l
[Electroless plating conditions]
Liquid temperature of 33 ° C.
(17) A commercially available photosensitive dry film is pasted on the electroless copper plating film 67 formed in (16), a mask is placed, exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate. Then, a plating resist 68 having a thickness of 15 μm was provided (see FIG. 6A).
[0109]
(18) Next, electroplating is performed on the plating resist non-forming portion under the following conditions, and an electroplating film 69 having a thickness of 20 μm is provided to provide a conductor layer on which the upper conductor circuit 72 is to be formed. The inside is filled with a plating film 69 to form a via hole 70 (FIG. 6B).
reference).
(Electrolytic plating aqueous solution)
Copper sulfate pentahydrate: 60 g / l
Leveling agent (manufactured by Atotech, HL): 40 ml / l
Sulfuric acid: 190 g / l
Brightener (Atotech, UV): 0.5 ml / l
Chlorine ion: 40ppm
[Electrolytic plating conditions]
Bubbling: 3.0 l / min Current density: 0.5 A / dm ²
Set current value: 0.18 A
Plating time: 130 minutes [0110]
(19) After stripping and removing the plating resist 68, the electroless plating film 67 under the plating resist is dissolved and removed with an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate, or ammonium persulfate. An upper conductor circuit 72 composed of the electrolytic plating film 67 and the electrolytic copper plating film 69 and having a thickness of about 20 μm and L / S = 25 μm / 25 μm was formed.
At this time, the surface of the via hole 70 was flat, and the levels of the conductor circuit surface and the via hole surface were the same.
[0111]
(20) The roughened layer 84 is formed on the substrate in the same manner as in the above (11), and the procedures of the above (12) to (19) are further repeated so that the upper interlayer resin insulating layer 76 and the conductor circuit 82 ( 1 layer including the via hole 80) was laminated to obtain a build-up wiring layer of 3 layers on one side and 6 layers on both sides (see FIG. 7A).
Here, a roughened layer 84 made of copper-nickel-phosphorus is provided on the surface of the conductor circuit 82, but a tin-substituted plating layer is not formed on the surface of the roughened layer 84.
[0112]
(21) On the other hand, 46.67 parts by weight of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of epoxy group of 60% by weight of cresol nopolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG. , 80 wt% bisphenol A type epoxy resin dissolved in methyl ethyl ketone (Epika Shell, Epicoat 1001) 14.121 parts by weight, imidazole curing agent (Shikoku Kasei 2E4MZ-CN) 1.6 parts by weight, photosensitivity 1.5 parts by weight of a polyvalent acrylic monomer (manufactured by Nippon Kayaku Co., Ltd., R604), 30 parts by weight of a polyacrylic monomer (manufactured by Kyoeisha Chemical Co., DPE6A), a leveling agent comprising an acrylic ester polymer (manufactured by Kyoeisha, Polyflow No. 75) 0.36 part by weight is mixed, and benzopheno as a photoinitiator is mixed with this mixture 20 parts by weight (manufactured by Kanto Chemical Co., Inc.), 0.2 parts by weight of EAB (manufactured by Hodogaya Chemical) as a photosensitizing ratio, and 10 parts by weight of DMDG (diethylene glycol dimethyl ether) are added. A solder resist composition adjusted to 4 ± 0.3 pa · s was obtained.
Viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type). In the case of 60 rpm, rotor No. 4 was used, and in the case of 6 rpm, rotor No. 3 was used.
[0113]
(22) The solder resist composition obtained in (21) was applied to both sides of the build-up wiring layer obtained in (20) at a thickness of 20 μm.
Next, after performing a drying treatment at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, a soda lime glass base slope having a thickness of 5 mm in which a circular pattern (mask pattern) of the solder resist opening is drawn by the chromium layer, The side on which the chromium layer was formed was brought into close contact with the solder resist layer, exposed to 1000 mJ / cm ² of ultraviolet light, and DMTG developed.
Further, heat treatment was performed at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and the pad portion opened (opening diameter 200 μm). Solder resist layer 90 (thickness 20 μm) Formed.
[0114]
(23) Next, the substrate on which the solder resist layer 90 is formed is applied to an electroless nickel plating solution having a pH of 5 and made of nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, and sodium citrate 10 g / 1. A nickel plating layer 92 having a thickness of 5 μm was formed in the opening by dipping for 5 minutes.
Further, the substrate was placed on an electroless gold plating solution composed of 2 g / 1 gold cyanide, 75 g / 1 ammonium chloride, 50 g / 1 sodium citrate, and 10 g / 1 sodium hypophosphite at 93 ° C. A 0.03 μm thick gold plating layer 94 was formed on the nickel plating layer 92 by dipping for 2 seconds.
[0115]
(24) Then, a solder paste made of tin / antimony solder having a melting point of 230 ° C. is printed on the gold plating layer 94 exposed in the opening of the solder resist layer 90 below the buildup wiring layer, and the atmosphere near the melting point By reflowing at a temperature, the T pin 98 or the solder ball 100 is fixed on the solder pad, and on the gold plating layer 94 (solder pad) exposed from the opening of the solder resist layer 90 above the buildup wiring layer, A solder paste made of tin / lead solder having a melting point of 183 ° C. was printed and reflowed at an ambient temperature in the vicinity of the melting point to form solder bumps 96 on the solder pads, thereby producing a multilayer circuit board (FIG. 7B). )reference).
[0116]
In the multilayer circuit board manufactured as described above, the land shape of the via hole of the multilayer core substrate can be made into a perfect circle, and the land pitch can be set to about 600 μm, so that the via hole can be formed densely and the density of the via hole is increased. Can be easily achieved. In addition, since the number of via holes in the core substrate can be increased, sufficient electrical connection between the conductor circuit in the multilayer core substrate and the conductor circuit in the build-up wiring layer can be ensured.
In addition, it is connected to an electronic component including a semiconductor chip such as an LSI via a solder bump 96 formed on a gold plating layer 94 (solder pad) exposed from an opening of a solder resist layer 90 provided above the buildup wiring layer. It is connected to a connection terminal on the motherboard or the like via conductive pins 98 or conductive balls 100 provided on a gold plating layer 94 (solder pad) exposed from an opening of a solder resist layer 90 provided below the buildup wiring layer. Therefore, high-density mounting of electronic components is possible.
[0117]
(Example 2)
The via hole is formed by filling the non-through hole for forming the via hole of the double-sided circuit board and the single-sided circuit board constituting the multilayer core substrate with the conductive paste, and the conductive paste is formed on the via hole by the same process as the via hole formation. A multilayer circuit board was produced in the same manner as in Example 1 except that the protrusions were formed by filling.
[0118]
(Example 3)
An interlayer resin insulation layer is formed by thermocompression-bonding an epoxy resin film having a thickness of 20 μm, an opening for forming a via hole having a diameter of 60 μm is provided by irradiating a carbon dioxide gas laser, and an interlayer resin insulation layer including an inner wall surface of the opening A multilayer circuit board was produced in the same manner as in Example 1 except that the surface of was roughened with a permanganic acid solution.
The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer.
[0119]
Example 4
Filling the non-through holes for via hole formation of the double-sided circuit board and single-sided circuit board constituting the multilayer core substrate with conductive paste to form via holes, and conductive paste on the via holes by the same process as the via hole formation A multilayer circuit board was produced in the same manner as in Example 3 except that the protrusions were formed by filling.
[0120]
(Example 5)
Instead of forming an interlayer resin insulation layer by thermocompression bonding a polyolefin resin film having a thickness of 20 μm, irradiating a carbon dioxide gas laser to provide an opening for forming a via hole having a diameter of 60 μm, and then forming an electroless plating film The same as in Example 1 except that a 0.1 μm thick Cu sputtered film or Cu—Ni sputtered film was formed on the surface of the interlayer resin insulating layer including the inner wall surface of the opening without performing the roughening treatment. Thus, a multilayer circuit board was manufactured.
[0121]
(Example 6)
Filling the non-through holes for via hole formation of the double-sided circuit board and single-sided circuit board constituting the multilayer core substrate with conductive paste to form via holes, and conductive paste on the via holes by the same process as the via hole formation A multilayer circuit board was manufactured in the same manner as in Example 5 except that the protrusions were formed by filling.
[0122]
(Comparative example)
(1) An insulating substrate made of a double-sided copper-clad laminate with a thickness of 0.8 μm is used as a core substrate. A 300 μm diameter through hole is drilled in the core substrate, and then electroless plating and electrolytic plating are performed. Then, a conductor layer including a through hole was formed, a roughening layer was provided on the entire surface of the conductor layer including the through hole, and a non-conductive filling material for filling a hole was filled in the through hole, which was then dried and cured. .
(2) Next, the filler protruding from the through hole is removed and flattened, and the surface thereof is subjected to electroless plating and electrolytic plating treatment to thicken the conductor circuit and the conductor covering the filler filled in the through hole. The part which becomes a layer was formed.
(3) An etching resist is formed on the surface of the substrate on which the conductor layer covering the conductor circuit and the filler filled in the through hole is formed, and the plating film in the portion where the etching resist is not formed is removed by etching. The etching resist was peeled off and a conductor layer covering the independent conductor circuit and the filler was formed. Furthermore, a multilayer circuit board was manufactured according to the same steps as (11) to (23) of Example 1.
[0123]
About the said Examples 1-6 and a comparative example, as a result of investigating the wiring length from IC chip to a solder bump, BGA (ball grid array) or PGA (pin grid array), and the land formation number of a core, compared with a comparative example In Examples 1 to 6, it is confirmed that the wiring length can be shortened by 10 to 25%, the number of core lands per unit area (cm ² ) can be increased by 10 to 30%, and the electrical characteristics and reliability are adversely affected. Was not.
[0124]
【The invention's effect】
As described above, according to the multilayer circuit board of the present invention, the multilayer core board is formed by laminating a large number of circuit boards having filled via holes and conductor circuits that can be finely formed by laser processing and collectively heat-pressing them. Since it is formed, the wiring in the multilayer core substrate can be densified, and electrical connection with the build-up wiring layer can be sufficiently secured through the filled via hole without providing a through-hole as in the prior art. .
[0125]
Further, since conductive bumps, conductive pins or conductive balls are disposed on the conductor layer located on the outermost side of the build-up wiring layer, the wiring layer in the build-up wiring layer has such a conductive property. It can be connected to electronic components and motherboards including semiconductor chips such as LSI via conductive bumps, conductive pins, or conductive balls with the shortest wiring length, enabling high-density wiring and high-density mounting of electronic components. Become.
[0126]
Furthermore , since the single-sided or double-sided circuit boards are formed of the same material and are laminated, cracks and peeling starting from the interface caused by thermal expansion are unlikely to occur, and therefore the reliability for the temperature cycle test is improved. In addition, when a multilayer circuit board is configured using only a single-sided circuit board, there is also an effect that warpage hardly occurs regardless of whether or not wiring is formed.
[Brief description of the drawings]
FIGS. 1A to 1F are diagrams showing a part of a manufacturing process of a double-sided circuit board constituting a multilayer core board that is a base of a multilayer circuit board according to the present invention.
FIGS. 2A to 2E are diagrams showing a part of a manufacturing process of a single-sided circuit board constituting a multilayer core board that is a base of the multilayer circuit board according to the present invention.
FIG. 3 is a diagram showing a part of a manufacturing process of a multilayer core substrate which is a base of the multilayer circuit board according to the present invention.
FIG. 4 is a view showing a multilayer core substrate which is a base of the multilayer circuit board according to the present invention.
FIGS. 5A to 5F are diagrams showing a part of a manufacturing process of a multilayer circuit board according to the present invention. FIGS.
FIGS. 6A to 6C are diagrams showing a part of a manufacturing process of a multilayer circuit board according to the present invention. FIGS.
FIGS. 7A to 7B are diagrams showing a part of a manufacturing process of a multilayer circuit board according to the present invention. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Insulating base material 12 Adhesive 14 Protective film 16 Opening for via hole formation 18 Conductive paste 20 Via hole 22 Copper foil 24 Conductor circuit 30 Double-sided circuit boards 32, 34, 36 Single-sided circuit board 40 Insulating base material 42 Copper foil 44 PET Film 46 Via hole forming opening 48 Conductive paste 49 Via hole 50 Etching protection film 52 Conductor circuit 53 Protruding conductor 54 Adhesive layer 60 Multilayer core substrate 62 Roughening layer 64 Electroless plating adhesive layer 65 Via hole forming opening 66 Rough Electrolytic plating layer 68 Electroless plating film 68 Plating resist 69 Electrolytic plating film 70 Via hole 72 Conductor circuit 74 Roughening layer 76 Electroless plating adhesive layer 80 Via hole 82 Conductor circuit 84 Roughening layer 90 Solder resist layer 92 Nickel plating layer 94 Gold Plating layer 96 Solder bump 98 T-pin 1 00 Solder ball

Claims (9)

An interlayer resin insulation layer and a conductor layer formed by a semi-additive method are alternately laminated on a multilayer core substrate having a conductor circuit in the inner layer, and a build-up wiring layer in which each conductor layer is connected by a via hole is formed. In the multilayer circuit board
The multilayer core substrate has a conductor circuit on one or both sides of an insulating hard base formed from a hard resin material that has been completely cured, and the holes reach the conductor circuit through the insulating hard base. In addition, a plurality of circuit boards having via holes filled with a conductive material are laminated via an adhesive layer, and are formed by being collectively heat-pressed ,
Each circuit board constituting the multilayer core substrate is a projection that is electrically connected to the via hole of the hole of the insulating hard base and protrudes from the hole, penetrates the adhesive layer by a hot press and is thermally deformed. A multilayer circuit board comprising a conductor . A build-up wiring layer in which an interlayer resin insulation layer and a conductor layer formed by a semi-additive method are alternately laminated on both surfaces of a multilayer core substrate having a conductor circuit in an inner layer, and each conductor layer is connected by a via hole In the multilayer circuit board formed,
The multilayer core substrate has a conductor circuit on one or both sides of an insulating hard base formed from a hard resin material that has been completely cured, and the holes reach the conductor circuit through the insulating hard base. In addition, a plurality of circuit boards having via holes filled with a conductive material are laminated via an adhesive layer, and are formed by being collectively heated and pressed,
Solder bumps are provided on the surface of the outermost conductor layer constituting one of the buildup wiring layers, and conductive pins are provided on the surface of the outermost conductor layer constituting the other of the buildup wiring layer. Or conductive balls are arranged ,
Each circuit board constituting the multilayer core substrate is a projection that is electrically connected to the via hole of the hole of the insulating hard base and protrudes from the hole, penetrates the adhesive layer by a hot press and is thermally deformed. A multilayer circuit board comprising a conductor .   The multilayer circuit board according to claim 1, wherein the conductive material is metal plating formed by electrolytic plating.   3. The multilayer circuit board according to claim 1, wherein the conductive substance is a conductive paste made of metal particles and a thermosetting resin or a thermoplastic resin.   The multilayer circuit board according to claim 1, wherein the protruding conductor is formed from a conductive paste. Some of the via hole of the buildup wiring layer, positioned immediately above the via holes formed in the multilayer core substrate, to any one of claims 1 to 5, characterized in that it is directly connected to the via hole The multilayer circuit board as described. The insulating base material of each circuit board constituting the multilayer core substrate is glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material, aramid nonwoven fabric-epoxy resin base material, aramid It forms from the hard base material in any one chosen from a nonwoven fabric-a polyimide resin base material, The multilayer circuit board in any one of Claims 1-6 characterized by the above-mentioned. The insulating base material of each circuit board constituting the multilayer core substrate is formed of a glass cloth epoxy resin base material having a thickness of 20 to 100 μm, and the filling via hole diameter is 50 to 250 μm. Item 8. The multilayer circuit board according to Item 7 . The via hole of each circuit board constituting the multilayer core substrate is made of glass cloth under the conditions of pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50. The multilayer circuit board according to claim 8 , wherein the multilayer circuit board is formed with respect to an opening formed by a carbon dioxide laser irradiated on a surface of the epoxy resin base material.

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