JP4417058B2 - Repeater device - Google Patents

Description

  The present invention relates to a repeater device that is used for wireless communication and has a function of suppressing an interference signal caused by sneaking into a receiving antenna that occurs when a received signal is retransmitted at the same frequency.

Conventionally, a repeater device (also called a relay device or a wireless relay booster) has been used to improve the radio wave conditions in buildings, tunnels, or mountainous areas where radio base station radio waves are difficult to reach.
Such a repeater device basically amplifies the radio wave received by the receiving antenna and transmits it through the transmitting antenna. Therefore, there is no need to install a dedicated line like a base station, and the cost in terms of equipment is low. There is an advantage that can be reduced.

However, since the reception signal and the transmission signal in the repeater device have the same frequency, if the transmission signal radiated from the transmission antenna wraps around the reception antenna, it becomes an interference signal with respect to the desired signal. If the repeater device has a large retransmission gain, there is a problem of causing oscillation.
In such a case, a method of reducing the amount of coupling between the antennas by physically separating the transmission antenna and the reception antenna may be considered. However, with such a method, the equipment scale of the repeater device becomes large and cannot be physically installed. In some cases, there is a problem in terms of versatility.

As another method, a predetermined delay amount corresponding to a delay of one chip or more in the CDMA signal is added to the received signal, and the signal with the delay is output as a transmission signal. A correlation operation between the received signal and the transmitted signal is performed to detect the residual component of the interference signal. Based on the detected residual component, the interference signal is generated to have the opposite phase, the same amplitude, and the same delay. A technique is known in which an interference signal generated when a transmission signal wraps around a reception antenna is canceled by a suppression signal (see, for example, Patent Document 1).
According to this method, the residual component of the interference signal is detected by performing a correlation operation between the received signal added with the retransmitted signal as an interference signal and the transmission signal, and the retransmission is performed when the residual component is detected. Since a delay of one chip or more in the CDMA signal is added to the transmission signal to be transmitted, the correlation between the signal other than the correlation between the transmission signal serving as the reference signal and the residual component of the interference signal is lowered, and the residual component is accurately detected. There is an advantage that it can be detected well.
Japanese Patent Laid-Open No. 2001-196994 (page 2-5, FIG. 3)

  However, a roundabout interference signal between antennas may be propagated through a plurality of paths from one transmitting antenna to a receiving antenna due to the influence of the environment around the apparatus. In particular, when a structure such as a new building appears in the area covered by the repeater device, the arrival state of interference signals arriving at the receiving antenna changes due to the influence of such a structure. Cannot recognize such a change in the arrival state of the interference signal, and depending on the situation, the oscillation of the repeater device may become a problem due to the influence of the interference signal.

  Therefore, the present invention has been made in view of the above problems, and a repeater that can maintain a stable retransmission gain without degrading the interference suppression amount even when the arrival state of an interference signal changes. An object is to provide an apparatus.

In order to solve the above problems, the present invention proposes the following means.
The invention according to claim 1 monitors at least one interference signal suppression circuit that suppresses an interference signal that is generated when a transmission signal is reflected by a nearby structure and wraps around the reception antenna, and a new interference signal is generated. When the new interference signal is generated, a propagation delay time of the new interference signal is detected, and a monitoring control circuit for assigning the interference signal suppression circuit, and a signal received from the receiving antenna is converted into a digital signal A / D converter, delay amount adding means for adding a predetermined delay amount to the signal outputted from the A / D converter, and D / D for converting the signal outputted from the delay amount adding means into an analog signal An A converter and transmission means for outputting a signal output from the D / A converter as a transmission signal, and the interference signal suppression circuit is a single unit that is the reciprocal of the sampling frequency of the A / D converter. A delay time setting means for setting a delay time corresponding to an integral multiple of the time, and performing a correlation operation between the output signal of the A / D converter and the output signal of the delay amount adding means with the set delay time. , At least one interference signal detecting means for detecting an interference signal, and at least one for generating a suppression signal having the same amplitude, the same delay and an opposite phase as the interference signal from the interference signal detected by the interference signal detecting means Suppression signal generating means; suppression signal combining means for combining the suppression signals generated in the suppression signal generating means; and signal combining means for combining the signal generated in the suppression combining means and the received signal. The monitoring control circuit sweeps a delay time range that requires monitoring every delay time corresponding to an integral multiple of a unit time that is the reciprocal of the sampling frequency of the A / D converter. A correlation operation between the output signal of the A / D converter and the output signal of the delay amount adding means is performed to detect an interference signal, and the delay time detected for each interference signal is set to the delay time setting means of each interference signal suppression circuit. Signal intensity storage means for storing the intensity of the interference signal allocated to the interference signal suppression circuit, and the interference signal generated in all the interference signal suppression circuits. Is assigned, a new interference signal is detected, and the intensity of the newly detected interference signal is compared with the lowest signal intensity stored in the signal intensity storage means. A signal intensity comparing means for performing the assignment, and when the intensity of the newly detected interference signal is larger than the intensity of the interference signal having the smallest intensity, the interference signal having the smallest intensity is assigned. The present invention proposes a repeater that assigns the interference signal suppression circuit that is used to the newly detected interference signal .

  According to the present invention, the supervisory control circuit monitors the arrival of an interference signal, and when a new interference signal arrives due to changes in the surrounding environment, the delay time of the new interference signal is set and The interference signal suppression circuit is assigned. Therefore, even if the arrival state of the interference signal changes, the interference suppression amount does not deteriorate.

According to the present invention, the interference signal detection means of the interference signal suppression circuit constituting the repeater device is inputted with the digital signal to which the predetermined delay amount is added and the digitized reception signal, and the correlation operation is performed. An interference signal is generated. Each of the generated interference signals is input to a suppression signal generation unit, and a suppression signal having the same amplitude and antiphase as the interference signal is generated. The generated suppression signal is combined by the suppression signal combining unit and then combined with the digitized reception signal by the signal combining unit.
Further, the supervisory control circuit performs a correlation operation between the output signal of the A / D converter and the output signal of the delay amount adding means for each unit time which is the reciprocal of the sampling frequency of the A / D converter, and outputs the interference signal When detecting and detecting an interference signal, each detected interference signal is assigned to each interference signal suppression circuit by assigning the detected delay time to the delay time setting means of the interference signal suppression circuit for each detected interference signal. Correspond to.

According to the present invention, when all the interference signal suppression circuits in the repeater device are assigned to the incoming interference signal, the supervisory control circuit newly detects the arrival of the new interference signal. The level of the interference signal is compared with the level of the interference signal having the lowest level among the already assigned interference signals.
As a result, when the level of the newly detected interference signal is higher than the level of the already assigned interference signal, the interference signal suppression circuit to which the lowest level interference signal is assigned is changed to a new interference signal. Therefore, even when a new interference signal arrives, the suppression amount of the entire interference signal is not deteriorated.

According to the present invention, it is possible to maintain a stable retransmission gain without degrading the suppression amount of the interference signal even when the arrival state of the interference signal changes due to the environment near the repeater device changing. Even if the environment around the repeater device changes, the original service area can be maintained even if the arrival state (propagation environment) of the interference signal changes.
In addition, since the interference signal suppression circuit and the monitoring control circuit in the repeater device are configured by digital processing, the same function can be realized at a lower cost compared to processing a high-frequency signal by an analog circuit. There is.

  Hereinafter, a repeater apparatus according to an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows an outline of a communication system including a repeater device according to the present invention. This communication system includes a base station 1, a repeater device 2, and a terminal 4, and 3a and 3b indicate buildings.
The environment where the repeater device is installed is a place where a propagation environment is not preferable, such as buildings lined up around. The repeater device amplifies it at the same frequency as the received radio wave, and then radiates it through the transmission antenna.

  However, not all of the radio waves transmitted from the transmission antenna reach the terminal 4, and a part of the transmission signal arrives directly at the reception antenna from the transmission antenna, and part of the building 3a, 3b Then, the signal arrives at the receiving antenna, and these signals become interference signals. Further, these signals have the property that the arrival time at the receiving antenna differs depending on the propagation path. Therefore, when a new structure appears around the repeater device, the situation of the incoming interference signal also changes (see FIG. 4).

FIG. 2 shows an example of the arrival status of such an interference signal. The horizontal axis of FIG. 2 shows the delay time from the reference time of the incoming interference signal, and the vertical axis shows the intensity of the interference signal. The axis scale indicates the unit time width that is the reciprocal of the sampling frequency of the digital signal processing unit.
In this figure, three interference signals have arrived corresponding to the propagation paths (1), (2) or (3) in FIG. 1, and the delay times are τ1, τ2, and τ3, respectively.
These interference signals are observed as signals having a certain width. The dotted line in FIG. 2 is an analog representation of the incoming interference signal.

In general, when signals processed by a repeater device are processed in an analog manner, the delay time and level of these interference signals are detected, and signals having the same phase and the same amplitude as those of the above interference signals are used as interference signals. If they are added together with the same delay, the interference signal can be canceled.
However, if the signal processing is to be performed digitally, the delay time is determined by the unit time width that is the reciprocal of the sampling frequency of the digital signal processing unit, so that it is possible to accurately reproduce the delay time of the interference signal without error. It is extremely difficult.
Therefore, the interference signal suppression circuit in the repeater apparatus according to the present invention is characterized by using suppression signals having two or more different delay amounts in order to reduce one interference signal.

That is, in the example of FIG. 2, two suppression signals having timings t11 and t12 are used to reduce the interference signal having the delay time τ1.
Specifically, as shown in FIG. 3, an interference signal is detected for each unit time width that is the reciprocal of the sampling frequency of the digital signal processing unit, and interference suppression with the same delay, same amplitude, and opposite phase as the detected interference signal. Interference signals are suppressed by generating signals and combining them.

Next, the configuration and operation of the repeater device according to the embodiment of the present invention will be described.
As shown in FIG. 5, the repeater apparatus includes a base station antenna 11, an antenna duplexer 12, a mobile station antenna 13, low-noise amplifiers 14a and 14b for uplink and downlink, and a frequency converter. 15a, 15b, 15c, 15d, interference suppression devices 16a, 16b, and high-power amplifiers 17a, 17b.

  The base station antenna 11 is an antenna for transmitting / receiving radio waves to / from the base station, and the mobile station antenna 13 is an antenna for transmitting / receiving radio waves to / from the mobile station. The antenna duplexer 12 is a device for supplying the radio wave received from the base station to the downlink and supplying the signal from the uplink transmitted to the base station to the antenna 11 for the base station. A device 12 is also provided in the antenna 13 for mobile stations.

The low noise amplifiers 14a and 14b are low noise amplifiers that amplify weak radio waves received via the base station antenna 11 or the mobile station antenna 13. The frequency converters 15a, 15b, 15c, and 15d perform frequency conversion and orthogonal conversion on the received RF signals to generate IQ (In-Phase Quadrature Phase) baseband signals.
In addition, the reverse process is performed, and the IQ baseband signal is orthogonally modulated, frequency-converted, and converted into an RF signal. The high-power amplifiers 17a and 17b are high-amplification amplifiers that amplify radio waves to be transmitted.

Further, as shown in FIG. 6, the interference signal suppressing apparatus in the repeater apparatus according to the embodiment of the present invention includes an A / D converter 21, a chip delay unit 22, a D / A converter 23, and an adder. 24, phase amplitude controllers 25a, 25b, and 25c that form an interference signal suppression circuit, correlation integrators 26a, 26b, and 26c, delay units 27a, 27b, and 27c, and a monitoring control circuit 28.
Each of the phase amplitude controllers 25a, 25b, 25c, the correlation integrators 26a, 26b, 26c and the delay units 27a, 27b, 27c forms a set to form an interference signal suppression circuit for one interference signal. is doing.

The A / D converter 21 is a converter that converts an analog signal into a digital signal at a predetermined sampling frequency. In the present embodiment, the A / D converter 21 converts a signal received by a receiving antenna (not shown) into a digital signal and proceeds to the next stage. Supply.
The D / A converter 23 is a converter having an operation opposite to that of the A / D converter 21 and converts a digital signal into an analog signal. In the present embodiment, a signal obtained by adding a predetermined delay amount to a digitized reception signal is converted into an analog signal, which is output as a transmission signal from a transmission antenna (not shown).

The chip delay unit 22 adds a delay of one chip or more of a CDMA (CDMA: Code Division Multiple Access) signal at the time of retransmission in order to reduce the correlation between a desired received signal and an interference signal that passes between the transmitting antenna and the receiving antenna. This is a delay circuit.
The correlation integrators 26a, 26b, and 26c are arithmetic circuits for detecting the amplitude and phase of the interference signal from the combined signal of the desired wave and the interference signal using the signal that has passed through the chip delay unit 22 as a reference signal. However, in order for the calculation to function effectively, it is necessary to know the delay of the interference signal in advance, so that each of the correlation integrators 26a, 26b, 26c and the phase amplitude controllers 25a, 25b, 25c corresponds. Delay devices 27a, 27b, and 27c are provided, and signals to which a delay corresponding to the delay of the interference signal is given by the delay devices 27a, 27b, and 27c are input.

The phase / amplitude controllers 25a, 25b, and 25c are circuits for generating a suppression signal having the same amplitude as that of the interference signal and an opposite phase to the reference signal, and the control signal for generating the suppression signal is correlated. It is generated from the integrators 26a, 26b, and 26c.
The adder 24 is a circuit that adds the interference suppression signals generated in the phase amplitude controllers 25a, 25b, and 25c to the desired wave that includes the interference signal.

  The monitoring control circuit 28 includes a correlation integrator 31, a CPU 32, and a delay unit 33. The function of the correlation integrator 31 is the same as that of the correlation integrators 26a, 26b, and 26c described above.

The delay unit 33, the correlation integrator 31, and the phase / amplitude controllers 25a, 25b, and 25c operate in synchronization with a clock signal supplied from a clock generator (not shown). The clock signal is converted into an A / D converter. When it is input to 21, it functions as a sampling clock. This clock signal is also supplied to the CPU 32. Further, the delay unit 33 sets a delay amount corresponding to the clock signal to the input reception signal subjected to the chip delay process, and supplies it to the correlation integrator 31.
The correlation integrator 31 detects the amplitude and phase of the interference signal from the combined signal of the desired wave and the interference signal, using the signal input from the delay unit 33 as a reference. The detected amplitude and phase information of the interference signal is output to the control unit 32, and the CPU 33 associates the delay amount with the amplitude and phase information of the interference signal, and sets the delay amount of the detected interference signal to each of the delay devices 27a, 27b, By setting to 27c, each interference signal is associated with one interference signal suppression circuit.

Next, the operation of the repeater apparatus according to the embodiment of the present invention, mainly the monitoring control circuit, will be described with reference to FIGS.
As shown in FIG. 6, the repeater apparatus of the present invention monitors the generation of a new interference signal by the monitoring control circuit 28, assigns an interference signal suppression circuit to the new interference signal, and suppresses the interference signal. Is to do. A specific procedure will be described below with reference to FIGS.
As shown in FIG. 7, the CPU 32 in the monitoring control circuit 28 first sets a delay time range (step 101), then sets an initial delay time (step 102), which is set in the monitoring control circuit 28. (Step 103). The delay unit 33 set with the delay time outputs a received signal corresponding to the set delay time from the digitized received signal output from the chip delay unit 22 to the correlation integrator 31 in the monitoring control circuit 28. .

The correlation integrator 31 receives the output signal from the adder 24 and the output signal from the delay unit 33 in the monitoring control circuit 28, performs a correlation operation, and detects an interference signal (step 104).
The correlation calculation result is read by the CPU 32 and recorded in a memory (not shown) in the CPU 32 (step 105).
When the CPU 32 finishes the correlation calculation process for the initial delay time, it adds a unit time corresponding to the reciprocal of the sampling frequency to the initial delay time, sets the next delay time (step 106), and sets the delay time in advance. It is determined whether it is within the set range (step 107).

As a result of the determination, if the newly set delay time is within the setting range, this delay time is set in the delay device 33 in the monitoring control circuit 28 (step 103). On the other hand, if the newly set delay time is outside the set range, the correlation calculation process is stopped.
Next, as shown in FIG. 8, when the CPU 32 in the monitoring control circuit 28 stops the correlation calculation process, the CPU 32 detects the intensity of the interference signal from the correlation calculation result recorded in the memory in the CPU 32. Specifically, n = 1 is set as an initial value (step 201), and the maximum one of interference signal strengths stored in the memory is searched (step 202).
Next, the retrieved delay time of the interference signal is read (step 203), and this delay time is set in the delay devices 27a, 27b, and 27c in one interference signal suppression circuit among the plurality of interference signal suppression circuits ( Step 204).

When the above setting is completed, the CPU 32 in the monitoring control circuit 28 adds 1 to the previous n (step 205), and determines whether there is an unused interference signal suppression circuit (step 206).
As a result of the determination, when it is determined that there is an unused interference signal suppression circuit, an interference signal having the next highest intensity is detected from the correlation calculation result recorded in the memory. Such processing is continued until there is no unused interference signal suppression circuit.
When the delay time is set for all the interference signal suppression circuits, the CPU 32 in the monitoring control circuit 28 activates all the interference signal suppression circuits and shifts to the state monitoring mode (step 207).

  Further, as shown in FIG. 9, when the state monitoring mode is entered, the CPU 32 in the monitoring control circuit 28 sets a delay time range again (step 208), and then sets an initial delay time (step 209). This is set in the delay unit 33 in the monitoring control circuit 28 (step 210). The delay unit 33 set with the delay time outputs a reception signal corresponding to the delay time set from the digitized reception signal output from the chip delay unit 22 to the correlation integrator 31 in the monitoring control circuit 28. .

The correlation integrator 31 receives the output signal from the adder 24 and the output signal from the delay unit 33 in the monitoring control circuit 28, performs correlation calculation, and detects an interference signal (step 211).
The correlation calculation result is read by the CPU 32 and recorded in a memory (not shown) in the CPU 32 (step 212). Subsequently, it is determined whether or not the read correlation value (interference signal intensity) is equal to or greater than a predetermined threshold (step 213).

  As a result of the determination, if the read correlation value (interference signal strength) is equal to or greater than a predetermined threshold, it is determined whether there is an unused interference signal suppression circuit in the interference signal suppression device, as shown in FIG. If there is an unused interference signal suppression circuit that is searched, delay times are set in the delay devices 27a, 27b, and 27c in the interference signal suppression circuit (step 217), and the suppression operation is started (step 218). . Thereafter, the process returns to step 208 to continue the state monitoring.

  As a result of the determination, if the read correlation value (interference signal intensity) is less than or equal to a predetermined threshold, one step is added to the delay time (step 214), and whether or not the delay time is within the set range. Is determined (step 215). As a result, when it is determined that it is within the set range, the process returns to step 210, and when it is determined that it is not within the set range, the process returns to step 209 to continue the processing.

  On the other hand, if there is no unused interference signal suppression circuit, the minimum correlation value (interference signal strength) set in the active interference signal suppression circuit and the correlation detected in the current state monitoring The value (interference signal intensity) is compared (step 219). As a result, if the value detected this time is larger, the delay time detected this time is set in the delay unit of the interference signal suppression circuit assigned to the minimum correlation value (step 220), and the suppression operation is started (step 220). Step 221). Thereafter, the process returns to step 208 to continue the state monitoring.

  Note that the above processing procedure is for assigning interference signal suppression circuits in descending order of correlation values (interference signal strength) detected by the monitoring control circuit. A method of assigning an interference signal suppression circuit for those exceeding this threshold may be used.

For example, when the correlation calculation within the set delay time range is completed in steps 101 to 107, the correlation calculation result recorded in the memory in the CPU 32 is compared with the threshold value, and the allocation to the interference signal suppressing device is performed. decide.
Specifically, n = 1 and m = 1 are set as initial values (step 222), the first correlation value (intensity of interference signal) is read from the memory (step 223), and this is compared with a threshold value. (Step 225).
As a result of the comparison, when the read correlation value (interference signal strength) is smaller than the threshold value, 1 is added to n and the second correlation value (interference signal strength) is read from the memory (step 224). .

On the other hand, when the read correlation value (interference signal intensity) exceeds the threshold value, the delay time is set in the delay devices 27a, 27b, 27c in the first interference signal suppression circuit (step 226). When the delay time setting process is completed, 1 is added to each of n and m to determine whether there is an unused interference signal suppression circuit. If there is an unused interference signal suppression circuit, step 223 is performed. Returning to FIG. 5, the second correlation value (interference signal intensity) is read from the memory, and the same processing is executed.
On the other hand, when there is no unused interference signal suppression circuit, all the interference signal suppression circuits are activated, and the process proceeds to the state monitoring mode and moves to the process of step 208 (step 229).

As described above, in this embodiment, even when the communication environment changes and a new interference signal is generated due to the operation of the monitoring control circuit, a stable retransmission gain is maintained without degrading the suppression amount of the interference signal. can do.
In this embodiment, since interference signal suppression is performed digitally, a plurality of interference signal suppression circuits and a monitoring control circuit can be mounted on one DSP or FPGA, thereby reducing the cost of the entire apparatus. be able to.

It is the figure which showed the outline | summary of the communication system containing a repeater apparatus. It is the conceptual diagram which showed the arrival time of the interference signal. It is the conceptual diagram which showed the suppression method of an interference signal. It is the figure which showed generation | occurrence | production of the new interference signal by an environmental change. It is a block diagram of a repeater apparatus. It is a block diagram of an interference suppression apparatus. It is a processing flow figure of a present Example. It is a processing flow figure of a present Example. It is a processing flow figure of a present Example. It is a processing flow figure of a present Example. It is a processing flow figure of a present Example. It is the figure which showed the suppression procedure of an interference signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Base station, 2 ... Repeater apparatus, 3a, 3b ... Building, 4 ... Terminal, 11 ... Antenna for base stations, 12 ... Antenna duplexer, 13 ... Antennas for mobile stations, 14a, 14b ... low noise amplifiers, 15a, 15b, 15c, 15d ... frequency converters, 16a, 16b ... interference suppression devices, 17a, 17b ... high output amplifiers, 21 ... A / D converter, 22 ... Chip delay, 23 ... D / A converter, 24 ... Adder, 25a, 25b, 25c ... Phase amplitude controller, 26a, 26b , 26c, 31 ... correlation integrator, 27a, 27b, 27c, 33 ... delay unit, 28 ... supervisory control circuit, 32 ... CPU,

Claims (1)

At least one interference signal suppression circuit that suppresses an interference signal generated when a transmission signal is reflected by a nearby structure and wraps around a reception antenna;
A monitoring control circuit that monitors the generation of a new interference signal, detects the propagation delay time of the new interference signal when the new interference signal occurs, and assigns the interference signal suppression circuit ;
An A / D converter that converts a signal received from the receiving antenna into a digital signal;
Delay amount adding means for adding a predetermined delay amount to the signal output from the A / D converter;
A D / A converter for converting the signal output from the delay amount adding means into an analog signal;
Transmission means for outputting a signal output from the D / A converter as a transmission signal;
A delay time setting means for setting the delay time corresponding to an integral multiple of a unit time that is a reciprocal of the sampling frequency of the A / D converter;
At least one interference signal detecting means for detecting an interference signal by performing a correlation operation between the output signal of the A / D converter and the output signal of the delay amount adding means with the set delay time;
At least one suppression signal generation means for generating a suppression signal having the same amplitude and delay as the interference signal and having an opposite phase from the interference signal detected by the interference signal detection means;
Suppression signal synthesis means for synthesizing the suppression signal generated by the suppression signal generation means;
Signal combining means for combining the signal generated in the suppression combining means and the received signal;
The supervisory control circuit sweeps a delay time range that requires monitoring every delay time corresponding to an integral multiple of a unit time that is the reciprocal of the sampling frequency of the A / D converter. Correlation between the output signal and the output signal of the delay amount adding means is performed to detect an interference signal, and the delay time detected for each interference signal is assigned to the delay time setting means of each interference signal suppression circuit. And
The monitoring control circuit stores signal strength storage means for storing the strength of the interference signal assigned to the interference signal suppression circuit;
When interference signals generated in all the interference signal suppression circuits are assigned, a new interference signal is detected and stored in the signal strength storage means and the newly detected interference signal strength. Signal strength comparison means for comparing the lowest signal strength of the signal strength,
When the intensity of the newly detected interference signal is greater than the intensity of the interference signal having the smallest intensity, the interference signal suppression circuit to which the interference signal having the smallest intensity is assigned is newly detected. A repeater device that is assigned to an interference signal.

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