JP4031408B2 - Mosトランジスタの製造方法 - Google Patents
Mosトランジスタの製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000012535 impurity Substances 0.000 claims description 86
- 150000002500 ions Chemical class 0.000 claims description 79
- 239000004065 semiconductor Substances 0.000 claims description 76
- 239000000758 substrate Substances 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 62
- 238000005468 ion implantation Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 2
- 230000007547 defect Effects 0.000 description 14
- -1 boron ions Chemical class 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
IBM J.RES. DEVELOP., v.36、p170,1992 J.Y.Cheng et.al.,「"Formation of extended defects in silicon by high energy implantation of B and P"」J.Appl.Phys.,v80(4)p.2105,1996 S.NhSU,et.al.,「"Annealing behaviors of dislocation loops near the prejected range in high−dose As implanted(001)Si"」J.Appl.Phys.v.86(9),p.4503,1990
2.ゲートパターンを形成し、熱処理工程を実施してゲートパターンの形成時に、損傷した半導体基板を治癒することができる。
3.ソース/ドレイン不純物イオンを注入した後に、急速熱処理を実施してソース/ドレイン領域の拡張された欠陷を治癒して半導体装置の信頼度を増加させることができる。
32 素子分離膜
34 犠牲酸化膜
36 Nウェル領域
38 第2チャンネル領域
40 Pウェル領域
42 第1チャンネル領域
43 ゲート酸化膜
50a 第1ゲートパターン
50b 第2ゲートパターン
56 ソース/ドレイン領域
a NMOSトランジスタ領域
b PMOSトランジスタ領域
Claims (16)
- 半導体基板の所定の領域に素子分離膜を形成して活性領域を限定する段階と、
前記活性領域を有する半導体基板にウェル不純物イオンを注入する段階と、
前記活性領域の表面にチャネル不純物イオンを注入する段階と、
前記ウェル不純物イオン及び前記チャネル不純物イオンを急速熱処理工程を使用して拡散させて前記ウェル不純物イオンでドーピングされたウェル領域、及び前記チャネル不純物イオンでドーピングされたチャネル領域を形成する段階と、
前記ウェル領域及び前記チャネル領域を有する半導体基板上に導電膜を形成する段階と、
前記導電膜をパターニングして前記活性領域の上部を横切るゲートパターンを形成する段階と、
前記ゲートパターンを含む半導体基板を熱処理して、前記導電膜をパターニングする間に前記半導体基板に与えられたエッチング損傷を治癒する段階と、
前記ゲートパターンをイオン注入マスクとして使用して前記活性領域にソース/ドレイン不純物イオンを注入する段階と、
前記ソース/ドレイン不純物イオンを拡散させてソース/ドレイン領域を形成する段階と、
を含み、
前記ゲートパターンを含む半導体基板を熱処理する段階は、
前記活性領域にソース/ドレイン不純物イオンを注入する段階の前に実施され、
酸素雰囲気の反応炉で、前記ゲートパターンを含む前記半導体基板を熱酸化する段階と、
熱酸化された前記半導体基板を急速熱処理する段階と、
を具備することを特徴とするMOSトランジスタの製造方法。 - 前記チャンネル不純物イオンを注入する段階は前記ウェル不純物イオンを注入する段階の前に実施することを特徴とする請求項1に記載のMOSトランジスタの製造方法。
- 前記急速熱処理工程は950〜1050℃で50秒以内に進行することを特徴とする請求項1に記載のMOSトランジスタの製造方法。
- 前記ゲートパターンを含む前記半導体基板を熱酸化する段階は800〜900℃で10〜20分間進行することを特徴とする請求項1に記載のMOSトランジスタ製造方法。
- 熱酸化された前記半導体基板を急速熱処理する段階は950〜1050℃で20秒以内に進行することを特徴とする請求項1に記載のMOSトランジスタの製造方法。
- 前記ソース/ドレイン不純物イオンを拡散させる段階は1000〜1050℃で20秒以内に急速熱処理して進行することを特徴とする請求項1に記載のMOSトランジスタの製造方法。
- 前記ゲートパターンを含む半導体基板を熱処理する段階と、前記活性領域にソース/ドレイン不純物イオンを注入する段階との間に、
前記ゲートパターンをイオン注入マスクとして使用して前記活性領域に不純物イオンを注入してLDD領域を形成する段階と、
前記ゲートパターンを覆う絶縁膜をコンフォマルに蒸着する段階と、
前記絶縁膜をエッチバックして前記ゲートパターンの側壁を覆うスペーサを形成する段階と、
前記スペーサを含む半導体基板を熱酸化して、前記絶縁膜をエッチバックする間に前記半導体基板に与えられたエッチング損傷を治癒する段階と、
を具備することを特徴とする請求項1に記載のMOSトランジスタの製造方法。 - 前記スペーサを含む半導体基板を熱酸化する段階は800〜900℃で10〜20分間進行することを特徴とする請求項7に記載のMOSトランジスタの製造方法。
- NMOSトランジスタ領域及びPMOSトランジスタ領域を有する半導体基板を準備する段階と、
前記半導体基板の所定の領域に素子分離膜を形成して前記NMOSトランジスタ領域及び前記PMOSトランジスタ領域内に各々第1及び第2活性領域を限定する段階と、
前記NMOSトランジスタ領域内の半導体基板及び前記PMOSトランジスタ領域内の半導体基板に各々Pウェル不純物イオン及びNウェル不純物イオンを注入する段階と、
前記第1活性領域の表面及び前記第2活性領域の表面に各々第1及び第2チャネル不純物イオンを注入する段階と、
前記ウェル不純物イオン及び前記チャネル不純物イオンを急速熱処理工程を使用して拡散させて、前記NMOSトランジスタ領域及び前記PMOSトランジスタ領域に各々Pウェル領域及びNウェル領域を形成すると同時に、前記第1及び第2活性領域の表面に各々第1及び第2チャネル領域を形成する段階と、
前記ウェル領域及び前記チャネル領域を有する半導体基板上に導電膜を形成する段階と、
前記導電膜をパターニングして前記第1活性領域の上部を横切る第1ゲートパターン及び前記第2活性領域の上部を横切る第2ゲートパターンを形成する段階と、
前記第1及び第2ゲートパターンを含む半導体基板を熱処理して、前記導電膜をパターニングする間に前記半導体基板に与えられたエッチング損傷を治癒する段階と、
前記第1ゲートパターンをイオン注入マスクとして使用して前記第1活性領域にN型不純物イオンを注入する段階と、
前記N型不純物イオンを拡散させてN型ソース/ドレイン領域を形成する段階と、
前記第2ゲートパターンをイオン注入マスクとして使用して前記第2活性領域にP型不純物イオンを注入する段階と、
前記P型不純物イオンを拡散させてP型ソース/ドレイン領域を形成する段階と、
を含み、
前記第1及び第2ゲートパターンを含む半導体基板を熱処理する段階は、
前記第1活性領域にN型不純物イオンを注入する段階及び前記第2活性領域にP型不純物イオンを注入する段階の前に実施され、
酸素雰囲気の反応炉で、前記第1及び第2ゲートパターンを含む前記半導体基板を熱酸化する段階と、
熱酸化された前記半導体基板を急速熱処理する段階と、
を具備することを特徴とするMOSトランジスタの製造方法。 - 前記第1及び第2チャンネル不純物イオンを注入する段階は前記Pウェル及びNウェル不純物イオンを注入する段階の前に実施することを特徴とする請求項9に記載のMOSトランジスタの製造方法。
- 前記急速熱処理工程は950〜1050℃で50秒以内に進行することを特徴とする請求項9に記載のMOSトランジスタの製造方法。
- 前記第1及び第2ゲートパターンを含む前記半導体基板を熱酸化する段階は800〜900℃で10〜20分間進行することを特徴とする請求項9に記載のMOSトランジスタの製造方法。
- 熱酸化された前記半導体基板を急速熱処理する段階は950〜1050℃で20秒以内に進行することを特徴とする請求項9に記載のMOSトランジスタの製造方法。
- 前記N型不純物イオンを拡散させる段階は1000〜1050℃で20秒以内に急速熱処理して進行することを特徴とする請求項9に記載のMOSトランジスタの製造方法。
- 前記第1及び第2ゲートパターンを含む半導体基板を熱処理する段階と、前記第1活性領域にN型不純物イオンを注入する段階及び前記第2活性領域にP型不純物イオンを注入する段階との間に、
前記第1ゲートパターンをイオン注入マスクとして使用して前記第1活性領域にN型不純物イオンを注入してLDD領域を形成する段階と、
前記第1及び第2ゲートパターンを覆う絶縁膜をコンフォマルに蒸着する段階と、
前記絶縁膜をエッチバックして前記第1及び第2ゲートパターンの側壁を覆うスペーサを形成する段階と、
前記スペーサを含む半導体基板を熱酸化して、前記絶縁膜をエッチバックする間に前記半導体基板に与えられたエッチング損傷を治癒する段階と、
を具備することを特徴とする請求項9に記載のMOSトランジスタの製造方法。 - 前記スペーサを含む半導体基板を熱酸化する段階は800〜900℃で10〜20分間進行することを特徴とする請求項15に記載のMOSトランジスタの製造方法。
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US7259072B2 (en) * | 2004-04-21 | 2007-08-21 | Chartered Semiconductor Manufacturing Ltd. | Shallow low energy ion implantation into pad oxide for improving threshold voltage stability |
CN102446762B (zh) * | 2010-10-13 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其制作方法 |
CN102479677A (zh) * | 2010-11-29 | 2012-05-30 | 无锡华润上华半导体有限公司 | 半导体器件及其制造方法 |
CN103730344B (zh) * | 2012-10-12 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | 形成金属硅化钨栅极的氧化硅侧墙的方法 |
CN112786693A (zh) * | 2021-01-22 | 2021-05-11 | 上海华虹宏力半导体制造有限公司 | 半导体器件的制备方法 |
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US4027380A (en) * | 1974-06-03 | 1977-06-07 | Fairchild Camera And Instrument Corporation | Complementary insulated gate field effect transistor structure and process for fabricating the structure |
US5141882A (en) * | 1989-04-05 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor |
JP3002371B2 (ja) * | 1993-11-22 | 2000-01-24 | 富士通株式会社 | 半導体装置とその製造方法 |
US5960319A (en) * | 1995-10-04 | 1999-09-28 | Sharp Kabushiki Kaisha | Fabrication method for a semiconductor device |
KR100231594B1 (ko) * | 1995-12-29 | 1999-11-15 | 김주용 | 반도체 소자의 웰 형성방법 |
JPH09252056A (ja) * | 1996-03-14 | 1997-09-22 | Ricoh Co Ltd | 半導体装置の製造方法 |
KR100283712B1 (ko) * | 1996-06-24 | 2001-04-02 | 모리시타 요이찌 | 반도체 장치의 제조 방법 |
JP3354535B2 (ja) * | 1996-06-24 | 2002-12-09 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6051471A (en) * | 1996-09-03 | 2000-04-18 | Advanced Micro Devices, Inc. | Method for making asymmetrical N-channel and symmetrical P-channel devices |
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
JPH11195786A (ja) * | 1998-01-05 | 1999-07-21 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
KR100257999B1 (ko) * | 1998-04-14 | 2000-06-01 | 김규현 | 반도체 소자내의 웰 형성방법 |
JP2000031265A (ja) * | 1998-07-14 | 2000-01-28 | Nec Corp | 半導体装置の製造方法 |
JP2000150882A (ja) * | 1998-09-04 | 2000-05-30 | Toshiba Corp | Mis型半導体装置及びその製造方法 |
US6162694A (en) * | 1998-11-25 | 2000-12-19 | Advanced Micro Devices, Inc. | Method of forming a metal gate electrode using replaced polysilicon structure |
JP2000243958A (ja) * | 1999-02-24 | 2000-09-08 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2002009173A (ja) * | 2000-06-26 | 2002-01-11 | Toshiba Corp | 半導体装置の製造方法 |
US6586296B1 (en) * | 2001-04-30 | 2003-07-01 | Cypress Semiconductor Corp. | Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks |
US6680230B2 (en) * | 2001-07-25 | 2004-01-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
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