JP4080550B2 - Connection test method - Google Patents

Description

The present invention relates to a method for testing a signal path in a circuit, the method comprising the step of supplying a test signal to a terminal of said signal path. The invention also relates to a testable circuit and an integrated circuit for implementing the method.
In-circuit technology is widely used to test signal paths connected to ICs of integrated circuit (IC) assemblies such as printed circuit boards and multichip modules. Due to the trend toward smaller electronic components, this approach is becoming difficult. The preferred approach is to use a specific IC with dedicated test hardware to test the signal path in test mode. A particularly useful example of such an approach for a digital signal path with connections between the digital portions of the IC is IEEE Std. Boundary scanning approach as defined by 1149.1. In the boundary scan approach, the first IC pin at one end of such a signal path is brought to a high or low level and the second IC pin at the other end of the signal path is sensed. In digital assemblies, the digital signal path is usually a flat wire, so the signals at both ends need to be the same. In this way, signal path defects such as open connections and short connections can be easily detected.
However, the analog signal path may comprise an analog circuit such as a filter. For example, driving the input of a high pass filter at a DC voltage level does not necessarily result in the same voltage when captured on its output pin, so the boundary scan approach cannot be used for such signal paths. A method for testing such a signal is described in WO 97/14974 (Attorney Docket No. PHN 15.527 corresponding to US patent specification 08 / 734,009). According to a known method, a time-varying test signal is generated at the input of the signal path, whereas a response signal is detected at a test point coupled to the output of the signal path. Defects in the signal path can thus be detected based on the temporal behavior of the response signal.
The object of the present invention is to provide a method as described at the beginning which can be applied in general compared to known methods. To this end, the method according to the present invention causes the terminal to generate a result characterizing the signal path by the test signal, and the response signal corresponds to a result characterizing the signal path . Therefore, it is utilized that a test signal is supplied to a terminal of a signal path to generate a result characterizing the signal path at the same terminal. This result having the form of a response signal can be evaluated.
The present invention is particularly useful when only one terminal of the signal path to be tested is available for testing. This applies, for example, to elements that are widely used as decoupling capacitance between an IC pin and a feed line such as a ground line. When testing the presence of such a capacitance from within the IC, the capacitance can only be accessed via the IC pin. Since known methods require both the input and output portions of the signal path, the known method cannot be used to test such analog signal paths. Another example is when an IC or other device that does not provide a boundary scanning approach or test hardware according to the above method is connected to one end of the signal path to be tested. In either case, the signal path can be tested by the method of the present invention.
The response signal can completely or partially match the test signal. The test signal and the response signal may be separate signals. This is because, for example, when energy is stored in an ineffective component of the signal path such as capacitance or inductance, a test signal is supplied in the first stage, energy is injected into the signal path, and a terminal is connected in the second stage. This is the case when energy is released through to form a response signal. In any case, only one terminal of the signal path to be tested needs to be accessible.
The result of the evaluation, and thus the test, can be a binary that represents whether a response signal having an expected response has occurred on the signal path. In this regard, a level detection method is used, for example, to detect whether a response signal within a certain time interval has reached a predetermined level or whether a predetermined instantaneous response signal has a predetermined level. Can do. Also, the result of the evaluation is a more comprehensive suitability of signal paths for circuit parameters such as resistance, capacitance and reached voltage level.
In a predetermined case, it is not practical to use the level detection method and detect whether the response signal has reached a predetermined level. For example, if the response signal is weak, this requires a more accurate detection method. In one example of the method according to the invention, the evaluation step comprises taking a secondary signal having an integral form of the response signal and comparing the level of the secondary signal with a threshold value. Since the signal path characteristics accumulate at the value of the secondary signal at a given instant, this signal can be a more reliable representation of the signal path and is therefore more suitable for using level detection methods. Signal. This aspect of the invention is particularly useful for small and decreasing response signals, such as signals generated by discharge capacitance. Integration produces a secondary signal with a positive slope, the amplitude of the secondary signal being a measure of capacitance. However, the secondary signal needs to be an accurate integral form of the response signal. It is sufficient to relate the value of the secondary signal at a given instant to the value of the response signal in the previous interval. Therefore, the secondary signal comprises an integral form of the response signal.
Preferably, the method according to the invention is applied to the testing of the signal path of an IC assembly, in which case the circuit is an IC assembly, the signal path is external to the IC and the terminals are IC pins.
These and other aspects of the invention will be apparent with reference to the embodiments described below.
In the drawing,
FIG. 1 is a linear diagram of a circuit according to the invention.
FIG. 2 shows certain signals generated in a circuit according to the invention.
FIG. 3 shows another signal path that can be tested by the method of the present invention.
FIG. 1 is a linear diagram of a circuit 100 according to the present invention. The circuit 100 has a terminal 110 that connects the signal path 112 to the signal path 114 in the normal mode of the circuit 100. Signal path 114 grounds terminal 110 through a separate capacitance 195. Terminal 110 is also connected to test circuit 120 through signal path 116 to test in test mode whether signal path 114 is established, ie, whether capacitance 195 is present. Means for switching between the normal mode and the test mode, for example, a switch connecting one of the signal path 112 and the signal path 116 to the terminal 110 are excluded from the figure for the sake of clarity.
The test circuit includes a switching mechanism 122, an impedance 124 mainly having resistance characteristics, an integrator 130, and a detector 140. In addition, two digital boundary scan cells 150, 152 are included for monitoring and control.
In the first mode of the test circuit, switching mechanism 122 connects terminal 110 to V +, thereby supplying a test signal to the terminal and charging capacitance 195. Then, in the second mode, the switching mechanism 122 connects the terminal 110 to V− via the impedance 124, thereby discharging the capacitance 195 and establishing a response signal on the terminal 110. The response signal has the form of a descending RC curve, the frequency of which represents the value of the capacitance. A response signal is provided to integrator 130, which provides a secondary signal to detector 140 comprising an integrated form of the response signal. The secondary signal has a maximum value determined by the shape of the response signal. If this maximum value exceeds the detector threshold, the detector output changes. The maximum value of the detectable capacitance 195 depends on the value of the impedance 124, the integration operation of the integrator 195 and the threshold value of the detector 140.
In FIG. 2, curves 210 and 220 represent the first response signal and the first secondary signal that occur in circuit 100, particularly when capacitance 195 is low. Curves 212 and 222 represent the second response signal and the second secondary signal, particularly when the value of capacitance 195 is high. In addition, FIG. 2 shows the threshold of detector 140 as line 230. In this case, it is obvious that the output of the detector 140 is changed by the second secondary signal 222.
If the secondary signals 220, 222 are the exact integral form of the corresponding response signals 210, 212, the secondary signals 220, 222 will be rising RC curves rather than curves with declining slopes. However, in this case, it is assumed that integrator 130 has a very simple configuration, which performs approximate integration without performing accurate integration. Further, V− and ground are the same in a predetermined circuit. However, this requires no circuit or test method changes.
The output of the detector is connected to the input of the boundary scan cell 150. In this way, the test results can be easily used by shifting. The test circuit of FIG. 1 also has control signals 162 and 164 that are generated by the outputs of boundary scan cells 152 and 150, respectively. The control signal 162 controls the switching mechanism 122, while the control signal 164 resets the detector 140 and prepares for pulse detection. Generating the control signals 162 and 164 by the boundary scan cell has the advantage that the test circuit can be easily controlled from the outside.
The circuit of FIG. 1 can detect manufacturing defects in the signal path 114, such as a short circuit between the terminal 110 and ground or an open circuit of the signal path 114. For such defects, there is a small parasitic capacitance between the terminal 110 and ground. Therefore, it is necessary to select the minimum value of the capacitance 195 that can be detected by the test circuit 120 as at least the maximum value of the parasitic capacitance between the terminal 110 and the ground.
In FIG. 1, a capacitance 195 is an individual component. Also, there may be parasitic capacitance in capacitance 195, whereas it is clear that the test is aimed at detecting whether the parasitic capacitance exceeds a preset value. Such a test can be used to test whether a flat wire exists between two nodes, for example, two IC pins, as reflected in the value of the parasitic capacitance. Of course, it does not matter for such a test whether the node on one side of the wire belongs to an analog circuit or a digital circuit.
With minor changes, the circuit 100 can test a full range of signal paths that differ from the signal path 114, eg, a signal path that connects to V + instead of ground through a capacitance. In the latter case, the capacitance is discharged in the first mode and the capacitance is charged in the second mode, thereby generating a response signal. Another testable signal path is, for example, a signal path that is grounded through an inductance. In this case, the circuit according to the present invention, for example, stores energy in the inductance in the first step, releases energy from the inductance in the second step, and deforms the test circuit 120 so that the voltage can be detected instead of the current. . With any suitable modification, any kind of signal path connected to terminal 110 can be tested. Impedance 124 can be selected to generate a critical response signal at terminal 110. The impedance 124 can be omitted for a certain signal path.
Until now, a binary result indicating whether a predetermined level has been detected in the secondary signal has been obtained. In this text, testing a signal path also means characterizing the signal path by all measurements. In this regard, the methods described thus far can be repeatedly performed, for example, by a plurality of different impedances 124 or a plurality of different threshold detectors 140. Each of the following runs may add another bit to the n-bit characteristic of signal path 114, eg, the n-bit value of capacitance 195.
Circuit 100 is divided into two parts by line 190. This serves to clarify a particularly important application of the present invention: the right part of line 190 of circuit 100 is the IC, the terminal 110 is the IC pin, and the left part of line 190 of circuit 100 is the IC. Represents the environment. Particularly in the present embodiment of the present invention, it is advantageous to use the same test circuit 120 not only for the terminal 110 but also for a plurality of terminals. By sharing the test circuit among a plurality of IC pins, the area occupied by the test hardware can be reduced. With appropriate channels, a single test circuit can be used in combination with the terminals of multiple individual ICs to further reduce the required area.
FIG. 3 shows another signal path that can be tested by the method according to the invention. The signal path extends from the input terminal 310 to the output terminal 320, with the terminals 310, 320 being part of a high pass filter circuit 300 comprising a resistor 330 and a capacitance 340. To illustrate testing such a signal path using the method according to the present invention, reference is made to FIG. 1 assuming that the circuit 300 replaces the signal path 110. In this regard, the input terminal 310 is connected to the terminal 110, the output terminal 320 is connected to the input of another circuit, and the circuit is equipped with hardware that performs the known method as applied to most commercial ICs. Provide. Therefore, known methods cannot be used when testing this signal path.
However, if the output terminal 320 is held at least approximately at a DC level, such as V + or V-, the above-described embodiment of the present invention can be fully followed for this type of signal path. By operating the switching mechanism 122 as already described, a response signal in the form of a descending RC curve is also obtained, the frequency of which has information on the presence of a value, ie a charge amount of capacitance. The impedance 124 is not required with respect to the resistor 330 that already exists.
Although the present invention has been described primarily with respect to signal paths in an IC assembly, the present invention can be applied to testing any type of signal path in a circuit.
The present invention is not limited to the above-described embodiment, and many changes and modifications can be made. The present invention can be implemented by hardware comprising a plurality of individual elements and a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware.

Claims (8)

A signal path from the terminal of the integrated circuit to the integrated circuit external connection part, a method for testing the signal path comprising a device for storing energy, the method,
Supplying a test signal to a terminal of the signal path, and changing the amount of energy stored in the element from a first amount to a second amount ;
Forming a response signal on the terminal by changing the stored energy amount from the second amount to the first amount for the element; and
Method characterized by comprising the step of evaluating the response signal on the terminal. Evaluating the response signal comprises:
Extracting a secondary signal having an integral form of the response signal;
The method of claim 1 including the step of comparing the level of the secondary signal with a threshold value. A signal path connecting the terminal and <br/> the terminal connecting portions of the integrated circuit outside the said signal path comprising a device for storing energy,
In an integrated circuit comprising a test circuit connected to the terminal,
The test circuit is
Supplying a test signal to the terminal;
The amount of energy stored in the element by the test signal is changed from the first amount to the second amount,
And generating means configured to cause the element to form a response signal on the terminal by changing the stored energy amount from the second amount to the first amount ;
Integrated circuit, characterized in that it comprises an evaluation means for evaluating the response signal on the terminal. An integrated circuit and the signal path comprising an element for storing energy outside the integrated circuit, the integrated circuit comprising:
A terminal connected to the external signal path;
An integrated circuit assembly comprising a test circuit connected to the terminal;
The test circuit is
Supplying a test signal to the terminal;
The amount of energy stored in the element by the test signal is changed from the first amount to the second amount,
And generating means configured to cause the element to form a response signal on the terminal by changing the stored energy amount from the second amount to the first amount ;
Integrated circuit assembly, characterized in that it comprises an evaluation means for evaluating the response signal on the terminal. The generating means comprises a switching mechanism for supplying the test signal to the terminal in the first mode of the test circuit and establishing the response signal on the terminal in the second mode of the test circuit; 5. The integrated circuit assembly according to claim 4, further comprising control means for controlling the switching mechanism. The evaluation means is
An integration circuit for extracting a secondary signal having an integration form of the response signal;
6. The integrated circuit assembly according to claim 4, further comprising a detection circuit that compares a level of the secondary signal with a threshold value. 7. The integrated circuit assembly according to claim 6, wherein an output portion of the detection circuit is connected to an input portion of a boundary scan cell. 6. The integrated circuit assembly according to claim 5, wherein the control means includes a boundary scan cell, and the switching mechanism is controlled by an output of the boundary scan cell.

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