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JP3938337B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor light emitting device and manufacturing method thereof Download PDF

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Publication number
JP3938337B2
JP3938337B2 JP2002192699A JP2002192699A JP3938337B2 JP 3938337 B2 JP3938337 B2 JP 3938337B2 JP 2002192699 A JP2002192699 A JP 2002192699A JP 2002192699 A JP2002192699 A JP 2002192699A JP 3938337 B2 JP3938337 B2 JP 3938337B2
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side electrode
layer
light emitting
auxiliary
element body
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JP2003031851A (en
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幸男 尺田
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Rohm Co Ltd
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Rohm Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Description

【0001】
【産業上の利用分野】
本願発明は、半導体発光素子およびその製造方法に関し、特に発光作用を行わせるための素子本体に対してサブマウント部材を付加的に取り付けて構成される半導体発光素子およびその製造方法に関する。
【0002】
【従来の技術】
近年においては、有機金属化学気相成長法(以下、MOCVD法という)を利用して、サファイア基板上に窒化ガリウム系化合物半導体の結晶を成長させることなどにより、高輝度特性を備えた青色発光用の半導体発光素子が開発されるに至っている。
【0003】
上記高輝度の青色発光用半導体発光素子は、図9に示すように、透明のサファイア基板70上にGaNのバッファ層71を成長させ、このバッファ層71の表面上に、N型半導体層72(GaN層、AlGaN層)、発光層73(InGaN層)、およびP型半導体層74(AlGaN層、GaN層)を積層状に成長させたものである。そして、上記N型半導体層72におけるGaN層と、P型半導体層74におけるGaN層とに、N側電極75およびP側電極76がそれぞれ形成される。
【0004】
一方、被マウント部材である図示例のリードフレーム77に対する上記半導体発光素子の取り付け構造は、上記N側電極75およびP側電極76を双方共に、ワイヤ78,79を用いてリードフレーム77のN側端子部77aとP側端子部77bとにそれぞれボンディングされた状態にある。そして、このように取り付けられた半導体発光素子は、同図に矢印で示すように、上記電極76の配設側の面から光を発するように構成されている。
【0005】
【発明が解決しようとする課題】
ところで、上記従来の半導体発光素子は、リードフレーム等の被マウント部材における2箇所に対してワイヤボンディングを施す必要があり、その搭載作業あるいは結線作業の工程数が増加するなどして、作業の煩雑化ならびに複雑化を余儀なくされているのが実情であった。
【0006】
また、この種の半導体発光素子は、電極の配設面側から光から発せられる構成であることから、図10に示すように、発光領域A内に電極76が存在しており、この電極76の配設箇所は非発光部となる。したがって、実質的発光領域は上記電極76に相当する分だけ狭くなり、図示例のものでは、素子全体中に占める実質的発光領域は全表面積の1/2以下になる。この結果、上述のように高輝度特性を備えているにも拘らず、十分な発光量を得ることができず、各種表示ボード等への使用時における高い明度の要請に応じることが困難になるという問題を有している。
【0007】
本願発明は、上述の事情のもとで考え出されたものであって、半導体発光素子の被マウント部材に対するワイヤボンディングの個数を削減して、その結線作業を簡便に行えるようにするとともに、半導体発光素子における実質的発光領域を可及的に増大させて十分な発光量の確保および明度の向上を図ることをその課題とする。
【0008】
【課題を解決するための手段】
上記の課題を解決するため、本願発明では、次の技術的手段を講じている。
【0009】
すなわち、本願の請求項1に記載した発明は、透明のサファイア基板の表面上にN型半導体層、発光層、およびP型半導体層を形成し、かつ上記P型半導体層の表面にP側電極が形成され、上記N型半導体層における露出表面部にN側電極を形成して構成される素子本体と、導電性基板の表面に対して絶縁状態となるように形成されるとともに上記N側電極と対向する補助N側電極層、および上記導電性基板の表面に対して導通状態となるように直接的かつ平面的に形成されるとともに上記P側電極と対向する補助P側電極層を有するサブマウント部材と、を備え、上記サブマウント部材と上記素子本体との双方の表面側を相互に対向させて配置し、かつ、上記補助N側電極層と上記N側電極との間、および上記補助P側電極層と上記P側電極との間がそれぞれ導通状態となるように、上記サブマウント部材と上記素子本体とを一体化させることにより、上記補助P側電極層が上記素子本体の発光層から発せられた光を反射する反射面として機能するとともに、上記透明のサファイア基板の裏面側から光が発せられるようにしたことを特徴としている。
【0011】
一方、本願の請求項に記載した発明は、上記請求項1に記載した半導体発光素子の製造方法であって、上記素子本体と上記サブマウント部材とを別々に製作した後に、上記素子本体の表面側と上記サブマウント部材の表面側とを対向させた状態の下で、上記補助N側電極層と上記N側電極、および上記補助P側電極層と上記P側電極とをそれぞれ直接的に接着させるようにしたことを特徴としている。
【0013】
【発明の作用および効果】
上記請求項1に記載した半導体発光素子は、素子本体がサブマウント上に搭載された格好で一体化されている。したがって、この半導体発光素子は、リードフレーム等に対して、上記半導体発光素子のサブマウント部材をボンディングすることにより、簡便にマウントすることができる。
【0014】
さらに、上記素子本体からの発光は、両電極の配設面とは反対側の面であるサファイア基板の裏面からなされることになり、従来のようにP側電極が発光を阻害することはなくなる。これにより、サファイア基板の裏面の大半が実質的発光領域となり、十分な発光量を確保できるとともに、この種の半導体発光素子の使用時における高い明度の要請に応じることが可能になる。
【0015】
また、上記素子本体の発光層からサブマウント部材側に発せられた光は、サブマウント部材の表面の補助電極層等で反射することになるので、上記素子本体におけるサファイア基板の裏面からのトータル発光量は、上記の反射光をも含んでさらに増大し、より高い明度を得ることが可能になる。
【0017】
一方、上記請求項に記載した発明によれば、素子本体とサブマウント部材とを別々に製作した後に、この両者を表面側どうしを対向させて両補助電極と両電極とを接着させることにより、上述の請求項1に記載した半導体発光素子が得られる。このような手法によれば、上記両者を別々に製作する段階において量産化が促進されるとともに、この種の半導体発光素子に新たな構成要素であるサブマウント部材を付加したにも拘らず、製作作業の複雑化が効果的に回避される。
【0019】
【実施例の説明】
以下、本願発明の好ましい実施例を、図面を参照しつつ具体的に説明する。
【0020】
図1は本願発明の第1実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図、図2はその概略平面図、図3は上記半導体発光素子の構成要素であるサブマウント部材を示す概略縦断正面図、図4はその概略平面図、図5は上記半導体発光素子の全体構成ならびにリードフレームへの取り付け状態を示す概略縦断面図である。
【0021】
図1に示すように、第1実施例に係る半導体発光素子1の素子本体2は、基本的には、透明性の絶縁基板であるサファイア基板3上に、N型半導体層4と、発光層5と、P型半導体層6とを備えて構成される積層部7を形成したものである。詳細には、上記積層部7は、透明または半透明のサファイア基板3の表面上に窒化ガリウム(GaN)のバッファ層8を成長させ、その表面側に、下層部分から順に、N型GaNの層41と、N型Al0.2 Ga0.8 Nの層42と、発光層としてのIn0.15Ga0.85Nの層5と、P型Al0.2 Ga0.8 Nの層61と、P型GaNの層62と、を形成したものである。そして、上記発光層5からは、青色に対応した波長(好ましくは470nm)の光が発せられるようになっている。
【0022】
加えて、上記N型GaNの層41およびN型Al0.2 Ga0.8 Nの層42には、Siが添加され、P型Al0.2 Ga0.8 Nの層61およびP型GaNの層62には、Mgが添加されているとともに、上記In0.15Ga0.85Nの層5にはZnが添加されている。そして、上記In0.15Ga0.85Nの層5におけるInのGaに対する組成比(混晶比)を増加させた場合には、この層5から発せられる光の波長が長くなるとともに、上記Znの添加量を増加させた場合には、上記組成比を増加させた場合よりもさらに光の波長が長くなるという特性を備えている。なお、上記各層の厚みは、下層側から各層41、42、5、61、62のそれぞれの順に、たとえば3μm、300nm、50nm、300nm、150nmに設定されている。
【0023】
上記図示例の素子本体2は、最終的に単一のチップとして得られるたとえば平面視が一辺0.5mmの正方形状のものであるが、実際の製造に際しては、MOCVD法により上記図示例の構造のものを所定面積のウエハとして一括して形成した後、ダイシングにより上記単一のチップに分割することにより得られる。
【0024】
そして、上記N型半導体層4におけるGaN層41のエッチングにより除去した露出表面部にN側電極9が形成され、P型半導体層6におけるGaN層の表面部にP側電極10が形成されている。なお、このN側電極9とP側電極10とは、概略的には、図2に示すような平面視形状とされた上で配設されている。
【0025】
一方、図3に示すように、この第1実施例に係る半導体発光素子1のサブマウント部材11は、不透明の導電性を有するシリコン基板12の表面にSiO2 でなる絶縁酸化皮膜13を形成し、その中央部をエッチングで除去して補助P側電極層14を形成し、かつその外周側における上記酸化皮膜13の表面部に補助N側電極層15を形成したものである。この双方の補助電極層14,15は、AuとSnとの合金あるいはインジウム系の合金を使用して蒸着により形成したものであり、後述するように電極とハンダ用メタルとを兼用するものである。
【0026】
そして、上記補助P側電極層14と補助N側電極層15とは、概略的には、図4に示すような平面視形状とされた上で配設されている。加えて、同図に示すように、シリコン基板12の一側部には、2箇所の補助N側電極層15に導通される帯状の補助N側電極層15aが、上記絶縁酸化皮膜13の表面部に形成されている。
【0027】
次に、上記の構成を備えた素子本体2とサブマウント部材11とを接合一体化させて半導体発光素子1を製造する方法、ならびにこれによって得られる半導体発光素子1の構成について説明する。
【0028】
まず、上記素子本体2とサブマウント部材11とを別々に製作した後に、この両者の表面側どうしを対向させて配置し、素子本体2のN側電極9およびP側電極10に対してそれぞれ、サブマウント部材11の補助N側電極層15および補助P側電極層14をハンダ付けする。このはんだ付け作業は、上記サブマウント部材11の双方の補助電極層15,14がハンダ用メタルを兼用していることから、これらの補助電極層15,14を適宜溶融固化させることにより行われる。
【0029】
この結果、図5に示すように、素子本体2のサファイア基板3の裏面3aから矢印で示すように光が発せられる状態になる。加えて、上記素子本体の2のP側電極10はサブマウント部材11のシリコン基板12に導通状態となる一方、素子本体2のN側電極9は上記シリコン基板12に対して絶縁状態となる。なお、図1に示す素子本体2の積層部7の高さ寸法は、図5に示す積層部7の高さ寸法と比較して、説明の便宜上、長尺になっている。
【0030】
そして、上記のようにして得られた半導体発光素子1をリードフレーム17上に搭載するには、同図に示すように、リードフレーム16のP側端子部16aの上面部に上記サブマウント部材11の下面が導通状態になるようにボンディングされるとともに、サブマウント部材11の上記帯状の補助N側電極層15aとリードフレーム16のN側端子部16bとの間にワイヤボンディング17が施される。
【0031】
これにより、上記素子本体2のP側電極10は、導電性シリコン基板12を通じてリードフレーム16のP側端子部16aに導通状態とされ、かつ上記素子本体2のN側電極9は、ワイヤ17を通じてリードフレーム16のN側端子部16bに導通状態とされる。この後は、上記半導体発光素子1の外周部を樹脂封止することなどによって、青色発光用のLEDランプが得られる。
【0032】
このような構成とすることにより、素子本体2の透明サファイア基板3の裏面3aにおけるN側電極9の形成箇所以外の領域が発光領域となり、上記裏面3aの全面積の約75%が発光領域として利用される。したがって、従来のように電極による発光阻害が激減され、十分な発光量および高い明度を有する発光デバイスが得られることになる。
【0033】
加えて、上記素子本体2の発光層5から下方に向かって発せられた光は、不透明のサブマウント部材11(補助電極層14,15)で反射された後、サファイア基板3の裏面3aから外方に向かって照射されることになるので、光の利用効率が向上するという利点も得られる。
【0034】
さらに、上記サブマウント部材11を使用したことにより、P側電極10に対するワイヤボンディングが不要になり、結線作業の簡便化ならびに製作容易化が図られることになる。
【0035】
次に、本願発明に係る半導体発光素子1の第2実施例を、図6、7、8を参照しつつ説明する。なお、以下の第2実施例の説明に際して、上述の第1実施例と共通の構成要件については同一符号を付してその説明を省略する。
【0036】
この第2実施例に係る半導体発光素子1が上述の第1実施例と異なる点は、図6および図7に示すように、素子本体2の表面全域をCVD法を用いてSiO2 やSi3 4 等からなる絶縁層18で覆うとともに、この絶縁層18にN側電極9およびP側電極10にそれぞれ通じる貫通孔19,20を穿設し、かつ上記絶縁層18の表面部にAuとSnとの合金あるいはインジウム系の合金等でなる金属層21,22を相互に独立して形成した点にある。この場合、上記各貫通孔19,20には、上記各金属層21,22が埋設されることになるので、上記一方の金属層21は上記N側電極9に導通した状態になり、他方の金属層22は上記P側電極10に導通した状態になる。
【0037】
なお、サブマウント部材11の構成は、図7に示す各金属層21,22の平面視における形状および配設状態に対応して補助N側電極層15と補助P側電極層14とが形成されており、その他の部分、たとえば補助N側電極層15がSiO2 等の絶縁性皮膜13を介して形成されている点などについては上述の第1実施例と同一の構成である。
【0038】
そして、上記素子本体2とサブマウント部材11とは、両者の表面側どうしが対向配置された状態で、図8に示すように各金属層21,22と各補助電極層15,14とが接合一体化されることにより、半導体発光素子1が得られる。また、図示の構成によっても、上記素子本体2のP側電極10はリードフレーム16のP側端子部16aに導電性シリコン基板12を介して導通状態とされ、かつ上記素子本体2のN側電極9はリードフレーム16のN側端子部16bにワイヤ17を介して導通状態とされる。
【0039】
そして、この場合には、各金属層21,22と各補助電極層15,14との位置合わせが容易に行えることから、これらの両層の接合作業(ハンダ付け作業)、ひいては素子本体2とサブマウント部材11との接合作業が極めて簡便に行えることになる。
【0040】
また、この第2実施例によっても、上記第1実施例と同様に、十分な発光量を確保できることは言うまでもない。
【図面の簡単な説明】
【図1】本願発明の第1実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図である。
【図2】上記第1実施例に係る素子本体の概略平面図である。
【図3】上記第1実施例に係る半導体発光素子の構成要素であるサブマウント部材の概略縦断正面図である。
【図4】上記第1実施例に係るサブマウント部材の概略平面図である。
【図5】上記第1実施例に係る半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図6】本願発明の第2実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図である。
【図7】上記第2実施例に係る素子本体の概略平面図である。
【図8】上記第2実施例に係る半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図9】従来の半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図10】従来の半導体発光素子の概略平面図である。
【符号の説明】
1 半導体発光素子
2 素子本体
3 透明絶縁性基板(サファイア基板)
4 N型半導体層
5 発光層
6 P型半導体層
9 N側電極
10 P側電極
11 サブマウント部材
12 導電性基板(シリコン基板)
14 補助P側電極層
15 補助N側電極層
[0001]
[Industrial application fields]
The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device configured by additionally attaching a submount member to an element body for performing a light emitting action and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, by using metalorganic chemical vapor deposition (hereinafter referred to as MOCVD method), a crystal of a gallium nitride compound semiconductor is grown on a sapphire substrate. Semiconductor light emitting devices have been developed.
[0003]
As shown in FIG. 9, the high-luminance blue light-emitting semiconductor light-emitting device has a GaN buffer layer 71 grown on a transparent sapphire substrate 70, and an N-type semiconductor layer 72 ( A GaN layer, an AlGaN layer), a light emitting layer 73 (InGaN layer), and a P-type semiconductor layer 74 (AlGaN layer, GaN layer) are grown in a laminated form. An N-side electrode 75 and a P-side electrode 76 are formed on the GaN layer in the N-type semiconductor layer 72 and the GaN layer in the P-type semiconductor layer 74, respectively.
[0004]
On the other hand, in the mounting structure of the semiconductor light emitting element to the lead frame 77 of the illustrated example which is a mounted member, both the N side electrode 75 and the P side electrode 76 are connected to the N side of the lead frame 77 using wires 78 and 79. The terminal portion 77a and the P-side terminal portion 77b are bonded to each other. The semiconductor light emitting element attached in this way is configured to emit light from the surface on the side where the electrode 76 is disposed, as indicated by an arrow in FIG.
[0005]
[Problems to be solved by the invention]
By the way, the conventional semiconductor light emitting element needs to be wire-bonded at two places on a mounted member such as a lead frame, and the number of steps for mounting or connecting is increased. The reality is that it has been forced to become complicated and complicated.
[0006]
In addition, since this type of semiconductor light emitting element emits light from the electrode mounting surface side, an electrode 76 exists in the light emitting region A as shown in FIG. The arrangement location is a non-light emitting portion. Therefore, the substantial light emitting region is narrowed by an amount corresponding to the electrode 76, and in the example shown in the drawing, the substantial light emitting region occupying the entire element is 1/2 or less of the total surface area. As a result, a sufficient amount of light emission cannot be obtained in spite of having the high luminance characteristics as described above, and it becomes difficult to meet the demand for high brightness when used for various display boards. Has the problem.
[0007]
The invention of the present application has been conceived under the above circumstances, and the number of wire bondings to a mounted member of a semiconductor light-emitting element can be reduced so that the connection work can be easily performed, and a semiconductor It is an object of the present invention to increase a substantial light-emitting region in a light-emitting element as much as possible to secure a sufficient light emission amount and improve brightness.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention takes the following technical means.
[0009]
That is, according to the first aspect of the present invention, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed on the surface of a transparent sapphire substrate, and a P-side electrode is formed on the surface of the P-type semiconductor layer. And an element main body formed by forming an N-side electrode on the exposed surface portion of the N-type semiconductor layer, and an N-side electrode formed so as to be insulated from the surface of the conductive substrate. And an auxiliary N-side electrode layer that is formed directly and planarly so as to be conductive with respect to the surface of the conductive substrate and that has an auxiliary P-side electrode layer that faces the P-side electrode. A mounting member, arranged so that the surface sides of both the submount member and the element body face each other, and between the auxiliary N-side electrode layer and the N-side electrode, and the auxiliary P-side electrode layer and P-side power The auxiliary P-side electrode layer reflects light emitted from the light emitting layer of the element body by integrating the submount member and the element body so that each of the submount member and the element body is in a conductive state. and it functions as a surface, is characterized in that as light is emitted from the back side of the transparent sapphire substrate.
[0011]
On the other hand, the invention described in claim 2 of the present application is a method for manufacturing a semiconductor light emitting device according to claim 1, in which the element body and the submount member are separately manufactured, and then the element body. The auxiliary N-side electrode layer and the N-side electrode, and the auxiliary P-side electrode layer and the P-side electrode are directly connected to each other in a state where the surface side and the surface side of the submount member are opposed to each other. It is characterized by being glued.
[0013]
Operation and effect of the invention
The semiconductor light-emitting device according to the first aspect is integrated with the device main body mounted on the submount. Therefore, this semiconductor light emitting device can be easily mounted by bonding a submount member of the semiconductor light emitting device to a lead frame or the like.
[0014]
Further, light emission from the element body is performed from the back surface of the sapphire substrate, which is the surface opposite to the surface on which both electrodes are disposed, and the P-side electrode does not hinder light emission as in the conventional case. . Thereby, most of the back surface of the sapphire substrate becomes a substantial light emitting region, and a sufficient amount of light emission can be secured, and it is possible to meet a demand for high brightness when using this type of semiconductor light emitting element.
[0015]
Further, light emitted to the submount member side from the light-emitting layer of the device body, so it will be reflected by the auxiliary electrode layer of the surface of the submount member, from the rear surface of the sapphire board in the device body The total light emission amount further increases including the above reflected light, and higher brightness can be obtained.
[0017]
On the other hand, according to the invention described in claim 2 , after the element body and the submount member are separately manufactured, both the auxiliary electrodes and the electrodes are bonded to each other with the surface sides facing each other. Thus, the semiconductor light-emitting device described in claim 1 is obtained. According to such a method, mass production is promoted at the stage where both of the above are separately manufactured, and the manufacturing is performed despite the addition of a submount member which is a new component to this type of semiconductor light emitting device. Work complexity is effectively avoided.
[0019]
[Explanation of Examples]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
1 is a schematic longitudinal front view showing an element body which is a component of a semiconductor light emitting element according to a first embodiment of the present invention, FIG. 2 is a schematic plan view thereof, and FIG. 3 is a sub view which is a component of the semiconductor light emitting element. FIG. 4 is a schematic plan view showing the mount member, FIG. 4 is a schematic plan view thereof, and FIG. 5 is a schematic vertical cross-sectional view showing the overall configuration of the semiconductor light emitting device and the state of attachment to the lead frame.
[0021]
As shown in FIG. 1, the element body 2 of the semiconductor light emitting element 1 according to the first embodiment basically includes an N-type semiconductor layer 4 and a light emitting layer on a sapphire substrate 3 which is a transparent insulating substrate. 5 and a P-type semiconductor layer 6 are formed. More specifically, the stacked unit 7 grows a gallium nitride (GaN) buffer layer 8 on the surface of a transparent or semi-transparent sapphire substrate 3, and an N-type GaN layer sequentially from the lower layer portion on the surface side. 41, an N-type Al 0.2 Ga 0.8 N layer 42, an In 0.15 Ga 0.85 N layer 5 as a light emitting layer, a P-type Al 0.2 Ga 0.8 N layer 61, and a P-type GaN layer 62. Formed. The light emitting layer 5 emits light having a wavelength corresponding to blue (preferably 470 nm).
[0022]
In addition, Si is added to the N-type GaN layer 41 and the N-type Al 0.2 Ga 0.8 N layer 42, and the P-type Al 0.2 Ga 0.8 N layer 61 and the P-type GaN layer 62 include Mg. In addition, Zn is added to the In 0.15 Ga 0.85 N layer 5. Then, the case of increasing the composition ratio Ga of In in the layer 5 of the In 0.15 Ga 0.85 N (the composition ratio), together with the wavelength of light emitted from the layer 5 is increased, the amount of the Zn When the ratio is increased, the wavelength of light becomes longer than when the composition ratio is increased. In addition, the thickness of each said layer is set to 3 micrometers, 300 nm, 50 nm, 300 nm, 150 nm in order of each layer 41, 42, 5, 61, 62 from the lower layer side, for example.
[0023]
The element body 2 in the illustrated example is a square shape finally obtained as a single chip, for example, having a square shape with a side of 0.5 mm in plan view. However, in actual manufacturing, the structure of the illustrated example is formed by MOCVD. Can be obtained by dividing the wafer into a single chip by dicing.
[0024]
An N-side electrode 9 is formed on the exposed surface portion removed by etching of the GaN layer 41 in the N-type semiconductor layer 4, and a P-side electrode 10 is formed on the surface portion of the GaN layer in the P-type semiconductor layer 6. . The N-side electrode 9 and the P-side electrode 10 are generally arranged in a plan view as shown in FIG.
[0025]
On the other hand, as shown in FIG. 3, the submount member 11 of the semiconductor light emitting device 1 according to the first embodiment has an insulating oxide film 13 made of SiO 2 formed on the surface of an opaque conductive silicon substrate 12. The auxiliary P-side electrode layer 14 is formed by removing the central portion by etching, and the auxiliary N-side electrode layer 15 is formed on the surface portion of the oxide film 13 on the outer peripheral side. Both the auxiliary electrode layers 14 and 15 are formed by vapor deposition using an alloy of Au and Sn or an indium-based alloy. As will be described later, both the electrode and the solder metal are used. .
[0026]
The auxiliary P-side electrode layer 14 and the auxiliary N-side electrode layer 15 are roughly arranged in a plan view as shown in FIG. In addition, as shown in the figure, a band-shaped auxiliary N-side electrode layer 15 a that is electrically connected to two auxiliary N-side electrode layers 15 is provided on one side of the silicon substrate 12. It is formed in the part.
[0027]
Next, a method for manufacturing the semiconductor light emitting device 1 by joining and integrating the device body 2 and the submount member 11 having the above configuration, and the configuration of the semiconductor light emitting device 1 obtained thereby will be described.
[0028]
First, after the element body 2 and the submount member 11 are separately manufactured, the surface sides of the two are opposed to each other, and the N-side electrode 9 and the P-side electrode 10 of the element body 2 are respectively disposed. The auxiliary N-side electrode layer 15 and the auxiliary P-side electrode layer 14 of the submount member 11 are soldered. This soldering operation is performed by appropriately melting and solidifying these auxiliary electrode layers 15 and 14 since both auxiliary electrode layers 15 and 14 of the submount member 11 also serve as solder metal.
[0029]
As a result, as shown in FIG. 5, light is emitted from the back surface 3 a of the sapphire substrate 3 of the element body 2 as indicated by an arrow. In addition, the two P-side electrodes 10 of the element body are electrically connected to the silicon substrate 12 of the submount member 11, while the N-side electrode 9 of the element body 2 is insulated from the silicon substrate 12. In addition, the height dimension of the lamination | stacking part 7 of the element main body 2 shown in FIG. 1 is long compared with the height dimension of the lamination | stacking part 7 shown in FIG. 5 for convenience of explanation.
[0030]
In order to mount the semiconductor light emitting device 1 obtained as described above on the lead frame 17, the submount member 11 is formed on the upper surface of the P-side terminal portion 16a of the lead frame 16, as shown in FIG. Bonding is performed so that the lower surface of the submount member 11 is in a conductive state, and wire bonding 17 is applied between the band-shaped auxiliary N-side electrode layer 15 a of the submount member 11 and the N-side terminal portion 16 b of the lead frame 16.
[0031]
As a result, the P-side electrode 10 of the element body 2 is brought into conduction with the P-side terminal portion 16 a of the lead frame 16 through the conductive silicon substrate 12, and the N-side electrode 9 of the element body 2 is passed through the wire 17. The N-side terminal portion 16b of the lead frame 16 is brought into conduction. Thereafter, an LED lamp for blue light emission is obtained by resin sealing the outer peripheral portion of the semiconductor light emitting element 1.
[0032]
By adopting such a configuration, a region other than the formation position of the N-side electrode 9 on the back surface 3a of the transparent sapphire substrate 3 of the element body 2 becomes a light emitting region, and about 75% of the total area of the back surface 3a is a light emitting region. Used. Therefore, the light emission inhibition by the electrodes is drastically reduced as in the prior art, and a light emitting device having a sufficient light emission amount and high brightness can be obtained.
[0033]
In addition, the light emitted downward from the light emitting layer 5 of the element body 2 is reflected by the opaque submount member 11 (auxiliary electrode layers 14 and 15), and then is emitted from the back surface 3a of the sapphire substrate 3. Therefore, there is an advantage that the light use efficiency is improved.
[0034]
Furthermore, the use of the submount member 11 eliminates the need for wire bonding to the P-side electrode 10 and simplifies the wiring work and facilitates production.
[0035]
Next, a second embodiment of the semiconductor light emitting device 1 according to the present invention will be described with reference to FIGS. In the following description of the second embodiment, the same constituent elements as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.
[0036]
The semiconductor light emitting device 1 according to the second embodiment is different from the first embodiment described above in that, as shown in FIGS. 6 and 7, the entire surface of the device body 2 is made of SiO 2 or Si 3 by using the CVD method. The insulating layer 18 is covered with an insulating layer 18 made of N 4 or the like, and through holes 19 and 20 are formed in the insulating layer 18 so as to communicate with the N-side electrode 9 and the P-side electrode 10, respectively. The metal layers 21 and 22 made of an alloy with Sn or an indium alloy are formed independently of each other. In this case, since the metal layers 21 and 22 are embedded in the through holes 19 and 20, the one metal layer 21 is brought into conduction with the N-side electrode 9, and the other The metal layer 22 is brought into conduction with the P-side electrode 10.
[0037]
The submount member 11 is configured such that the auxiliary N-side electrode layer 15 and the auxiliary P-side electrode layer 14 are formed corresponding to the shape and arrangement state of the metal layers 21 and 22 shown in FIG. The other parts, for example, the auxiliary N-side electrode layer 15 is formed through an insulating film 13 such as SiO 2 are the same as those in the first embodiment.
[0038]
The element body 2 and the submount member 11 are bonded to each other with the metal layers 21 and 22 and the auxiliary electrode layers 15 and 14 as shown in FIG. By being integrated, the semiconductor light emitting element 1 is obtained. Even in the illustrated configuration, the P-side electrode 10 of the element body 2 is brought into conduction with the P-side terminal portion 16a of the lead frame 16 through the conductive silicon substrate 12, and the N-side electrode of the element body 2 is also provided. 9 is brought into conduction with the N-side terminal portion 16 b of the lead frame 16 through the wire 17.
[0039]
In this case, since the alignment between the metal layers 21 and 22 and the auxiliary electrode layers 15 and 14 can be easily performed, the joining work (soldering work) of these two layers, and the element main body 2 as well. The joining work with the submount member 11 can be performed very simply.
[0040]
Needless to say, the second embodiment can secure a sufficient amount of light emission as in the first embodiment.
[Brief description of the drawings]
FIG. 1 is a schematic longitudinal sectional front view showing an element body which is a component of a semiconductor light emitting element according to a first embodiment of the present invention.
FIG. 2 is a schematic plan view of an element body according to the first embodiment.
FIG. 3 is a schematic longitudinal front view of a submount member which is a component of the semiconductor light emitting device according to the first embodiment.
FIG. 4 is a schematic plan view of a submount member according to the first embodiment.
FIG. 5 is a schematic longitudinal sectional side view showing the overall configuration of the semiconductor light emitting device according to the first embodiment and its mounting state on a mounted member.
FIG. 6 is a schematic longitudinal sectional front view showing an element body which is a constituent element of a semiconductor light emitting element according to a second embodiment of the present invention.
FIG. 7 is a schematic plan view of an element body according to the second embodiment.
FIG. 8 is a schematic longitudinal sectional side view showing the overall configuration of the semiconductor light emitting device according to the second embodiment and its mounting state on a mounted member.
FIG. 9 is a schematic longitudinal sectional side view showing an overall configuration of a conventional semiconductor light emitting element and its attached state to a mounted member.
FIG. 10 is a schematic plan view of a conventional semiconductor light emitting device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor light-emitting device 2 Element body 3 Transparent insulating substrate (sapphire substrate)
4 N-type semiconductor layer 5 Light emitting layer 6 P-type semiconductor layer 9 N-side electrode 10 P-side electrode 11 Submount member 12 Conductive substrate (silicon substrate)
14 Auxiliary P-side electrode layer 15 Auxiliary N-side electrode layer

Claims (2)

透明のサファイア基板の表面上にN型半導体層、発光層、およびP型半導体層を形成し、かつ上記P型半導体層の表面にP側電極が形成され、上記N型半導体層における露出表面部にN側電極を形成して構成される素子本体と、
導電性基板の表面に対して絶縁状態となるように形成されるとともに上記N側電極と対向する補助N側電極層、および上記導電性基板の表面に対して導通状態となるように直接的かつ平面的に形成されるとともに上記P側電極と対向する補助P側電極層を有するサブマウント部材と、を備え、
上記サブマウント部材と上記素子本体との双方の表面側を相互に対向させて配置し、かつ、上記補助N側電極層と上記N側電極との間、および上記補助P側電極層と上記P側電極との間がそれぞれ導通状態となるように、上記サブマウント部材と上記素子本体とを一体化させることにより、上記補助P側電極層が上記素子本体の発光層から発せられた光を反射する反射面として機能するとともに、上記透明のサファイア基板の裏面側から光が発せられるようにしたことを特徴とする、半導体発光素子。
An N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed on the surface of the transparent sapphire substrate, and a P-side electrode is formed on the surface of the P-type semiconductor layer. An element body formed by forming an N-side electrode on
An auxiliary N-side electrode layer formed so as to be insulative with the surface of the conductive substrate and facing the N-side electrode, and directly and so as to be conductive with respect to the surface of the conductive substrate. A submount member formed in a plane and having an auxiliary P-side electrode layer facing the P-side electrode,
Both the submount member and the element body are disposed so that the surface sides thereof face each other, and between the auxiliary N-side electrode layer and the N-side electrode, and between the auxiliary P-side electrode layer and the P The auxiliary P-side electrode layer reflects the light emitted from the light-emitting layer of the element body by integrating the submount member and the element body so that each side electrode is in a conductive state. A semiconductor light emitting device characterized in that it functions as a reflecting surface and emits light from the back side of the transparent sapphire substrate.
上記請求項1に記載した半導体発光素子の製造方法であって、
上記素子本体と上記サブマウント部材とを別々に製作した後に、上記素子本体の表面側と上記サブマウント部材の表面側とを対向させた状態の下で、上記補助N側電極層と上記N側電極、および上記補助P側電極層と上記P側電極とをそれぞれ直接的に接着させるようにしたことを特徴とする、半導体発光素子の製造方法。
A method of manufacturing a semiconductor light emitting device according to claim 1,
After the element body and the submount member are separately manufactured, the auxiliary N-side electrode layer and the N-side are formed in a state where the surface side of the element body and the surface side of the submount member are opposed to each other. A method of manufacturing a semiconductor light emitting device, wherein the electrode and the auxiliary P-side electrode layer and the P-side electrode are directly bonded to each other.
JP2002192699A 2002-07-01 2002-07-01 Semiconductor light emitting device and manufacturing method thereof Expired - Fee Related JP3938337B2 (en)

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