JP3889476B2 - Microwave semiconductor integrated circuit manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microwave semiconductor integrated circuit having passive elements such as capacitors, resistors, and inductors. circuit (MMIC: Microwave Monolithic Integrated Circuit) Manufacturing method It is about.
[0002]
[Prior art]
Currently, the MMIC is used in a transmission / reception circuit of a cellular phone, and in a transmission / reception module, a high-power amplifier (HPA) on the transmission side and a low-noise amplifier (LNA) on the reception side are included. ), Used in mixer circuits.
[0003]
Among them, there is a passive MMIC composed only of passive elements (capacitors, resistors, inductors). This passive MMIC is a part of an LNA or a mixer circuit and has functions such as a matching unit and a filter.
[0004]
In general, a microwave semiconductor integrated circuit having passive elements such as a capacitor, a resistor, and an inductor includes an MIM (Metal Insulator Metal) capacitor, an injection resistor, a spiral inductor, and the like. This conventional microwave semiconductor integrated circuit will be described with reference to FIGS. FIG. 63 shows a structure of a conventional microwave semiconductor integrated circuit. 64 to 74 are diagrams showing a process flow of a conventional microwave semiconductor integrated circuit.
[0005]
In FIG. 63, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 7 is an MIM insulating film, 10 is a second passivation film, 14 is a plating electrode, and 15 is a final passivation film.
[0006]
Next, a process of the above-described conventional microwave semiconductor integrated circuit will be described.
[0007]
First, as a first step, a marker 2 is formed on a GaAs semiconductor substrate 1 as shown in FIG. Next, as a second step, an injection resistor 3 is formed as shown in FIG. Next, as a third step, as shown in FIG. 66, the electrode 4 of the injection resistor 3 is formed (lift-off: first time), and the first passivation film 5 is deposited. Next, as a fourth step, as shown in FIG. 67, the first passivation film 5 on the electrode 4 is etched.
[0008]
Next, as a fifth step, as shown in FIG. 68, the MIM capacitor base electrode 6 and wiring are formed (lift-off: second time), and the MIM insulating film 7 is deposited. Next, as a sixth step, the MIM insulating film 7 is etched as shown in FIG. Next, as a seventh step, as shown in FIG. 70, the MIM capacitor upper electrode 8, the inductor base electrode 9, and the wiring are formed (lift-off: third time), and the second passivation film 10 is deposited. Next, as an eighth step, as shown in FIG. 71, the second passivation film 10 is etched.
[0009]
Next, as a ninth step, as shown in FIG. 72, a first-layer plating electrode pattern (resist) 11 is formed, and as shown in FIG. 73, a power feeding layer 12 is formed. Next, as a tenth step, as shown in FIG. 73, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Also, as shown in FIG. 74, the resist is removed, and a final passivation film 15 is formed.
[0010]
Then, as an eleventh step, although not shown, the final passivation film 15 is etched to form the extraction electrode.
[0011]
[Problems to be solved by the invention]
In the conventional microwave semiconductor integrated circuit and the manufacturing method thereof as described above, as can be seen from the process flow, the number of steps is as large as 11 steps, which hinders cost reduction. Note that the number of steps described above is the number of times that photolithography is performed.
[0012]
Further, in the conventional MIM capacitor, since it is difficult to obtain a good insulating film / metal interface, the insulating film cannot be thinned and the electrode area is large. For this reason, there was a problem that the chip area had to be increased.
[0013]
Further, in order to produce the injection resistor, it is necessary to use a high-quality semiconductor substrate in order to stabilize the resistance value, and there is a problem that the cost is increased.
[0014]
Furthermore, in the conventional structure and process flow, there are three lift-off processes in which appearance defects are likely to occur, resulting in a decrease in yield.
[0015]
By the way, since the thin film resistor used in the present invention has almost no etching selectivity with respect to the insulating film, it is necessary to devise how to make the contact. FIG. 75 shows a contact structure of another conventional microwave semiconductor integrated circuit. In this structure, a metal electrode is formed on a thin film resistor in advance, but it is necessary to use a lift-off process, and there is a problem in that the same yield as described above is lowered.
[0016]
The present invention was made to solve the above-described problems, and can be reduced in the number of processes, the chip area can be reduced, and the cost can be reduced. Circuit manufacturing method The purpose is to obtain.
[0024]
[Means for Solving the Problems]
A method of manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning After forming a capacitor composed of the MIM upper electrode, the second insulating film, and the metal film, A first passivation film is formed on the semiconductor substrate. Deposition And a thin film resistor on the first passivation film. film And a third step of depositing the thin film resistor film Patterning A thin film resistor is formed on the first passivation film in the thin film resistor forming region. A fourth step of On the thin film resistor Thin film resistance electrode And on the first passivation film in the inductor formation region Inductor base electrode is formed After And a second passivation film on the semiconductor substrate. Deposition And a fifth step A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer A sixth step of etching the second and first passivation films; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition A seventh step of etching, and an eighth step of etching the final passivation film to form the extraction electrode.
[0025]
Also, a method for manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning After forming a capacitor composed of the MIM upper electrode, the second insulating film, and the metal film, A first passivation film is formed on the semiconductor substrate. Deposition And a thin film resistor on the first passivation film. film And a third step of depositing the thin film resistor film Patterning A thin film resistor is formed on the first passivation film in the thin film resistor forming region. A fourth step of On the thin film resistor Thin film resistor The pole Forming After And a second passivation film on the semiconductor substrate. Deposition And a fifth step A plating electrode electrically connected to each of the MIM upper electrode and the thin film resistance electrode is formed, and a resist is formed to form the plating electrode in the inductor formation region. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer A sixth step of etching the second and first passivation films; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And a seventh step of etching the final passivation film to form the extraction electrode.
[0026]
Also, a method for manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in a thin film resistance forming region; A first passivation film is formed on the semiconductor substrate. Deposition Third step to perform, and thin film resistance contact portion The first passivation film and the second insulating film Patterning After exposing a part of the thin film resistance electrode, Thin film resistor film And a thin film resistor. film Patterning To form a thin film resistor electrically connected to the thin film resistor electrode And a fifth step On the first passivation film in the inductor formation region Inductor base electrode is formed After And a second passivation film on the semiconductor substrate. Deposition A sixth step of: A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film A seventh step of etching Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And an eighth step of etching the final passivation film to form the extraction electrode.
[0027]
Also, a method for manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in the thin film resistance forming area, And forming an inductor base electrode made of the metal film covered with the second insulating film, A first passivation film is formed on the semiconductor substrate. Deposition Third step to perform, and thin film resistance contact portion The first passivation film and the second insulating film Patterning After exposing a part of the thin film resistance electrode, Thin film resistor film And a thin film resistor. film Patterning After forming a thin film resistor electrically connected to the thin film resistor electrode, on the semiconductor substrate A fifth step of depositing a second passivation film; A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film A sixth step of etching Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition A seventh step of performing, and an eighth step of etching the final passivation film to form the extraction electrode.
[0028]
Furthermore, a method of manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in the thin film resistance forming area, And forming an inductor base electrode made of the metal film covered with the second insulating film, A first passivation film is formed on the semiconductor substrate. Deposition A third step of On the thin film resistor electrode The first passivation film And the second insulating film Patterning After exposing the thin film resistor electrode, Thin film resistor film And a thin film resistor. film Patterning After forming a thin film resistor electrically connected to the thin film resistor electrode, on the semiconductor substrate A fifth step of depositing a second passivation film; A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film Etching Further, the thin film resistor covering the thin film resistor electrode is also etched. A sixth step of: Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And a seventh step of etching the final passivation film to form the extraction electrode.
[0029]
Furthermore, a method of manufacturing a microwave semiconductor integrated circuit according to the present invention is provided on a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And deposit an etching stopper layer on it Deposition A first step of: The etching stopper layer and the continuous MIM film Patterning The capacitor lower electrode made of the metal film covered with the second insulating film and the etching stopper layer in the capacitor forming region, and the metal covered with the second insulating film and the etching stopper layer in the thin film resistance forming region. After forming a thin film resistance electrode made of a film and an inductor base electrode made of the metal film covered with the second insulating film and the etching stopper layer in an inductor formation region, A second step of depositing a first passivation film on the semiconductor substrate; On the thin film resistor electrode The first passivation film The etching stopper layer and the second insulating film Patterning After exposing the thin film resistor electrode, Thin film resistor film A third step of depositing the thin film resistor and the deposited thin film resistor film Patterning To form a thin film resistor electrically connected to the thin film resistor electrode A fourth step of Above Inductor base electrode The first passivation film, the etching stopper layer, and the second insulating film on Patterning After exposing the inductor base electrode, A second passivation film is formed on the semiconductor substrate. Deposition And a fifth step A plating electrode that is electrically connected to the thin film resistor electrode and the inductor base electrode is formed, and a resist is formed to form a plating electrode that becomes a capacitor upper electrode above the capacitor lower electrode. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films; The thin film resistor that selectively etches with respect to the etching stopper layer and further covers the thin film resistor electrode portion is also provided. A sixth step of etching; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And a seventh step of etching the final passivation film to form the extraction electrode.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a cross-sectional structure of Embodiment 1 of the present invention. 2 to 12 are diagrams showing a process flow of the first embodiment of the present invention. In addition, in each figure, the same code | symbol shows the same or equivalent part.
[0031]
In FIG. 1, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 10 is a second passivation film, 14 is a plating electrode, 15 is a final passivation film, 21 is an MIM upper electrode (metal), and 22 is a thin film resistor (WSiN). ), 23 is a thin film resistance electrode, and 24 is an inductor base electrode.
[0032]
Next, the process flow of the first embodiment will be described.
[0033]
First, as a first step, as shown in FIG. 2, a marker 2 is formed on a GaAs semiconductor substrate 1 by patterning. Next, as shown in FIG. 3, a continuous MIM, that is, three layers 20 of insulating film (SiON) / metal / insulating film (SiN) is deposited.
[0034]
Next, as a second step, as shown in FIG. 4, an MIM upper electrode (metal) 21 is formed by vapor deposition (lift-off: first time).
[0035]
Next, as a third step, the continuous MIM is patterned as shown in FIG. 5, and the first passivation film 5 is deposited as shown in FIG. Next, as shown in FIG. 7, a thin film resistor (WSiN) 22 is deposited.
[0036]
Next, as a fourth step, the thin film resistor 22 is patterned as shown in FIG.
[0037]
Next, as a fifth step, as shown in FIG. 9, the thin film resistance electrode 23 and the inductor base electrode 24 are formed (lift-off: second time), and the second passivation film 10 is formed.
[0038]
Next, as a sixth step, as shown in FIG. 10, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films 10 and 5 are etched. For this etching, for example, the gas is CHF. _Three 10 sccm, O ₂ The ECR etching is performed at 10 sccm, a pressure of 2 mtorr, and a microwave power of 200 W. Next, as shown in FIG. 11, the power feeding layer 12 is formed.
[0039]
Next, as a seventh step, as shown in FIG. 11, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 12, the resist is removed, and a final passivation film 15 is formed.
[0040]
Next, as an eighth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0041]
In the microwave semiconductor integrated circuit according to the first embodiment, as described above, a continuous MIM capacitor and a thin film resistor are applied instead of the conventional MIM capacitor and the injection resistor.
[0042]
In the continuous MIM capacitor, since three layers of insulating film / metal / insulating film are continuously deposited as in the first step shown in FIGS. 2 and 3, a good metal / insulating film interface can be obtained. The insulating film thickness can be reduced, resulting in a smaller chip area.
[0043]
As the material of the continuous MIM capacitor, the first layer insulating film is SiON (1500 mm), the second base electrode is Ti / Au (500/2000 mm), the third layer MIM film is SiN (1000 mm), and the upper electrode Ti / Au (500 / 10000cm).
[0044]
In the conventional structure, the MIM film that was about 1500 mm can be thinned to about 1000 mm by using a continuous MIM. The manufacturing method is shown below.
[0045]
First, the SiON film method uses a SiH gas. _Four 1400ccm, NH _Three , 500 ccm, N ₂ The plasma CVD is O, 1000 ccm, pressure 2.0 torr, and temperature 300 ° C. The thickness is 1500 mm.
[0046]
Subsequently, the method of the base electrode (Ti / Au) is sputtering. The thickness is 500 mm for Ti and 2000 mm for Au.
[0047]
Next, the MIM film (SiN) method uses a gas of SiH. _Four , 200sccm, NH _Three , 500 sccm, pressure 0.7 torr, temperature 320 ° C. plasma CVD. The thickness is 1000 mm.
[0048]
Subsequently, the method of the upper electrode (Ti / Au) is electron beam evaporation (EB evaporation). The thickness is 500 mm for Ti and 1 μm for Au.
[0049]
Subsequently, the etching of the continuous MIM three-layer structure is first performed by insulating film etching (RIE) → ion milling (Au) → Ti etching (RIE) → insulating film etching (RIE). In addition, the method uses SFN, SiN, and Ti for gas. ₆ Reactive ion etching (RIE) with 228 sccm, He, 105 sccm, pressure 0.3 torr, RF power 50 W, and ion milling (IM) with respect to Au.
[0050]
In addition, thin film resistors do not require ion implantation unlike conventional implantation resistors, so that an inexpensive semiconductor substrate can be used. The method of contact is conventional.
[0051]
In the above description, WSiN has been described as the material for the thin film resistor. However, there are TaN, WN, and the like, and when the material is WSiN, for example, it is manufactured by the following method. For deposition, the target is WSi and the gas is Ar / N. ₂ (80%) 5 mtorr reactive sputtering. The thickness is about 1000 mm, and the sheet resistance is about 200Ω / □. Etching is performed using CF as a method. _Four + O ₂ (4%) Reactive ion etching (RIE) with 1 torr and RF power of 60 W. The selection ratios are WSiN / SiON-3 and WSiN / SiO-10.
[0052]
A method for manufacturing the inductor is shown below. First, the technique of the base electrode (common to the thin film resistance electrode) is electron beam evaporation (EB evaporation). The thickness is Ti (500 Å) / Au (1000 Å) / Mo (500 Å).
[0053]
A method of forming a power feeding layer in forming a plated electrode (plated wiring) is sputtering. The thickness is Ti (500 Å) / Au (2000 Å). Further, in electrolytic gold plating, the plating solution is a sulfite-based gold plating solution and the thickness is ˜3 μm.
[0054]
In order to reduce the number of processes and the lift-off process, a process flow is devised in which the thin film resistance electrode 23 and the inductor base electrode 24 are formed simultaneously in the fifth process.
[0055]
Further, in order to reduce the number of steps, the contact formation process between the eighth and ninth steps and the plating electrode that has been performed in two steps in the conventional process flow is performed in one step of the sixth step in the first embodiment. It is devised to. Conventionally, insulating film etching has been performed by reactive ion etching (RIE). In this case, the resist mask is greatly damaged, and a mask pattern margin cannot be widened. Therefore, after forming a small contact hole in advance, plating is performed. The electrode 14 was formed. In the first embodiment, a process flow is formed in one step by using an electron cyclotron resonance (ECR) etching method or a plasma etching method with little damage to the resist.
[0056]
As a result, the number of processes could be reduced from the conventional 11 processes to 8 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 processes to 2 processes.
[0057]
Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. FIG. 13 shows a cross-sectional structure of the second embodiment of the present invention. 14 to 21 are diagrams showing a process flow according to the second embodiment of the present invention.
[0058]
In FIG. 13, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 10 is a second passivation film, 14 is a plating electrode, 15 is a final passivation film, 21 is an MIM upper electrode (metal), and 22 is a thin film resistor (WSiN). ) And 23 are thin film resistance electrodes.
[0059]
Next, the process flow of the second embodiment will be described.
[0060]
First, since the first step and the second step are the same as those in the first embodiment, description thereof is omitted.
[0061]
Next, as a third step, the continuous MIM is patterned as shown in FIG. 14, and the first passivation film 5 is deposited as shown in FIG. Next, as shown in FIG. 16, a thin film resistor (WSiN) 22 is deposited.
[0062]
Next, as a fourth step, the thin film resistor 22 is patterned as shown in FIG.
[0063]
Next, as a fifth step, as shown in FIG. 18, a thin film resistance electrode 23 is formed (lift-off: second time), and a second passivation film 10 is formed.
[0064]
Next, as a sixth step, as shown in FIG. 19, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films 10 and 5 are etched. For this etching, for example, the gas is CHF. _Three 10 sccm, O ₂ The ECR etching is performed at 10 sccm, a pressure of 2 mtorr, and a microwave power of 200 W. Next, as shown in FIG. 20, the power feeding layer 12 is formed.
[0065]
Next, as a seventh step, as shown in FIG. 20, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 21, the resist is removed, and a final passivation film 15 is formed.
[0066]
Next, as an eighth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0067]
The microwave semiconductor integrated circuit according to the second embodiment is a modification of the first embodiment, and uses a continuous MIM capacitor and a thin film resistor as in the first embodiment. The inductor is formed by one layer of plating electrode. For this reason, the first layer insulating film of the continuous MIM capacitor is formed thick. The manufacturing method of each structure is the same as that of the first embodiment.
[0068]
As a result, the number of processes could be reduced from the conventional 11 processes to 8 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 processes to 2 processes.
[0069]
Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIGS. FIG. 22 shows a cross-sectional structure of the third embodiment of the present invention. 23 to 33 are diagrams showing a process flow according to the third embodiment of the present invention.
[0070]
In FIG. 22, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 10 is a second passivation film, 14 is a plating electrode, 15 is a final passivation film, 21 is an MIM upper electrode (metal), and 22 is a thin film resistor (WSiN). ), 23 is a thin film resistance electrode, and 24 is an inductor base electrode.
[0071]
Next, the process flow of the third embodiment will be described.
[0072]
First, as a first step, as shown in FIG. 23, a marker 2 is formed on a GaAs semiconductor substrate 1 by patterning. Next, as shown in FIG. 24, a continuous MIM, that is, three layers 20 of insulating film (SiON) / metal / insulating film (SiN) is deposited.
[0073]
Next, as a second step, as shown in FIG. 25, the MIM upper electrode (metal) 21 is formed by vapor deposition (lift-off: first time).
[0074]
Next, as a third step, as shown in FIG. 26, the continuous MIM and the thin film resistance electrode are patterned, and the first passivation film 5 is deposited.
[0075]
Next, as a fourth step, the thin film resistor contact portion is patterned as shown in FIG. 27, and a thin film resistor (WSiN) 22 is deposited as shown in FIG.
[0076]
Next, as a fifth step, the thin film resistor 22 is patterned as shown in FIG.
[0077]
Next, as a sixth step, as shown in FIG. 30, the inductor base electrode 24 is formed (lift-off: second time), and the second passivation film 10 is formed.
[0078]
Next, as a seventh step, as shown in FIG. 31, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films 10 and 5 are etched. For this etching, for example, the gas is CHF. _Three 10 sccm, O ₂ The ECR etching is performed at 10 sccm, a pressure of 2 mtorr, and a microwave power of 200 W. Next, as shown in FIG. 32, the power feeding layer 12 is formed.
[0079]
Next, as an eighth step, as shown in FIG. 32, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 33, the resist is removed, and a final passivation film 15 is formed.
[0080]
Next, as a ninth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0081]
The microwave semiconductor integrated circuit according to the third embodiment is characterized in that the contact between the thin film resistor and the plating electrode is formed without a lift-off process. As described in the third to fifth steps, the structure of the continuous MIM capacitor is used for the electrode of the thin film resistor, and a contact is made on the lower side of the thin film resistor. Therefore, a contact with the thin film resistor can be formed without a lift-off process. However, since the base electrode of the inductor must be formed by lift-off, the number of lift-off processes as a whole is the same as in the first and second embodiments.
[0082]
As a result, the number of processes could be reduced from the conventional 11 processes to 9 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 processes to 2 processes. And the electrode contact without a lift-off process can be formed.
[0083]
In the description of the third embodiment, plan views of typical steps, FIGS. 34 to 39, are attached. The numerical value in each figure is a reference value (unit: mm) to the last.
[0084]
FIG. 34 shows a plan view after the MIM upper electrode 21 is formed in the second step. The MIM upper electrode 21 is, for example, a 0.3 × 0.4 square. FIG. 35 is a plan view after the first passivation film 5 is deposited by patterning the continuous MIM and the thin film resistance electrode in the third step. FIG. 36 shows a plan view after patterning the thin film resistor 22 in the fifth step. FIG. 37 is a plan view of the sixth step, FIG. 38 is a seventh step, and FIG. 39 is a plan view of the eighth step. In FIG. 39, the shaded area represents an air bridge.
[0085]
Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 40 shows a cross-sectional structure of the fourth embodiment of the present invention. FIGS. 41 to 44 are diagrams showing a process flow according to the fourth embodiment of the present invention.
[0086]
In FIG. 40, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 10 is a second passivation film, 14 is a plating electrode, 15 is a final passivation film, 21 is an MIM upper electrode (metal), and 22 is a thin film resistor (WSiN). ), 23 is a thin film resistance electrode, and 24 is an inductor base electrode.
[0087]
Next, the process flow of the fourth embodiment will be described.
[0088]
First, the first step and the second step are the same as those in the third embodiment.
[0089]
Next, as a third step, as shown in FIG. 41, the continuous MIM, the thin-film resistance electrode 23, and the inductor base electrode 24 are patterned, and the first passivation film 5 is deposited.
[0090]
Next, the fourth step and the fifth step are the same as those in the third embodiment. That is, the thin film resistance contact portion is patterned, and the thin film resistance (WSiN) 22 is deposited. Next, the second passivation film 10 is deposited by patterning the thin film resistor 22.
[0091]
Next, as a sixth step, as shown in FIG. 42, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films 10 and 5 are etched. For this etching, for example, the gas is CHF. _Three 10 sccm, O ₂ The ECR etching is performed at 10 sccm, a pressure of 2 mtorr, and a microwave power of 200 W. Next, as shown in FIG. 43, the power feeding layer 12 is formed.
[0092]
Next, as a seventh step, as shown in FIG. 43, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 44, the resist is removed, and a final passivation film 15 is formed.
[0093]
Next, as an eighth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0094]
The microwave semiconductor integrated circuit according to the fourth embodiment is a modification of the third embodiment, and uses a continuous MIM capacitor structure for the base electrode of the inductor. As a result, the number of lift-off processes can be reduced as a whole.
[0095]
As a result, the number of processes could be reduced from the conventional 11 processes to 8 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 processes to 1 process. And the electrode contact without a lift-off process can be formed.
[0096]
Embodiment 5 FIG.
A fifth embodiment of the present invention will be described with reference to FIGS. FIG. 45 shows a cross-sectional structure of the fifth embodiment of the present invention. 46 to 51 are diagrams showing a process flow according to the fifth embodiment of the present invention.
[0097]
45, 1 is a GaAs semiconductor substrate, 5 is a first passivation film, 10 is a second passivation film, 14 is a plating electrode, 15 is a final passivation film, 21 is an MIM upper electrode (metal), and 22 is a thin film resistor (WSiN). ), 23 is a thin film resistance electrode, and 24 is an inductor base electrode.
[0098]
Next, the process flow of the fifth embodiment will be described.
[0099]
First, the first to third steps are the same as in the fourth embodiment.
[0100]
Next, as a fourth step, the thin film resistor contact portion is patterned as shown in FIG. 46, and the thin film resistor 22 is deposited as shown in FIG.
[0101]
Next, as a fifth step, as shown in FIG. 48, the thin film resistor 22 is patterned and the second passivation film 10 is deposited.
[0102]
Next, as a sixth step, as shown in FIG. 49, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films 10 and 5 are etched. For this etching, for example, the gas is CHF. _Three 10 sccm, O ₂ The ECR etching is performed at 10 sccm, a pressure of 2 mtorr, and a microwave power of 200 W. Next, as shown in FIG. 50, the power feeding layer 12 is formed.
[0103]
Next, as a seventh step, as shown in FIG. 50, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 51, the resist is removed, and a final passivation film 15 is formed.
[0104]
Next, as an eighth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0105]
The microwave semiconductor integrated circuit according to the fifth embodiment is a modification of the fourth embodiment, in which the contact portion of the thin film resistor is simplified and the area of the contact portion is reduced. As shown from the fourth step to the seventh step, a contact hole is also opened in the thin film resistor, and contact with the thin film resistor is obtained from the lower electrode (continuous MIM structure) at the periphery.
[0106]
As a result, the number of processes could be reduced from the conventional 11 processes to 8 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 processes to 1 process. And the electrode contact without a lift-off process can be formed. Furthermore, the electrode contact area without lift-off can be reduced.
[0107]
Embodiment 6 FIG.
A sixth embodiment of the present invention will be described with reference to FIGS. FIG. 52 shows a cross-sectional structure of the sixth embodiment of the present invention. FIGS. 53 to 62 are views showing a process flow of the sixth embodiment of the present invention.
[0108]
52, 1 is a GaAs semiconductor substrate, 5 is a first passivation film (SiN), 10 is a second passivation film (SiN), 14 is a plating electrode, 15 is a final passivation film, 25 is an etching stopper layer (SiO), 22 is a thin film resistor (WSiN), 23 is a thin film resistor electrode, and 24 is an inductor base electrode.
[0109]
Next, the process flow of the sixth embodiment will be described.
[0110]
First, as a first step, as shown in FIG. 53, the marker 2 is formed on the GaAs semiconductor substrate 1 by patterning. Next, as shown in FIG. 54, the continuous MIM, that is, the three layers 20 of insulating film (SiON) / metal / insulating film (SiN) is deposited, and the etching stopper layer 25 (SiO) is deposited.
[0111]
Next, as a second step, as shown in FIG. 55, the continuous MIM, the thin-film resistance electrode 23, and the inductor base electrode 24 are patterned, and the first passivation film 5 is deposited.
[0112]
Next, as a third step, the thin film resistor contact portion is patterned as shown in FIG. 56, and the thin film resistor 22 is deposited as shown in FIG.
[0113]
Next, as a fourth step, the thin film resistor 22 is patterned as shown in FIG.
[0114]
Next, as a fifth step, as shown in FIG. 59, the inductor base electrode is patterned to form a second passivation film 10.
[0115]
Next, as a sixth step, as shown in FIG. 60, a first-layer plating electrode pattern (resist) 11 is formed, and the second and first passivation films (SiN) 10 and 5 are selectively etched. . Next, as shown in FIG. 61, the power feeding layer 12 is formed.
[0116]
Next, as a seventh step, as shown in FIG. 61, a second-layer plating electrode pattern (resist) 13 is formed. Next, the plating electrode 14 is formed. Next, as shown in FIG. 62, the resist is removed, and a final passivation film 15 is formed.
[0117]
Next, as an eighth step, although not shown, the final passivation film 15 is etched to form an extraction electrode.
[0118]
The microwave semiconductor integrated circuit according to the sixth embodiment is a modification of the fifth embodiment and completely eliminates the lift-off process. For this reason, the upper electrode of the MIM capacitor is also a plating electrode. Further, as shown in FIG. 60, an etching stopper layer SiO is added so that the MIM film thickness d can be controlled. As will be described later, the etching rate of the SiO is 1/10 to 1/20 compared to SiN, so that it is easy to stop etching in the SiO layer. The passivation film thickness of the thin film resistor and the inductor section is smaller than that of the MIM capacitor section, and the etching other than the MIM is devised so that the etching other than the MIM ends before the etching reaches the etching stopper layer (SiO) 25.
[0119]
RIE (SF ₆ The etching rate of each film when etching is performed with + He plasma is as follows. First, SiO is 100 Å / min, while SiN is 1000 to 2000 Å / min. WSiN is 1000 で / min. Therefore, the selection ratio SiN / SiO = 10-20.
[0120]
As a result, the number of processes could be reduced from the conventional 11 processes to 8 processes. Further, the chip area can be reduced, and the cost can be reduced. Furthermore, the lift-off process could be reduced from 3 steps to 0 steps. And the electrode contact without a lift-off process can be formed. Furthermore, the electrode contact area without lift-off can be reduced.
[0128]
【The invention's effect】
As described above, the method for manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning After forming a capacitor composed of the MIM upper electrode, the second insulating film, and the metal film, A first passivation film is formed on the semiconductor substrate. Deposition And a thin film resistor on the first passivation film. film And a third step of depositing the thin film resistor film Patterning A thin film resistor is formed on the first passivation film in the thin film resistor forming region. A fourth step of On the thin film resistor Thin film resistance electrode And on the first passivation film in the inductor formation region Inductor base electrode is formed After And a second passivation film on the semiconductor substrate. Deposition And a fifth step A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer A sixth step of etching the second and first passivation films; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And the eighth step of etching the final passivation film to form the extraction electrode, the number of steps can be reduced as compared to the conventional method, the chip area can be reduced, and the cost can be reduced. And the lift-off process can be reduced.
[0129]
In addition, as described above, the method for manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning After forming a capacitor composed of the MIM upper electrode, the second insulating film, and the metal film, A first passivation film is formed on the semiconductor substrate. Deposition And a thin film resistor on the first passivation film. film And a third step of depositing the thin film resistor film Patterning A thin film resistor is formed on the first passivation film in the thin film resistor forming region. A fourth step of On the thin film resistor Thin film resistor The pole Forming After And a second passivation film on the semiconductor substrate. Deposition And a fifth step A plating electrode electrically connected to each of the MIM upper electrode and the thin film resistance electrode is formed, and a resist is formed to form the plating electrode in the inductor formation region. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer A sixth step of etching the second and first passivation films; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And the eighth step of etching the final passivation film to form the extraction electrode, the number of steps can be reduced as compared to the conventional method, the chip area can be reduced, and the cost can be reduced. And the lift-off process can be reduced.
[0130]
In addition, as described above, the method for manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in a thin film resistance forming region; A first passivation film is formed on the semiconductor substrate. Deposition Third step to perform, and thin film resistance contact portion The first passivation film and the second insulating film Patterning After exposing a part of the thin film resistance electrode, Thin film resistor film And a thin film resistor. film Patterning To form a thin film resistor electrically connected to the thin film resistor electrode And a fifth step On the first passivation film in the inductor formation region Inductor base electrode is formed After And a second passivation film on the semiconductor substrate. Deposition A sixth step of: A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film A seventh step of etching Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition This includes the eighth step of performing and the ninth step of etching the final passivation film to form the take-out electrode, so that it is possible to form an electrode contact without a lift-off step.
[0131]
In addition, as described above, the method for manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in the thin film resistance forming area, And forming an inductor base electrode made of the metal film covered with the second insulating film, A first passivation film is formed on the semiconductor substrate. Deposition Third step to perform, and thin film resistance contact portion The first passivation film and the second insulating film Patterning After exposing a part of the thin film resistance electrode, Thin film resistor film And a thin film resistor. film Patterning After forming a thin film resistor electrically connected to the thin film resistor electrode, on the semiconductor substrate A fifth step of depositing a second passivation film; A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film A sixth step of etching Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition This includes the seventh step and the eighth step of etching the final passivation film to form the extraction electrode, so that an electrode contact without a lift-off step can be formed.
[0132]
Furthermore, as described above, the method of manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And depositing the continuous MIM film A second step of forming an MIM upper electrode thereon, and said continuous MIM film Patterning Forming a capacitor made of the MIM upper electrode, the second insulating film and the metal film, and forming a thin film resistance electrode made of the metal film covered with the second insulating film in the thin film resistance forming area, And forming an inductor base electrode made of the metal film covered with the second insulating film, A first passivation film is formed on the semiconductor substrate. Deposition A third step of On the thin film resistor electrode The first passivation film And the second insulating film Patterning After exposing the thin film resistor electrode, Thin film resistor film And a thin film resistor. film Patterning After forming a thin film resistor electrically connected to the thin film resistor electrode, on the semiconductor substrate A fifth step of depositing a second passivation film; A resist is used to form plated electrodes that are electrically connected to the MIM upper electrode, the thin film resistor electrode, and the inductor base electrode, respectively. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films And the second insulating film Etching Further, the thin film resistor covering the thin film resistor electrode is also etched. A sixth step of: Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And an eighth step of etching the final passivation film to form the extraction electrode, so that an electrode contact without a lift-off process can be formed and an electrode contact area without a lift-off process can be reduced. There is an effect that can be done.
[0133]
Furthermore, as described above, the method of manufacturing a microwave semiconductor integrated circuit according to the present invention is applied to a semiconductor substrate. It consists of a first insulating film, a metal film, and a second insulating film in order from the bottom Continuous MIM film And deposit an etching stopper layer on it Deposition A first step of: The etching stopper layer and the continuous MIM film Patterning The capacitor lower electrode made of the metal film covered with the second insulating film and the etching stopper layer in the capacitor forming region, and the metal covered with the second insulating film and the etching stopper layer in the thin film resistance forming region. After forming a thin film resistance electrode made of a film and an inductor base electrode made of the metal film covered with the second insulating film and the etching stopper layer in an inductor formation region, A second step of depositing a first passivation film on the semiconductor substrate; On the thin film resistor electrode The first passivation film The etching stopper layer and the second insulating film Patterning After exposing the thin film resistor electrode, Thin film resistor film A third step of depositing the thin film resistor and the deposited thin film resistor film Patterning To form a thin film resistor electrically connected to the thin film resistor electrode A fourth step of Above Inductor base electrode The first passivation film, the etching stopper layer, and the second insulating film on Patterning After exposing the inductor base electrode, A second passivation film is formed on the semiconductor substrate. Deposition And a fifth step A plating electrode that is electrically connected to the thin film resistor electrode and the inductor base electrode is formed, and a resist is formed to form a plating electrode that becomes a capacitor upper electrode above the capacitor lower electrode. Form a plating electrode pattern for the first layer After , Exposed from the plating electrode pattern of the first layer The second and first passivation films; The thin film resistor that selectively etches with respect to the etching stopper layer and further covers the thin film resistor electrode portion is also provided. A sixth step of etching; Made of resist Form the plating electrode pattern by forming the second layer plating electrode pattern After , Second and first plating electrode patterns made of the resist Remove the final passivation film Deposition And an eighth step of etching the final passivation film to form the extraction electrode, so that an electrode contact without a lift-off process can be formed and an electrode contact area without a lift-off process can be reduced. There is an effect that can be done.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross-sectional structure of a first embodiment of the present invention.
FIG. 2 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 6 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 7 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 8 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 9 is a diagram showing a process flow of the first embodiment of the present invention.
FIG. 10 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 11 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 12 is a diagram showing a process flow according to the first embodiment of the present invention.
FIG. 13 is a diagram showing a cross-sectional structure of a second embodiment of the present invention.
FIG. 14 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 15 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 16 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 17 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 18 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 19 is a diagram showing a process flow of the second embodiment of the present invention.
FIG. 20 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 21 is a diagram showing a process flow of a second embodiment of the present invention.
FIG. 22 is a diagram showing a cross-sectional structure of a third embodiment of the present invention.
FIG. 23 is a diagram showing a process flow of the third embodiment of the present invention.
FIG. 24 is a diagram showing a process flow of the third embodiment of the present invention.
FIG. 25 is a diagram showing a process flow of the third embodiment of the present invention.
FIG. 26 is a diagram showing a process flow according to the third embodiment of the present invention.
FIG. 27 is a diagram showing a process flow of a third embodiment of the present invention.
FIG. 28 is a diagram showing a process flow of the third embodiment of the present invention.
FIG. 29 is a diagram showing a process flow of a third embodiment of the present invention.
FIG. 30 is a diagram showing a process flow of a third embodiment of the present invention.
FIG. 31 is a diagram showing a process flow of a third embodiment of the present invention.
FIG. 32 is a diagram showing a process flow according to the third embodiment of the present invention.
FIG. 33 shows a process flow according to the third embodiment of the present invention.
FIG. 34 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 35 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 36 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 37 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 38 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 39 is a plan view showing a process according to the third embodiment of the present invention.
FIG. 40 is a diagram showing a cross-sectional structure of a fourth embodiment of the present invention.
FIG. 41 is a diagram showing a process flow according to the fourth embodiment of the present invention.
FIG. 42 is a diagram showing a process flow according to the fourth embodiment of the present invention.
FIG. 43 is a diagram showing a process flow according to the fourth embodiment of the present invention.
FIG. 44 is a diagram showing a process flow according to the fourth embodiment of the present invention.
FIG. 45 shows a cross-sectional structure of a fifth embodiment of the present invention.
FIG. 46 is a diagram showing a process flow of embodiment 5 of the present invention.
FIG. 47 is a diagram showing a process flow according to the fifth embodiment of the present invention.
FIG. 48 is a diagram showing a process flow of embodiment 5 of the present invention.
FIG. 49 is a diagram showing a process flow of embodiment 5 of the present invention.
FIG. 50 is a diagram showing a process flow of embodiment 5 of the present invention.
FIG. 51 is a diagram showing a process flow of embodiment 5 of the present invention.
FIG. 52 shows a cross-sectional structure of a sixth embodiment of the present invention.
FIG. 53 is a diagram showing a process flow according to the sixth embodiment of the present invention.
FIG. 54 is a diagram showing a process flow of the sixth embodiment of the present invention.
FIG. 55 is a diagram showing a process flow according to the sixth embodiment of the present invention.
FIG. 56 is a diagram showing a process flow of embodiment 6 of the present invention.
FIG. 57 is a diagram showing a process flow of embodiment 6 of the present invention.
FIG. 58 is a diagram showing a process flow of the sixth embodiment of the present invention.
FIG. 59 is a diagram showing a process flow of embodiment 6 of the present invention.
FIG. 60 is a diagram showing a process flow of embodiment 6 of the invention.
FIG. 61 is a diagram showing a process flow of embodiment 6 of the present invention.
FIG. 62 shows a process flow of the sixth embodiment of the present invention.
FIG. 63 is a diagram showing a cross-sectional structure of a conventional microwave semiconductor integrated circuit.
FIG. 64 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 65 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 66 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 67 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 68 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 69 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 70 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 71 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 72 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 73 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 74 is a diagram showing a process flow of a conventional microwave semiconductor integrated circuit.
FIG. 75 is a diagram showing a contact structure of another conventional microwave semiconductor integrated circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 GaAs semiconductor substrate, 5 1st passivation film, 10 2nd passivation film, 14 Plating electrode, 15 Final passivation film, 21 MIM upper electrode (metal), 22 Thin film resistance (WSiN), 23 Thin film resistance electrode, 24 Inductor base electrode 25 Etching stopper layer.

Claims (6)

A first step of depositing a continuous MIM film comprising a first insulating film, a metal film, and a second insulating film in order from the bottom on a semiconductor substrate;
A second step of forming an MIM upper electrode on the deposited continuous MIM film ;
After patterning the continuous MIM film to form a capacitor made of the MIM upper electrode, the second insulating film, and the metal film , a first passivation film is deposited on the semiconductor substrate, and the first passivation film is formed on the first passivation film. A third step of depositing a thin film resistive film ;
A fourth step of patterning the thin film resistance film to form a thin film resistance on the first passivation film in the thin film resistance formation region ;
To form a thin film resistor electrode on the thin film resistor, after the formation of the inductor base electrode on the first passivation film inductor forming region, and a fifth step of depositing a second passivation layer on the semiconductor substrate ,
In order to form a plating electrode electrically connected to each of the MIM upper electrode, the thin film resistance electrode, and the inductor base electrode, a first plating electrode pattern made of a resist is formed, and then the first layer A sixth step of etching the second and first passivation films exposed from the plating electrode pattern ;
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the seventh depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And an eighth step of etching the final passivation film to form a take-out electrode. A first step of depositing a continuous MIM film comprising a first insulating film, a metal film, and a second insulating film in order from the bottom on a semiconductor substrate;
A second step of forming an MIM upper electrode on the deposited continuous MIM film ;
After patterning the continuous MIM film to form a capacitor made of the MIM upper electrode, the second insulating film, and the metal film , a first passivation film is deposited on the semiconductor substrate, and the first passivation film is formed on the first passivation film. A third step of depositing a thin film resistive film ;
A fourth step of patterning the thin film resistance film to form a thin film resistance on the first passivation film in the thin film resistance formation region ;
After forming the thin film resistor electrodes on the thin film resistor, and a fifth step of depositing a second passivation layer on the semiconductor substrate,
A plating electrode electrically connected to each of the MIM upper electrode and the thin film resistance electrode was formed, and a first plating electrode pattern made of resist was formed to form a plating electrode in the inductor formation region . after, a sixth step of etching the second and first passivation film exposed from the plating electrode patterns of the first layer,
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the seventh depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And an eighth step of etching the final passivation film to form a take-out electrode. A first step of depositing a continuous MIM film comprising a first insulating film, a metal film, and a second insulating film in order from the bottom on a semiconductor substrate;
A second step of forming an MIM upper electrode on the deposited continuous MIM film ;
The continuous MIM film is patterned to form a capacitor made of the MIM upper electrode, the second insulating film, and the metal film, and the thin film resistor forming region is made of the metal film covered with the second insulating film. A third step of depositing a first passivation film on the semiconductor substrate after forming the thin film resistance electrode ;
A fourth step of depositing the thin film resistance film after patterning the first passivation film and the second insulating film of the thin film resistance contact portion to expose a part of the thin film resistance electrode ;
A fifth step of patterning the thin film resistor film to form a thin film resistor electrically connected to the thin film resistor electrode ;
A sixth step of depositing a second passivation film on the semiconductor substrate after forming an inductor base electrode on the first passivation film in an inductor formation region ;
In order to form a plating electrode electrically connected to each of the MIM upper electrode, the thin film resistance electrode, and the inductor base electrode, a first plating electrode pattern made of a resist is formed, and then the first layer A seventh step of etching the second and first passivation films and the second insulating film exposed from the plating electrode pattern ;
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the eighth depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And a ninth step of etching the final passivation film to form an extraction electrode. A method for manufacturing a microwave semiconductor integrated circuit, comprising: A first step of depositing a continuous MIM film comprising a first insulating film, a metal film, and a second insulating film in order from the bottom on a semiconductor substrate;
A second step of forming an MIM upper electrode on the deposited continuous MIM film ;
The continuous MIM film is patterned to form a capacitor made of the MIM upper electrode, the second insulating film, and the metal film, and the thin film resistor forming region is made of the metal film covered with the second insulating film. A third step of depositing a first passivation film on the semiconductor substrate after forming a thin film resistance electrode and an inductor base electrode made of the metal film covered with the second insulating film in an inductor formation region ;
A fourth step of depositing the thin film resistance film after patterning the first passivation film and the second insulating film of the thin film resistance contact portion to expose a part of the thin film resistance electrode ;
A fifth step of depositing a second passivation film on the semiconductor substrate after patterning the thin film resistor film to form a thin film resistor electrically connected to the thin film resistor electrode ;
In order to form a plating electrode electrically connected to each of the MIM upper electrode, the thin film resistance electrode, and the inductor base electrode, a first plating electrode pattern made of a resist is formed, and then the first layer A sixth step of etching the second and first passivation films exposed from the plating electrode pattern and the second insulating film ;
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the seventh depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And an eighth step of etching the final passivation film to form a take-out electrode. A first step of depositing a continuous MIM film comprising a first insulating film, a metal film, and a second insulating film in order from the bottom on a semiconductor substrate;
A second step of forming an MIM upper electrode on the deposited continuous MIM film ;
The continuous MIM film is patterned to form a capacitor made of the MIM upper electrode, the second insulating film, and the metal film, and the thin film resistor forming region is made of the metal film covered with the second insulating film. A third step of depositing a first passivation film on the semiconductor substrate after forming a thin film resistance electrode and an inductor base electrode made of the metal film covered with the second insulating film in an inductor formation region ;
A fourth step of depositing a thin film resistance film after patterning the first passivation film and the second insulating film on the thin film resistance electrode to expose the thin film resistance electrode ;
A fifth step of depositing a second passivation film on the semiconductor substrate after patterning the thin film resistor film to form a thin film resistor electrically connected to the thin film resistor electrode ;
In order to form a plating electrode electrically connected to each of the MIM upper electrode, the thin film resistance electrode, and the inductor base electrode, a first plating electrode pattern made of a resist is formed, and then the first layer A sixth step of etching the second and first passivation films and the second insulating film exposed from the plating electrode pattern , and further etching the thin film resistor covering the thin film resistance electrode portion ;
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the seventh depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And an eighth step of etching the final passivation film to form a take-out electrode. A first step of depositing a continuous MIM film composed of a first insulating film, a metal film, and a second insulating film on the semiconductor substrate in order from the bottom and depositing an etching stopper layer thereon;
The etching stopper layer and the continuous MIM film are patterned, and a capacitor lower electrode made of the metal film covered with the second insulating film and the etching stopper layer is formed in the capacitor forming region, and the second electrode is formed in the thin film resistor forming region. A thin-film resistance electrode made of the metal film covered with an insulating film and the etching stopper layer is formed, and an inductor base electrode made of the metal film covered with the second insulating film and the etching stopper layer is formed in an inductor formation region, respectively. A second step of depositing a first passivation film on the semiconductor substrate;
A third step of depositing a thin film resistance film after patterning the first passivation film , the etching stopper layer and the second insulating film on the thin film resistance electrode to expose the thin film resistance electrode ;
A fourth step of patterning the deposited thin film resistor film to form a thin film resistor electrically connected to the thin film resistor electrode ;
After patterning the first passivation film, the etching stopper layer, and the second insulating film on the inductor base electrode to expose the inductor base electrode, a second passivation film is deposited on the semiconductor substrate. And the process of
In order to form a plating electrode electrically connected to each of the thin film resistance electrode and the inductor base electrode, and to form a plating electrode serving as a capacitor upper electrode above the capacitor lower electrode, a first layer made of resist is formed. portion after the formation of the plated electrode pattern, the second and first passivation film exposed from the plating electrode patterns of the first layer is selectively etched with respect to the etching stopper layer, further the thin film resistor electrode And a sixth step of etching the thin film resistor covering the top ,
After forming the plated electrode to form a second layer of plating electrode pattern made of a resist, the seventh depositing a final passivation film by removing the second layer and the first layer of the plating electrode pattern made of the resist Process,
And an eighth step of etching the final passivation film to form a take-out electrode.

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