JP3673334B2 - Semiconductor diode - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor diode having a small forward voltage drop and a fast switching operation. In particular, the present invention uses a MOSFET structure and enables two-terminal operation by self-bias.
[Prior art]
[0002]
In a situation where the operating voltage of the VLSI circuit is being reduced, there is a demand for further reducing the forward voltage drop of an output diode used for a switching power supply or the like and reducing the loss. Under the present circumstances, a Schottky barrier diode or a synchronous rectifier diode using a MOSFET can be cited as a diode that satisfies this requirement.
[Problems to be solved by the invention]
[0003]
However, in the Schottky barrier diode, if the potential barrier is reduced to reduce the forward voltage drop, the reverse leakage current increases, and the size of the potential barrier is determined by the metal material. .
[0004]
In addition, a synchronous rectifier diode that is made into a diode by three-terminal operation using a MOSFET can have a considerably lower on-voltage than a Schottky barrier diode, but requires a control gate signal for synchronization for rectification. There is a problem that the loss of the circuit increases.
[0005]
OBJECT OF THE INVENTION
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a MOS type diode which can conduct a two-terminal operation by making a MOSFET structure conductive by self-bias without requiring a gate signal and has a small forward voltage drop. .
[0006]
[Means for Solving the Problems]
  In order to solve the above problems, in the invention according to claim 1 of the present invention, the following means is used so that the self-bias is applied to the MOS gate. Without using the short-circuit structure between the semiconductor region B and the semiconductor region D employed in the conventional power MOSFET structure, that is, the body short-circuit structure, the second electrode E₂And short circuit electrode of MOS gate Gdoing.
[0007]
In order to solve the above problems, in the invention according to claim 2, in addition to the structure of the invention of claim 1, the metal semiconductor alloy layer F and the semiconductor region S are added.₂Schottky barrier region M formed by_SAre connected in parallel, and when the ON voltage of the element of claim 1 increases, the Schottky barrier diode becomes conductive and maintains a low ON voltage.
[0008]
Furthermore, in order to solve the above-mentioned problem, the invention according to claim 3 is a junction J that becomes a PN junction instead of the Schottky barrier region of the structure of the invention of claim 2._FourAre connected in parallel, and the semiconductor region S₂Minority carriers are injected into the substrate so that a low on-state voltage can be realized even under a large current.
[0010]
  And claims4In the invention ofIn the invention of any one of claims 1 to 3Second electrode E₂The gate electrode G is made of the same metal and has an integrated structure.
[0011]
  Furthermore, in order to realize a low on-voltage of the diode,OrClaim6According to the present invention, the threshold voltage of the MOS gate is reduced in order to further reduce the on-voltage of the semiconductor diode according to the first to third aspects of the invention. In the following, claim 5OrClaim6The on-voltage reduction means in the invention will be described.
[0012]
  Claim5In this invention, the effect of lowering the threshold voltage by introducing a fixed charge into the gate oxide film of the MOS gate structure is used.
[0013]
  Claims6In this invention, by forming a MOS gate on the (111) plane of the silicon (Si) crystal plane, the effect of decreasing the threshold voltage by increasing the interface state is used.
[0016]
  Claim 5OrClaim6By applying the present invention to the MOS diode according to the first to third aspects of the present invention, a further lower on-voltage can be realized.
[0017]
Features and principles of operation of the invention
Hereinafter, detailed features and operations of the invention according to the claims will be described.
(Characteristics and Principle of Operation of Claim 1)
The feature of claim 1 is that, as shown in FIG. 1, the second electrode E is used without using the short-circuited structure between the semiconductor region B and the semiconductor region D employed in the conventional power MOSFET structure.₂And the MOS gate electrode G are short-circuited. Another feature is that the threshold voltage of the MOS gate is reduced.
[0018]
Next, the operation principle of this semiconductor element will be described. In FIG. 1, the first electrode E₁And the second electrode E₂The voltage applied between them is junction J_ThreeConsider the case where the polarity is reverse biased. In this state, since the semiconductor region B and the semiconductor region D are not short-circuited, most of the applied voltage is applied to the junction J formed by these regions._ThreeIs spent as a reverse bias voltage. Therefore, this junction J_ThreeA voltage is also applied between the MOS gate electrode G in a parallel connection configuration and the surface of the semiconductor region B immediately below the gate. While the applied voltage is small, the semiconductor region B immediately below the MOS gate is depleted. However, when the applied voltage is equal to or higher than the threshold voltage of the MOS gate, an inversion layer is formed on the surface of the semiconductor region B immediately below the gate. . As a result, the semiconductor region S₁Majority carrier is S₂Through the inversion layer and reverse junction J_ThreeAre discharged and become conductive. In the semiconductor device according to this claim, by reducing the threshold voltage of the MOS gate, the semiconductor device can be rendered conductive with a considerably small on-voltage.
[0019]
As a means for reducing the threshold voltage, there is a method of forming a thin gate oxide film or reducing the impurity density at the oxide film semiconductor interface. Further, ions having a conductivity type opposite to that of the semiconductor region B may be implanted into the oxide semiconductor interface. This ion implantation is generally performed for adjusting the threshold voltage, and a peak density of implanted ions is generated at the oxide semiconductor interface.
[0020]
Next, the operation when a voltage in the direction opposite to the above polarity is applied will be considered. In this case, most of the applied voltage is the junction J₂The reverse bias voltage of the junction J_ThreeOnly a small voltage is applied at the forward bias junction. As a result, J_ThreeSince no voltage is applied so much between the MOS gate in the parallel connection configuration and the semiconductor region B immediately below the gate, no electrical change occurs on the surface of the semiconductor region B immediately below the MOS gate. Thus, for this polarity, the reverse-biased junction J₂In this case, only the applied voltage is consumed, and a non-conductive state is obtained.
[0021]
As described above, in the element of the first aspect of the invention, the first electrode E₁And second electrode E₂Will have a rectifying action between the two terminals. In addition, unlike the conventional synchronous rectification, a self-bias is applied to the MOS gate, so that a gate signal is not required and a two-terminal operation is possible. Further, a low on-voltage characteristic can be expected by reducing the threshold voltage, and since it is a majority carrier device, high-speed switching can also be achieved.
[0022]
(Characteristics and operating principle of the invention according to claim 2)
The feature of the invention according to claim 2 is that, as shown in FIG. 2, in addition to the structure of claim 1, a metal semiconductor alloy layer F and a semiconductor region S are provided.₂Schottky barrier region M_SAre formed so as to be connected in parallel, and the MOS gate structure is formed to extend over the semiconductor region D and the metal semiconductor alloy layer F. Further, after the threshold voltage is reduced, the second electrode E is formed in the same manner as in the first aspect.₂, Third electrode E_ThreeIn addition, the MOS gate electrode G is short-circuited to enable two-terminal operation. Next, the operation principle of this semiconductor element will be described.
[0023]
In FIG. 2, the first electrode E as in the element according to the invention of claim 1 is used.₁And the second electrode E₂The polarity of the voltage applied between them is_ThreeConsider the case where becomes a reverse bias voltage. In this case, as described above, the forward conduction state is established, and the Schottky barrier region M_SIs also forward. When the applied voltage is increased to the extent that an inversion layer is formed on the surface of the semiconductor region B immediately below the gate, the semiconductor region S₁Majority carrier is S₂Through the inversion layer and reverse bias junction J_ThreeThe current is conducted. In this state, the semiconductor region S immediately below the MOS gate.₂An accumulation layer is formed on the surface, and a Schottky barrier region M directly under the MOS gate._SHowever, due to the presence of the accumulation layer, some current flows in a leaky manner due to a tunnel effect or the like. When the applied voltage is further increased, Schottky barriers other than those directly under the MOS gate become conductive, and the conductive region is expanded, so that the on-resistance can be kept small.
[0024]
When a voltage opposite in polarity to the above voltage polarity is applied, as in the first aspect of the invention, no electrical change occurs on the surface of the semiconductor region B immediately below the MOS gate, and the Schottky barrier is also reversed. Directional operation is performed, and a non-conduction state is established. Further, the semiconductor region S₂Since the MOS gate on the surface also serves as a field plate structure, it works to alleviate the electric field at the junction end of the Schottky barrier and increase the breakdown voltage.
[0025]
As described above, also in the element of the invention of claim 2, the first electrode E₁And second electrode E₂Since a rectifying action is applied between the two terminals and a self-bias is applied to the MOS gate, a two-terminal operation is possible. Further, a low on-voltage characteristic can be expected by reducing the threshold voltage, and since it is a majority carrier device, high-speed switching can also be achieved.
[0026]
(Characteristics and operating principle of the invention according to claim 3)
As shown in FIG. 3, the feature point of claim 3 is a Schottky barrier region M in the invention of claim 2._SInstead of J, it becomes a normal PN junction_FourIs formed in parallel connection. Further, as in the first and second aspects of the invention, the second electrode E₂, Third electrode E_ThreeAnother feature is that the MOS gate electrode G is short-circuited, enabling two-terminal operation. Next, the operation principle of this semiconductor element will be described.
[0027]
In FIG. 3, as in the case of the invention of claim 1, the first electrode E₁And the second electrode E₂The voltage applied between them is junction J_ThreeConsider the case where the polarity is reverse biased. In this case, as described above, the forward conductive state is established, and the semiconductor region I and the semiconductor region S.₂Joined J formed by_FourIs also forward. Applied voltage is junction J_Four1 is exactly the same as the element having the structure shown in FIG. 1, and the conduction current mainly passes through the inversion layer formed on the surface of the semiconductor region B immediately below the MOS gate. In addition to this, the semiconductor region S₂A tunnel current is applied by a junction formed by the accumulation layer and the semiconductor region I on the surface of the semiconductor layer.
[0028]
Applied voltage is junction J_FourWhen this voltage exceeds the conduction start voltage, the junction J_FourLesser carriers are in region S₂This semiconductor region S is injected into₂This produces a conductivity modulation effect, and operates at a forward voltage of a normal PN junction. Furthermore, J_FourThe minority carriers injected more reach the semiconductor region B and accumulate in this semiconductor region, so that the semiconductor regions B and S₂J made by₂Works to be forward-biased. Therefore, this effect is achieved by the semiconductor region S₂The majority carriers are injected into the region B and reach the region D, so that the emitters are respectively connected to the semiconductor region S.₂The parasitic bipolar transistor having the semiconductor region B as the base and the semiconductor region D as the collector is operated, the conduction region is further expanded, and low on-resistance characteristics can be expected even under a large current.
[0029]
However, in the above operation, the joint J_FourMinority carriers are injected from, so there is a concern about an increase in reverse recovery time when switching from the forward direction to the reverse direction. In the invention of claim 3, in order to suppress this effect, the MOS gate structure is bonded to the junction J._FourIn the state where the reverse voltage is applied to the device in the reverse recovery state, the semiconductor region S immediately below the MOS gate is formed.₂An inversion layer is formed. By this action, carriers injected in the forward direction in the reverse recovery state and accumulated in the semiconductor region B are transferred to the semiconductor region S immediately below the MOS gate.₂By pulling out from the semiconductor region I through the inversion layer, an increase in reverse recovery time is suppressed.
[0030]
Further, when a reverse voltage is applied to the diode of the present invention, the semiconductor region S directly under the MOS gate₂The inversion layer formed in (1) operates so as to short-circuit between the semiconductor region D and the semiconductor region B, and thus has the effect of reducing the reverse leakage current of the parasitic bipolar transistor described above. Therefore, according to the present invention, a semiconductor diode with a small reverse leakage current can be provided.
[0031]
As described above, according to the third aspect of the present invention, as in the first aspect, the two-terminal operation is possible, and the on-resistance is reduced under a large current by injecting minority carriers.
[0033]
  (Claims4Features and principles of the invention)
  Claims 1 to3In the operation of the diode of the invention in claim4According to the inventionWhatSecond electrode E₂In addition, the gate electrode G can be made of the same metal and have an integrated structure, so that it is easy to manufacture and the device integration density can be improved.
[0034]
  Next, claim 5OrClaim6Although the features and principles of the invention according to the present invention will be described, these means are different, but the object is the same, and the threshold voltage of the MOS gate is reduced.
[0035]
  (Claims5Features and principles of the invention)
  Claim5In this invention, in order to reduce the threshold voltage of the MOS gate, a fixed charge is introduced into the gate oxide film. By this action, carriers are induced in the semiconductor region directly under the gate, an inversion layer is easily formed, and the threshold voltage can be reduced. In general, the threshold voltage adjustment method by ion implantation is performed by changing the doping at the oxide semiconductor interface, and the peak density of the implanted ions is generated at the oxide semiconductor interface. . Accordingly, a deep and relatively high dose of ions is implanted through the oxide film so as to reach the semiconductor interface, and there is a problem that damage to the gate oxide film is increased.
[0036]
The introduction of the fixed charge into the gate oxide film according to the present invention similarly uses the ion implantation method. However, the fixed charge is mainly formed in the gate oxide film to reduce the threshold voltage, and is shallow. In addition, low dose ion implantation is performed. Therefore, there is almost no doping at the oxide semiconductor interface, and damage to the oxide film can be suppressed. Further, the threshold voltage voltage shift due to the introduction of the fixed charge in the gate oxide film according to the present invention is almost proportional to the fixed charge amount in the oxide film, so that the threshold voltage can be easily controlled.
[0037]
  (Claims6Features and principles of the invention)
  Claim6The invention of claim5Similar to the object of the present invention, the threshold voltage of the MOS gate is reduced, and as a means therefor, the MOS gate structure is formed on the (111) plane of the silicon crystal plane.
[0038]
Compared to the (100) plane of silicon, the interface state density is 10 orders of magnitude greater on the (111) plane.¹¹cm^-2The threshold voltage is lowered by this effect.
[0039]
(Characteristics of embodiment using polysilicon gate as MOS gate material)
  This example isPolysilicon gate as MOS gate materialUseIncreasing the impurity density in the polysilicon gateByAs a result, the work function difference between the polysilicon gate and the semiconductor directly under the MOS gate increases, and as a result, the threshold voltage can be reduced.
[0040]
  This exampleAlthough the impurity density of the polysilicon may be increased during the process, it can be performed mainly by re-doping the polysilicon portion by ion implantation and low-temperature annealing after the end of the diffusion process. Therefore, ion implantation is possible only in the polysilicon portion, and the gate oxide film is not damaged at all. Further, there is a feature that the threshold voltage can be easily readjusted after the diffusion process is completed.
[0041]
(Characteristics of embodiment using metal as MOS gate material)
  This example isMetal as MOS gate materialUseThe threshold voltage is reduced by using a metal material that increases the work function difference between the metal and the semiconductor in the MOS gate.
[0042]
  Thus, claim 5OrClaim6The invention of claim 1 to claim3By applying the present invention to the diode of the invention, the threshold voltage of the MOS gate constituting the diode is reduced, and a further lower on-voltage can be realized.
[0043]
【Example】
Specific embodiments of the invention of each claim will be described below.
[0044]
(Embodiment corresponding to the invention of claim 1)
FIG. 4 is a sectional structural view showing an embodiment of the invention of claim 1 in which a diode using a MOSFET structure is realized by a vertical structure of silicon. In this figure, the semiconductor region S of the first conductivity type in FIG.₁, Semiconductor region S₂And the semiconductor region D are respectively N-conducting semiconductor regions N_S ⁺, Semiconductor region N_SAnd semiconductor region N_D ⁺It corresponds to. In addition, the semiconductor region B which is the semiconductor region of the second conductivity type in FIG. 1 is the semiconductor region P of the P conductivity type._BIt corresponds to. Note that the first electrode E in FIG.₁Corresponds to the cathode electrode K of FIG. 4, and the second electrode E of FIG.₂As for the MOS gate electrode G, the anode electrode A is integrally formed in FIG. However, in the embodiment of FIG. 4, it is a case where the self-alignment process is used, and the anode electrode A and the gate oxide film SiO.₂In between, a polysilicon layer Poly-Si is formed.
[0045]
Next, fabrication of a diode using the MOSFET structure of this embodiment will be described. In the device of the present invention, it is necessary to select the impurity density of the silicon substrate used for fabrication in accordance with the reverse breakdown voltage. In this embodiment, the case of realizing low on-resistance with low breakdown voltage is taken as an example. explain.
[0046]
In production, N / N⁺The epitaxial growth substrate is used. The resistivity of the substrate is 0.015 Ωcm or less and the thickness is about 500 μm. The epitaxial growth layer is about 0.5 Ωcm and the thickness is about 3 μm.
[0047]
In the manufacturing process, a field oxide film having a thickness of 1 μm is first formed by steam oxidation, and the thermal oxide film is selectively etched by photolithography to form an active region of the device. Subsequently, a gate oxide film SiO having a thickness of about 200 mm is formed by dry oxidation for forming a gate oxide film.₂Then, a polysilicon layer Poly-Si is formed to a thickness of about 1 μm by CVD.
[0048]
Next, similarly to a normal vertical MOSFET, polysilicon and a gate oxide film are selectively opened, and a semiconductor region P is formed by a self-alignment process._BAnd semiconductor region N_DForm. In this case, the semiconductor region P_BSurface density of about 3 × 10¹⁸/ Cm^ThreeThe diffusion depth is about 2 μm and the semiconductor region N_DSurface density of about 10²⁰/ Cm^ThreeThe diffusion depth is about 1 μm. In the process of the present embodiment, as a means for reducing the threshold voltage of the MOS gate, the gate oxide film is formed as thin as about 200 mm, and the impurity density at the oxide film semiconductor interface is set to 10.¹⁷cm^-3It is lowered to the extent. Further, the region P is formed on the oxide semiconductor interface by means of a means for reducing the threshold voltage by ion implantation that is generally performed._BAnd reverse conductivity type phosphorus ions are implanted. In order to further reduce the threshold value, the gate oxide film is thinned to about 100 mm and the impurity density at the oxide film semiconductor interface is set to 10.¹⁷cm^-3The following is desired.
[0049]
Further, in order to activate the implanted ions and recover the damage, the semiconductor diode according to claim 1 shown in FIG. 4 is realized by performing an annealing process at 950 ° C. and depositing metal on both surfaces to form electrodes. .
[0050]
Next, the operation of this semiconductor element will be described. In FIG. 4, when a positive voltage is applied to the anode electrode with respect to the cathode electrode,_ThreeBecomes the reverse bias voltage._ThreeThus, an effective gate voltage is also applied to the MOS gate in a parallel connection configuration. While this applied voltage is small, the semiconductor region B immediately below the MOS gate is depleted, but when the applied voltage is equal to or higher than the threshold voltage of the MOS gate, an inversion layer is formed. As a result, the semiconductor region N_S ⁺Majority carriers in region N_SAnd the reverse bias junction J through the inversion layer._ThreeDischarged from the semiconductor region N_DReaches the conductive state. In the semiconductor device of this embodiment, by reducing the threshold voltage of the MOS gate G, it becomes possible to make it conductive with a considerably small voltage.
[0051]
Next, when a voltage in the direction opposite to the above polarity is applied, most of the applied voltage is the junction J₂The reverse bias voltage of the junction J_ThreeOnly a slight forward bias voltage is applied. As a result, J_ThreeSince no voltage is applied to the MOS gate in a parallel connection configuration, no electrical change occurs on the surface of the semiconductor region B immediately below the MOS gate. Thus, for this polarity, the reverse-biased junction J₂Only the applied voltage is consumed, and this semiconductor diode becomes non-conductive.
[0052]
As described above, the device of the embodiment shown in FIG. 4 has a rectifying action between the anode electrode and the cathode electrode. In addition, unlike the conventional synchronous rectification, a self-bias is applied to the MOS gate, so that no gate signal is required, and a two-terminal operation using the anode electrode A and the cathode electrode K is possible. Further, a low on-voltage characteristic can be expected by reducing the threshold voltage, and since it is a majority carrier device, high-speed switching can also be achieved. As will be described later in detail with reference to FIG. 8, the electrode is formed on the semiconductor region P at the periphery of the device of this embodiment._BThe PN junction diode portion may be formed by ohmic contact. The conduction region is expanded by the action of the PN junction diode, and a reduction in on-resistance characteristics can be expected even under a large current.
[0053]
The above embodiment can be applied to a device having a trench structure as shown in FIG. 5 and can be easily realized by performing reactive ion etching. Each semiconductor region in FIG. 5 and the operation mechanism are the same as those in FIG.
[0054]
(Embodiment corresponding to invention of Claim 2)
Next, the invention of claim 2 will be described. FIG. 6 is a sectional structural view showing an embodiment of the invention of claim 2 in which a diode using a MOSFET structure is implemented by a vertical structure of silicon. In this figure, the semiconductor region S of the first conductivity type in FIG.₁, Semiconductor region S₂And the semiconductor region D are respectively N-conducting semiconductor regions N_S ⁺, Semiconductor region N_SAnd semiconductor region N_D ⁺It corresponds to. Further, the second conductivity type semiconductor region B in FIG. 2 is a P conductivity type semiconductor region P._BMetal semiconductor alloy layer F and Schottky barrier region M_SThe same applies to FIG. Note that the first electrode E in FIG.₁Corresponds to the cathode electrode K of FIG. 6, and the second electrode E of FIG.₂, Third electrode E_ThreeAs for the MOS gate electrode G, the anode electrode A is integrally formed in FIG. 6 also shows a case where the self-alignment process is used as in the embodiment of FIG. 4, and the anode electrode and the gate oxide film SiO.₂In between, a polysilicon layer Poly-Si is formed.
[0055]
Next, fabrication of a diode using the MOSFET structure of this embodiment will be described. Also in this embodiment, the semiconductor region P is formed by a substrate used for manufacturing and a self-alignment process._BAnd semiconductor region N_DThe ion implantation process performed for reducing the threshold voltage of the MOS gate and the annealing process thereof are the same as those in the first embodiment. In this embodiment, the following Schottky barrier region M_SA through-hole process is added for formation. Subsequently, a metal is deposited and heat-treated at an appropriate temperature according to the metal material, thereby forming a silicide layer corresponding to the metal semiconductor alloy layer F in the silicon interface, and the Schottky barrier region M_SForm. Also, in this process, each electrode is formed at the same time, and the second electrode E in FIG.₂, Third electrode E_ThreeIn this embodiment, the MOS gate electrode G and the MOS gate electrode G are short-circuited to become an anode electrode A having an integral structure.
[0056]
Next, the operation principle of this semiconductor element will be described. In FIG. 6, as in the first aspect of the invention, the first electrode E₁And the second electrode E₂The polarity of the voltage applied between them is_ThreeConsider a forward conduction state in which becomes a reverse bias voltage. In this state, the Schottky barrier region M_SIs also forward. The applied voltage is applied to the semiconductor region P directly under the gate._BWhen the inversion layer is formed on the surface, the semiconductor region N_S ⁺Majority carriers in the semiconductor region N_SThrough the inversion layer and reverse junction J_ThreeAre discharged and become conductive. In this state, the semiconductor region N directly under the MOS gate_SAn accumulation layer is formed on the surface, and a Schottky barrier region M directly under the MOS gate._SIn FIG. 5, a certain amount of current flows due to the tunnel effect due to the presence of the accumulation layer. In addition, the density of current flowing through the inversion layer increases and the voltage drop increases, so when the applied voltage increases, Schottky barriers other than those directly under the MOS gate also conduct, forming a conduction region with the inversion layer. Therefore, low on-resistance can be maintained.
[0057]
When a voltage opposite to the above voltage polarity is applied, the semiconductor region P immediately below the MOS gate is applied._BThere is no electrical change on the surface, and the Schottky barrier also operates in the reverse direction, resulting in a non-conductive state. Also, the semiconductor region N_SSince the MOS gate on the surface also serves as a field plate structure, it works to alleviate the electric field at the junction end of the Schottky barrier and increase the breakdown voltage.
[0058]
As described above, the embodiment of FIG. 6 showing the invention of claim 2 of the present invention also has a rectifying action between the anode A and the cathode K terminal, can be operated at two terminals, and has low on-voltage characteristics. High speed switching can also be achieved. In the invention of claim 2 as well, a device having a trench structure can be realized, and the structure is shown in FIG. The operation is the same as that of the device having the structure shown in FIG.
[0059]
(Embodiment corresponding to invention of Claim 3)
FIG. 8 is a sectional structural view showing an embodiment of the invention according to claim 3 in which a diode using a MOSFET structure is realized by a vertical structure of silicon. In this figure, the semiconductor region S of the first conductivity type in FIG.₁, Semiconductor region S₂And the semiconductor region D are respectively N-conducting semiconductor regions N_S ⁺, Semiconductor region N_SAnd semiconductor region N_D ⁺It corresponds to. Further, the second conductivity type semiconductor region B and the semiconductor region I in FIG._BAnd semiconductor region P_IIt corresponds to. Note that the first electrode E in FIG.₁Corresponds to the cathode electrode K of FIG. 8, and the second electrode E of FIG.₂, Third electrode E_ThreeAs for the MOS gate electrode G, the anode electrode A is integrally formed in FIG. FIG. 8 also shows a case where the self-alignment process is used, and the anode electrode and the gate oxide film SiO.₂In between, a polysilicon layer Poly-Si is formed.
[0060]
Next, fabrication of a diode using the MOSFET structure of this embodiment will be described. Since this device is suitable for a high voltage diode, the case of an embodiment of a high voltage device will be described.
[0061]
In production, N / N⁺The epitaxial growth substrate is used. The resistivity of the substrate is 0.015 Ωcm or less and the thickness is about 500 μm. For the epitaxial growth layer, the resistivity is about several Ωcm and the thickness is about several tens of μm.
[0062]
In the manufacturing process, an oxide film is first formed by steam oxidation, and the region P is formed._IIn order to selectively form the film, the thermal oxide film is etched by photolithography. The subsequent process is the same as that of the first aspect of the invention._BIn order to increase the withstand voltage, it is necessary to adjust the depth according to the withstand voltage to form a diffusion depth of about several μm. Furthermore, in the reverse direction of the element to which the high voltage is applied, the semiconductor region P is prevented so that the high voltage is not applied to the gate oxide film._BAnd semiconductor region P_IIt is necessary to adjust the interval. In addition, it is necessary to take measures for increasing the breakdown voltage such as a field plate structure and a guard ring structure in joining the ends of the device.
[0063]
The other processes are almost the same as those of the invention of claim 1, and after forming the electrodes, the embodiment of claim 3 shown in FIG. 8 can be realized. Also in the embodiment of FIG. 8, the second electrode E of FIG.₂, Third electrode E_ThreeAs for the MOS gate electrode G, the anode electrode A has an integral structure. Next, the operation of this semiconductor diode will be described.
[0064]
In FIG. 8, the anode electrode has a positive polarity with respect to the cathode electrode, and the magnitude of the applied voltage is the junction J_FourThe behavior of the element when it is smaller than the conduction start voltage is exactly the same as that of the embodiment of FIG. 4 of the above-mentioned claim 1, and the conduction current is mainly the semiconductor region P directly under the MOS gate._BThrough the inversion layer formed on the surface of the semiconductor region N_SAnd a semiconductor region P formed on the surface of the semiconductor layer P_ITunnel current due to the junction is added. As the voltage drop increases due to a large increase in the density of the current flowing through the inversion layer, the applied voltage becomes the junction J_FourWhen this voltage exceeds the conduction start voltage, the junction J_FourMinority carrier holes are present in the semiconductor region N_STo produce a conductivity modulation effect in this semiconductor region. Furthermore, J_FourThe holes injected more than the semiconductor region P_BReaches the semiconductor region P and accumulates in this semiconductor region._BAnd semiconductor region N_SJ made by₂Works to be forward-biased.
[0065]
Therefore, this action is caused by the semiconductor region N_SMajority carriers in the semiconductor region P_BAnd the semiconductor region N_D ⁺So that each emitter is connected to the semiconductor region N._S, Base the semiconductor region P_B, Collector the semiconductor region N_D ⁺As a result, the conduction region is further expanded, and a reduction in on-resistance characteristics can be expected even under a large current.
[0066]
In addition, as described above, the MOS gate structure has a junction J for the purpose of suppressing an increase in reverse recovery time when switching from the forward direction to the reverse direction._FourSemiconductor region P forming_IIn a state where a reverse voltage is applied to the device in a reverse recovery state, the semiconductor region N immediately below the MOS gate is formed._SA P-type inversion layer is formed on the substrate. By this action, the semiconductor region P is injected into the forward direction in the reverse recovery state._BThe carriers accumulated in the semiconductor region P are routed through the P-type inversion layer immediately below the MOS gate._IBy pulling out from, the increase in reverse recovery time can be suppressed.
[0067]
Further, the semiconductor region N immediately below the MOS gate formed when a reverse voltage is applied to the diode of the present invention._SThe P-type inversion layer on the surface is the semiconductor region N of the parasitic NPN transistor described above._D ⁺And semiconductor region P_BSince the carrier is prevented from being injected by operating so as to short-circuit the junction constituted by, there is also an effect of reducing the reverse leakage current.
[0068]
In the high voltage application state in the reverse direction,₂And J_FourThe depletion layer extending from the gate behaves so that a high voltage is not applied to the gate oxide film. As described above, the element of the embodiment shown in FIG. 8 can be expected to have a rectifying action with a two-terminal operation using the anode electrode A and the cathode electrode K and a low on-voltage characteristic, as in the previous embodiment. , Semiconductor region N from PN junction_SA low on-state voltage can be expected even in a high current state from the hole injection into. The above embodiment can also be applied to the trench structure device of the embodiment as shown in FIGS. 9 and 10, and can be easily realized by performing reactive ion etching. Each semiconductor region and the operation mechanism in FIGS. 9 and 10 are the same as those in FIG.
[0069]
Although the diode structures in the above embodiments are all described in the case of the vertical structure, as shown in FIG. 11, a lateral device that can be easily applied to an integrated circuit or the like can be realized. In this lateral diode structure, the semiconductor region D is also the semiconductor region S.₁Is also present on one surface side of the semiconductor substrate region B across a part of the semiconductor substrate region B, and the first electrode E₁, Second electrode E₂The MOS gate electrode G is also present on one side of the semiconductor substrate.
[0070]
FIGS. 12, 13 and 14 are embodiments in which the diode using the double diffusion MOSFET structure of the invention of claims 1 to 3 is realized by a lateral structure of silicon, and each is implemented by a vertical structure. This corresponds to the horizontal shape shown in FIGS. Since these principles and features are exactly the same as those of the respective vertical structures, description thereof will be omitted. In the embodiments of FIGS. 12 to 14, the same symbols are used for the same symbols as those used in FIGS. 4, 6, and 8, respectively. Furthermore, the embodiments shown in FIGS. 12 to 14 can adopt a trench gate structure in the same manner as the embodiments shown in FIGS.
[0071]
  Next, an example in which the present invention is applied to a lateral MOSFET structure will be described with reference to FIG.This figure is a cross-sectional structure diagram in which a diode using a normal lateral MOSFET structure is realized with silicon. In this figure, the semiconductor substrate region B in FIG._B, Semiconductor region S of the opposite conductivity type₁And the semiconductor region D are respectively connected to the semiconductor region N._SAnd semiconductor region N_DIt corresponds to. In this embodiment, N_B ⁺P / N with substrate area⁺Although an epitaxial growth substrate is used, it may be formed on a P well layer diffused on a P substrate and an N substrate.
[0072]
Electrode E in FIG.₁Corresponds to the cathode electrode K in FIG. 15, and the electrode E in FIG.₂As for the MOS gate electrode G, the anode electrode A having an integral structure is also used in FIG. The MOS gate is a polysilicon gate.
[0073]
The manufacture of a diode using the MOSFET structure of this embodiment will be described. As a first step, the substrate is thermally oxidized to form a field oxide film. Next, the field oxide film corresponding to the gate oxide portion is removed by photolithography, and a gate oxide film of about several hundreds of inches is formed by dry oxidation. Subsequently, polysilicon is deposited by low pressure CVD. Further, the polysilicon and gate oxide film in regions corresponding to the source and drain regions of the MOSFET are removed by a self-alignment process, and an N-type region is formed by an ion implantation process and annealing diffusion. Next, an oxide film is deposited by plasma CVD, and the deposited oxide film is selectively etched by photolithography so that only the polysilicon gate and the anode electrode are short-circuited. Next, the embodiment of FIG. 15 is realized by forming electrodes. The semiconductor diode of the embodiment of FIG. 15 is characterized in that the device can be realized by a single diffusion process without double diffusion. The principle of operation of this semiconductor diode is the same as that of the embodiment shown in FIG.
[0074]
  Each of the above claims 1 to claims3For the invention of4Second electrode E according to the invention₂In this embodiment, an integrated structure of the gate electrode G is applied.
[0075]
  Next, claim 5OrClaim6An embodiment corresponding to the invention will be described. As mentioned above, claim 5OrClaim6The object of the present invention is as follows.3In order to further reduce the on-voltage of the semiconductor diode according to the present invention, the threshold voltage of the MOS gate is reduced. For these inventions, claims 1 to3It can be applied to any of the inventions.
[0076]
  (Claims5Example corresponding to the invention of
  Claim5The method of reducing the threshold voltage of the MOS gate according to the invention is to introduce fixed charges into the gate oxide film. By this action, carriers are induced in the semiconductor region directly under the gate, an inversion layer is easily formed, and the threshold voltage can be reduced. As this specific method, an ion implantation method is preferable from the viewpoint of controllability.
[0077]
  Next, the claim5An embodiment corresponding to the invention will be described. This claimOf 5The invention is as follows.3The present invention can be applied to any of the inventions, but in this embodiment, a case where the invention is applied to the invention of claim 1 will be described.
[0078]
As in the invention of claim 1, the process before the introduction of the fixed charge is performed by selectively opening the polysilicon and the gate oxide film and then by the self-line process to form the semiconductor region P._BAnd semiconductor region N_DAnd further to contact hole formation.
[0079]
According to the first aspect of the present invention, since an inversion layer having electrons as carriers is formed immediately below the gate, a positive charge is required as a fixed charge in order to reduce the threshold voltage. For example, phosphorus ion (P⁺) Will be described. Further, an example will be described in which the polysilicon gate layer is formed as thin as about 0.3 μm so that a fixed charge can be easily formed in the gate oxide film. Other process conditions are the same as those in the first embodiment. When phosphorus ions are implanted into this structure, in order to avoid damage due to ion implantation of the oxide film and to suppress doping at the oxide semiconductor interface, implantation is mainly performed so that ions stop in the polysilicon and oxide film regions. In addition, it is necessary to carry out under ion implantation conditions (acceleration voltage and dose) that can reduce the threshold voltage.
[0080]
Therefore, in this embodiment, in the implantation distribution of phosphorus ions expressed by the Gaussian distribution in the polysilicon and the gate oxide film region, the position where the peak density NPEAK is given is about 0.1 μm from the surface of the polysilicon. Is about 2 × 10²⁰cm^-3So that the acceleration voltage E_A80 keV, dose ST 2 × 10¹⁵cm^-2Set to be about. Under this ion implantation condition, the peak density exists in the polysilicon, and the dose amount of phosphorus ions in the oxide film is about 10%.¹¹cm^-2Since it is relatively small, deterioration of the oxide film can be suppressed. Further, the ion implantation density at the oxide semiconductor interface is determined by the semiconductor region P._BTherefore, the doping effect is small. Furthermore, the threshold voltage shift due to the ion implantation conditions is substantially determined by the amount of ions in the gate oxide film, and as a result, the threshold voltage can be expected to be about 0.1V.
[0081]
After ion implantation for reducing the threshold voltage, heat treatment is performed at a relatively low temperature of about 950 ° C. for about 30 minutes, thereby suppressing ion diffusion and activating the implanted ions and damaging the oxide film due to the ion implantation. Do recovery. If an electrode is formed following this process, a diode having a very low on-voltage to which the invention of claim 5 is applied can be realized.
[0082]
In this embodiment, the method of reducing the threshold voltage mainly for introducing a fixed charge into the oxide film has been described. Of course, the peak density of implanted ions at the interface of the oxide film semiconductor is generally performed. You may use together with the ion implantation method performed so that it may occur. In this embodiment, the case where the thickness of the polysilicon is 0.3 μm and the thickness of the oxide film is 0.05 μm is shown. Of course, even if these thicknesses are changed, the polysilicon is further removed and directly applied to the oxide film. Even if ion implantation is performed, it can be realized by appropriately selecting optimum ion implantation conditions.
[0083]
In this embodiment, the case of phosphorus ions has been described as an example of positive charges, but other positive ions may be used. However, from the viewpoint of device reliability, ions having a large mass and a small diffusion coefficient are desirable in order to reduce fluctuations in threshold voltage. Note that a device in which the conductivity type of each region in the diode of the above embodiment is reversed can be realized. In this case, however, the fixed charge necessary for reducing the threshold voltage is a negative charge.
[0084]
  (Claims6Example corresponding to the invention of
  Claim6The method of reducing the threshold voltage of the MOS gate according to the present invention is to form the MOS gate structure on the (111) plane of the silicon crystal surface having a large interface state, and the threshold value increases as the interface state density increases. The effect of lowering the value voltage is used. The interface state density of the (100) plane of silicon is 5 × 10^Tencm^-2In the (111) plane, 5 × 10 that is one digit larger¹¹cm^-2It will be about.
[0085]
  This claim6In practicing the present invention, it is important to specify the crystal plane of the substrate so that the crystal plane forming the MOS gate structure is the (111) plane.3The present invention can be applied to any of these inventions. As shown in FIG. 4 showing an embodiment of the present invention, when a MOS gate structure is formed on the substrate surface, the substrate surface is a (111) plane. Further, when the MOS gate structure is formed with the (111) plane being the surface perpendicular to the substrate surface, such as the trench gate of FIG. 5 showing the embodiment of the present invention, the substrate surface is the (110) plane. It is necessary to specify as follows.
[0086]
When the process of the device of FIG. 4 in the embodiment of claim 1 is performed on the (100) plane and the (111) plane, the theoretical value of the threshold voltage is compared. The voltage is 65 V and 0.23 V on the (111) plane, and the (111) plane is effective in reducing the threshold voltage.
[0087]
In this embodiment, the MOS gate is formed on the (111) plane. Of course, the MOS gate is formed on the (100) plane, and other measures for reducing the threshold voltage are taken by employing means such as a thin gate oxide film. May be.
[0088]
  (Use polysilicon as gate electrode material for MOS gateExample)
  thisThe method for reducing the threshold voltage of the MOS gate is the case where polysilicon is used as the gate electrode material of the MOS gate, and the work function difference between the polysilicon gate and the semiconductor is increased by increasing the impurity density in the polysilicon. To increase the threshold voltage. This invention also claims 1 to3It can be applied to any of the inventions.
[0089]
  First, the diode of FIG.This exampleThe case where is applied will be described.thisThe impurity density of polysilicon may be increased at the same time as the diffusion process. However, in order not to adversely affect the characteristics such as breakdown voltage and channel resistance, ion implantation and low temperature are performed after the diffusion process so as not to change the impurity profile. It is preferable to perform the annealing. In addition, the threshold voltage can be readjusted by introducing a preceding monitor into the process, evaluating the threshold voltage, and using this process again.
[0090]
Also in this embodiment, the substrate used for device fabrication and the semiconductor region P by self-alignment process using polysilicon._BAnd N_DThe process up to the formation is the same as the diode embodiment shown in FIG. However, it is desirable that the thickness of the polysilicon layer is relatively thin in order to make the impurity density uniform throughout the polysilicon layer. Therefore, in this embodiment, this thickness is set to about 0.5 μm.
[0091]
Next, a process for reducing the threshold voltage will be described. In the embodiment of FIG. 4 according to the invention of claim 1, the semiconductor region P immediately below the polysilicon gate and the MOS gate is provided._BIn order to increase the work function difference, it is necessary to introduce an N-type impurity into the polysilicon gate. In this embodiment, phosphorus is introduced as an impurity by ion implantation. Here, according to the profile inside the device, the dose amount is 10% in the average density in the polysilicon.²⁰cm^-3To 10^{twenty one}cm^-3The acceleration voltage is set to about 100 keV.
[0092]
Under this condition, the projection range that gives the peak density of the implanted ions is about 0.13 μm, and the projection dispersion that gives the spread of the distribution is about 0.06 μm, so that the phosphorus ions extend from the surface of the polysilicon to about 0.2 μm. Will be injected. Therefore, the implanted ions do not reach the gate oxide film, and the oxide film is hardly damaged.
[0093]
Next, annealing diffusion is performed at a temperature of about 950 ° C. in order to make the impurity density of the entire polysilicon uniform. By this process, the semiconductor region N in the diode of FIG._D ⁺As described above, the depth of the channel is as deep as about 1 μm and does not reach the region where the channel is formed. Therefore, there is no adverse effect on characteristics such as channel resistance and breakdown voltage.
[0094]
Next, the threshold voltage when the average impurity density in the polysilicon is changed is taken for an example of a device having an impurity profile and a gate oxide film thickness of 200 mm in the diode of FIG. 4 according to the embodiment of claim 1. Compare the theoretical values of. However, in this case, assuming that the MOS gate is formed on the (111) plane, the interface state density is 5 × 10 5.¹¹cm^-2Is assumed. The calculation result shows that the average impurity density of polysilicon is 10²⁰cm^-3The theoretical value of the threshold voltage is about 0.203 V, and the average impurity density of polysilicon is 10^{twenty one}cm^-3Is about 0.143V. Therefore, the higher the average impurity density of polysilicon, the lower the threshold voltage.
[0095]
  This exampleClaim 2OrClaim3However, when the Schottky barrier and the P-type diffusion layer are exposed on the silicon surface as in claims 2 and 3, the regions where these are formed are preliminarily formed in an oxide film or the like. Therefore, it is necessary to perform ion implantation after masking.
[0096]
In this embodiment, phosphorus is used, but other impurities may be used as long as they are N-type. The case where the N channel is formed has been described, but the P channel may of course be used. In this case, the polysilicon gate needs to have a P type.
[0097]
  (Use metal as electrode material for MOS gateExample)
  thisThe method of reducing the threshold voltage of the MOS gate is a case where a metal is used as the electrode material of the MOS gate. A metal material that increases the work function difference between the metal and the semiconductor is selected, and This is intended to reduce the voltage. The present invention is also applicable to any one of the first to third aspects of the invention, and may be carried out in the final electrode formation process.
[0098]
The important point of this method is that the magnitude of the metal work function of the MOS gate is determined in accordance with the conductivity type of the inversion layer.
[0099]
When the semiconductor region immediately below the MOS gate is P-type and an N-type inversion layer is formed, by selecting a metal having a small metal work function, such as titanium (Ti), chromium (Cr), and aluminum (Al). The work function difference with the semiconductor becomes large, and the threshold voltage can be reduced. Conversely, when the semiconductor region directly under the MOS gate is N-type and a P-type inversion layer is formed, a metal having a large metal work function, such as platinum (Pt), palladium (Pd), or nickel (Ni), is selected. There is a need to. There are many metal materials other than those described above, but chemically stable metals such as the above metals are desirable. For forming these metals, an ordinary sputtering apparatus or an electron beam evaporation apparatus is used.
[0100]
  This exampleIs applied to the diode of FIG. 6 and FIG. 7 showing the embodiment according to the invention of claim 2, it goes without saying that it can be realized by one electrode material serving as the MOS gate, ohmic electrode and Schottky barrier metal as electrodes. .
[0101]
  As described above, claim 5OrClaim6In any of the inventions, the threshold voltage of the MOS gate is reduced.3By applying the present invention to the diode of the invention, the forward conduction start voltage can be made as close as possible to 0 V, and characteristics close to an ideal diode can be expected.
[0102]
As mentioned above, although the invention of each claim was mentioned, it is also possible to realize a device having a configuration in which each of the embodiments is combined, and a device in which the conductivity type of each device is reversed is easily realized in the same manner. it can.
[0103]
【The invention's effect】
As described above, according to the present invention, a two-terminal semiconductor diode capable of high-speed operation using a MOSFET structure having a smaller forward voltage drop than that of a conventional semiconductor diode can be obtained.
[Brief description of the drawings]
FIG. 1 is a view for explaining a basic structure of a two-terminal type semiconductor diode using a MOSFET structure according to the first aspect of the present invention;
FIG. 2 is a view for explaining a basic structure of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a Schottky barrier according to the second aspect of the present invention;
FIG. 3 is a view for explaining a basic structure of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a PN junction in the invention of claim 3;
FIG. 4 is a drawing showing an embodiment of a two-terminal semiconductor diode using a MOSFET structure according to the invention of claim 1;
FIG. 5 is a drawing showing an embodiment of a trench structure in a two-terminal semiconductor diode using a MOSFET structure according to the invention of claim 1;
6 is a drawing showing an embodiment of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a Schottky barrier according to the invention of claim 2. FIG.
7 is a drawing showing an embodiment of a trench structure in a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a Schottky barrier according to the invention of claim 2. FIG.
FIG. 8 is a drawing showing an embodiment of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a PN junction according to the invention of claim 3;
9 is a drawing showing an embodiment of a trench structure in a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a PN junction according to the invention of claim 3. FIG.
FIG. 10 is a drawing showing another embodiment of a trench structure in a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a PN junction according to the invention of claim 3;
FIG. 11Horizontal typeIt is drawing for performing the basic description of the two-terminal type semiconductor diode using a MOSFET structure.
12 is a drawing showing an embodiment of a lateral structure of a two-terminal semiconductor diode using a MOSFET structure according to the invention of claim 1; FIG.
FIG. 13 is a view showing an embodiment of a lateral structure of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a Schottky barrier according to the invention of claim 2;
FIG. 14 is a drawing showing an embodiment of a lateral structure of a two-terminal semiconductor diode having a parallel structure of a MOSFET structure and a PN junction according to the invention of claim 3;
FIG. 15Horizontal typeOf a two-terminal semiconductor diode using a MOSFET structureOne caseIt is drawing which shows.
[Explanation of symbols]
S₁, S₂, D: Semiconductor region of first conductivity type
            (From FIG. 4 onward, in order, N_S ⁺, N_S, N_D ⁺Equivalent to
B, I ... Semiconductor region of the second conductivity type opposite to the first conductivity type
            (In FIG. 4 and subsequent figures,_B, P_IEquivalent to
F: Metal semiconductor alloy layer (silicide layer from FIG. 6)
M_S... Schottky barrier area
E₁... Semiconductor region S₁Electrode provided on
E₂... Electrodes provided in semiconductor region D
A ... Anode electrode
K ... Cathode electrode
G ... MOS gate electrode
N_B ⁺ ... P / N⁺Substrate region of epitaxial growth substrate

Claims (6)

A first semiconductor region (S ₁ ) having a _first conductivity type and a high impurity density in which a _first electrode (E ₁ ) is formed on one main surface side;
The other and main surface side of the first conductivity type in the second semiconductor region forming a first junction _(J 1) _(S 2) between said first semiconductor region _(S 1),
One main surface side is the second semiconductor region (S ₂₎ and the second joining the first of the second conductivity type opposite to that of the conductivity type third semiconductor region forming the (J ₂₎ (B) When,
Forming one main surface side is the third semiconductor region (B) and the third junction (J _3), and a first conduction second electrode on the other main surface side (E ₂₎ is formed A fourth semiconductor region (D) having a high impurity density in the form;
A double diffusion MOSFET comprising a MOS gate structure formed to cover the fourth semiconductor region (D), the third semiconductor region (B), and the second semiconductor region (S ₂ ) A semiconductor diode having a mold structure,
The fourth semiconductor region (D) and the third semiconductor region (B) are not short-circuited,
The second electrode _(E 2) and the gate electrode of the MOS gate structure (G) is short-circuited, and the third semiconductor region (B) is the second electrode _(E 2) and the gate electrode ( G) is not connected to any of the above,
The third semiconductor region (B) and the fourth semiconductor region (D) are not short-circuited, and the second electrode (E ₂ ) and the gate electrode (G) of the MOS gate structure are short-circuited. it allows the self-bias when the second junction (J ₂₎ a polarity voltage of the forward bias is applied is applied to the MOS gate, and the first electrode (E ₁₎ and the second electrode ( A semiconductor diode characterized in that a terminal characteristic between E ₂ ) is a rectifying characteristic. In claim 1,
A third electrode (E ₃ ) is formed on one main surface side, and a Schottky barrier region (M ) between the other main surface side and the other main surface side of the second semiconductor region (S ₂ ). _S ) comprising a metal semiconductor alloy layer (F) forming
Said MOS gate is formed to span the said metal semiconductor alloy layer (F),
The third electrode _(E 3), the second electrode _(E 2) and the gate electrode (G) and the semiconductor diode, characterized in that it is short-circuited to. In claim 1,
The third electrode (E ₃₎ is formed on one main surface side, and a fourth junction between the other main surface side of the other main surface side to the second semiconductor region (S ₂₎ A fifth semiconductor region (I) of the second conductivity type and forming a high impurity density forming (J4) ;
The MOS gate is formed to extend to the fifth semiconductor region (I) ,
The third electrode _(E 3), the second electrode _(E 2) and the gate electrode (G) and the semiconductor diode, characterized in that it is short-circuited to. In any one of Claims 1 thru | or 3,
The second electrode (E ₂₎ and the gate electrode (G) and the semiconductor diode, characterized in that the integrated structure with the same metal. In any one of Claims 1 thru | or 3,
A semiconductor diode characterized in that the threshold voltage is reduced by introducing a fixed charge into the gate oxide film of the MOS gate. In any one of Claims 1 thru | or 5,
A threshold voltage is reduced by forming the MOS gate on a (111) plane of a silicon (Si) crystal plane.

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