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JP3656307B2 - Hybrid integrated circuit device and manufacturing method thereof - Google Patents

Hybrid integrated circuit device and manufacturing method thereof Download PDF

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Publication number
JP3656307B2
JP3656307B2 JP02143296A JP2143296A JP3656307B2 JP 3656307 B2 JP3656307 B2 JP 3656307B2 JP 02143296 A JP02143296 A JP 02143296A JP 2143296 A JP2143296 A JP 2143296A JP 3656307 B2 JP3656307 B2 JP 3656307B2
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JP
Japan
Prior art keywords
conductor
thick film
film substrate
integrated circuit
circuit device
Prior art date
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Expired - Fee Related
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JP02143296A
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Japanese (ja)
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JPH09213881A (en
Inventor
貴久 子安
浩二 沼崎
斎藤  光弘
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Denso Corp
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Denso Corp
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、厚膜基板上に露出して形成された導体と半導体素子の電極とがはんだ付けされてなる混成集積回路装置およびその製造方法に関する。
【0002】
【従来の技術】
図7に従来の混成集積回路装置の構成を示す。(a)は断面構成図、(b)は半導体素子としての半導体チップを厚膜基板にはんだ付けする前の状態を示す平面図である。
混成集積回路装置は、厚膜基板1上に複数の導体2をスクリーン印刷し、導体2の一部が露出するように厚膜基板1の上に絶縁膜としての保護ガラス3をスクリーン印刷し、露出した導体2上に四角形状の半導体チップ4の電極5(表面がはんだで覆われたもの)をはんだ付けして構成される。
【0003】
保護ガラス3は、図7(b)に示すように、導体2の一部の領域(以下、導体ランドという)2aが露出するように開口部6を有して形成されており、その導体ランド2aに半導体チップ4の電極5がはんだ付けされる。なお、図7(b)において、保護ガラス3の形成領域をハッチングで示している。
【0004】
【発明が解決しようとする課題】
上記した従来のものでは、導体2の長手方向の1箇所を保護ガラス3で区切ることにより導体ランド2aを形成している。
この場合、導体2と保護ガラス3のマスク合わせズレが生じなければ、全ての導体ランド2aの面積を均一にして、半導体チップ4の電極5を良好にはんだ付けすることができる。
【0005】
しかしながら、導体2と保護ガラス3のマスク合わせズレが生じると、導体ランド2aの面積が一定にならない。例えば、図8(b)に示すように保護ガラス3が図の右側へズレて形成された場合には、露出距離a、bが異なり、左右の導体ランド2aの面積が不均一になる。このため、導体ランド2a上に供給されるはんだ高さが不均一になり、図8(a)に示すように半導体チップ4を適正に組み付けることができない。また、場合によっては電極5のオープン、はんだつぶれによる導体ランド2a間のショートなどの問題も生じうる。
【0006】
特に、近年、ICの高集積化および1チップ化により、半導体チップ4の電極数が多くなってきており、半導体チップ4の電極サイズおよび導体ランド2aを微細化する場合には、上記した問題が顕著になる。
本発明は上記問題に鑑みたもので、導体と絶縁膜との間に位置ズレが生じても導体ランドの面積を一定にすることを目的とする。
【0007】
【課題を解決するための手段】
上記目的を達成するため、請求項1乃至1に記載の発明においては、絶縁膜(3)は、導体(2)の一部を露出させるための開口部(7、7a〜7d、7e〜7r)を有し、かつ帯状の導体長手方向において導体上に開口部の両端が位置するように形成されており、さらに、絶縁膜は、上部に半導体素子(4)が位置する領域において厚膜基板(1)が露出するように形成され、半導体素子と厚膜基板との間にモールド材を入れるための空間が確保されていることを特徴としている。
【0008】
従って、導体の長手方向に絶縁膜との間で位置ズレが生じても、開口部の両端間の距離が一定であるため、導体ランドの面積を一定にすることができる。このことにより、半導体素子を適正に実装することができる。また、上部に半導体素子が位置する領域において厚膜基板が露出するように絶縁膜を形成し、半導体素子と前記厚膜基板との間にモールド材を入れるための空間を確保しているので、モールドする際のモールド材の侵入を容易にすることができる。なお、請求項11に記載の発明のように、導体群(A〜D)毎に4つの開口部(7a〜7d)を分離して形成し、それぞれのコーナー部において導体を形成するようにすれば、コーナー部に電極を有する半導体素子においても、適正に導体ランドを形成することができる。
【0010】
【発明の実施の形態】
(第1実施形態)
図1(a)に第1実施形態に係る混成集積回路装置の断面構成を示し、同図(b)に半導体チップを厚膜基板にはんだ付けする前の平面構成を示す。
厚膜基板1上には、並列配置された複数の帯状の導体2が形成されており、それらは四角形の4辺の位置関係をなす第1乃至第4の導体群A〜Dを構成している。ここで、導体ランド2aを形成するための保護ガラス3の開口部は、図7で示した従来の開口部6と異なり、図1(b)に示すように、第1乃至第4の導体群A〜Dのそれぞれを横切るようにして形成された1つの枠状の開口部7となっている。
【0011】
この開口部7は、それぞれの導体2の長手方向において導体2上に両端が位置しているため、開口部7が導体2に対し上下左右方向にズレても、開口部7の両端が導体2上に位置している限り、導体ランド2aの面積は一定となる。
なお、導体2および保護ガラス3には印刷ズレがあり、また導体2と保護ガラス3との間にはマスク合わせズレがあるが、前者をαμm、後者を±βμmとした時、導体2の端部と開口部7の端部との距離(図(b)に示すd)が、α+βμm以上になるように設定しておけば、図2に示すように最大限のズレが生じても、導体1上に開口部7の両端を位置させることができるため、導体ランド2aの面積を一定にすることができる。
【0012】
従って、導体ランド2a上に供給されるはんだ高さを均一にして、半導体チップ4を適正に組み付けることができる。
次に、本実施形態に係る混成集積回路装置の製造方法について図3を基に説明する。
〔図3(a)の導体印刷工程〕
厚膜導体1上に印刷マスク10を設置し、導体ペースト11をスキージ12を用いてスクリーン印刷し、厚さ約10μmの導体2を形成する。
〔図3(b)の焼成・乾燥工程〕
導体2が印刷された厚膜導体1を、焼成し、乾燥させる。
〔図3(c)の抵抗印刷・焼成・乾燥工程〕
所望の導体2間に、混成集積回路の一部をなす抵抗体13を印刷形成し、その後、焼成、乾燥を行う。
〔図3(d)の保護ガラス印刷工程〕
印刷マスク14を設置し、ガラスペースト15をスキージ16を用いてスクリーン印刷し、厚さ約15μmの保護ガラス3を形成する。この場合、印刷マスク14として、保護ガラス3の形成パターンが図1(b)のようになるものを用いる。
〔図3(e)の焼成・乾燥工程〕
保護ガラス3が形成された厚膜導体1を、焼成し、乾燥させる。
〔図3(f)のはんだ印刷工程〕
印刷マスク17を設置し、はんだペースト18をスキージ19を用いてスクリーン印刷し、導体ランド2a上にはんだ20を形成する。
〔図3(g)の素子組付工程〕
半導体チップ4の電極5を導体ランド2a上のはんだ20に位置合わせしてはんだ付けする。
(第2実施形態)
半導体チップ4のサイズが小さくコーナー部にも電極5が存在する場合には、図4に示すように、コーナー部に導体2が存在するように導体2の形成パターンを設定し、保護ガラス3の開口部を、第1乃至第4の導体群A〜Dのそれぞれに対応して分割した開口部7a〜7dとする。
【0013】
この場合、4つの開口部7a〜7dは四角形状の4辺の位置関係にあり、それぞれのコーナー部において、導体2が存在することになる。
従って、この実施形態においても、それぞれの開口部により導体ランド2aの面積を一定にすることができる。
(第3実施形態)
上記した第1実施形態では、半導体チップ4と厚膜基板1との間に保護ガラス3が存在して形成されるが、このようにすると、半導体チップ4を実装後、樹脂モールドする際に、モールド材が半導体チップ4と厚膜基板1との間に入りにくくなる可能性がある。
【0014】
そこで、この実施形態においては、図5に示すように、上部に半導体チップ4が位置する領域8において保護ガラス3を形成せずに厚膜導体1を露出させるようにしている。従って、半導体チップ4と厚膜基板1との間に空間が確保されるため、モールド材を半導体チップ4と厚膜基板1との間に入れやすくすることができる。
(第4実施形態)
上記した種々の実施形態では、導体群に対して開口部を形成するものを示したが、図6に示すように、個々の導体2に対して開口部7e〜7rを形成するようにしてもよい。この場合、上下左右方向に導体2と保護ガラス3間においてマスク合わせズレが生じても、導体2の長手方向、幅方向に開口部3aのそれぞれの両端が位置するため、導体ランド2aの面積を一定にすることができる。
【0015】
この実施形態における開口部としては、図に示すような正方形に限らず、それ以外の多角形でもよく、また円形でもよい。
また、この実施形態に対し、上記第3実施形態のように、上部に半導体チップ4が位置する領域8において保護ガラス3を形成しないようにしてもよい。
なお、上述した種々の実施形態において、厚膜基板1としては、単層の基板に限らず、絶縁膜を介して下部と上部導体が形成される厚膜2層基板や、導体が内部に何層も形成されている多層基板であってもよい。
【0016】
また、導体上に形成する絶縁膜としては、保護ガラス以外に、絶縁ガラスを用いることもできる。
【図面の簡単な説明】
【図1】本発明の第1実施形態に係る混成集積回路装置の構成を示す図である。
【図2】図1に示すものにおいて、導体2と保護ガラス3との間に位置ズレが生じた場合の状態を示す図である。
【図3】図1に示す混成集積回路装置の製造工程を示す工程図である。
【図4】本発明の第2実施形態を示す図である。
【図5】本発明の第3実施形態を示す図である。
【図6】本発明の第4実施形態を示す図である。
【図7】従来の混成集積回路装置の構成を示す図である。
【図8】図7に示すものにおいて、導体2と保護ガラス3との間に位置ズレが生じた場合の問題点を説明するための図である。
【符号の説明】
1…厚膜基板、2…導体、3…保護ガラス、4…半導体チップ、5…電極、
7、7a〜7d、7e〜7r…開口部。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a hybrid integrated circuit device in which a conductor exposed on a thick film substrate and an electrode of a semiconductor element are soldered, and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 7 shows a configuration of a conventional hybrid integrated circuit device. (A) is a cross-sectional block diagram, (b) is a top view which shows the state before soldering the semiconductor chip as a semiconductor element to a thick film board | substrate.
The hybrid integrated circuit device screen-prints a plurality of conductors 2 on the thick film substrate 1, screen-prints a protective glass 3 as an insulating film on the thick film substrate 1 so that a part of the conductor 2 is exposed, The exposed conductor 2 is configured by soldering an electrode 5 (having a surface covered with solder) of a rectangular semiconductor chip 4.
[0003]
As shown in FIG. 7B, the protective glass 3 is formed with an opening 6 so that a partial region 2a (hereinafter referred to as a conductor land) 2a of the conductor 2 is exposed. The electrode 5 of the semiconductor chip 4 is soldered to 2a. In addition, in FIG.7 (b), the formation area of the protective glass 3 is shown by hatching.
[0004]
[Problems to be solved by the invention]
In the above-described conventional one, the conductor land 2 a is formed by dividing one place in the longitudinal direction of the conductor 2 with the protective glass 3.
In this case, if there is no mask alignment deviation between the conductor 2 and the protective glass 3, the area of all the conductor lands 2a can be made uniform, and the electrodes 5 of the semiconductor chip 4 can be soldered well.
[0005]
However, if mask misalignment between the conductor 2 and the protective glass 3 occurs, the area of the conductor land 2a is not constant. For example, as shown in FIG. 8B, when the protective glass 3 is formed to be shifted to the right side of the drawing, the exposure distances a and b are different, and the areas of the left and right conductor lands 2a are not uniform. For this reason, the solder height supplied on the conductor land 2a becomes non-uniform, and the semiconductor chip 4 cannot be assembled properly as shown in FIG. In some cases, problems such as opening of the electrode 5 and short-circuiting between the conductor lands 2a due to solder crushing may occur.
[0006]
In particular, in recent years, the number of electrodes of the semiconductor chip 4 has increased due to the high integration and integration of ICs. When the electrode size of the semiconductor chip 4 and the conductor lands 2a are miniaturized, the above-described problems have occurred. Become prominent.
The present invention has been made in view of the above problems, and an object of the present invention is to make the area of a conductor land constant even if a positional deviation occurs between a conductor and an insulating film.
[0007]
[Means for Solving the Problems]
To achieve the above object, in the invention according to claims 1 to 1 3, the insulating film (3), an opening for exposing a portion of the conductor (2) (7,7a~7d, 7e~ 7r) and is formed so that both ends of the opening are positioned on the conductor in the longitudinal direction of the strip-shaped conductor , and the insulating film has a thickness in a region where the semiconductor element (4) is positioned above. The film substrate (1) is formed so as to be exposed, and a space for inserting a molding material is secured between the semiconductor element and the thick film substrate .
[0008]
Therefore, even if a positional deviation occurs between the insulating film and the longitudinal direction of the conductor, the distance between both ends of the opening is constant, so that the area of the conductor land can be made constant. As a result, the semiconductor element can be properly mounted. In addition, an insulating film is formed so that the thick film substrate is exposed in a region where the semiconductor element is located at the top, and a space for placing a molding material is secured between the semiconductor element and the thick film substrate. Intrusion of the molding material at the time of molding can be facilitated. As in the invention described in claim 11, four openings (7a to 7d) are formed separately for each conductor group (A to D), and a conductor is formed at each corner. For example, a conductor land can be appropriately formed even in a semiconductor element having an electrode at a corner.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1A shows a cross-sectional configuration of the hybrid integrated circuit device according to the first embodiment, and FIG. 1B shows a plan configuration before the semiconductor chip is soldered to the thick film substrate.
A plurality of strip-shaped conductors 2 arranged in parallel are formed on the thick film substrate 1, and they constitute first to fourth conductor groups A to D that form a positional relationship of four sides of a quadrangle. Yes. Here, the opening portion of the protective glass 3 for forming the conductor land 2a is different from the conventional opening portion 6 shown in FIG. 7, as shown in FIG. 1B, the first to fourth conductor groups. One frame-shaped opening 7 is formed so as to cross each of A to D.
[0011]
Since both ends of the opening 7 are positioned on the conductor 2 in the longitudinal direction of the respective conductors 2, both ends of the opening 7 are connected to the conductor 2 even if the opening 7 is displaced in the vertical and horizontal directions with respect to the conductor 2. As long as it is located above, the area of the conductor land 2a is constant.
The conductor 2 and the protective glass 3 have a printing misalignment, and there is a mask alignment misalignment between the conductor 2 and the protective glass 3, but when the former is α μm and the latter is ± β μm, the end of the conductor 2 If the distance between the portion and the end of the opening 7 (d shown in FIG. (B)) is set to be not less than α + β μm, the conductor is not affected even if the maximum deviation occurs as shown in FIG. Since the both ends of the opening 7 can be positioned on 1, the area of the conductor land 2a can be made constant.
[0012]
Accordingly, the semiconductor chip 4 can be properly assembled with the solder height supplied onto the conductor land 2a being uniform.
Next, a method for manufacturing a hybrid integrated circuit device according to this embodiment will be described with reference to FIG.
[Conductor printing process in FIG. 3 (a)]
A printing mask 10 is placed on the thick film conductor 1 and the conductor paste 11 is screen-printed using a squeegee 12 to form a conductor 2 having a thickness of about 10 μm.
[Firing / Drying Process in FIG. 3B]
The thick film conductor 1 on which the conductor 2 is printed is fired and dried.
[Resistance printing / firing / drying process of FIG. 3 (c)]
A resistor 13 forming a part of the hybrid integrated circuit is printed between the desired conductors 2 and then baked and dried.
[Protective glass printing process of FIG. 3 (d)]
The printing mask 14 is installed, and the glass paste 15 is screen-printed using the squeegee 16 to form the protective glass 3 having a thickness of about 15 μm. In this case, a printing mask 14 having a protective glass 3 forming pattern as shown in FIG.
[Firing / Drying Process of FIG. 3 (e)]
The thick film conductor 1 on which the protective glass 3 is formed is fired and dried.
[Solder printing process in FIG. 3 (f)]
A printing mask 17 is installed, and solder paste 18 is screen-printed using a squeegee 19 to form solder 20 on the conductor land 2a.
[Element assembly process in FIG. 3 (g)]
The electrode 5 of the semiconductor chip 4 is positioned and soldered to the solder 20 on the conductor land 2a.
(Second Embodiment)
When the size of the semiconductor chip 4 is small and the electrodes 5 are also present at the corners, the formation pattern of the conductors 2 is set so that the conductors 2 are present at the corners as shown in FIG. The openings are referred to as openings 7a to 7d divided corresponding to the first to fourth conductor groups A to D, respectively.
[0013]
In this case, the four openings 7a to 7d are in a quadrangular positional relationship, and the conductor 2 exists at each corner.
Therefore, also in this embodiment, the area of the conductor land 2a can be made constant by each opening.
(Third embodiment)
In the first embodiment described above, the protective glass 3 is formed between the semiconductor chip 4 and the thick film substrate 1. In this way, when the semiconductor chip 4 is mounted and then resin-molded, There is a possibility that the molding material will not easily enter between the semiconductor chip 4 and the thick film substrate 1.
[0014]
Therefore, in this embodiment, as shown in FIG. 5, the thick film conductor 1 is exposed without forming the protective glass 3 in the region 8 where the semiconductor chip 4 is located in the upper part. Therefore, since a space is secured between the semiconductor chip 4 and the thick film substrate 1, the molding material can be easily put between the semiconductor chip 4 and the thick film substrate 1.
(Fourth embodiment)
In the above-described various embodiments, the openings are formed in the conductor group. However, as shown in FIG. 6, the openings 7 e to 7 r may be formed in the individual conductors 2. Good. In this case, even if mask misalignment occurs between the conductor 2 and the protective glass 3 in the vertical and horizontal directions, both ends of the opening 3a are located in the longitudinal direction and the width direction of the conductor 2, so that the area of the conductor land 2a is Can be constant.
[0015]
The opening in this embodiment is not limited to a square as shown in the figure, and may be a polygon other than that, or a circle.
In contrast to this embodiment, the protective glass 3 may not be formed in the region 8 in which the semiconductor chip 4 is located at the top as in the third embodiment.
In the above-described various embodiments, the thick film substrate 1 is not limited to a single layer substrate, but a thick film double layer substrate in which the lower and upper conductors are formed via an insulating film, and what the conductor is inside. It may be a multilayer substrate on which layers are also formed.
[0016]
Further, as the insulating film formed on the conductor, insulating glass can be used in addition to the protective glass.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a hybrid integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a state where a positional deviation occurs between a conductor 2 and a protective glass 3 in the one shown in FIG.
FIG. 3 is a process diagram showing a manufacturing process of the hybrid integrated circuit device shown in FIG. 1;
FIG. 4 is a diagram showing a second embodiment of the present invention.
FIG. 5 is a diagram showing a third embodiment of the present invention.
FIG. 6 is a diagram showing a fourth embodiment of the present invention.
FIG. 7 is a diagram showing a configuration of a conventional hybrid integrated circuit device.
8 is a diagram for explaining a problem when a positional deviation occurs between the conductor 2 and the protective glass 3 in the one shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Thick film board | substrate, 2 ... Conductor, 3 ... Protective glass, 4 ... Semiconductor chip, 5 ... Electrode,
7, 7a-7d, 7e-7r ... opening.

Claims (14)

厚膜基板(1)と、この厚膜基板上に形成された帯状の導体(2)と、この導体の一部が露出するように前記厚膜基板上に形成された絶縁膜(3)と、前記露出した導体上に電極(5)がはんだ付けされた半導体素子(4)とを有する混成集積回路装置において、
前記絶縁膜は、前記導体の一部を露出させるための開口部(7、7a〜7d、7e〜7r)を有し、かつ前記帯状の導体の長手方向において前記導体上に前記開口部の両端が位置するように形成されており、
さらに、前記絶縁膜は、上部に前記半導体素子が位置する領域において前記厚膜基板が露出するように形成され、前記半導体素子と前記厚膜基板との間にモールド材を入れるための空間が確保されていることを特徴とする混成集積回路装置。
A thick film substrate (1), a strip-shaped conductor (2) formed on the thick film substrate, and an insulating film (3) formed on the thick film substrate so that a part of the conductor is exposed. In a hybrid integrated circuit device having a semiconductor element (4) with an electrode (5) soldered on the exposed conductor,
The insulating film has openings (7, 7a to 7d, 7e to 7r) for exposing a part of the conductor, and both ends of the opening on the conductor in the longitudinal direction of the strip-shaped conductor. Is formed to be located,
Further, the insulating film is formed so that the thick film substrate is exposed in a region where the semiconductor element is located above, and a space for inserting a molding material is secured between the semiconductor element and the thick film substrate. A hybrid integrated circuit device.
前記厚膜基板上に、前記帯状の導体が複数並列配置されており、それらの帯状の導体を横切るように前記絶縁膜の開口部(7、7a〜7d)が形成されていることを特徴とする請求項1に記載の混成集積回路装置。  A plurality of the strip-shaped conductors are arranged in parallel on the thick film substrate, and openings (7, 7a to 7d) of the insulating film are formed so as to cross the strip-shaped conductors. The hybrid integrated circuit device according to claim 1. 前記開口部(7e〜7r)は前記導体の幅方向にも両端を有しており、この幅方向の両端が前記導体上に位置するように前記絶縁膜が形成されていることを特徴とする請求項に記載の混成集積回路装置。It said opening (7e~7r) also in the width direction of the conductor has two ends, and wherein the insulating film is formed so as to both ends of the width direction is positioned on the conductor The hybrid integrated circuit device according to claim 1 . 前記厚膜基板上に、前記帯状の導体が前記長手方向に対向して離間配置されており、それらの対向配置した帯状の導体のそれぞれに前記開口部(7、7a〜7d、7e〜7r)が形成されていることを特徴とする請求項1乃至3のいずれか1つに記載の混成集積回路装置。On the thick film substrate, the strip-shaped conductors are spaced apart from each other in the longitudinal direction, and the openings (7, 7a to 7d, 7e to 7r) are provided in the respective strip-shaped conductors that are disposed to face each other. hybrid integrated circuit device according to any one of claims 1 to 3, characterized in that There are formed. 厚膜基板(1)と、
この厚膜基板上に並列配置された複数の帯状の導体(2)からなる第1の導体群(A(又はB))と、
前記厚膜基板上に前記第1の導体群と離間して並列配置された複数の帯状の導体からなる第2の導体群(C(又はD))と、
前記それぞれの導体の一部が露出するように前記厚膜基板上に形成された絶縁膜(3)と、
前記露出した導体上に電極(5)がはんだ付けされた半導体素子(4)とを備え、
前記絶縁膜は、前記それぞれの導体の一部を露出させるための開口部(7、7a〜7d、7e〜7r)を有し、かつ前記開口部は、前記それぞれの導体上で導体の長手方向において両端が位置するように形成されており、
さらに、前記絶縁膜は、上部に前記半導体素子が位置する領域において前記厚膜基板が露出するように形成され、前記半導体素子と前記厚膜基板との間にモールド材を入れるための空間が確保されていることを特徴とする混成集積回路装置。
A thick film substrate (1);
A first conductor group (A (or B)) composed of a plurality of strip-like conductors (2) arranged in parallel on the thick film substrate;
A second conductor group (C (or D)) composed of a plurality of strip-shaped conductors arranged in parallel and spaced apart from the first conductor group on the thick film substrate;
An insulating film (3) formed on the thick film substrate so that a part of each of the conductors is exposed;
A semiconductor element (4) soldered with an electrode (5) on the exposed conductor;
The insulating film has openings (7, 7a to 7d, 7e to 7r) for exposing a part of the respective conductors, and the openings are arranged in the longitudinal direction of the conductors on the respective conductors. In which both ends are located ,
Further, the insulating film is formed so that the thick film substrate is exposed in a region where the semiconductor element is located above, and a space for inserting a molding material is secured between the semiconductor element and the thick film substrate. hybrid integrated circuit device characterized by being.
前記開口部(7)は、枠状のものであって、その1辺が前記第1の導体群を横切り、他の1辺が前記第2の導体群を横切るように形成されていることを特徴とする請求項5に記載の混成集積回路装置。  The opening (7) has a frame shape and is formed so that one side thereof crosses the first conductor group and the other side crosses the second conductor group. The hybrid integrated circuit device according to claim 5, characterized in that: 前記開口部は、前記第1の導体群を横切るように形成された第1の開口部(7a(又は7b))と、前記第2の導体群を横切るように形成された第2の開口部(7c(又は7d))を有していることを特徴とする請求項5に記載の混成集積回路装置。  The opening includes a first opening (7a (or 7b)) formed so as to cross the first conductor group, and a second opening formed so as to cross the second conductor group. The hybrid integrated circuit device according to claim 5, wherein (7c (or 7d)) is included. 厚膜基板(1)と、
この厚膜基板上に、四角形における4辺の位置関係で形成され、それぞれの辺において並列配置された複数の帯状の導体(2)からなる第1乃至第4の導体群(A〜D)と、
前記それぞれの導体の一部が露出するように前記厚膜基板上に形成された絶縁膜(3)と、
前記露出した導体上に電極(5)がはんだ付けされた半導体素子(4)とを備え、
前記絶縁膜は、前記それぞれの導体の一部を露出させるための開口部(7、7a〜7d、7e〜7r)を有し、かつ前記開口部は、前記それぞれの導体上で導体の長手方向において両端が位置するように形成されており、
さらに、前記絶縁膜は、上部に前記半導体素子が位置する領域において前記厚膜基板が露出するように形成され、前記半導体素子と前記厚膜基板との間にモールド材を入れるための空間が確保されていることを特徴とする混成集積回路装置。
A thick film substrate (1);
On the thick film substrate, first to fourth conductor groups (A to D) formed of a plurality of strip-shaped conductors (2) formed in a positional relationship of four sides of a quadrangle and arranged in parallel on each side; ,
An insulating film (3) formed on the thick film substrate so that a part of each of the conductors is exposed;
A semiconductor element (4) soldered with an electrode (5) on the exposed conductor;
The insulating film has openings (7, 7a to 7d, 7e to 7r) for exposing a part of the respective conductors, and the openings are arranged in the longitudinal direction of the conductors on the respective conductors. In which both ends are located ,
Further, the insulating film is formed so that the thick film substrate is exposed in a region where the semiconductor element is located above, and a space for inserting a molding material is secured between the semiconductor element and the thick film substrate. hybrid integrated circuit device characterized by being.
前記開口部は前記第1乃至第4の導体群を横切るようにして形成された1つの開口部(7)からなることを特徴とする請求項8に記載の混成集積回路装置。  9. The hybrid integrated circuit device according to claim 8, wherein the opening includes one opening formed so as to cross the first to fourth conductor groups. 前記開口部は前記第1乃至第4の導体群の導体群毎に分離して形成された4つの開口部(7a〜7d)からなることを特徴とする請求項8に記載の混成集積回路装置。  9. The hybrid integrated circuit device according to claim 8, wherein the opening is composed of four openings (7a to 7d) formed separately for each conductor group of the first to fourth conductor groups. . 前記4つの開口部は四角形状の4辺の位置関係あり、それぞれのコーナー部において前記第1乃至第4群のいずれかに属する導体が形成されていることを特徴とする請求項10に記載の混成集積回路装置。  11. The four openings are in a quadrilateral four-sided positional relationship, and a conductor belonging to any of the first to fourth groups is formed at each corner. Hybrid integrated circuit device. 前記開口部(7e〜7r)は、前記それぞれの導体上で導体の長手方向と幅方向に両端を有する多角形のものであることを特徴とする請求項5又は8に記載の混成集積回路装置。  9. The hybrid integrated circuit device according to claim 5, wherein the openings (7 e to 7 r) are polygonal having both ends in the longitudinal direction and the width direction of the conductors on the respective conductors. 9. . 前記開口部(7e〜7r)は、前記それぞれの導体上に位置するように形成された円形のものであることを特徴とする請求項5又は8に記載の混成集積回路装置。  9. The hybrid integrated circuit device according to claim 5, wherein the openings (7e to 7r) are circular ones formed so as to be located on the respective conductors. 厚膜基板(1)上に導体(2)を印刷形成し、導体の一部が露出するように絶縁膜(3)を前記厚膜基板上に印刷形成し、前記露出した導体上に半導体素子(4)の電極(5)をはんだ付けするようにした混成集積回路装置の製造方法において、
前記絶縁膜を前記導体の長手方向において前記導体上に両端を有して開口形成するとともに、上部に前記半導体素子が位置する領域において前記厚膜基板が露出するように形成して、前記半導体素子と前記厚膜基板との間にモールド材を入れるための空間を確保したことを特徴とする混成集積回路装置の製造方法。
A conductor (2) is printed on the thick film substrate (1), an insulating film (3) is printed on the thick film substrate so that a part of the conductor is exposed, and a semiconductor element is formed on the exposed conductor. In the method of manufacturing a hybrid integrated circuit device in which the electrode (5) of (4) is soldered,
Wherein an insulating film, as well as longitudinal direction with both ends on the conductor in the opening formed of the conductor, and formed so that the thick film substrate in a region where the semiconductor element to the upper position exposing said semiconductor A method for manufacturing a hybrid integrated circuit device, wherein a space for placing a molding material is secured between an element and the thick film substrate .
JP02143296A 1996-02-07 1996-02-07 Hybrid integrated circuit device and manufacturing method thereof Expired - Fee Related JP3656307B2 (en)

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