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JP3643706B2 - Semiconductor device - Google Patents

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Publication number
JP3643706B2
JP3643706B2 JP21819898A JP21819898A JP3643706B2 JP 3643706 B2 JP3643706 B2 JP 3643706B2 JP 21819898 A JP21819898 A JP 21819898A JP 21819898 A JP21819898 A JP 21819898A JP 3643706 B2 JP3643706 B2 JP 3643706B2
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semiconductor chip
semiconductor
chip
electrode pad
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JP2000058743A (en
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誠 坪野谷
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip type semiconductor device wherein an insulating spacer is held between fist and second semiconductor chips to allow wire bonding to an electrode pad concealed under the chip. SOLUTION: A first semiconductor chip 10 is fitted to an island 13 while a second semiconductor chip 11 is fitted on the first semiconductor chip 10 with a spacer 30 in between. The first semiconductor chip 10 is connected to a lead terminal 17 with a first bonding wire 16a while the second semiconductor chip 11 is connected to the lead terminal 17 with a second bonding wire 16b. The first and the second semiconductor chips 10 and 11 have similar chip size and shape, and a first electrode pad 12a is concealed under the second semiconductor chip 11 from a top view. Using a space 19 formed by the spacer 30, the first electrode pad 12a is connected to the second bonding wire 16a.

Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップを重ね合わせてモールドしつつ、近似した大きさを持つ半導体チップの組み合わせでも小型化できる半導体装置に関する。
【０００２】
【従来の技術】
半導体装置の封止技術として最も普及しているのが、図６（Ａ）に示したような、半導体チップ１の周囲を熱硬化性のエポキシ樹脂２で封止するトランスファーモールド技術である。半導体チップ１の支持素材としてリードフレームを用いており、リードフレームのアイランド３に半導体チップ１をダイボンドし、半導体チップ１のボンディングパッドとリード４をワイヤ５でワイヤボンドし、所望の外形形状を具備する金型内にリードフレームをセットし、金型内にエポキシ樹脂を注入、これを硬化させることにより製造される。
【０００３】
一方、各種電子機器に対する小型、軽量化の波はとどまるところを知らず、これらに組み込まれる半導体装置にも、一層の大容量、高機能、高集積化が望まれることになる。
【０００４】
そこで、以前から発想としては存在していた（例えば、特開昭５５ー１１１１５１７号）、１つのパッケージ内に複数の半導体チップを封止する技術が注目され、実現化する動きが出てきた。つまり図６（Ｂ）に示すように、アイランド３上に第１の半導体チップ１ａを固着し、第１の半導体チップ１ａの上に第２の半導体チップ１ｂを固着し、対応するボンディングパッドとリード端子４とをボンディングワイヤ５ａ、５ｂで接続し、樹脂２で封止したものである。
【０００５】
【発明が解決しようとする課題】
図６（Ｂ）の構成は、第１の半導体チップ１ａとのワイヤボンディングを確保するため、第２の半導体チップ１ｂを固着したときに第１の半導体チップ１ａの電極パッド部分が露出していること、即ちチップサイズに差のあることが絶対的な条件となる。そのため、例えば同一機種のチップを２個組み込む、或いは別機種のチップであってもそのチップサイズが近似する場合には採用できない欠点があった。２つの半導体チップを十文字に重ね合わせることも考えられるが、これとてチップサイズの縦×横の寸法に差があることが条件となり、依然として制約が残るものである。
【０００６】
【課題を解決するための手段】
本発明は上述した従来の課題に鑑み成されたもので、第１と第２の半導体チップと、前記第１と第２の半導体チップの各表面に形成した電極パッドと、外部接続用の電極手段と、前記第１と第２の半導体チップの電極パッドと前記電極手段とを各々接続するボンディングワイヤとを具備し、前記第１と第２の半導体チップを重畳して１つのパッケージに封止した半導体装置において、
前記第１の半導体チップと前記第２の半導体チップと間にスペーサを設け、該スペーサは前記第１の半導体チップの電極パッドを避けてその上部に空間を形成し、前記空間の上部には前記第２の半導体チップが位置し、
前記第１の半導体チップの電極パッドに接続するボンディングワイヤが、前記空間を通過して前記第１の半導体チップの電極パッドにボンディングされていることを特徴とするものである。
【０００７】
【発明の実施の形態】
以下に本発明の一実施の形態を詳細に説明する。
【０００８】
先ず、図１は本発明の半導体装置の主要部を示す断面図、図２（Ａ）は全体を示す断面図、同じく図２（Ｂ）は全体を示す平面図である。
【０００９】
これらの図において、１０、１１は各々第１と第２の半導体チップを示している。第１と第２の半導体チップ１０、１１のシリコン表面には、前工程において各種の拡散熱処理などによって多数の能動、受動回路素子が形成されている。第１と第２の半導体チップ１０、１１のチップ周辺部分には外部接続用の第１と第２の電極パッド１２ａ、１２ｂがアルミ電極によって形成されている。各電極パッド１２ａ、１２ｂの上にはパッシベーション皮膜が形成され、電極パッド１２ａ、１２ｂの上部が電気接続のために開口されている。パッシベーション被膜はシリコン窒化膜、シリコン酸化膜、ポリイミド系絶縁膜などである。図２（Ｂ）の例では、各電極パッド１２ａ、１２ｂは半導体チップ１０、１１の対向する２辺に沿って集約して配置されている。
【００１０】
第１の半導体チップ１０がリードフレームのアイランド１３上に接着剤１４によりダイボンドされる。第２の半導体チップ１１が第１の半導体チップ１０の前記パッシベーション皮膜上に固着されている。接着剤１４は導電性または絶縁性である。
【００１１】
第１の電極パッド１２ａには、金線からなる第１のボンディングワイヤ１６ａの一端が接続されており、第１のボンディングワイヤ１６ａの他端は外部導出用のリード端子１７にワイヤボンドされている。また、第２の電極パッド１２ｂの表面には、第２のボンディングワイヤ１６ｂの一端がワイヤボンドされており、第２のボンディングワイヤ１６ｂの他端は外部導出用のリード端子１７にワイヤボンドされている。
【００１２】
第１と第２の半導体チップ１０、１１、リード端子１７の一部、および第１と第２のボンディングワイヤ１６ａ、１６ｂを含む主要部は、周囲をエポキシ系の熱硬化樹脂１８でモールドされて半導体装置のパッケージを形成する。リード端子１７はパッケージの側壁から外部に導出されて外部接続端子となる。導出されたリード端子１７はＺ字型に曲げ加工されている。アイランド１３の裏面側は樹脂１８の表面に露出しており、樹脂１８表面と同一平面を形成している。
【００１３】
第１と第２の半導体チップ１０、１１の組み合わせは任意である。例えば、第１と第２の半導体チップ１０、１１としてＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を用いた場合（第１の組み合わせ例）は、１つのパッケージで記憶容量を２倍、３倍・・・にすることができる。また、第１の半導体チップ１０にＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を、第２の半導体チップ１１にはＳＲＡＭ等の半導体記憶装置を形成するような場合（第２の組み合わせ例）ことも考えられる。どちらの組み合わせの場合でも、各チップにはデータの入出力を行うＩ／Ｏ端子と、データのアドレスを指定するアドレス端子、及びデータの入出力を許可するチップイネーブル端子とを具備しており、両チップのピン配列が酷似している。そのため、第１と第２の半導体チップ１０、１１のＩ／Ｏ端子やアドレス端子用のリード端子１７を共用することが可能であり、各チップに排他的なチップイネーブル信号を印加することにより、どちらか一方の半導体チップのメモリセルを排他的に選択することが可能である。
【００１４】
上記第１の組み合わせ例の場合には当然の事ながら、第１の半導体チップ１０と第２の半導体チップ１１が大略同じ大きさと形状を有し、電極パッド１２ａ、１２ｂの配列も同じである。そのため、両者を重ねると、第１の半導体チップ１０の電極パッド１２ａが第２の半導体チップ１１の陰に隠れる。具体的に、図２（Ｂ）の例では第２の電極パッド１２ｂの直下に第１の電極パッド１２ａが位置する。又第２の組み合わせ例の場合でも、チップサイズと形状が近似し且つピン配列が酷似する場合があり得る。
【００１５】
而して、第１と第２の半導体チップ１０、１１の間にスペーサ３０を形成して、第１の電極パッド１２ａの上方に空間１９を形成し、第２の半導体チップ１１をひさし状に突出させている。この空間１９は、第１の半導体チップ１０の端部から第１の電極１２ａを露出するだけの幅（図１：Ｗ）を持ち、更には第１のボンディングワイヤ１６ａのワイヤ高さを収納するだけの高さ（図１：ｔ１）を持つ。但しスペーサ３０と各半導体チップ１０、１１との接着剤１５の膜厚をも考慮する。この様なスペーサ３０としては、膜厚が１００〜２００μ程度の絶縁接着テープ、直径が１００〜２００μの粒状の絶縁フィラーを混入した絶縁性のエポキシ系接着剤等が利用できる。
【００１６】
スペーサ３０は第１の電極パッド１２ａの上方に空間１９を形成し、この空間内で第１のボンディングワイヤ１６ａが第１の電極パッド１２ａにボールボンディングされている。ボール部２０から連続する第１のボンディングワイヤ１６ａは空間１９を通過し、リード端子１７にセカンドボンドされる。第１の半導体チップ１０の表面の高さに対してリード端子１７の表面が高いような場合には、第１のボンディングワイヤ１６ａは第１の電極１２ａから空間１９を通過して横方向に導出され、第２の半導体チップ１１の端より外側で上昇し、リード端子１７先端部に到達する様な軌跡を描く。
【００１７】
この様に、スペーサ３０によって第１の電極パッド１２ａの上に空間１９を設けることによって、第１の半導体チップ１０へのワイヤボンディングを可能にし、且つ第１のボンディングワイヤ１６ａが第２の半導体チップ１１の裏面と接触することを回避している。
【００１８】
本実施の形態では、アイランド１３の板厚が１５０〜２００μであり、第１と第２の半導体チップ１０、１１の厚みがバックグラインド工程により２５０〜３００μとなっている、接着剤１４、１５の厚みとして２０〜３０μ必要であり、更にはボンディングワイヤの上部に樹脂の残り厚みとして１５０〜２００μは必要である。本願出願人は、これらの厚みを収納しつつ、パッケージの高さｔ２を１．０ｍｍ以下にまで薄形化した半導体装置を実現した。
【００１９】
図３に第２の実施の形態を示した。リードフレームに代えてテープキャリアと半田ボールを用いた例である。第１の半導体チップ１０がポリイミド系のベースフィルム４０の上に接着固定され、第１の半導体チップ１０の上に第２の半導体チップ１１がスペーサ３０を挟んで固着される。ベースフィルム４０の表面にはリード端子１７に相当する導電パターン４１が形成されており、第１と第２の電極パッド１２ａ、１２ｂと導電パターン４１とが各々第１と第２のボンディングワイヤ１６ａ、１６ｂで接続されている。ベースフィルム４０には貫通穴が形成され、該貫通穴を介して、ベースフィルム４０の裏面に形成した半田ボール４２と接続されている、そして、周囲を熱硬化性の樹脂でモールドされている。
【００２０】
尚、上記実施例は半導体チップが２個の場合を記載したが、３個、４個を積層する場合でも同様に実施できることは言うまでもない。
【００２１】
【発明の効果】
以上に説明した通り、本発明によれば、第１と第２の半導体チップ１０、１１の間にスペーサ３０を設け、スペーサ３０が形成する空間１９を利用して第１の電極１２ａに第１のボンディングワイヤ１２ａをボンディングするので、半導体チップ１０、１１の大きさと形状が近似した場合でも複数の半導体チップを積層してワイヤボンディングが可能になる利点を有する。これにより、例えば１つのパッケージに２倍の記憶容量を持たせることが可能になる。
【００２２】
更に、半導体チップ１０、１１としてどのようなサイズ、形状のものでも組み合わせが可能になり、製品展開の自由度が増す利点をも有する。
【図面の簡単な説明】
【図１】本発明を説明するための断面図である。
【図２】本発明を説明するための（Ａ）断面図、（Ｂ）平面図である。
【図３】本発明の、第２の実施の形態を示す断面図である。
【図４】従来例を説明するための断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that can be miniaturized even by a combination of semiconductor chips having approximate sizes while superposing and molding a plurality of semiconductor chips.
[0002]
[Prior art]
The most widespread as a sealing technique for a semiconductor device is a transfer mold technique for sealing the periphery of the semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. A lead frame is used as a support material for the semiconductor chip 1, the semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pad of the semiconductor chip 1 and the lead 4 are wire-bonded with the wire 5 to have a desired outer shape. The lead frame is set in a mold to be manufactured, and an epoxy resin is injected into the mold and is cured.
[0003]
On the other hand, the wave of miniaturization and weight reduction for various electronic devices is not limited, and further higher capacity, higher functionality, and higher integration are desired for semiconductor devices incorporated therein.
[0004]
Therefore, a technique that has existed as an idea for a long time (for example, Japanese Patent Application Laid-Open No. 55-1111517) has been attracting attention and a movement to realize it has attracted attention. That is, as shown in FIG. 6B, the first semiconductor chip 1a is fixed on the island 3, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and leads are fixed. The terminal 4 is connected with bonding wires 5 a and 5 b and sealed with a resin 2.
[0005]
[Problems to be solved by the invention]
In the configuration of FIG. 6B, in order to secure wire bonding with the first semiconductor chip 1a, the electrode pad portion of the first semiconductor chip 1a is exposed when the second semiconductor chip 1b is fixed. That is, the difference in chip size is an absolute condition. For this reason, for example, there are disadvantages that cannot be adopted when two chips of the same model are incorporated, or even if the chip size is similar even if the chips are of different models. It is conceivable to superimpose two semiconductor chips on a cross, but this still requires that there is a difference in the vertical and horizontal dimensions of the chip size, and there are still restrictions.
[0006]
[Means for Solving the Problems]
The present invention has been made in view of the above-described conventional problems, and includes first and second semiconductor chips, electrode pads formed on the surfaces of the first and second semiconductor chips, and electrodes for external connection. And a bonding wire for connecting the electrode pads of the first and second semiconductor chips and the electrode means, respectively, and the first and second semiconductor chips are overlapped and sealed in one package In the semiconductor device
A spacer is provided between the first semiconductor chip and the second semiconductor chip, and the spacer avoids an electrode pad of the first semiconductor chip and forms a space above the space. A second semiconductor chip is located,
A bonding wire connected to the electrode pad of the first semiconductor chip passes through the space and is bonded to the electrode pad of the first semiconductor chip.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail.
[0008]
First, FIG. 1 is a sectional view showing the main part of the semiconductor device of the present invention, FIG. 2A is a sectional view showing the whole, and FIG. 2B is a plan view showing the whole.
[0009]
In these drawings, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. A large number of active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 by various diffusion heat treatments in the previous step. First and second electrode pads 12a and 12b for external connection are formed of aluminum electrodes in the peripheral portions of the first and second semiconductor chips 10 and 11. A passivation film is formed on each electrode pad 12a, 12b, and the upper part of electrode pad 12a, 12b is opened for electrical connection. The passivation film is a silicon nitride film, a silicon oxide film, a polyimide insulating film, or the like. In the example of FIG. 2B, the electrode pads 12a and 12b are collectively arranged along two opposing sides of the semiconductor chips 10 and 11.
[0010]
The first semiconductor chip 10 is die-bonded with an adhesive 14 on the island 13 of the lead frame. The second semiconductor chip 11 is fixed on the passivation film of the first semiconductor chip 10. The adhesive 14 is conductive or insulating.
[0011]
One end of a first bonding wire 16a made of a gold wire is connected to the first electrode pad 12a, and the other end of the first bonding wire 16a is wire-bonded to an external lead terminal 17. . One end of the second bonding wire 16b is wire-bonded to the surface of the second electrode pad 12b, and the other end of the second bonding wire 16b is wire-bonded to the lead terminal 17 for external lead-out. Yes.
[0012]
The main parts including the first and second semiconductor chips 10 and 11, a part of the lead terminal 17, and the first and second bonding wires 16 a and 16 b are molded with an epoxy-based thermosetting resin 18. A semiconductor device package is formed. The lead terminal 17 is led out from the side wall of the package and becomes an external connection terminal. The derived lead terminal 17 is bent into a Z-shape. The back side of the island 13 is exposed on the surface of the resin 18 and forms the same plane as the surface of the resin 18.
[0013]
The combination of the first and second semiconductor chips 10 and 11 is arbitrary. For example, when a semiconductor storage device such as an EEPROM (flash memory) is used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity is doubled, tripled,・ ・In some cases, a semiconductor memory device such as an EEPROM (flash memory) is formed on the first semiconductor chip 10 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example). Conceivable. In either combination, each chip has an I / O terminal for inputting / outputting data, an address terminal for designating an address of data, and a chip enable terminal for permitting input / output of data, The pin arrangement of both chips is very similar. Therefore, it is possible to share the I / O terminal of the first and second semiconductor chips 10 and 11 and the lead terminal 17 for the address terminal, and by applying an exclusive chip enable signal to each chip, It is possible to exclusively select the memory cells of either one of the semiconductor chips.
[0014]
In the case of the first combination example, as a matter of course, the first semiconductor chip 10 and the second semiconductor chip 11 have substantially the same size and shape, and the arrangement of the electrode pads 12a and 12b is also the same. Therefore, when both are overlapped, the electrode pad 12 a of the first semiconductor chip 10 is hidden behind the second semiconductor chip 11. Specifically, in the example of FIG. 2B, the first electrode pad 12a is located immediately below the second electrode pad 12b. Even in the case of the second combination example, the chip size and shape may be approximated and the pin arrangement may be very similar.
[0015]
Thus, the spacer 30 is formed between the first and second semiconductor chips 10 and 11, the space 19 is formed above the first electrode pad 12a, and the second semiconductor chip 11 is shaped like an eave. It is protruding. This space 19 has a width (FIG. 1: W) sufficient to expose the first electrode 12a from the end of the first semiconductor chip 10, and further accommodates the wire height of the first bonding wire 16a. (Fig. 1: t1). However, the thickness of the adhesive 15 between the spacer 30 and each of the semiconductor chips 10 and 11 is also considered. As such a spacer 30, an insulating adhesive tape having a film thickness of about 100 to 200 μm, an insulating epoxy adhesive mixed with a granular insulating filler having a diameter of 100 to 200 μm, or the like can be used.
[0016]
The spacer 30 forms a space 19 above the first electrode pad 12a, and the first bonding wire 16a is ball-bonded to the first electrode pad 12a in this space. The first bonding wire 16 a continuous from the ball portion 20 passes through the space 19 and is second bonded to the lead terminal 17. When the surface of the lead terminal 17 is higher than the surface height of the first semiconductor chip 10, the first bonding wire 16a passes through the space 19 from the first electrode 12a and is led out in the lateral direction. Then, a locus is drawn that rises outside the end of the second semiconductor chip 11 and reaches the tip of the lead terminal 17.
[0017]
Thus, by providing the space 19 on the first electrode pad 12a by the spacer 30, wire bonding to the first semiconductor chip 10 is possible, and the first bonding wire 16a is used as the second semiconductor chip. 11 to avoid contact with the back surface.
[0018]
In the present embodiment, the thickness of the island 13 is 150 to 200 μm, and the thickness of the first and second semiconductor chips 10 and 11 is 250 to 300 μm by the back grinding process. The thickness needs to be 20-30 μm, and further, the remaining thickness of the resin needs to be 150-200 μm above the bonding wire. The applicant of the present application has realized a semiconductor device in which the thickness t2 of the package is reduced to 1.0 mm or less while accommodating these thicknesses.
[0019]
FIG. 3 shows a second embodiment. In this example, a tape carrier and solder balls are used instead of the lead frame. The first semiconductor chip 10 is bonded and fixed on the polyimide base film 40, and the second semiconductor chip 11 is fixed on the first semiconductor chip 10 with the spacer 30 interposed therebetween. A conductive pattern 41 corresponding to the lead terminal 17 is formed on the surface of the base film 40, and the first and second electrode pads 12a, 12b and the conductive pattern 41 are respectively connected to the first and second bonding wires 16a, 16b. A through hole is formed in the base film 40 and connected to a solder ball 42 formed on the back surface of the base film 40 through the through hole, and the periphery is molded with a thermosetting resin.
[0020]
In the above embodiment, the case where there are two semiconductor chips is described, but it goes without saying that the present invention can be similarly implemented even when three or four semiconductor chips are stacked.
[0021]
【The invention's effect】
As described above, according to the present invention, the spacer 30 is provided between the first and second semiconductor chips 10, 11, and the first electrode 12 a is formed on the first electrode 12 a using the space 19 formed by the spacer 30. Therefore, even when the sizes and shapes of the semiconductor chips 10 and 11 are approximated, a plurality of semiconductor chips can be stacked to perform wire bonding. As a result, for example, one package can have twice the storage capacity.
[0022]
Further, any size and shape of the semiconductor chips 10 and 11 can be combined, and there is an advantage that the degree of freedom of product development is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining the present invention.
2A is a sectional view and FIG. 2B is a plan view for explaining the present invention.
FIG. 3 is a cross-sectional view showing a second embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining a conventional example.

Claims (3)

第１の半導体チップ及び前記第１の半導体チップ上に積層された第２の半導体チップと、前記第１及び第２の半導体チップの各第１主面に形成した電極パッドと、前記電極パッドの各々とボンディングワイヤにより電気的に接続された外部接続用の電極手段と、前記第１及び第２の半導体チップを樹脂モールドして形成されたパッケージと、を具備し、
前記第１の半導体チップと前記第２の半導体チップとの間には、スペーサが配置されており、
前記第１の半導体チップの電極パッドと前記電極手段とを接続するボンディングワイヤは、前記スペーサの厚みにより前記第１の半導体チップと前記第２の半導体チップとの間に形成された空間内に第１の頂部を有すると共に、前記空間の外部に第２の頂部を有し、
前記第２の頂部は、前記第１の頂部よりも高い箇所に位置することを特徴とする半導体装置。A first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, an electrode pad formed on each first main surface of the first and second semiconductor chips, and an electrode pad An external connection electrode means electrically connected to each other by a bonding wire, and a package formed by resin-molding the first and second semiconductor chips,
A spacer is disposed between the first semiconductor chip and the second semiconductor chip,
A bonding wire connecting the electrode pad of the first semiconductor chip and the electrode means is formed in a space formed between the first semiconductor chip and the second semiconductor chip according to the thickness of the spacer. Having a top and a second top outside the space;
The semiconductor device according to claim 1, wherein the second top is positioned higher than the first top. 前記スペーサは、絶縁性フィラーが混入した絶縁性接着剤からなることを特徴とする請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the spacer is made of an insulating adhesive mixed with an insulating filler. 前記電極手段は、前記パッケージから導出されたリード端子、または前記第１の半導体チップが固着されるフィルム上に形成された導電パターンであることを特徴とする請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the electrode means is a lead pattern derived from the package or a conductive pattern formed on a film to which the first semiconductor chip is fixed.
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