JP3643764B2 - Circuit device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a circuit device, and more particularly to a method of manufacturing a circuit device having a multilayer wiring without a support substrate.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a circuit device set in an electronic device is employed in a mobile phone, a portable computer, and the like, and thus, a reduction in size, thickness, and weight are required.
[0003]
For example, a semiconductor device as an example of a circuit device will be described. As a general semiconductor device, there is a package type semiconductor device sealed by a conventional transfer mold. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.
[0004]
In this package type semiconductor device, the periphery of the semiconductor chip 2 is covered with a resin layer 3, and lead terminals 4 for external connection are led out from the side of the resin layer 3.
[0005]
However, the package type semiconductor device 1 has lead terminals 4 protruding from the resin layer 3 and has a large overall size, which does not satisfy the miniaturization, thickness reduction, and weight reduction.
[0006]
Therefore, various companies have competed to develop various structures to achieve miniaturization, thinning, and weight reduction, and recently called CSP (chip size package), wafer scale CSP equivalent to chip size, or chip size A slightly larger CSP has been developed.
[0007]
FIG. 12 shows a CSP 6 that uses a glass epoxy substrate 5 as a support substrate and is slightly larger than the chip size. Here, description will be made assuming that the transistor chip T is mounted on the glass epoxy substrate 5.
[0008]
A first electrode 7, a second electrode 8 and a die pad 9 are formed on the surface of the glass epoxy substrate 5, and a first back electrode 10 and a second back electrode 11 are formed on the back surface. The first electrode 7 and the first back electrode 10 are electrically connected to the second electrode 8 and the second back electrode 11 through the through hole TH. Further, the bare transistor chip T is fixed to the die pad 9, the emitter electrode of the transistor and the first electrode 7 are connected via the fine metal wire 12, and the base electrode of the transistor and the second electrode 8 are connected to the fine metal wire 12. Connected through. Further, a resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.
[0009]
The CSP 6 employs the glass epoxy substrate 5, but unlike the wafer scale CSP, the extending structure from the chip T to the backside electrodes 10 and 11 for external connection is simple, and has an advantage that it can be manufactured at low cost.
[0010]
The CSP 6 is mounted on the printed circuit board PS as shown in FIG. The printed circuit board PS is provided with electrodes and wirings constituting an electric circuit, and the CSP 6, the package type semiconductor device 1, the chip resistor CR, the chip capacitor CC, and the like are electrically connected and fixed.
[0011]
And the circuit comprised with this printed circuit board is attached in various sets.
[0012]
Next, a method for manufacturing the CSP will be described with reference to FIGS.
[0013]
First, a glass epoxy substrate 5 is prepared as a base material (support substrate), and Cu foils 20 and 21 are pressure-bonded to both surfaces via an insulating adhesive. (See FIG. 13A above)
Subsequently, the Cu foils 20, 21 corresponding to the first electrode 7, the second electrode 8, the die pad 9, the first back electrode 10, and the second back electrode 11 are covered with an etching resistant resist 22, and Cu The foils 20 and 21 are patterned. Patterning may be performed separately for the front and back sides. (See FIG. 13B above)
Subsequently, a hole for the through hole TH is formed in the glass epoxy substrate by using a drill or a laser, and the hole is plated to form the through hole TH. The first electrode 7 and the first back electrode 10, and the second electrode 8 and the second back electrode 10 are electrically connected through the through hole TH. (See FIG. 13C above)
Further, although omitted in the drawing, the first electrode 7 and the second electrode 8 that become bonding posts are plated with Ni, and the die pad 9 that becomes a die bonding post is plated with Au, and the transistor chip T is die bonded. To do.
[0014]
Finally, the emitter electrode of the transistor chip T and the first electrode 7, the base electrode of the transistor chip T and the second electrode 8 are connected via the metal thin wire 12 and covered with the resin layer 13. (See FIG. 13D above)
With the above manufacturing method, a CSP type electric element employing the support substrate 5 is completed. This manufacturing method is the same even if a flexible sheet is adopted as the support substrate.
[0015]
On the other hand, a manufacturing method employing a ceramic substrate is shown in the flow of FIG. After preparing the ceramic substrate as the support substrate, through holes are formed, and then the front and back electrodes are printed and sintered using a conductive paste. After that, it is the same as the manufacturing method of FIG. 13 until the resin layer of the previous manufacturing method is coated. However, the ceramic substrate is very brittle, and unlike a flexible sheet or a glass epoxy substrate, it will be chipped immediately. There is a problem that can not be molded. Therefore, the potting resin is potted and cured, and then polishing for flattening the sealing resin is performed, and finally, the dicing apparatus is used for individual separation.
[0016]
[Problems to be solved by the invention]
In FIG. 12, a transistor chip T, connection means 7 to 12 and a resin layer 13 are necessary components for electrical connection with the outside and protection of the transistor. It has been difficult to provide a circuit element that can be made thinner, thinner and lighter.
[0017]
Moreover, the glass epoxy board | substrate 5 used as a support substrate is an essentially unnecessary thing as mentioned above. However, since the electrodes are bonded together in the manufacturing method, it is adopted as a support substrate, and the glass epoxy substrate 5 cannot be eliminated.
[0018]
For this reason, the use of the glass epoxy substrate 5 increases the cost. Further, since the glass epoxy substrate 5 is thick, it becomes thick as a circuit element, and there is a limit to miniaturization, thickness reduction, and weight reduction.
[0019]
Furthermore, glass epoxy substrates and ceramic substrates must be built in these substrates to realize multilayer wiring, so a through-hole forming process for connecting multilayer wiring layers is indispensable, and the manufacturing process is long and not suitable for mass production. There was also a problem.
[0020]
[Means for Solving the Problems]
The present invention is made in view of the above-mentioned many problems, and a conductive foil is prepared, and a separation groove shallower than the thickness of the conductive foil is formed in the conductive foil in a region excluding the first layer conductive pattern. A step of forming a first layer conductive pattern, a step of forming a plurality of layers of conductive patterns on the first layer conductive pattern via an interlayer insulating film, and incorporating a circuit element in the desired conductive pattern A step of covering the circuit element and molding the whole with an insulating resin, a step of removing the conductive foil in a thickness portion where the separation groove is not provided, and the insulating resin for each circuit element. And a step of separating each circuit device by dicing.
[0021]
In the present invention, the conductive foil forming the conductive pattern is a starting material, and the conductive foil has a supporting function until the insulating resin is molded, and after the molding, the insulating resin has a supporting function. A multilayer wiring that eliminates the need for a substrate can be realized and the conventional problems can be solved.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
First, a method for manufacturing a circuit device of the present invention will be described with reference to FIG.
[0023]
The present invention provides a conductive foil, and forms a first-layer conductive pattern by forming a separation groove shallower than the thickness of the conductive foil in the conductive foil in a region excluding the first-layer conductive pattern. A step of forming a plurality of layers of conductive patterns on the first layer conductive pattern via an interlayer insulating film, a step of incorporating circuit elements in the desired conductive pattern, and covering the entire circuit element It comprises a step of molding with an insulating resin, a step of removing the conductive foil in a thickness portion where the separation groove is not provided, and a step of separating the insulating resin by dicing for each of the circuit elements. .
[0024]
The flow shown in FIG. 1 does not coincide with the above-described process, but the first layer conductive pattern is formed by two flows of Cu foil and half etching. A plurality of conductive patterns are formed on the conductive foil in the flow of forming the multilayer wiring layer. The circuit element is fixed to the conductive pattern and the electrodes of the circuit element and the conductive pattern are connected by two flows of die bonding and wire bonding. In the flow of transfer molding, molding with an insulating resin is performed. In the flow of removing the rear Cu foil, the conductive foil in the thickness portion without the separation groove is etched. In the back surface processing flow, electrode processing of the conductive pattern exposed on the back surface is performed. In the dicing flow, the insulating resin is diced and separated into individual circuit elements.
[0025]
Below, each process of this invention is demonstrated with reference to FIGS.
[0026]
As shown in FIGS. 2 to 4, the first step of the present invention is to prepare a conductive foil, and in the conductive foil in the region excluding the first-layer conductive pattern, the separation groove shallower than the thickness of the conductive foil. Forming a first-layer conductive pattern.
[0027]
In this step, first, a sheet-like conductive foil 30 is prepared as shown in FIG. The conductive foil 30 is selected in consideration of the adhesion and plating properties of the brazing material. The material is a conductive foil mainly made of Cu, a conductive foil mainly made of Al, Fe-Ni, or the like. A conductive foil made of the above alloy is employed.
[0028]
The thickness of the conductive foil 30 is preferably about 10 μm to 300 μm in consideration of later etching, and here, a copper foil of 70 μm (2 ounces) is employed. However, it is basically good if it is 300 μm or more and 10 μm or less. As will be described later, it is sufficient that the separation groove 31 shallower than the thickness of the conductive foil 30 can be formed.
[0029]
In addition, the sheet-like conductive foil 30 is prepared by being wound into a roll with a predetermined width, for example, 45 mm, and this may be conveyed to each step described later, or a strip-shaped cut into a predetermined size. The conductive foil 30 may be prepared and conveyed to each process described later.
[0030]
Subsequently, a first layer conductive pattern 41 is formed.
[0031]
First, as shown in FIG. 3, a photoresist (etching resistant mask) PR is formed on the Cu foil 30, and the photoresist PR is patterned so that the conductive foil 30 excluding the region to be the conductive pattern 41 is exposed. Then, as shown in FIG. 4, the conductive foil 30 is selectively etched through the photoresist PR.
[0032]
The depth of the separation groove 31 formed by etching is, for example, 50 μm, and the side surface thereof becomes a rough surface, so that the adhesiveness with the insulating resin 50 is improved.
[0033]
The side walls of the separation groove 31 are schematically illustrated as straight, but have different structures depending on the removal method. This removal process can employ wet etching, dry etching, laser evaporation, and dicing. In the case of wet etching, ferric chloride or cupric chloride is mainly used as the etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Since wet etching is generally non-anisotropic, the side surface has a curved structure.
[0034]
In the case of dry etching, etching can be performed anisotropically or non-anisotropically. At present, it is said that Cu cannot be removed by reactive ion etching, but it can be removed by sputtering. Etching can be anisotropic or non-anisotropic depending on sputtering conditions.
[0035]
Further, in the laser, the separation groove 31 can be formed by direct laser light irradiation. In this case, the side surface of the separation groove 31 is formed straight.
[0036]
The second step of the present invention is to form a plurality of conductive patterns 43 on the first conductive pattern 41 via an interlayer insulating film 42 as shown in FIG. 5A.
[0037]
This step is a feature of the present invention, and a multilayer wiring structure is realized by laminating the interlayer insulating film 42 and the conductive pattern 43. As the interlayer insulating film 42, there are a case where a non-photosensitive thermosetting resin is used and a case where a photosensitive resist layer is used. Epoxy resins and polyimide resins are known as thermosetting resins, and are supplied in liquid or dry film form. As the resist layer, photosensitive epoxy resin, epoxy acrylate resin, and polyimide resin are known, and are similarly supplied in liquid or dry film form.
[0038]
In this step, as shown in FIG. 5B, the first-layer conductive pattern 41 is first chemically polished to clean the surface and roughen the surface. Next, the isolation groove 31 and the entire surface of the first conductive pattern 41 are covered with a thermosetting resin on the conductive pattern 41 of the first layer, and the interlayer insulating film 42 having a flat surface is formed by heat curing. . Further, via holes 44 having a diameter of about 100 μm are formed in the interlayer insulating film 42 on the desired first-layer conductive pattern 41 using a carbon dioxide laser. Thereafter, an excimer laser is irradiated to remove the etching soot. Subsequently, a copper plating layer 45 is formed on the entire surface of the interlayer insulating film 42 and the via hole 44. The copper plating layer 45 is first formed by electroless copper plating so as to have a thin thickness of about 0.5 μm, and subsequently formed by electroplating to a thickness of about 20 μm so as not to break at the step of the via hole 44. The copper plating layer 45 is patterned using a photoresist to form a second conductive pattern 43.
[0039]
By repeating the above-described steps, many layers of conductive patterns 43 can be stacked on the conductive foil 30 via the interlayer insulating film 42. In addition, since the multi-layer conductive pattern 43 is supported by the conductive foil 30 on which the first-layer conductive pattern 41 is formed, a multilayer wiring structure can be formed without using a support substrate such as a glass epoxy substrate. .
[0040]
Further, when the interlayer insulating film 42 is formed with a photosensitive resist layer in this step, a portion of the interlayer insulating film 42 exposed by a well-known photoresist process is removed with an alcohol-based solvent to form a via hole 44. . The other steps are the same as when the interlayer insulating film 42 is formed with a thermosetting resin.
[0041]
The third step of the present invention is to incorporate a circuit element 46 in a desired conductive pattern 43 as shown in FIG.
[0042]
The circuit element 46 is a semiconductor element such as a transistor, a diode, or an IC chip, or a passive element such as a chip capacitor or a chip resistor. Although the thickness is increased, face-down semiconductor elements such as CSP and BGA can also be mounted.
[0043]
Here, a bare transistor chip 46A is die-bonded to a conductive pattern 43A, and an emitter electrode and a conductive pattern 43B, and a base electrode and a conductive pattern 43B are fixed by ball bonding by thermocompression bonding or wedge bonding by ultrasonic waves. 47 is connected. The passive element 46B such as a chip capacitor is fixed to the conductive pattern 43 with a brazing material such as solder or a conductive paste.
[0044]
The fourth step of the present invention is to cover the circuit element 46 and mold the whole with an insulating resin 50 as shown in FIG. In particular, a plurality of circuit devices provided on the conductive foil 30 are commonly molded with one mold.
[0045]
In this step, the insulating resin 50 completely covers the circuit elements 46A and 46B and the conductive pattern 43, and the conductive pattern 43 is supported by the insulating resin 50.
[0046]
Further, this step can be realized by transfer molding, injection molding, potting or dipping. As the resin material, a thermosetting resin such as epoxy resin can be realized by transfer molding or potting, and a thermoplastic resin such as polyimide resin and polyphenylene sulfide can be realized by injection molding.
[0047]
The thickness of the insulating resin 50 covering the surface of the conductive pattern 43 is adjusted so as to cover about 100 μm from the top of the metal thin wire 47 of the circuit element 46. This thickness can be increased or decreased in consideration of strength.
[0048]
The feature of this step is that the conductive foil 30 that becomes the conductive pattern 41 of the first layer becomes a support substrate until the insulating resin 50 is covered. Conventionally, as shown in FIG. 12, the conductive paths 7 to 11 are formed by using the support substrate 5 that is not originally required. However, in the present invention, the conductive foil 30 serving as the support substrate is necessary as an electrode material. Material. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.
[0049]
Further, since the separation groove 31 is formed shallower than the thickness of the conductive foil 30, the conductive foil 30 is not individually separated as the first-layer conductive pattern 41. Therefore, the sheet-like conductive foil 30 can be handled as a unit, and when the insulating resin 50 is molded, it has a feature that the work of transporting to the mold and mounting to the mold becomes very easy.
[0050]
As shown in FIG. 8, the fifth step of the present invention is to remove the conductive foil 30 in the thickness portion where the separation groove 31 is not provided.
[0051]
In this step, the back surface of the conductive foil 30 is chemically and / or physically removed and separated as the conductive pattern 51. This step is performed by polishing, grinding, etching, laser metal evaporation, or the like.
[0052]
In the experiment, the entire surface is cut by about 30 μm by a polishing apparatus or a grinding apparatus, and the insulating resin 50 is exposed from the separation groove 31. This exposed surface is indicated by a dotted line in FIG. As a result, the first conductive pattern 41 having a thickness of about 40 μm is separated. Alternatively, wet etching may be performed on the entire surface of the conductive foil 30 until the insulating resin 50 is exposed, and then the entire surface may be shaved by a polishing or grinding apparatus to expose the insulating resin 50. Further, the insulating resin 50 may be exposed by wet etching the entire surface of the conductive foil 30 to the dotted line.
[0053]
As a result, the insulating resin 50 has a structure in which the back surface of the first conductive pattern 41 is exposed. That is, the surface of the insulating resin 50 filled in the separation groove 31 and the surface of the first layer conductive pattern 41 are substantially coincident. Therefore, the circuit device according to the present invention does not have a step as in the conventional backside electrodes 10 and 11 shown in FIG. 11, and thus has a feature that it can be moved by the surface tension of solder or the like as it is and is self-aligned during mounting. .
[0054]
Further, the back surface treatment of the conductive foil 30 is performed to obtain the final structure shown in FIG. That is, if necessary, a conductive material such as solder is applied to the exposed conductive pattern 41 to form the back electrode 51, thereby completing the circuit device 60. The conductive pattern 41 that does not require the back electrode 51 is preferably covered with a protective film 52 such as an epoxy resin resist material.
[0055]
The sixth step of the present invention is to separate the insulating resin 50 by dicing for each circuit device including each circuit element 46 as shown in FIG.
[0056]
In this step, a large number of circuit devices 60 are formed in a matrix on the conductive foil 30, and the black-colored pattern indicates the first-layer conductive pattern 41. White portions indicate the separation grooves 31 between the conductive patterns 41 and between the circuit devices 60. Under this conductive pattern 41, there are a plurality of conductive patterns 43 and an interlayer insulating film 42. A circuit element 46 is mounted on the uppermost conductive pattern 43 and covered with an insulating resin 50. That is, the circuit device 60 shown in FIG. 9 is turned over.
[0057]
In this step, a large number of circuit devices 60 that are integrally supported by the insulating resin 50 are attached to the dicing sheet 62 and adsorbed on the mounting table of the dicing device in a vacuum, and a dicing blade 55 is used between the circuit devices 60. The insulating resin 50 in the separation groove 31 is diced along the dicing line 56 and separated into individual circuit devices 60.
[0058]
In this step, the dicing blade 55 completely cuts the insulating resin 50 and performs dicing at a cutting depth that reaches the surface of the dicing sheet 62 to completely separate each individual circuit device 60. At the time of dicing, the alignment mark 61 provided inside the frame-like pattern 57 around each block provided in the first step described above is recognized in advance and dicing is performed based on this. As is well known, after dicing all dicing lines 56 in the vertical direction, the mounting table is rotated 90 degrees and dicing is performed according to the dicing lines 56 in the horizontal direction.
[0059]
In this process, the dicing line 56 has only the interlayer insulating film 42 and the insulating resin 50 filled in the separation groove 31, so that the dicing blade 55 does not cut the conductive patterns 41 and 43, and wears little. There is a feature that can be diced into an extremely accurate outer shape.
[0060]
Furthermore, even after this process, after dicing, the dicing sheet 62 does not separate the individual circuit devices 60, and the subsequent taping process can be efficiently performed. That is, the circuit device 60 integrally supported by the dicing sheet 62 can identify only non-defective products and can be separated from the dicing sheet 62 by the suction collet and stored in the carrier tape storage hole. For this reason, even the minute circuit device 60 has a feature that it is not separated even once until taping.
[0061]
【The invention's effect】
In the present invention, the conductive foil itself, which is the material of the conductive pattern, functions as a support substrate, and the whole is supported by the conductive foil until the separation groove is formed or the circuit element is mounted and the insulating resin is applied. When separating the foil as each conductive pattern, the insulating resin is used as a support substrate to function. Therefore, the circuit element, conductive foil, and insulating resin can be manufactured with the minimum necessary. As described in the conventional example, a support substrate is not necessary in constructing a circuit device originally, and the cost can be reduced.
[0062]
In the present invention, a plurality of conductive patterns can be formed on the first conductive pattern, and these conductive patterns are supported by a conductive foil or an insulating resin during the manufacturing process. A supporting insulating substrate can be eliminated. As a result, even in a small circuit device, a multilayer wiring structure can be built in the inside, and the supporting substrate can be made unnecessary, so that a very thin and small circuit device can be manufactured in large quantities. Furthermore, the dicing process has the advantage that recognition of the dicing line is quickly and reliably performed using the alignment mark. The dicing may be performed by cutting only the interlayer insulating film and the insulating resin layer, and the dicing blade is not cut by cutting the conductive pattern. The life of the metal foil can be extended, and no metal burrs are generated when the conductive foil is cut.
[0063]
Finally, as is apparent from FIG. 14, the through-hole formation process, conductor printing process (in the case of a ceramic substrate), etc. can be omitted, so that the manufacturing process can be greatly shortened compared to the prior art, and the entire process can be produced internally Have Also, a frame mold is not required at all, and this is a manufacturing method with extremely short delivery time.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a production flow of the present invention.
FIG. 2 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 3 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 4 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 9 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 10 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 11 is a diagram illustrating a mounting structure of a conventional circuit device.
FIG. 12 is a diagram illustrating a conventional circuit device.
FIG. 13 is a diagram for explaining a conventional method of manufacturing a circuit device.
FIG. 14 is a diagram illustrating a conventional method for manufacturing a circuit device.
[Explanation of symbols]
31 Separation Groove 41 First Layer Conductive Pattern 42 Interlayer Insulating Film 43 Multiple Layer Conductive Pattern 44 Via Hole 46 Circuit Element 50 Insulating Resin 60 Individual Circuit Device

Claims (9)

Preparing a conductive foil in which a first layer conductive pattern is formed by forming a separation groove shallower than the thickness of the conductive foil in a conductive foil in a region excluding the first layer conductive pattern;
While supporting with the conductive foil, the separation groove and the entire conductive pattern of the first layer are covered with a thermosetting resin, and are cured by heating to form an interlayer insulating film having a flat surface. Forming a via hole on the first layer conductive pattern using a laser, forming a plating layer on the interlayer insulating film and the via hole, and then patterning to form a second layer conductive pattern; ,
Further, the step is repeated to laminate a desired number of conductive patterns through an interlayer insulating film,
Incorporating a circuit element into the desired conductive pattern;
Covering the circuit element and molding the whole with an insulating resin;
And a step of removing the conductive foil in a thickness portion where the separation groove is not provided. Preparing a conductive foil in which a first layer conductive pattern is formed by forming a separation groove shallower than the thickness of the conductive foil in a conductive foil in a region excluding the first layer conductive pattern;
While supporting with the conductive foil, the separation groove and the entire conductive pattern of the first layer are covered with a thermosetting resin, and are cured by heating to form an interlayer insulating film having a flat surface. Forming a via hole on the first layer conductive pattern using a laser, forming a plating layer on the interlayer insulating film and the via hole, and then patterning to form a second layer conductive pattern; ,
Further, the step is repeated to laminate a desired number of conductive patterns through an interlayer insulating film,
Incorporating a circuit element into the desired conductive pattern;
Covering the circuit element and molding the whole with an insulating resin;
Removing the conductive foil in a thickness portion not provided with the separation groove;
And a step of separating the insulating resin by dicing for each circuit device including each of the circuit elements.   The method for manufacturing a circuit device according to claim 1, wherein the conductive foil is made of any one of copper, aluminum, and iron-nickel.   The method for manufacturing a circuit device according to claim 1, wherein the separation groove selectively formed in the conductive foil is formed by chemical or physical etching.   3. The method of manufacturing a circuit device according to claim 1, wherein the plurality of conductive patterns are formed of a copper plating layer.   6. The method of manufacturing a circuit device according to claim 5, wherein the copper plating layer is formed by electroless plating and electroplating.   3. The method of manufacturing a circuit device according to claim 1, wherein either one or both of a semiconductor bare chip and a chip circuit component are fixed to the circuit element. The method of manufacturing a circuit device according to claim 1, wherein the circuit element is a face-down CSP or BGA.   The method for manufacturing a circuit device according to claim 1, wherein the insulating resin is molded by transfer molding or potting.

Images