JP3538088B2 - Thin film transistor and method for manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) and a method of manufacturing the same, and more particularly, to an inverted staggered channel etch type TFT used for a liquid crystal display (LCD) and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, the mainstream of TFTs used in LCDs is an inverted staggered (back) channel etch type. FIG. 15A and FIG. 15 which are schematic plan views of a TFT.
Referring to FIG. 15B, which is a schematic cross-sectional view taken along the line AA in FIG. 15A, when such a TFT is configured to include an amorphous silicon layer, the result is as follows. .

The surface of the glass substrate 301 on which the gate wiring 302 and the gate electrode 303 are provided includes the gate insulating film 30 including the gate wiring 302 and the gate electrode 303.
9. For example, a chromium film is formed on the surface of the glass substrate 301 by sputtering, and this chromium is taper-etched to form a gate wiring 302 and a gate electrode 303. The gate insulating film 309 is formed by stacking, for example, a silicon oxide film 305 having a thickness of about 100 nm and a silicon nitride film 306 having a thickness of about 400 nm, for example. The silicon oxide film 305 is formed by sputtering, atmospheric pressure vapor deposition (APCVD), or plasma enhanced vapor deposition (PECVD). At least the silicon nitride film 306 is formed by PECVD and contains hydrogen (H). The reason why the gate insulating film 309 has a stacked structure of the silicon oxide film 305 and the silicon nitride film 306 is to take measures against pinholes existing in the silicon oxide film 305.

On the surface of the gate insulating film 309, an amorphous silicon film island 315 is provided. A source wiring 321 is provided on the surface of the gate insulating film 309, and has a form extending from the surface of the amorphous silicon film island 315 to the surface of the gate insulating film 309.
2 and a drain electrode 323 are provided. This T
The channel length L and channel width W of the FT are, for example, 6 μm,
12 μm.

The formation of this structure is performed as follows.

After the silicon nitride film 306 is formed, the same PECVD apparatus is used to undo the undoped film having a thickness of about 300 nm on the surface of the gate insulating film 309 by PECVD using, for example, monosilane (SiH ₄ ) as a source gas. Of the first amorphous silicon layer (not explicitly shown). Subsequently, the surface of the first amorphous silicon film, for example, a SiH ₄ as a raw material gas, phosphine (PH
₃ ) By PECVD using an additional gas, for example, 50 n
An n ⁺ -type second amorphous silicon layer (not shown) having a thickness of about m is formed. The first and second amorphous silicon layers also contain hydrogen. The phosphorus concentration of the second amorphous silicon layer is of the order of 10 ²⁶ m ⁻³ (10 ²⁰ cm ⁻³ ).

A first photoresist film pattern (not shown) is formed on the surface of the second amorphous silicon layer. Using this first photoresist film pattern as a mask, SF
_The layered amorphous silicon film (consisting of the second and first amorphous silicon layers) is patterned by dry etching with ₆ + Cl _{2, and} an amorphous silicon film pattern (at the first stage) Not specified) is formed. For example, a chromium film is formed on the entire surface by, for example, sputtering. Wet etching using a second photoresist film pattern (not shown) as a mask, Cl ₂ and oxygen (O ₂ )
The chromium film is patterned by dry etching using a mixed gas of the source electrode 321, the source wiring 321, the source electrode 322, and the drain electrode 323 are formed.

[0008] The second photoresist film pattern is organically stripped. Subsequently, using the source electrode 322 and the drain electrode 323 as a mask, dry etching (channel etching) using a mixed gas of SF ₆ and HCl is performed on the first-stage amorphous silicon film island, and the channel etching portion 317 is formed. Is formed, and an amorphous silicon film island 315 (second stage) composed of the remaining first amorphous silicon layer 311 and second amorphous silicon layer 314 is formed. The amorphous silicon layer 314 is formed on the source electrode 32.
2. It is left only under the drain electrode 323. The thickness of the amorphous silicon layer 311 in the portion where the channel is etched is, for example, about 200 nm.

[0009] Including the source wiring 321 and the TFT,
The surface of the gate insulating film 309 is covered with an interlayer insulating film 325. The drain electrode 32 is formed on the interlayer insulating film 325.
3 is provided, and an ITO electrode (pixel electrode) 32 provided on the surface of the interlayer insulating film 325 is provided.
8 is connected to the drain electrode 323 via the contact hole 327.

In the TET including the amorphous silicon film island, the Id in the case of the above various parameters
The measured value of the -Vg characteristic is as shown in FIG. FIG.
In the graph, a white circle indicates the Id-Vg characteristic when white light is irradiated, and a black circle indicates the Id-Vg characteristic when dark. FIG.
6 (a) shows the Id-Vg characteristics in the semi-log display, and FIG. 16 (b) shows the Id-Vg characteristics when the Id is in the 10 ^-6 A range.

In the case of a TFT having a channel region formed of a polycrystalline silicon film pattern, the gate insulating film is formed of a single-layer silicon oxide film, and the polycrystalline silicon film pattern is formed on the undoped first polycrystalline silicon layer. n ⁺ type second
Are stacked. In this case, the gate insulating film is formed by low pressure chemical vapor deposition (LPCVD) containing a TEOS-based gas as a source gas, and the first and second polycrystalline silicon layers are continuously formed using the same LPCVD apparatus. Is done.

[0012]

[0005] High definition LCDs have been developed today, and accordingly, it has been required to improve the performance of TFTs used in LCDs. One of them is to increase the resistance R _off when the TFT is off,
To lower the R _on the time on the TFT has been demanded.

However, in a conventional (back) channel etch type (and inversely staggered) TFT, the source,
N ⁺ -type second amorphous silicon layer (or n ⁺ -type second polycrystalline silicon layer) in self-alignment with the drain electrode
In the channel etching for dividing the gate electrode, this etching is performed at the interface between the second amorphous silicon layer and the undoped first amorphous silicon layer (or between the second polycrystalline silicon layer and the undoped first polycrystalline silicon layer). Interface with silicon layer)
It is difficult to stop accurately in the vicinity. One of the causes is that the etching rate ratio of the second and first amorphous silicon layers (or the second and first polycrystalline silicon layers) is 1%.
(Approximately 1.2: 1). For this reason, in order to completely separate the second amorphous silicon layer (or the second polycrystalline silicon layer) in this channel etching, the second amorphous silicon layer (or the second
It is necessary to make the thickness of the polycrystalline silicon layer) sufficiently large.

As a result, in the conventional TFT having the above structure,
R _off is lower than its expected value (because the thickness of the first amorphous or polycrystalline silicon layer constituting the channel region contributes to the resistance as “width”), and R _on is lower than the source (drain). The film thickness of the first amorphous or polycrystalline silicon layer immediately below the electrode contributes to the resistance as a "length", which is higher than its expected value.

Therefore, the purpose of the TFT of the present invention is to set R _on
It is an object of the present invention to provide a TFT having a structure capable of increasing R _off by suppressing an increase in Roff. Further, the object of the method for manufacturing a TFT of the present invention is to provide a method for manufacturing
By providing a manufacturing method capable of accurately and selectively removing the n ⁺ type amorphous or polycrystalline silicon layer,
T that can suppress R _on increase and increase R _off
An object of the present invention is to provide an FT manufacturing method.

[0016]

[0017]

[0018]

According to a first aspect of the TFT of the present invention, a glass substrate having a surface provided with a gate electrode and a gate wiring is covered with a gate insulating film including the gate electrode and the gate wiring. A silicon film island having a laminated structure is provided on the surface of the gate insulating film. The silicon film island is an undoped first silicon layer directly covering the surface of the gate insulating film, and the first silicon layer. Composed of an O ₂ leak layer on the surface of
A second silicon layer having a thickness of not less than 8 nm and an undoped third layer provided on the surface of the second silicon layer;
Silicon layer and the and a third fourth silicon layer of n ⁺ -type formed on the surface of the silicon layer, including the silicon film island source wiring on the surface of the gate insulating film, a source electrode And a drain electrode are provided.
Is characterized in that the silicon layer is removed by self-alignment with these source and drain electrodes.

Preferably, each of the first to third silicon layers constituting the silicon film island is an amorphous silicon layer, and the gate insulating film is a laminated insulating film of a silicon oxide film and a silicon nitride film; Alternatively, it is a stacked insulating film including a silicon oxide film, a silicon nitride film, and a second silicon oxide film. Alternatively, each of the first to third silicon layers constituting the silicon film island is made of a polycrystalline silicon layer, and the gate insulating film is made of a silicon oxide film.

According to a first aspect of the method of manufacturing a TFT of the present invention, a gate wiring and a gate electrode are formed on a surface of a glass substrate, a gate insulating film is formed on a surface of the glass substrate, and a surface of the gate insulating film is formed. Forming a stacked silicon film including a first silicon layer undoped, an O ₂ leak layer, a _second silicon layer having a thickness of 3 nm or more and 8 nm or less, and an n ⁺ -type third silicon layer; A first photoresist film pattern is formed on the surface of the laminated silicon film, and using the first photoresist film pattern as a mask, a mixed gas of CF ₄ and CHF ₃ is used to form at least the third and second silicon layers. the etching, further, the first silicon was leaving the gas containing at least SF ₆ and the first photoresist film pattern as a mask Forming a silicon film island by etching the metal film, forming a metal film on the entire surface, etching the metal film using the second photoresist film pattern formed on the surface of the metal film as a mask, and forming a source electrode and a drain electrode, as a mask at least the source and drain electrodes to remove the contamination layer formed on the surface of the silicon film island, further, HCl and chlorine Cl ₂
While the a mixed gas of SF ₆ have a selectively removing the third silicon layer of the second silicon of the
An oxygen gas layer is formed after the formation of the first silicon layer.
By the low discharge, the surface of the first silicon layer is covered with the O ₂
It is characterized in that it is converted into a leak layer .

Preferably, the first, second and third silicon layers are made of an amorphous silicon layer, and the first, second and third silicon layers are respectively formed by a plasma enhanced chemical vapor deposition (PECVD). The gate insulating film is formed of a laminated insulating film of a silicon oxide film and a silicon nitride film, and at least the silicon nitride film is formed by PECVD. A laminated insulating film composed of a silicon film and a second silicon oxide film, at least the silicon nitride film and the second silicon oxide film are each made of PE.
It is formed by CVD. Alternatively, the first, second, and third silicon layers are made of a polycrystalline silicon layer, and the first, second, and third silicon layers are formed by low-pressure vapor deposition (LPCVD), respectively. The gate insulating film is made of a silicon oxide film, and this silicon oxide film is formed by LPCVD.

According to a second aspect of the method of manufacturing a TFT of the present invention, a gate wiring and a gate electrode are formed on a surface of a glass substrate, a gate insulating film is formed on the surface of the glass substrate, and a surface of the gate insulating film is formed. a first silicon layer of undoped, from _{O 2} leakage layer Do Ri 3nm or more 8nm following
A second silicon layer having a thickness of, forming a third silicon layer and n ⁺ -type fourth laminated silicon film made of a silicon layer of undoped, first photoresist on the surface of the laminated silicon film A film pattern is formed, and using the first photoresist film pattern as a mask, a gas mixture of CF ₄ and CHF ₃ is used to form at least the fourth and third films.
Forming a silicon film island by etching the second silicon layer and etching the remaining first silicon layer with a gas containing at least SF ₆ using the first photoresist film pattern as a mask. Forming a metal film on the entire surface and etching the metal film using the second photoresist film pattern formed on the surface of the metal film as a mask to form a source wiring, a source electrode and a drain electrode; Using at least the source electrode and the drain electrode as masks, removing a contaminant layer formed on the surface of the silicon film island, and further using the mixed gas of one of HCl and Cl ₂ with SF ₆ to form the fourth and fourth layers. 3) selectively removing the silicon layer.

Preferably, the first, second, and third silicon layers are made of an amorphous silicon layer, and the first, second, and third silicon layers are respectively formed by a plasma enhanced chemical vapor deposition (PECVD). The gate insulating film is formed of a laminated insulating film of a silicon oxide film and a silicon nitride film, and at least the silicon nitride film is formed by PECVD. A laminated insulating film composed of a silicon film and a second silicon oxide film, at least the silicon nitride film and the second silicon oxide film are each made of PE.
It is formed by CVD. Alternatively, the first, second, and third silicon layers are made of a polycrystalline silicon layer, and the first, second, and third silicon layers are formed by low-pressure vapor deposition (LPCVD), respectively. The gate insulating film is made of a silicon oxide film, and this silicon oxide film is formed by LPCVD.

[0024]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1A, which is a schematic plan view of a TFT, and FIG. 1B, which is a schematic cross-sectional view taken along the line AA in FIG. 1A, a first embodiment of the present invention is described. The TFT according to the first embodiment has a structure described below.

The surface of the glass substrate 101 on which the gate wiring 102 and the gate electrode 103 are provided includes the gate insulating film 10 including the gate wiring 102 and the gate electrode 103.
9a. The gate insulating film 109a is formed by stacking, for example, a silicon oxide film 105a having a thickness of about 100 nm and a silicon nitride film 106ab having a thickness of about 400 nm. At least the silicon nitride film 106ab is made of PE
Since the silicon nitride film 10 is formed by CVD,
6ab contains hydrogen (H). The reason why the gate insulating film 109a has a stacked structure of the silicon oxide film 105a and the silicon nitride film 106ab is to take measures against pinholes present in the silicon oxide film 105a.

An amorphous silicon film island 115aa is provided on the surface of the gate insulating film 109a. This amorphous silicon film island 115aa is, for example, 4
An undoped first amorphous silicon layer 111aa having a thickness of about 5 nm, for example, a second amorphous silicon layer (O ₂ leak layer) 112a containing oxygen having a thickness of about 5 nm, and n having a thickness of about 50 nm, for example. ^{It is} composed of a laminated film of a ⁺ type third amorphous silicon layer 114ab. Amorphous silicon layer 1
11aa, 112a, and 114ab each contain hydrogen.

On the surface of the gate insulating film 109a, a source wiring 121a is provided.
A source electrode 122a and a drain electrode 124a are provided so as to extend from the surface of 15aa to the surface of gate insulating film 109a. These source wirings 12
1a, source electrode 122a and drain electrode 124a
Is made of, for example, chromium (however, the invention is not limited to this, and may be made of an aluminum-based metal, molybdenum, or the like). In the amorphous silicon film island 115aa, the amorphous silicon layer 114a
b exists in a self-alignment manner only under the source electrode 122a and the drain electrode 124a. In portions not covered by the source electrode 122a and the drain electrode 124a, the amorphous silicon film island 115
The surface of aa is composed of the O ₂ leak layer 112a. The gate electrode 103a, the amorphous silicon film island 115aa,
The channel length L and channel width W of this TFT comprising the source electrode 122a and the drain electrode 124a are, for example, 6 μm and 12 μm (but are not limited to these values).

The surface of the gate insulating film 109a including the source wiring 121a and the TFT is covered with an interlayer insulating film 125.
a. A contact hole 127a reaching the drain electrode 124a is provided in the interlayer insulating film 125a, and an ITO electrode (pixel electrode) 128a provided on the surface of the interlayer insulating film 125a is connected to the drain electrode 124a via the contact hole 127a. .

The TF at the portion along the line AA in FIG.
2 and 3 which are schematic cross-sectional views of the manufacturing process of T, FIG. 1, FIG. 4 which is a graph for explaining the first to third amorphous silicon film formation methods, and FIG. Referring to FIG. 5 which is a graph for explaining the etching for forming the amorphous silicon film island 115aa,
A method for forming T will be described.

First, a metal film is formed on the surface of the glass substrate 101 by sputtering or the like. The metal film is, for example, aluminum (Al) or chromium (Cr), but is not limited thereto. This metal film is patterned by isotropic etching to form a gate wiring 102 and a gate electrode 103. The reason why isotropic etching is used for this patterning is to perform taper etching. Subsequently, the gate wiring 10
2 and the gate electrode 103, the glass substrate 101
A silicon oxide film 105a having a thickness of, for example, about 100 nm is formed on the surface of the substrate, and a silicon nitride film 106a having a thickness of, for example, about 400 nm is formed by PECVD. The silicon oxide film is formed by sputtering or APCVD, but may be formed by PECVD. Note that the thicknesses of the silicon oxide film 105a and the silicon nitride film 106a are not limited to the above values.

Next, referring to FIG. 4, a first amorphous silicon layer 111a and O ₂ (which is a _second amorphous silicon film)
Leak layer 112a and third amorphous silicon film 114
The method of forming a will be described. These amorphous silicon layers have a pressure of, for example, 65 Pa and an RF power of, for example, 50 W.
It is formed by PECVD under the following conditions.

About 1 l / min of H ₂ and about 0.25
1 / min of SiH ₄ is flowed for about 2.5 minutes,
An (undoped first) amorphous silicon layer 111a having a thickness of about 0 nm is formed. After the film forming gas is shut off for about 10 seconds, the gas is purged with nitrogen (N ₂ ) for about 1 minute. O ₂ (diluted to about 5% with N ₂ ) is flowed for about 1 minute at a flow rate of about 1.5 l / min, and the thickness of about 5 nm on the surface of the amorphous silicon O ₂ leak layer 112
is converted to a. Again, after the film forming gas is shut off for about 10 seconds, it is purged with nitrogen (N ₂ ) for about 1 minute.
A generally H ₂ of 0.4l / min, approximately 0.25l / mi
n of SiH ₄ and PH _{3 of} about 0.7 l / min (diluted to about 0.5% by H ₂ ) are flowed for about 2.5 minutes to form a 50 nm thick (n ⁺ type) Third)
An amorphous silicon layer 114a is formed. The phosphorus concentration of the amorphous silicon layer 114a is of the order of 10 ²⁶ m ⁻³ (10 ²⁰ cm ⁻³ ). The resistivity of the O ₂ leak layer 112a is about 2 to 4 times that of the amorphous silicon layer 111a (FIG. 2A).

The amorphous silicon layers 111a, O_Two Re
Thickness of Work Layer 112a and Amorphous Silicon Layer 114a
In addition, the formation conditions are not limited to the above. O_Two 
O when forming the leak layer 112a_Two Dilution is 1
It is preferably in the range of 00 ppm to 1%. O_Two Re
The thickness of the work layer 112a is determined by a (back)
3 to function as a stopper for channel etching
nm or more, and R_onFrom the contribution to
It is preferably 8 nm or less. In addition, SiH_Four Of
Disilane (Si_Two H₆ ) Can also be used. This
In the case of _Four Amorphous silicon layer than when using
The content of hydrogen in it is low.

Next, the first photoresist film pattern 1
31 as a mask, the amorphous silicon layer 114a, O_Two 
The leak layer 112a and the amorphous silicon layer 111a are
Next, it is etched. The amorphous silicon layer 114a and
O_Two The leak layer 112a is made of CF _Four + CHF_Three Due to isotropic
Dry-etched, the amorphous silicon layer 111a becomes SF ₆ 
Isotropic dry etching. Like this
Is performed for the following reason. CF_Four + CHF_Three 
Etching only with the silicon nitride film 106a
Is also considerably etched. On the other hand, SF₆ Only etch
When O is executed, as described later, O_Two In the leak layer 112a
Etching time is too long. This etching
The gas is switched by, for example, PF emission analysis.
It is. By this etching (the amorphous silicon layer 114
a, 111a are amorphous silicon layers 114aa,
111aa) amorphous silicon layer 111aa, O_Two 
Leak layer 112a and amorphous silicon layer 114aa are stacked
(First stage) amorphous silicon film pattern 11
5a is formed. SF₆ When etching by
The silicon nitride film 106a is also slightly etched,
It becomes the silicon film 106aa (FIG. 2B).

The photoresist film pattern is removed.
You. Then, for example, when the substrate temperature is 200 ° C., for example,
For example, a chromium film is formed on the entire surface by sputtering.
It is. Using the second photoresist film pattern 132 as a mask
Cerium ammonium nitrate ((NH_Four )_Two (Ce
(NO_Three )₆ )) Wet etching, Cl _Two 
+ Oxygen (O_Two ) By dry etching
The source film 121a and the source
The electrode 122a and the drain electrode 124a are formed.
You. This etching allows the amorphous silicon layer 114
On the surface of aa, a contamination film 119a is formed [FIG.
(C)].

The main component of the contamination film 119a is a natural oxide film. Since the film is exposed to the air and undergoes a cleaning process between the formation of the amorphous silicon layer 114a and the formation of chromium,
A natural oxide film has already been formed on the surface of the amorphous silicon film pattern 115a. One of the causes of the low control accuracy in the conventional (back) channel etching is the presence of the contaminant film 119a. At the stage when chromium is formed, the interface between chromium and the amorphous silicon film pattern 115a is Cr
₃ Si, it is likely that Cr ₅ Si _3, CrSi or chromium silicide such as CrSi ₂ is formed. Even if these chromium silicides are present, the chromium silicide is removed by dry etching with Cl ₂ + O ₂ . Further, hydrocarbons, which are general reaction products at the time of dry etching, are also removed by the etching containing O ₂ .

The photoresist film 132 is organically peeled off (FIG. 3A). Thereafter, using the source electrode 122a and the drain electrode 124a as a mask, the contamination film 119a is selectively removed by, for example, dry etching using hexafluorocyclobutane (C ₄ H ₈ ) [FIG.
(B)].

The subsequent (back) channel etching will be described with reference to FIG.

For example, RF power 1 kW, pressure 40 Pa
SF under₆ Is 0.03 l / min, SF₆ :
Cl_Two : H_Two Amorphous under the condition of flow rate ratio of 1: 4: 1
Silicon layer 114aa and O_Two The leak layer 112a
Etching, and further, the amorphous silicon layer 112aa
Until etched. Thereby, as shown in FIG.
Then, the etching rate ratio of each layer is obtained. That is,
Etching rate of doped amorphous silicon layer 112aa
Let 1 be n⁺ Type amorphous silicon layer 114aa and
And O_Two The etching rate ratio of leak layer 112a is 1.1.
About 5 and 0.05. Use this result
By O_Two Amorphous using leak layer 112a as stopper
The silicon layer 114aa is selectively removed by etching.
Can be. As a result, the channel etch portion 117a
The amorphous silicon layer 114aa is formed of amorphous silicon.
Layer 114ab, and the amorphous silicon layer 114ab,
O _Two Leak layer 112a and amorphous silicon layer 111a
(second stage) amorphous silicon film island
115aa is formed. Also, in this etching
The silicon nitride film 106aa is also slightly etched.
The silicon oxide film 10aa becomes the silicon nitride film 106aa.
5a on which a silicon nitride film 106aa is laminated.
The insulating film 109a is obtained [FIG. 3 (c), FIG. 1].

The conditions for the channel etching are not limited to the above conditions. In this channel etch, HCl may be used instead of Cl ₂ + H ₂ . Also, if the etching rate itself is reduced by reducing the RF power or the flow rate of SF ₆ (while maintaining the flow rate ratio), the first embodiment of the first embodiment of the first embodiment can be more accurately performed. Channel etch can be performed.

Thereafter, formation of an interlayer insulating film 125a, formation of a contact hole 127a, formation of an ITO film 128a, and the like are performed to obtain the structure shown in FIG.

The manufacturing method according to the first embodiment is not limited to the method shown in FIG. After the stage shown in FIG. 2C, (the TFT at the AA line portion in FIG.
The TFT of the first embodiment can also be obtained by the manufacturing method shown in FIG. 6 (in this method, in particular, the constituent material such as the source wiring is made of, for example, an aluminum-based metal). Is advantageous in cases).

After forming the source wiring 121, the source electrode 122 and the drain electrode 124a using the photoresist film pattern 132 as a mask, the photoresist film 13
Using the mask 2 as a mask, the contamination film 119a is selectively removed [FIG. 6 (a)].

Further, a photoresist film pattern 132
Is used as a mask to form a channel etch portion 117a, an amorphous silicon film island 115aa, a gate insulating film 109a, etc. (FIG. 6B).

Next, the photoresist film pattern 132 is removed by dry etching with nitrogen trifluoride (NF ₃ ) + H ₂ O. Thereafter, formation of the interlayer insulating film 125a, formation of the contact hole 127a, formation of the ITO film 128a, and the like are performed, and the structure in FIG. 1 is obtained.

In the case of the various parameters described above, the measured values of the Id-Vg characteristics of the TFT according to the first embodiment are as shown in FIG. By comparing FIG. 7A with FIG. 16A, the R of the TFT of the present embodiment is larger than that of the conventional TFT.
It becomes clear that the variation in the value of _off is reduced and increased. Further, from FIG. 7B and FIG. 16B, it can be seen that the value of R _on of the TFT of this embodiment is about 1/2 times lower than that of the conventional TFT.

The first embodiment of the first embodiment is a TFT including an amorphous silicon film island. The technical idea of the first embodiment is based on the assumption that a polycrystalline silicon film island is used. It is easy to apply to the TFT that includes.

In this case, a glass substrate made of quartz is used, and the gate insulating film is made of LTE using a TEOS-based source gas.
It consists of only a single layer of a silicon oxide film formed by PCVD. Also, a polycrystalline silicon film island is used instead of the amorphous silicon film island. This polycrystalline silicon film island is formed by laminating an undoped first polycrystalline silicon layer, an O ₂ leak layer as a _second polycrystalline silicon layer, and an n ⁺ -type third polycrystalline silicon layer. These first to third polycrystalline silicon layers are at 650 ° C.
It is formed by LPCVD to a certain degree. The sequence of this film formation is the same as that of the first embodiment. Also, the method of the first embodiment can be applied to a (back) channel etching method for a polycrystalline silicon film island. The TFT including the polycrystalline silicon film island can be formed without containing hydrogen in the gate insulating film and the polycrystalline silicon film island.

The TFT according to the second example of the first embodiment of the present invention is shown in FIGS.
This will be described with reference to FIG. 8B, which is a schematic cross-sectional view taken along the line AA in FIG. The difference between the second example of the first embodiment of the present invention and the first example of the first embodiment is in the structure of the amorphous silicon film island.

The surface of the glass substrate 101 on which the gate wiring 102 and the gate electrode 103 are provided includes the gate insulating film 10 including the gate wiring 102 and the gate electrode 103.
9b. The gate insulating film 109b is formed by stacking, for example, a silicon oxide film 105bb having a thickness of about 400 nm on a silicon oxide film 105b having a thickness of 100 nm. At least the silicon nitride film 106bb contains hydrogen (H).

An amorphous silicon film island 115ba is provided on the surface of the gate insulating film 109b. This amorphous silicon film island 115ba is, for example, 2
An undoped first amorphous silicon layer 111ba having a thickness of about 0 nm, for example, a second amorphous silicon layer (O ₂ leak layer) 112b containing oxygen having a thickness of about 5 nm,
For example, an undoped third amorphous silicon layer 113bb having a thickness of about 25 nm and n ⁺
And a stacked film of a fourth amorphous silicon layer 114bb. Amorphous silicon layers 111ba, 112b, 113b
b and 114bb each contain hydrogen.

The source wiring 121b is provided on the surface of the gate insulating film 109b, and the amorphous silicon film island 1 is formed.
A source electrode 122b and a drain electrode 124b are provided so as to extend from the surface of 15ba to the surface of gate insulating film 109b. These source wirings 12
1b, source electrode 122b and drain electrode 124b
Is made of, for example, chromium (however, the invention is not limited to this, and may be made of an aluminum-based metal, molybdenum, or the like). In the amorphous silicon film island 115ba, the amorphous silicon layer 114b
b and the amorphous silicon layer 113bb
2a and the self-alignment exist only under the drain electrode 124a. In portions not covered by the source electrode 122b and the drain electrode 124b, the surface of the amorphous silicon film island 115ba is formed of the O ₂ leak layer 112b. Gate electrode 103b, amorphous silicon film island 115ba, source electrode 122b
The channel length L and channel width W of the TFT including the drain electrode 124b are, for example, 6 μm and 12 μm (but are not limited to these values).

The surface of the gate insulating film 109b, including the source wiring 121b and the TFT, is covered with an interlayer insulating film 125.
b. A contact hole 127b reaching the drain electrode 124b is provided in the interlayer insulating film 125b, and an ITO electrode (pixel electrode) 128b provided on the surface of the interlayer insulating film 125b is connected to the drain electrode 124b via the contact hole 127b. .

The TF at the portion along the line AA in FIG.
The method of forming the TFT will be described with reference to FIGS.

First, a metal film is formed on the surface of the glass substrate 101 by sputtering or the like, and this metal film is patterned by isotropic etching to form a gate wiring 1.
02, a gate electrode 103 is formed. Subsequently, on the surface of the glass substrate 101 including the gate wiring 102 and the gate electrode 103, a silicon oxide film 105b having a thickness of, for example, about 100 nm is formed.
The silicon nitride film 106b having a thickness of about 0 nm is made of PECV
D. Note that the silicon oxide film 105b,
The thickness of the silicon nitride film 106b is not limited to the above value.

Next, using the method of forming an amorphous silicon layer used in the first embodiment, a non-doped first amorphous silicon layer 111a having a thickness of, for example, about 25 nm is formed. (diluted by, for example, about 5% N ₂₎
By exposing to an O ₂ atmosphere, the thickness of, for example, about 5 nm on the surface of the amorphous silicon layer 111b is converted into an O ₂ leak layer 112b (which is a second amorphous silicon layer).
n ⁺ -type third amorphous silicon layer 114 having a thickness of about nm
b is formed (FIG. 9A).

Next, the amorphous silicon layer 114 is formed using the first photoresist film pattern (not shown) as a mask.
b, amorphous silicon layer 113b, O ₂ leak layer 112b
And the amorphous silicon layer 111b are sequentially etched. Amorphous silicon layer 114b, amorphous silicon layer 11
3b and the O ₂ leak layer 112b are isotropically dry-etched with CF ₄ + CHF ₃ to form an amorphous silicon layer 111.
b is isotropic dry etching by SF _6. By this etching (the amorphous silicon layers 114b, 113b,
111b denotes amorphous silicon layers 114ba and 11ba, respectively.
3 ba, 111 ba) Amorphous silicon layer 111 b
a, O ₂ leak layer 112b, amorphous silicon layer 113b
a, an amorphous silicon layer 114ba is laminated (first
A (step) amorphous silicon film pattern 115b is formed. During the etching with SF ₆ , the silicon nitride film 106 b is also slightly etched,
6 ba (FIG. 9B).

The first photoresist film pattern is removed. Subsequently, at a substrate temperature of, for example, 200 ° C., a chromium film, for example, is formed on the entire surface by, for example, sputtering. Second photoresist film pattern 132
The chromium film is patterned by wet etching using (NH ₄ ) ₂ (Ce (NO ₃ ) ₆ ) with the mask as a mask, and dry etching with Cl ₂ + O ₂ to form a source wiring 121b, a source electrode 122b, and a drain electrode 124b. Is formed. By this etching,
A contamination film 119 is formed on the surface of the amorphous silicon layer 114ba.
b is formed [FIG. 9 (c)].

For example, after the photoresist film 132 is peeled off organically, the source electrode 122b and the drain electrode 1
Using the 24b as a mask, the contamination film 119b is made of, for example, C ₄ H
_{8 is} selectively removed by dry etching (note that the manufacturing method described in the first embodiment with reference to FIG. 6 can also be employed in the second embodiment).

Subsequently, using the method used in the first embodiment, the amorphous silicon layer 114ba and the amorphous silicon layer 113 are formed using the O ₂ leak layer 112b as a stopper.
Ba is selectively removed by etching. As a result, a channel etch portion 117b is formed, and the amorphous silicon layer 1 is formed.
14ba and 113ba are amorphous silicon layers 114bb1
13bb, and a (second stage) amorphous silicon film island 115ba consisting of the amorphous silicon layer 114bb, the amorphous silicon layer 113bb, the O ₂ leak layer 112b, and the amorphous silicon layer 111ba is formed. At the time of this etching, the silicon nitride film 106b
a is also etched slightly to form the silicon nitride film 106ba, and the silicon nitride film 106b is formed on the silicon oxide film 105b.
The gate insulating film 109b in which ba is laminated is obtained (FIGS. 9D and 8).

Thereafter, formation of an interlayer insulating film 125b, formation of a contact hole 127b, formation of an ITO film 128b, and the like are performed to obtain the structure shown in FIG.

In the case of the various parameters described above, the measured values of the Id-Vg characteristics of the TFT according to the second embodiment are as shown in FIG. By comparing FIG. 10A with FIG. 16A, the TFT of the present embodiment is compared with the conventional TFT.
It becomes clear that the variation in the value of R _off becomes smaller and higher. FIG. 10B and FIG.
From (b), the TFT of the present embodiment is compared with the conventional TFT.
It can be seen that the value of R _on is about 1/2 times lower. In comparison with the first embodiment, in the second embodiment (since the thickness of the first amorphous silicon layer is smaller in the second embodiment), the off characteristic is The on characteristics are further improved, and the on characteristics are slightly reduced.

The second example of the first embodiment is similar to the first example of the first embodiment.
It is easy to apply to a TFT including a polycrystalline silicon film island.

In the second embodiment of the present invention, the gate insulating film is composed of a laminated insulating film of a first silicon oxide film, a silicon nitride film and a second silicon oxide film. In the first embodiment, since the gate insulating film has the two-layer structure of the silicon oxide film and the silicon nitride film, the upper surface of the gate insulating film is slightly formed when forming the silicon film island and the (back) channel etch portion. Etch off.
In the second embodiment, it is easy to suppress the etch-off of the upper surface of the gate insulating film in these etching steps and to suppress an increase in the coupling capacitance between the gate wiring and the source wiring.

FIG. 11A which is a schematic plan view of a TFT and FIG. 11 which is a schematic cross-sectional view taken along line AA in FIG. 11A.
Referring to (b), the TFT according to the first example of the second embodiment of the present invention has a structure described below.

The surface of the glass substrate 201 on which the gate wiring 202 and the gate electrode 203 are provided includes the gate insulating film 20 including the gate wiring 202 and the gate electrode 203.
9a. The gate insulating film 209a is formed by stacking, for example, a first silicon oxide film 205a having a thickness of 100 nm, a silicon nitride film 206a having a thickness of about 100 nm, and a second silicon oxide film 207aa having a thickness of, for example, about 300 nm. At least the silicon nitride film 206a and the silicon oxide film 207aa are PECV
D, the silicon nitride film 206
a, The silicon oxide film 207aa contains hydrogen (H).

An amorphous silicon film island 215aa is provided on the surface of the gate insulating film 209a. This amorphous silicon film island 215aa is, for example, 4
An undoped first amorphous silicon layer 211aa having a thickness of about 5 nm, for example, a second amorphous silicon layer (O ₂ leak layer) 212a containing oxygen having a thickness of about 5 nm, and n having a thickness of about 50 nm, for example. ^{It is} composed of a laminated film of a ⁺ type third amorphous silicon layer 214ab. Amorphous silicon layer 2
11aa, 212a, and 214ab each contain hydrogen.

A source wiring 221a is provided on the surface of the gate insulating film 209a.
A source electrode 222a and a drain electrode 224a are provided so as to extend from the surface of 15aa to the surface of gate insulating film 209a. These source wirings 22
1a, source electrode 222a and drain electrode 224a
Is made of, for example, chromium (however, the invention is not limited to this, and may be made of an aluminum-based metal, molybdenum, or the like). In the amorphous silicon film island 215aa, the amorphous silicon layer 214a
b exists in the self-alignment only under the source electrode 222a and the drain electrode 224a. In a portion not covered by the source electrode 222a and the drain electrode 224a, the amorphous silicon film island 215
The surface of aa is composed of the O ₂ leak layer 212a. A gate electrode 203a, an amorphous silicon film island 215aa,
The channel length L and channel width W of this TFT comprising the source electrode 222a and the drain electrode 224a are, for example, 6 μm and 12 μm (but are not limited to these values).

The surface of the gate insulating film 209a including the source wiring 221a and the TFT is formed on the surface of the interlayer insulating film 225.
a. A contact hole 227a reaching the drain electrode 224a is provided in the interlayer insulating film 225a, and an ITO electrode (pixel electrode) 228a provided on the surface of the interlayer insulating film 225a is connected to the drain electrode 224a via the contact hole 227a. .

The T at the portion along the line AA in FIG.
12 and 13 which are schematic cross-sectional views of a manufacturing process of the FT.
A method for forming the TFT will be described with reference to FIGS.

First, a metal film is formed on the surface of the glass substrate 201 by sputtering or the like. This metal film is patterned by isotropic etching to form a gate wiring 202 and a gate electrode 203. Subsequently, on the surface of the glass substrate 201 including the gate wiring 202 and the gate electrode 203, a silicon oxide film 205a having a thickness of, for example, about 100 nm is formed.
The silicon nitride film 206a having a thickness of about 00 nm and the silicon oxide film 207a having a thickness of about 300 nm
It is formed by ECVD. This silicon oxide film 205
Although the film formation method a is sputtering or APCVD, it may be performed by PECVD. Note that the thicknesses of the silicon oxide film 205a, the silicon nitride film 206a, and the silicon oxide film 207a are not limited to the above values.

Next, by a method similar to that of the first embodiment of the first embodiment, the surface of the gate insulating film 209a is formed on the surface of the amorphous silicon layer 211a of, eg, about 45 nm by PECVD. O2 with a thickness of about 5 nm
A leak layer 212a, for example, an amorphous silicon layer 214a having a thickness of about 50 nm is formed (FIG. 12A).

Next, the first photoresist film pattern 2
31 as a mask, the first
Of the amorphous silicon layer 214a, O
_{2 The} leak layer 212a and the amorphous silicon layer 211a are sequentially etched. The amorphous silicon layer 214a and the O ₂ leak layer 212a are isotropically dry-etched with CF ₄ + CHF ₃ , and the amorphous silicon layer 211a is SF
₆ Isotropic dry etching. By this etching (the amorphous silicon layers 214a and 211a become amorphous silicon layers 214aa and 211aa, respectively), the amorphous silicon layer 211aa, the O ₂ leak layer 212a, and the amorphous silicon layer 214aa are laminated ( The first stage)
An amorphous silicon film pattern 215a is formed. In the present embodiment, unlike the first embodiment of the first embodiment, the etch-off of the upper surface of the gate insulating film 209a hardly occurs at the time of etching with SF ₆ (FIG. 12B).

The photoresist film pattern 231 is removed. Subsequently, at a substrate temperature of, for example, 200 ° C., a chromium film, for example, is formed on the entire surface by, for example, sputtering. Second photoresist film pattern 232
The chromium film is patterned by wet etching using (NH ₄ ) ₂ (Ce (NO ₃ ) ₆ ) with the mask as a mask and dry etching with Cl ₂ + O ₂ to form a source wiring 221a, a source electrode 222a, and a drain electrode 224a. Is formed. By this etching,
A contamination film 219 is formed on the surface of the amorphous silicon layer 214aa.
a is formed (FIG. 12C).

For example, the photoresist film 132 is organically peeled off. (In this embodiment, the manufacturing method described in FIG. 6 in the first embodiment of the first embodiment may be adopted. Is possible) [FIG.
(A)].

Thereafter, using the source electrode 222a and the drain electrode 224a as masks, the contamination film 219a is selectively removed by, for example, dry etching with C ₄ H ₈ . At this time, the surface of the silicon oxide film 207a is also slightly etched to become the silicon oxide film 207aa. Thus, the silicon oxide film 209a has a laminated structure of the silicon oxide film 205a, the silicon nitride film 206a, and the silicon oxide film 207aa (FIG. 13B).

Subsequently, the first embodiment of the first embodiment is described.
(Back) channel etching is performed by the same method as that of the embodiment. Thereby, the channel etch unit 2
17a is formed, the amorphous silicon layer 214aa becomes the amorphous silicon layer 214ab, and the amorphous silicon layer
A (second stage) amorphous silicon film island 215aa including the 4ab, O ₂ leak layer 212a and the amorphous silicon layer 211aa is formed. Unlike the first embodiment of the first embodiment, the upper surface of the gate insulating film 209a is not etched off during this etching [FIGS. 13 (c) and 11].

Thereafter, formation of an interlayer insulating film 225a, formation of a contact hole 227a, formation of an ITO film 228a, and the like are performed to obtain the structure of FIG.

This embodiment has the same effect as the Id-Vg characteristic of the first embodiment of the first embodiment. Further, the reduction of the parasitic capacitance due to the gate insulating film and the threshold voltage (Vt) of the TFT is easier than in the first example of the first embodiment.

The TFT according to the second example of the second embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. 14B, which is a schematic cross-sectional view taken along line AA of FIG.

The surface of the glass substrate 201 on which the gate wiring 202 and the gate electrode 203 are provided includes the gate insulating film 20 including the gate wiring 202 and the gate electrode 203.
9b. The gate insulating film 209b has a stacked structure of a silicon oxide film 205b having a thickness of, for example, 100 nm, a silicon nitride film 206b having a thickness of, for example, about 100 nm, and a silicon oxide film 207b having a thickness of, for example, about 300 nm. At least a silicon nitride film 206b,
The silicon oxide film 207b contains hydrogen (H).

An amorphous silicon film island 215b is provided on the surface of the gate insulating film 209b. This amorphous silicon film island 215b is, for example, 20 n
m-thick undoped first amorphous silicon layer 2
11b, for example, a second layer containing oxygen having a thickness of about 5 nm.
Amorphous silicon layer (O ₂ leak layer) 212b, for example, an undoped third amorphous silicon layer 213b having a thickness of about 25 nm, and an n ⁺ -type fourth
Of the amorphous silicon layer 214b. Amorphous silicon layers 211b, 212b, 213b, 214b
Each contain hydrogen.

On the surface of the gate insulating film 209b, a source wiring 221b is provided.
Source electrode 222b and drain electrode 124b are provided so as to extend from the surface of gate insulating film 209b to the surface of gate insulating film 209b. These source wirings 221
b, source electrode 222b and drain electrode 224b
Is made of, for example, chromium (however, the invention is not limited to this, and may be made of an aluminum-based metal, molybdenum, or the like). In the amorphous silicon film island 215b, the amorphous silicon layer 214bb
In addition, the amorphous silicon layer 213b has a source electrode 222a.
And self-alignment only under the drain electrode 224a. In the channel etch portion 217b, which is not covered by the source electrode 222b and the drain electrode 224b, the surface of the amorphous silicon film island 215b is made of the O ₂ leak layer 212b.
Gate electrode 203b, amorphous silicon film island 21
5ba, source electrode 222b and drain electrode 224
b, the channel length L and channel width W of this TFT
Are, for example, 6 μm and 12 μm (but are not limited to these values).

The surface of the gate insulating film 209b including the source wiring 221b and the TFT is covered with an interlayer insulating film 225.
b. A contact hole 227b reaching the drain electrode 224b is provided in the interlayer insulating film 225b, and an ITO electrode (pixel electrode) 228b provided on the surface of the interlayer insulating film 225b is connected to the drain electrode 224b via the contact hole 227b. .

The second embodiment has the same effect as the Id-Vg characteristic of the second embodiment of the first embodiment. Further, the reduction of the parasitic capacitance associated with the gate insulating film and the threshold voltage (Vt) of the TFT is easier than in the second example of the first embodiment.

[0087]

As described above, according to the present invention, the TF
T is formed on the following silicon film island. This silicon film island is formed by stacking an n ⁺ type silicon layer on an undoped silicon layer.
An O ₂ leak layer (which is an undoped silicon layer containing oxygen) is provided at the interface between the lower undoped silicon layer and the n ⁺ -type silicon layer or in the lower undoped silicon layer. Due to the presence of the O ₂ leak layer, the controllability and accuracy of the formation of the channel etch portion are improved. Furthermore, since no problem occurs even if the thickness of the underlying undoped silicon film is reduced, the IV characteristics can be easily improved.

[Brief description of the drawings]

FIG. 1 is a schematic plan view and a schematic sectional view of a first example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the first example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG.

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the first example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG.

FIG. 4 is a graph for explaining a method of forming an amorphous silicon layer in the first example of the first embodiment.

FIG. 5 is a graph for explaining a method of forming a channel-etched portion in the first example of the first embodiment.

FIG. 6 is a graph showing T of the first embodiment of the first embodiment;
FIG. 1 is a diagram for explaining another method of forming an FT, and FIG.
It is a cross section of a manufacturing process in an AA line of (a).

FIG. 7 shows T of the first embodiment of the first embodiment.
It is a graph of IV characteristic of FT.

FIG. 8 is a schematic plan view and a schematic cross-sectional view of a second example of the first embodiment.

FIG. 9 is a schematic cross-sectional view of the manufacturing process of the second example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG.

FIG. 10 is a graph of IV characteristics of the TFT of the second embodiment of the first embodiment.

FIG. 11 is a schematic plan view and a schematic sectional view of a first example of the second embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of the manufacturing process of the first example of the second embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG.

FIG. 13 is a schematic cross-sectional view of the manufacturing process of the first example of the second embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 11A.

FIG. 14 is a schematic plan view and a schematic cross-sectional view of a second example of the second embodiment of the present invention.

15A and 15B are a schematic plan view and a schematic cross-sectional view illustrating a conventional TFT.

FIG. 16 is a graph showing IV characteristics of the conventional TFT.

[Explanation of symbols]

101, 201, 301 Glass substrates 102, 202, 302 Gate wirings 103, 203, 303 Gate electrodes 105a, 105b, 205a, 205b, 207a,
207aa, 207b, 305 Silicon oxide films 106a, 106aa, 106ab, 106b, 106
ba, 106bb, 206a, 206b, 306 Silicon nitride films 111a, 111aa, 111b, 111ba, 113
b, 113ba, 113bb, 114a, 114aa,
114ab, 114b, 114ba, 114bb, 21
1a, 211ab, 211b, 211ba, 213b,
214a, 214aa, 214ab, 214b, 31
1,314 amorphous silicon layer 112a, 112b, 212a, 212b O 2 leakage layer 115a, 115aa, 115b, 115ba, 215
a, 215aa, 215b, 315 Amorphous silicon film islands 117a, 117b, 217a, 217b, 317
Channel etch portions 119a, 119b, 219a Contamination films 121a, 121b, 221a, 221b, 321
Source wiring 122a, 122b, 222a, 222b, 322
Source electrodes 124a, 124b, 224a, 224b, 324
Drain electrodes 125a, 125b, 225a, 225b, 325
Interlayer insulating films 127a, 127b, 227a, 227b, 327
Contact holes 128a, 128b, 228a, 228b, 328
ITO electrode 131, 132, 231, 232 Photoresist film pattern

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-5578 (JP, A) JP-A-61-281555 (JP, A) JP-A-1-209764 (JP, A) JP-A-3-3 283466 (JP, A) JP-A-4-186880 (JP, A) JP-A-62-213278 (JP, A) JP-A-63-308384 (JP, A) JP-A-3-217027 (JP, A) JP-A-2-260661 (JP, A) JP-A-8-335703 (JP, A) JP-A-64-57755 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (15)

(57) [Claims] A glass substrate provided with a gate electrode and a gate wiring on a surface thereof is covered with a gate insulating film including the gate electrode and the gate wiring, and a silicon film island having a laminated structure is provided on a surface of the gate insulating film. The silicon film island comprises an undoped first silicon layer directly covering the surface of the gate insulating film, and an O ₂ leak layer formed on the surface of the first silicon layer.
a second silicon layer having a thickness of not more than nm, an undoped third silicon layer provided on the surface of the second silicon layer, and n ⁺ provided on the surface of the third silicon layer.
A source line, a source electrode and a drain electrode are provided on the surface of the gate insulating film including the silicon film island, and the fourth and third silicon layers of the silicon film island are formed. Wherein the silicon layer is removed in a self-aligned manner with the source electrode and the drain electrode. Wherein said first to fourth silicon layer constituting the silicon film islands, thin film transistor according to claim 1, characterized in that each amorphous silicon layer. 3. The thin film transistor according to claim 2 , wherein said gate insulating film is formed by stacking a silicon nitride film on a surface of a silicon oxide film. 4. The thin film transistor according to claim 2 , wherein said gate insulating film is a laminated insulating film including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. Wherein said first to fourth silicon layer constituting the silicon film islands, each composed of a polysilicon layer, according to claim 1, wherein said gate insulating film, characterized in that a silicon oxide film The thin film transistor according to any one of the preceding claims. 6. A gate wiring and a gate electrode are formed on a surface of a glass substrate, a gate insulating film is formed on a surface of the glass substrate, and an undoped first silicon layer and an O ₂ leak are formed on the surface of the gate insulating film. the third of the second silicon layer and n ⁺ -type consisting of be 3nm or more 8nm thick or less layer
Forming a laminated silicon film composed of a silicon layer of the following; forming a first photoresist film pattern on the surface of the laminated silicon film, and using the first photoresist film pattern as a mask to form tetrafluoromethane (CF _4); ) And trifluoromethane (CHF ₃ ) to etch at least the third and second silicon layers, and further using the first photoresist film pattern as a mask to at least sulfur hexafluoride (SF ₆ ). Forming a silicon film island by etching the remaining first silicon layer by using a gas containing: a second metal film formed on the entire surface of the metal film;
Etching the metal film using the photoresist film pattern as a mask to form a source wiring, a source electrode and a drain electrode; and forming at least the source electrode and the drain electrode as a mask on the surface of the silicon film island. the formed contamination layer was removed, further, have a selectively removing said third silicon layer of a mixed gas of one and SF ₆ hydrogen chloride (HCl) and chlorine (Cl _2), The second silicon layer is formed by forming the first silicon layer.
Later, the first silicon is glowed by oxygen gas glow discharge.
A method for manufacturing a thin film transistor, comprising converting a layer surface to the O ₂ leak layer . 7. The first, second and third silicon layers comprise an amorphous silicon layer.
Each of the silicon layers is plasma-enhanced vapor phase epitaxy (PE
7. The method according to claim 6 , wherein the thin film transistor is formed by CVD. 8. The method of manufacturing a thin film transistor according to claim 7, wherein said gate insulating film comprises a laminated insulating film of a silicon oxide film and a silicon nitride film, and at least said silicon nitride film is formed by PECVD. 9. The gate insulating film comprises a laminated insulating film including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film, and at least the silicon nitride film and the second silicon oxide film are each made of PECVD. The method for manufacturing a thin film transistor according to claim 7 , wherein the thin film transistor is formed by: 10. The first, second and third silicon layers are made of a polycrystalline silicon layer, and the first, second and third silicon layers are respectively formed by a low pressure chemical vapor deposition (LPCV) method.
7. The method according to claim 6 , wherein the gate insulating film is formed of a silicon oxide film, and the silicon oxide film is formed by LPCVD. 11. A gate wiring and a gate electrode are formed on a surface of a glass substrate, a gate insulating film is formed on a surface of the glass substrate, and an undoped first film is formed on a surface of the gate insulating film.
Silicon layer, 3 nm or more 8nm consist _{O 2} leakage layer
Forming a stacked silicon film including a second silicon layer having the following thickness, an undoped third silicon layer, and an n ⁺ -type fourth silicon layer; and forming a first silicon layer on the surface of the stacked silicon film. Forming a photoresist film pattern, etching the at least the fourth, third and second silicon layers with a mixed gas of CF ₄ and CHF ₃ using the first photoresist film pattern as a mask; Etching the remaining first silicon layer with a gas containing at least SF ₆ using the first photoresist film pattern as a mask to form a silicon film island; forming a metal film on the entire surface; The second formed on the surface of
Forming a source wiring, a source electrode and a drain electrode by using the photoresist film pattern as a mask to form a source wiring, a source electrode and a drain electrode; Removing the formed contaminant layer, and further selectively removing the fourth and third silicon layers with a mixed gas of one of HCl and Cl ₂ and SF _6. Manufacturing method. 12. The first, second, third and fourth silicon layers comprise an amorphous silicon layer,
The process according to claim 1 1, wherein the thin film transistor, wherein a third and fourth silicon layer is formed by PECVD, respectively. Wherein said gate insulating film is a laminated insulating film of a silicon oxide film and a silicon nitride film, a manufacturing method of claim 1 wherein the thin film transistor at least the silicon nitride film is characterized by being formed by PECVD . 14. The gate insulating film comprises a laminated insulating film including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film, and at least the silicon nitride film and the second silicon oxide film are each made of PECVD. the method for fabricating the thin film transistor according to claim 1 2, wherein it is formed by. 15. The semiconductor device according to claim 15, wherein the first, second, third and fourth silicon layers comprise a polycrystalline silicon layer.
Third and fourth silicon layer is formed by LPCVD respectively, the gate insulating film is a silicon oxide film, the silicon oxide film is a thin film transistor according to claim 1 1, wherein the formed by LPCVD Production method.