JP3512893B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a basic cell having a normal driving capability (hereinafter referred to as a normal cell) and a basic cell having an enhanced driving capability (hereinafter referred to as a basic cell). , A reinforced cell), and a semiconductor integrated circuit device having an internal cell region.

[0002]

2. Description of the Related Art Normally, in a gate array, basic cells such as transistors are formed in a two-dimensional array by using a common underlying mask whose design and fabrication are completed in advance, and the basic cells are connected to each other. A master wafer in which the steps up to the step of forming the metal wiring have been completed is manufactured.
Then, this master wafer is provided in a short period of time as a low-cost semi-custom semiconductor device having a function according to each product by forming a customized metal wiring corresponding to each product.

Among such gate arrays, the channelless gate array is one of the most frequently used semi-custom semiconductor devices for a large number of products in small quantities. The structure of this channelless gate array and its problems will be described below.

FIG. 3 is a schematic view of an example of an internal cell region of a conventional channelless gate array. The internal cell region 20 of this channelless gate array is the normal cell 1
2 and reinforced cells 14 in the left-right direction in the figure,
The reinforcing cells 14 are provided between the normal cells 12 arranged in a row.
Are arranged so as to be inserted at predetermined intervals, and the normal cells 12 and the reinforced cells 14 are spread over the entire surface of the internal cell region 20 so as to be arranged in a strip shape in the vertical direction in the drawing.

Further, FIGS. 4 (a) and 4 (b) are layout diagrams of an example of a normal cell and a reinforced cell, respectively. The normal cell 12 shown in FIG. 4A has a p ⁺ diffusion layer 22 a (auxiliary p-transistor 26) smaller than the strengthening cell 14.
(including the p ⁺ diffusion layer 22d to be a) and the n ⁺ diffusion layer 2
2b and these p ⁺ diffusion layers 22a and n ⁺ diffusion layers 2
The upper layer 2b is composed of two gate electrodes 24 arranged in the vertical direction in the figure so as to straddle the p ⁺ diffusion layer 22a and the n ⁺ diffusion layer 22b. Also, this normal cell 1
2 further a smaller n ⁺ diffusion layer 22c, the upper layer of the n ⁺ diffusion layer 22c, the auxiliary n consisting of two gate electrodes 24b which are arranged so as to straddle the n ⁺ diffusion layer 22c in the vertical direction in the drawing It has a transistor 26b.

On the other hand, the reinforced cell 14 shown in FIG.
Compared with the normal cell 12 shown in FIG.
P ⁺ diffusion layer 22a and n ⁺ diffusion layer 22 larger than 2
and that it uses a b, auxiliary p transistor 26a and a point having no auxiliary n transistors 26b, n ⁺ well 36a and the figure n ⁺ diffusion for well contact to the top of the drawing p ⁺ diffusion layer 22a The only difference is that the p ⁺ well 36b for the base contact is provided on the layer 22b, and thus the same components are designated by the same reference numerals and the description thereof is omitted.

A power supply line 28 is provided at the same position on the upper layers of the normal cell 12 and the reinforced cell 14 in the left-right direction in the drawing.
And the ground line 30 is wired. Although not shown, power lines and ground lines are alternately arranged along the reinforcing cells in the vertical direction in the figure. In addition, the grid points in the figure indicate the positions where wiring is possible, contact holes and v
It is a grid which shows the arrangement possible position of a connection hole, such as an ia hole. In this channelless gate array, the reinforcing cells 14 are provided in a smaller ratio than the normal cells 12, for example, the ratio of the reinforcing cells 14 to the normal cells 12 is about 1 to 3. Therefore, the usage efficiency of the reinforced cell 14 is extremely high.

In the conventional channelless gate array thus constructed, in order to manufacture a semi-custom semiconductor device having a function according to each product, first of all, a logic such as an inverter, a NAND gate, a NOR gate is used. It is necessary to automatically place the cells on the base cells and then automatically route between these logic cells. Next, automatic placement of logic cells will be described.

FIGS. 5 (a) and 5 (b) respectively show a normal case.
When placing NAND gates in cells and reinforced cells
It is an example layout diagram. NAND shown in FIG.
In the gate 16a, p⁺The right part of the diffusion layer 22a in the figure
And the left part and the power supply line 28 made of the first metal layer,
First metal distribution through the contact holes 32a
Connected by line 34a, and similarly n⁺Of the diffusion layer 22b
In the left part of the figure and the ground wire 30 made of the first metal layer,
Is the first metal wiring 3 through the contact hole 32a.
It is connected by 4a. Also, p⁺Of the diffusion layer 22a
Central part and n in the figure ⁺The right part of the diffusion layer 22b in the figure is the contour.
Via the first hole 32 and via hole 32b
And are connected by the second metal wirings 34a, 34b
There is. The auxiliary p transistor 26a and the auxiliary n transistor
The transistor 26b is not used.

On the other hand, the NAND gate 1 shown in FIG.
6b is based on the point that the n ⁺ well 36a and the power supply line 28 are connected via the well contact 32c, and the p ⁺ well 36b and the ground line 30 are based on the NAND gate 16a shown in FIG. 5A. The only difference is that they are connected via contacts 32d, and NA
Since the wirings connected to arrange the ND gate 16b are the same, the same components are designated by the same reference numerals and the description thereof will be omitted. These NAND gates 16a, 1
As shown in FIG. 6b, automatically arranging the logic cells means that the basic cells are automatically wired to form the logic cells whose input / output terminals are unwired.

In the NAND gates 16a and 16b thus automatically arranged, the automatic wiring at the input / output terminals is
It is performed by passing a metal wiring on another logic cell that is automatically arranged or a basic cell on which the logic cell is not automatically arranged. However, as is clear from the illustrated example, these NAND gates 16a, 16b
By connecting the input and output ends of the normal cell 12 to the other logic cells, it is possible to pass the wiring in the left-right direction by about four lines such as the upper layer of the auxiliary n-transistor 26b. One cell 14 or even one cell 14 cannot pass the wiring in the left-right direction.

As described above, the reinforcing cells 14 are arranged in a strip shape in the vertical direction in the drawing, and the usage efficiency thereof is extremely high. That is, the reinforcing cells 14 in which the logic cells are automatically arranged are the normal cells 12. Reinforcement cell 14 in which logic cells are automatically arranged so as to act as a wall existing between them.
There is a problem in that the metal wiring cannot pass through the upper layer, and as a result, the metal wiring is laid around and the wiring length increases. Next, this problem will be described with a specific example.

FIG. 6 is a layout diagram of an example of an internal cell region of a conventional channelless gate array. In the internal cell region 20 of this channelless gate array, the normal cells 12 are arranged in the white parts in the figure, the reinforcing cells 14 are arranged in the shaded parts in the same manner, and the normal cells are respectively arranged in the encircled parts in the figure. 12 and the logic cells 16a and 16b of the strengthening cell 14 are automatically arranged. Further, the metal wiring 18 is connected between the logic cells 16 a automatically arranged in the normal cell 12.

As shown in this layout diagram, the strengthening cells 14 are arranged in a strip shape in the vertical direction in the figure, and the logic cells 16b are automatically arranged in the strengthening cells 14, so that the metal is formed on the upper layer of these logic cells 16b. It cannot pass through the wiring 18. Therefore, in order to provide the metal wiring 18 between the logic cells 16a automatically arranged in the normal cells 12 existing on the right side and the left side of the logic cell 16b in the figure, the metal wiring 18 is automatically arranged in the logic cell 16b. So that the metal cell 18 can be passed through the metal wiring 18 by diverting to the portion of the strengthening cell 14 which is not filled, or by forcibly moving the logic cell 16b automatically arranged in the strengthening cell 14 to another position to make it an unused cell. It was necessary to provide a wiring area.

Therefore, according to the conventional channelless gate array, the logic cell 1 which is automatically arranged in the enhancement cell 14 is provided.
Since 6b serves as a wall and interferes with the metal wiring 18 between the logic cells 16a automatically arranged in the normal cells 12 arranged on the left and right of the logic cell 16b, the automatic wiring is very difficult. Therefore, not only the unconnected portion of the metal wiring 18 is generated, but even if the metal wiring 18 can be connected, there is a limitation in automatically arranging the logic cell 16b in the strengthening cell 14, or the metal wiring 18 is not formed. However, there is a problem in that the wiring length becomes long because of a significant amount of wiring and the signal transmission speed decreases, which may cause a malfunction.

[0016]

SUMMARY OF THE INVENTION The object of the present invention is to improve the wiring efficiency between logic cells by improving the arrangement positions of normal cells and reinforced cells in view of the problems based on the above-mentioned prior art. It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing the wiring length.

[0017]

To achieve SUMMARY OF to the above objects, the present invention includes a CMOS-type group <br/> the cell with a normal drive capability, CMOS-type groups having enhanced drivability <br /> Channel with internal cell region composed of this cell
A-less gate array, first and basic cell columns basic cell of the CMOS type is staggered with the basic cells and the enhanced drive capability of the CMOS type having the normal driving capability, the normal C with the driving capability of
And a second basic cell row in which MOS-type basic cells are arranged.
And a CMOS type basic cell having the above-mentioned normal driving capability.
And a CMOS type having the enhanced drive capability
Power line and ground line are in the same position on the upper layer of the basic cell.
It is intended to provide a semiconductor integrated circuit device characterized by being wired .

Here, the first basic cell row and the second basic cell row
And the second basic cells are arranged alternately.
Between the first basic cell rows arranged on both sides of the row
Preferably, the take arrangement CMOS type group <br/> the cells are different with a basic cell and the enhanced drive capability of the CMOS type having the normal driving capability.

Further, it is preferable that the arrangement of the basic cell columns in the row direction is constant.

[0020]

The semiconductor integrated circuit device of the present invention has an internal cell region composed of normal cells and reinforced cells, and includes a basic cell row in which normal cells and reinforced cells are alternately arranged, The internal cell area is configured by the basic cell row in which only cells are arranged. Therefore, according to the semiconductor integrated circuit device of the present invention, the metal wiring between the logic cells automatically arranged in the normal cell is not disturbed by the logic cell automatically arranged in the reinforced cell, and the metal wiring is arranged in the shortest distance. Can be formed. Therefore, the wiring efficiency of the metal wiring can be improved,
The wiring length can be shortened.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor integrated circuit device of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a schematic view of an embodiment of the internal cell region of the semiconductor integrated circuit device of the present invention. The internal cell region 10 of this semiconductor integrated circuit device is composed of normal cells 12 and reinforced cells 14, and the reinforced cells 14 are arranged at predetermined intervals between the normal cells 12 arranged in a row in the horizontal direction in the drawing. The internal cell regions 10 are arranged so as to be inserted, and the normal cells 12 and the reinforcing cells 14 are half translated in the vertical direction in the drawing so as to be arranged alternately.
Is spread over the entire surface.

The normal cell 12 and the reinforced cell 14 are also provided.
Needless to say, may have any layout structure, but for example, those shown in FIGS. 4A and 4B exemplified in the prior art can be used.

As described above, the internal cell region 10 of the semiconductor integrated circuit device of the present invention is different from the internal cell region 20 of the conventional channelless gate array shown in FIG. It does not interfere with the metal wiring between the cells 12. Therefore, the wiring efficiency can be greatly improved, and as a result, unconnected wiring can be reduced and the wiring length can be further shortened, so that malfunction of the circuit can be prevented. Further, since the semiconductor integrated circuit device of the present invention basically only changes the arrangement structure of the basic cells, there is no need to reconstruct an existing cell library or the like.

Next, in the semiconductor integrated circuit device of the present invention having the internal cell region shown in FIG. 1, automatic placement and automatic operation are performed as in the case of the conventional channelless gate array having the internal cell region shown in FIG. A specific example of wiring will be described.

FIG. 2 is a layout diagram of an embodiment of the internal cell region of the semiconductor integrated circuit device of the present invention. In the internal cell region 10 of this semiconductor integrated circuit device, a normal cell 12 is arranged in a white portion in the drawing, a strengthening cell 14 is arranged in a shaded portion in the same manner, and a normal cell 12 is respectively arranged in a boxed portion in the drawing. And a logic cell 16 on the enhancement cell 14.
a and 16b are automatically arranged. Also, metal wiring 1
8 is connected between the logic cells 16a automatically arranged in the normal cell 12.

As shown in this layout diagram, the reinforcing cells 14 are arranged alternately in the vertical direction in the figure,
That is, unlike the conventional layout diagram shown in FIG. 6, the metal wiring 18 between the logic cells 16a automatically arranged in the normal cell 12 is connected without passing through the upper layer of the logic cell 16b arranged in the strengthening cell 14. be able to. Therefore, between the logic cells 16a automatically arranged in the normal cells 12, the normal cells 1 in which the logic cells 16a are not automatically arranged are
2 or the reinforcing cell 14 in which the logic cell 16b is not automatically arranged, and even the upper layer of the normal cell 12 in which the logic cell 16a is automatically arranged can pass through the metal wiring 18, so that the metal wiring 18 The wiring length can be shortened.

Therefore, according to the semiconductor integrated circuit device of the present invention, the logic cell 16b automatically arranged in the strengthening cell 14 serves as a wall, and the logic cell 1 automatically arranged in the normal cell 12 is formed.
Since it does not hinder the metal wiring 18 between 6a,
Automatic wiring is very easy. Therefore, the metal wiring 1
Not only is it possible to reduce the unconnected portion of No. 8 but also there is no particular limitation when automatically arranging the logic cell 16b in the strengthening cell 14, so that the use efficiency of the basic cell is improved and the wiring length is shortened. Therefore, there is an effect that the wiring efficiency is improved.

Although the semiconductor integrated circuit device of the present invention is basically constructed as described above, it is not limited to the illustrated examples described above. That is, the arrangement configuration of the basic cells applied to the semiconductor integrated circuit device of the present invention is
Any arrangement structure may be used as long as the reinforcing cells 14 do not interfere with the metal wiring between the normal cells 12.

For example, the normal cells 12 arranged in one horizontal row
The spacing for inserting the reinforcing cells 14 between the columns and the parallel movement amount between the rows for alternately arranging the normal cells 12 and the reinforcing cells 14 are not particularly limited. Further, in the embodiment, the normal cell 12 and the reinforcing cell 14 are arranged 1
Although the normal cells 12 and the reinforcing cells 14 are arranged so as to be staggered in each row, they may be arranged, for example, in every two rows or every three rows, and their intervals and movement amounts may be regular. It goes without saying that it may be determined as appropriate, such as not having to be regular.

[0031]

As described in detail above, the semiconductor integrated circuit device of the present invention includes a basic cell row in which normal cells and reinforcing cells are alternately arranged and a basic cell row in which only normal cells are arranged. The internal cell area is configured. Therefore, according to the semiconductor integrated circuit device of the present invention, the metal wiring between the logic cells automatically arranged in the normal cell is obstructed by the logic cell automatically arranged in the strengthening cell, and as a result, the metal wiring is laid out. Therefore, the wiring efficiency can be improved and the wiring length can be shortened.

[Brief description of drawings]

FIG. 1 is a schematic view of an example of an internal cell region of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a layout diagram of an example of an internal cell region of a semiconductor integrated circuit device of the present invention.

FIG. 3 is a schematic view of an example of an internal cell region of a conventional channelless gate array.

4A and 4B are layout diagrams of an example of a normal cell and a reinforced cell, respectively.

5A and 5B are layout diagrams of an example in which NAND gates are arranged in a normal cell and a reinforced cell, respectively.

FIG. 6 is a layout diagram of an example of an internal cell region of a conventional channelless gate array.

[Explanation of symbols]

10, 20 Internal cell region 12 Normal cell 14 Reinforcement cell 16a, 16b Logic cell 18 Metal wiring 22a, 22d p ⁺ Diffusion layers 22b, 22c n ⁺ Diffusion layer 24, 24b Gate electrode 26a Auxiliary p-transistor 26b Auxiliary n-transistor 28 Power line 30 ground line 32a contact hole 32b via hole 32c well contact 32d base contact 34a first metal wiring 34b second metal wiring 36a n ⁺ well 36b p ⁺ well

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Claims (3)

(57) [Claims] 1. A Chanerure comprising a basic cell of a CMOS type having a normal drive capacity, the internal cell region composed of a basic cell of a CMOS-type with enhanced drivability
A scan gate array, first and basic cell columns basic cell of the CMOS type is staggered with the basic cells and the enhanced drive capability of the CMOS type having the normal driving capability, the normal And a second basic cell column in which CMOS type basic cells having the driving capability are arranged , and a CMOS type basic cell having the normal driving capability and
And a CMOS type basic cell having the enhanced drive capability.
Power and ground wires in the same position on the upper layer of the
The semiconductor integrated circuit device characterized by being. 2. The first basic cell array and the second basic cell array.
Rows are alternately arranged and both sides of the second basic cell row are arranged.
Wherein disposed in the first between the adjacent basic cell columns, the basic cell of the CMOS type having a basic cell and the enhanced drive capability of the CMOS type having the normal drivability
The semiconductor integrated circuit device according to claim 1, which has a different arrangement. 3. The semiconductor integrated circuit device according to claim 2, wherein the array of the basic cell columns in the row direction is constant.