JP3547208B2 - Multiprocessor system and configuration method thereof - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a multiprocessor system in which a plurality of processors execute parallel processing using information stored in a distributed shared memory via a common bus, and a configuration method thereof.
[0002]
[Prior art]
In recent years, market demand has increased for parallel processing such as high-performance database retrieval in information processing and image processing in the field of science and technology. To cope with this demand, a multiprocessor system in which a plurality of processors are connected is provided. In particular, there is provided a multiprocessor system in which a processor and a memory are made independent as processor modules, and a plurality of these processor modules are connected via a common bus to perform parallel processing.
[0003]
In the multiprocessor system, memories are distributed and arranged in groups of one or more processors, and each processor accesses the distributed memory. The multiprocessor system performs parallel processing by a plurality of processors by reducing the load on the common bus. In addition, some multiprocessor systems have a distributed shared memory that can be directly accessed by each processor.
[0004]
In a multiprocessor system having such a distributed shared memory, one of the processor modules may be abnormal. In this case, it is necessary to degenerate the abnormal processor module and construct a multiprocessor system using the remaining normal processor modules.
[0005]
Further, in a multiprocessor system having the distributed memory or the distributed shared memory, since a plurality of processors operate independently, cooperative operation of the plurality of processors is important. In order for a plurality of processors to perform a cooperative operation, the versions (versions) of the initial operation programs that operate on each processor must match.
[0006]
[Problems to be solved by the invention]
However, different versions of processor modules may be mixed due to a work mistake. When the initial operation is performed at this time, the respective settings are different. Therefore, the cooperative operation cannot be maintained after the multiprocessor system is constructed, and the system cannot operate normally.
[0007]
In addition, the versions of the basic system are the same, and the version of the boot program memory including a non-rewritable non-volatile memory such as a program read only memory (PROM) for executing initial diagnosis, initial setting and boot of the system. Must also match.
[0008]
However, as described above, there may be cases where different versions of the initial operation program exist. In this case, since the initial operation program is stored in a non-rewritable program read only memory (PROM), it is necessary to exchange PROMs having different versions to make the same version number of the initial operation program. For this reason, replacement work was difficult. Therefore, it has been desired to rewrite different versions of the initial operation programs with the same version of the initial operation programs, to make all versions the same, and to start the system with all processor modules.
[0009]
The present inventionEyesSpecifically, the present invention provides a multiprocessor system in which a system can be configured with processor modules having the same version of the initial operation program even if different versions are mixed, and a configuration method thereof..
[0010]
[Means for Solving the Problems]
The multiprocessor system of the present invention employs the following means in order to solve the above problems.
[0011]
<Summary of Multiprocessor System of the Present Invention>
The multiprocessor system of the present invention is a multiprocessor system in which a plurality of processors 12 execute parallel processing through a common bus 6 as shown in FIG.
An initial operation unit 14, a distributed shared storage unit 8, and a determination unit 19 are provided (corresponding to claim 1). The point is that only the processor of the same version is activated.
[0012]
Hereinafter, the configuration will be described.
(Initial operation section)
The initial operation section 14 is provided in each processor 12 and diagnoses whether the initial operation of its own processor is normal or abnormal by an initial operation program. The initial operation program is stored in a rewritable nonvolatile memory such as a flash memory. .
(Distributed shared storage unit)
The distributed shared storage unit 8 stores initial operation state information indicating a diagnosis result of an initial operation diagnosed by an initial operation program for each processor, and version number information indicating a version number of the initial operation program. It is a distributed shared memory.
(Decision unit)
The deciding unit 19 degenerates an abnormal processor based on the initial operation state information stored in the distributed shared memory 8 and degenerates a processor having an initial operation program of a different version number based on the version number information, and It is determined that a system having a number of initial operation programs constitutes a system.
[0013]
The present invention can be realized by adding the following additional components. The other additional components are a system control mechanism unit 18 in which the determination unit 19 controls the entire system and determines a system configuration of the plurality of processors.You.
[0014]
The other additional component means that each of the plurality of processors mutually executes the system configuration determination processing.You.Further, the other additional components include a configuration mode information unit 20 for storing configuration mode information representing logic for determining the system configuration, and the determination unit 19 stores the configuration mode information stored in the configuration mode information unit 20. Determine system configuration based on configuration mode informationYou.
[0015]
Furthermore, a configuration mode setting unit 21 that performs at least one of a process of setting configuration mode information in the configuration mode information unit 20 and a process of changing the set configuration mode information to another configuration mode information is provided.You.
[0016]
Further, a system version information unit 23 for storing system version information indicating the version of the initial operation program selected by the determination unit 19 in the system configuration determination process, and an initial operation program not selected in the system configuration determination process. A storage device 25 for previously storing storage program data version information indicating a data version number, a system version comparison unit 22 for comparing the system version information with the storage program data version information, If the information does not match the stored program data version information, the system version information is rewritten to the stored program data version information, thereby rewriting all processors to the same version of the initial operation program. And a processing unit 27.
[0017]
Further, a rewrite state information section 28 is provided for storing rewrite state information indicating an operation state of the rewrite processing when the rewrite processing section executes rewriting of the initial operation program for each processor. The determination unit 19 configures a system with the abnormal processor by referring to the rewrite state information stored in the rewrite state information unit 28 when the initial operation program recognizes the abnormal processor, and performs a system operation. Start. The rewrite processing unit 27 recovers the abnormal initial operation program generated during the rewrite by retrying the rewrite process.You.
[0018]
The rewriting state information unit 28 sets retry number information that defines the number of times that retry of rewriting processing is performed.You.The rewrite state information unit 28 sets the number of retries with reference to maximum update number information indicating the maximum number of updates for updating each initial operation program.You.
[0019]
FIG. 2 is a flow chart showing the principle of a method for configuring a multiprocessor system according to the present invention. As shown in FIG. 2, the present invention relates to a system configuration method for configuring a multiprocessor system in which a plurality of processors execute parallel processing through a common bus, and determines whether the initial operation of its own processor is normal or abnormal. The initial operation step 101 for diagnosing the initial operation state, and the initial operation state information indicating the diagnosis result of the initial operation diagnosed by the initial operation program for each processor and the version information indicating the version number of the initial operation program are stored in the distributed shared memory. The storage step 102 stores the same processor by degenerating a processor having an abnormality based on the initial operation state information stored in the distributed shared memory and degenerating a processor having an initial operation program of a different version number based on the version number information. A system with a processor having an initial operation program of And a decision step 103 of determining suchYou.
[0020]
The determining step is performed by each of the plurality of processors.You.In the deciding step, the abnormal processor degeneration based on the initial operation state information is executed by a system control mechanism unit which controls the entire system, and the degeneration of processors having different versions is executed by a normal processor.You.
[0021]
The apparatus further comprises a configuration mode information step 104 for storing configuration mode information representing logic for determining the system configuration. The determination step 103 determines a system configuration based on the stored configuration mode information.You.
[0022]
The apparatus further includes a configuration mode setting step 105 for performing at least one of a process of setting the configuration mode information and a process of changing the set configuration mode information to another configuration mode information.You.
[0023]
Further, a system version number step 111 for storing system version number information indicating the version number of the initial operation program selected in the system configuration determination process, and a version number of the initial operation program data not selected in the system configuration determination process. A storage program data version information to be stored in advance 112; a system version number comparison step 113 for comparing the system version information with the storage program data version information; If the version information does not match, the system version information is rewritten to the stored program data version information, thereby rewriting all processors to the same version of the initial operation program.You.
[0024]
Further, there is provided a rewrite state information step 115 for storing, for each processor, rewrite state information indicating an operation state of a rewrite process at the time of executing the rewrite of the initial operation program. When a recognizable processor is recognized, a system is configured by the abnormal processor by referring to the rewrite state information stored in the rewrite state information unit, and a system operation is started. Restore the abnormal initial operation program that occurred during rewriting by trying again.You.
[0025]
The rewriting state information step 115 sets retry number information that defines the number of times that retrying of rewriting processing is performed.You.The rewriting state information step 115 sets the number of retries with reference to maximum update number information indicating the maximum number of updates for updating each initial operation program.You.
[0026]
[Action]
According to the present invention, when each initial operation unit 14 diagnoses whether the initial operation of its own processor is normal or abnormal by the initial operation program, the initial operation unit 14 displays an initial operation diagnosis result diagnosed by the initial operation program for each processor. The operation state information and version number information indicating the version number of the initial operation program are stored in the distributed shared storage unit 8.
[0027]
Then, the deciding unit 19 degenerates the abnormal processor based on the initial operation state information stored in the distributed shared storage unit 8. Further, the determining unit 19 determines, based on the version number information, that processors having different versions of the initial operation programs are degenerated and the system is configured by processors having the same version of the initial operation programs.
[0028]
That is, since the system is configured only with the initial operation programs having the same version number, the system can be started up in which the cooperative operation of the processors is guaranteed.
Further, the system control mechanism section 18 that controls the entire system can determine the system configuration of a plurality of processors. Further, each of the plurality of processors can mutually execute the system configuration determination processing.
[0029]
Further, the configuration mode information unit 20 stores configuration mode information representing logic for determining the system configuration, and the determination unit 19 determines the system configuration based on the configuration mode information stored in the configuration mode information unit 20. The system configuration can be determined by the determined logic.
[0030]
Further, the configuration mode setting unit 21 performs at least one of a process of setting configuration mode information in the configuration mode information unit 20 and a process of changing the set configuration mode information to another configuration mode information. The system configuration can be selected according to the situation of maintenance, testing, etc.
[0031]
Further, the system version comparison unit 22 does not select the system version information indicating the version of the initial operation program selected in the system configuration determination process (for example, the version is older) and the system configuration determination process ( For example, comparison is made with stored program data version information indicating the version of the initial operation program data (newer version).
[0032]
If the system version information does not match the stored program data version information, the rewriting processing unit 27 rewrites the system version information (older version) to stored program data version information (new version). Thus, all processors are unified to the same version of the initial operation program.
[0033]
Therefore, even if a plurality of versions exist, all versions can be made the same.
Further, when the initial operation program recognizes the abnormal processor, the determining unit 19 refers to the rewrite state information stored in the rewrite state information unit 28 to configure the system with the abnormal processor and starts the system operation. The rewriting processing unit 27 restores the abnormal initial operation program generated during the rewriting by retrying the rewriting process.
[0034]
Therefore, even if the processing is interrupted for some reason during the rewriting processing, the abnormal initial operation program can be restored.
By setting the retry count information in the rewrite state information unit 28, it is possible to prevent the rewrite process from being attempted more than necessary. Can be improved.
[0035]
The rewriting state information unit 28 can perform the recovery process in consideration of the limitation on the number of updates of the initial operation program by setting the number of retries with reference to the maximum number of updates information.
[0036]
【Example】
Hereinafter, embodiments of a multiprocessor system and a configuration method of the present invention will be described with reference to the drawings.
<Example 1>
FIG. 3 is a configuration block diagram showing Embodiment 1 of the multiprocessor system of the present invention. The multiprocessor system includes a plurality of processor modules (PM) 12-1 to 12-3 connected to a common bus 6, a system memory 8 connected to the common bus 6, and a system control mechanism unit connected to the system memory 8. 18, a system configuration determining unit 19 connected to the system memory 8. In the multiprocessor system, a plurality of processor modules 12-1 to 12-3 execute parallel processing through the common bus 6.
[0037]
The processor module 12-i (i = 1 to 3) includes a central processing unit (CPU) 13-i, an FRAM initial operation unit 14-i for storing an initial operation program, and a random access memory (RAM) 15-i.
[0038]
The RAM 15-i is set and diagnosed by each CPU, set as a distributed shared memory of the system when operating as a multiprocessor, and used as a system memory.
[0039]
The FRAM initial operation section 14-i has an initial operation program in an FRAM (flash memory) and diagnoses whether the initial operation of its own processor module 12-i is normal or abnormal by the initial operation program. The FRAM is a rewritable nonvolatile memory.
[0040]
The system memory 8 stores initial operation state information 16-i indicating a diagnosis result of each processor module 12-i diagnosed by the initial operation program in the FRAM initial operation section 14-i corresponding to the processor module 12-i. And FRAM version information 17-i (i = 1 to 3) indicating the version of the initial operation program in the FRAM initial operation section 14-i corresponding to the processor module 12-i.
[0041]
The system control mechanism section 18 is connected to the common bus 6 and controls the whole of a plurality of (multi) processor modules 12-1 to 12-3 separately from the CPU 13-i of the processor module 12-i. A CPU 180 is provided. Further, the system control mechanism section 18 controls the power supply of the system, controls reset processing, monitors a system state, and the like.
[0042]
The system configuration determining unit 19 is connected to the system memory 8 and the system control mechanism unit 18, has a system configuration determining program in an internal memory (not shown), and has an abnormality based on the initial operation state information stored in the system memory 8. Degenerate the processor. Degeneration refers to excluding an abnormal processor from the multiprocessor system configuration. The system configuration determining unit 19 determines, based on the version number information, to degenerate processors having different versions of the initial operation programs and configure the system with processor modules having the same version of the initial operation programs.
[0043]
Next, the operation of the first embodiment thus configured will be described with reference to the flowchart of FIG. First, when the reset of the multiprocessor system is executed by the system control mechanism unit 18 (step S1), each of the processor modules 12-1 to 12-3 recognizes the reset (step S2). Then, the FRAM initial operation unit 14-i executes an initial operation such as an initial setting and a diagnosis by an initial operation program (step S3a).
[0044]
The FRAM initial operation unit 14-i diagnoses and sets its own processor module according to its own initial operation program, and determines whether the result is normal or abnormal (step S3b).
[0045]
If the result is normal, the FRAM initial operation unit 14-i creates a normal status (step S4a), and sets the normal status in the system memory 8 as initial operation state information 16-i (step S5).
[0046]
On the other hand, if the result is abnormal, the FRAM initial operation unit 14-i creates an abnormal status (step S4b), and sets the abnormal status in the system memory 8 (step S5).
[0047]
Next, the FRAM initial operation unit 14-i sets the version number of its own initial operation program in the system memory 8 as FRAM version number information 17-i (step S6).
Further, after all the processor modules 12-1 to 12-3 store the information in the system memory 8, the system configuration determining unit 19 determines a processor module that configures the multiprocessor system based on the information stored in the system memory 8. Select (Step S7).
[0048]
The system configuration determination processing will be described in detail with reference to FIG. Here, the system control mechanism unit 18 monitors the status information of each processor module in steps 71 to 76 and performs the degeneration process of the abnormal module, and selects any one of the normal modules. The selected processor performs the processing of steps 77 to 80, and executes processing different from that of other modules in order to take over the processing performed by the system control mechanism unit 18.
[0049]
First, the system control mechanism 18 monitors the initial operation state information of the processor modules 12-1 to 12-3 (step 71). Then, it is determined whether the initial operation state information is set in the system memory 8 within a predetermined time (step S72).
[0050]
The system control unit 18 determines that an abnormality has occurred in the processor module for which the information has not been set, and executes the degeneration (isolation from the system) of the processor module (step S73).
[0051]
Next, the system control mechanism unit 18 checks the initial operation state information 16-1 to 16-3 of the processor modules 12-1 to 12-3 stored in the system memory 8 (step S74). The system control mechanism unit 18 determines whether an abnormal status has been set based on the initial operation state information (step S75). The system control unit 18 degenerates the processor module for which the abnormal status has been set (step S76). Then, any one of the normal processor modules is selected.
[0052]
Next, the selected processor checks the version number of the initial operation program of each processor module based on the FRAM version number information 17-1 to 17-3 of the system memory 8 (step S77), and the initial operation of all the processor modules. It is determined whether the version numbers of the programs are the same (step S78).
[0053]
If there is an initial operation program with a different version number, the selected processor executes processor module degeneration for the processor module with a different version number (step S79).
[0054]
It should be noted that which version of the processor module is to be left can be appropriately changed depending on the multiprocessor system. For example, the case where the latest version number is left or the case where a large version number is left are considered.
[0055]
Next, the selected processor forms a multiprocessor system with the remaining processor modules (step S80). For example, a distributed shared memory system can be constructed.
[0056]
The unselected processor modules operate in the same manner as the processing performed by the system control unit 18.
Further, when the version numbers are the same, all modules construct a system without any problem. However, if the selected module itself has a different version number (even during rewrite control), it is necessary to construct a system with other modules.
[0057]
In this case, the processor of the selected module selects a new module to operate as first selected by the system control mechanism unit 18 in order to take over control to the module to operate according to the version number comparison.
[0058]
The newly selected module executes the processing of step S77 and thereafter, but the processing of step S80 is executed as it is because the module is not degraded by comparing the version numbers.
[0059]
In this case, the reduction operation of another module (a module to be reduced by checking the version number) can be reduced by the following two methods.
In the first method, the processor of the module initially selected by the system control unit 18 degenerates another module, and after itself takes over control to the newly selected module, itself degenerates itself. In this case, the newly selected module operates normally (without degeneration) even if the check after S77 is performed, and there is no module with a different version number.
[0060]
In the second method, the processor of the module selected by the system control unit 18 first takes over the control to the newly selected module, and then returns to the same state as the other modules. When the newly selected module performs the processing from S77, the module for checking the version number is reduced.
[0061]
With the above processing, the processing of the system configuration determining unit 19 ends. Returning to the description of FIG. 4, each processor module loads software (step S8),
The system is started (Step S9).
[0062]
Thereafter, the processing is continued as a multiprocessor system including normal processor modules having the same version number. Further, the system control mechanism 18 monitors the system including the processor modules constituting the multiprocessor system (step S10).
[0063]
As described above, even if the initial operation programs of different versions are mixed, only the processor modules having the same version of the initial program are selected, so that the multi-processor system can maintain the cooperative operation by the processor modules of the same version. Can be started normally.
(A) Operation of the system configuration determining unit by the CPU in the system control mechanism unit
Next, a specific example in which the CPU in the system control mechanism unit 18 operates the system configuration determining unit to determine the configuration of the multiprocessor system will be described with reference to FIGS.
(A) First, FIG. 6 illustrates a case where the initial operation of the processor module 12-3 among the processor modules 12-1 to 12-3 is abnormal. It is assumed that the version numbers of the initial operation programs of each processor module are all the same and are the A version.
[0064]
First, in the processor modules 12-1 and 12-2, the initial operation units 14-1 and 14-2 set a normal status as initial operation state information in the system memory 8 by an initial operation program, and set A as an FRAM version number information. A version is set (step S11a).
[0065]
Next, in the processor module 12-3, the initial operation unit 14-3 sets the abnormal status as the initial operation state information in the system memory 8 by the initial operation program, and sets the A version as the FRAM version number information (step S12a). ).
[0066]
The system control unit 18 waits for all the processor modules to complete the initial operation and to set each information in the system memory 8 (step S13). The system control mechanism unit 18 determines whether the initial operation state information is normal (step S14).
[0067]
If the initial operation state information is abnormal, the system control mechanism unit 18 degenerates the abnormal processor (step S15), and proceeds to the processing of step S16. On the other hand, if the initial operation state information is normal, the process immediately proceeds to step S16.
[0068]
In this example, since the processor module 12-3 is abnormal, the processor module 12-3 is degenerated in step S15.
Next, the system control mechanism unit 18 determines whether or not the FRAM version information is the same (step S16). Is degenerated (step S17).
[0069]
The configuration of the multiprocessor system is determined by the remaining processor modules (step S18). In this example, since both the processor modules 12-1 and 12-2 have the A version of the initial operation program, the processor modules 12-1 and 12-2 are not degenerated and form a multiprocessor system.
[0070]
On the other hand, when the version numbers of all the processor modules are the same, the configuration of the multiprocessor system is determined by those processor modules.
After the processing of the system control unit 18 is completed, the normal processor modules 12-1 and 12-2 start operations such as setting and diagnosis for operating as a multiprocessor system (step S19).
[0071]
As described above, the system control mechanism section 18 can degenerate the abnormal processor module and determine the configuration of the multiprocessor only with the normal processor module.
(B) Next, referring to FIG. 7, among the processor modules 12-1 to 12-3, the version number of the FRAM initial operation program of the processor modules 12-1 and 12-2 is C, and The processing of the system control mechanism unit 18 when the version number of 12-3 is the B version will be described. It is assumed that the version number of the initial operation program is a new version number in alphabetical order, and the C version is a newer version number than the B version.
[0072]
First, in the processor modules 12-1 and 12-2, the initial operation sections 14-1 and 14-2 set a normal status as initial operation state information in the system memory 8 according to an initial operation program, and set C information as FRAM version number information. A version is set (step S11b).
[0073]
Next, in the processor module 12-3, the initial operation unit 14-3 sets the normal status as the initial operation state information in the system memory 8 according to the initial operation program, and sets the B version as the FRAM version number information (step S12b). ).
[0074]
The system control unit 18 waits for all the processor modules to complete the initial operation and to set each information in the system memory 8 (step S13). The system control mechanism unit 18 determines whether the initial operation state information is normal (step S14). In this example, since all the initial operation state information is normal, the degeneration of the processor module in step S15 is not performed.
[0075]
Next, the system control mechanism unit 18 determines whether the FRAM version number information is the same (step S16). In this example, since the processor module includes processor modules having different versions, the new version is selected when the version is selected.
[0076]
Since the version number of the processor module 12-3 is older than the version numbers of the processor modules 12-1 and 12-2, the processor module 12-3 is degenerated (step S17).
[0077]
A multiprocessor system is configured by the processor modules 12-1 and 12-2 (step S18).
As described above, even when the initial operation programs having different versions are mixed, the system control mechanism section 18 can also determine the configuration of the multiprocessor with the processor modules having the same version of the initial operation programs.
(B) Operation of the system configuration determining unit by the CPU in the processor module
Next, a specific example in which the CPU in the processor module operates the system configuration determining unit 19 to determine the configuration of the multiprocessor system will be described with reference to FIGS. In this case, the system control mechanism section 18 does not participate in determining the system configuration.
(A) First, in FIG. 8, a case where the initial operation of the processor module 12-3 is abnormal as in FIG. 6 will be described. The version numbers of the initial operation programs of each processor module are all A versions.
[0078]
First, the initial operation units 14-1 and 14-2 of the processor modules 12-1 and 12-2 set the normal status in the system memory 8 as the initial operation state information, and set the A version as the FRAM version number information ( Step S11a). The initial operation unit 14-3 of the processor module 12-3 sets the abnormal status in the system memory 8 as the initial operation state information, and sets the A version as the FRAM version number information (step S12a).
[0079]
Next, each processor module monitors the information setting operation of the other processor modules, and waits for the completion of the information setting of all the processor modules (step S20).
[0080]
Each processor module confirms that all the processor modules have been set, and starts checking the information of its own processor module. First, each processor module checks the initial operation state information of its own processor module, and if an abnormal status is set in the system memory 8, degrades the processor (step S21). In this example, the processor module 12-3 is degenerated.
[0081]
Next, each processor module checks the FRAM version number information, and the processor module having the abnormal version number is degenerated (step S22). In this case, each processor module compares the FRAM version number information of its own processor module with the version number information of another processor module, and if the version numbers are different, the processor module is degenerated.
[0082]
In this example, the A-version processor modules 12-1 and 12-2 constitute a multiprocessor system (step S23), and start operation of the multiprocessor system (step S19).
In this way, the CPU of each processor module operates the system configuration determining unit 19 to degenerate the processor module and determine the configuration of the multiprocessor only with the normal processor module.
(B) Next, referring to FIG. 9, when the version number of the FRAM initial operation program of the processor modules 12-1 and 12-2 is the C version and the version number of the processor module 12-3 is the B version The processing of each processor module will be described.
[0083]
First, the processor modules 12-1 and 12-2 set the normal status as the initial operation state information, and set the C version as the FRAM version number information (step S11b). The processor module 12-3 sets the normal status as the initial operation state information, and sets the B version as the FRAM version number information (step S12b).
[0084]
Next, each processor module performs the processing of the step 20 and further checks its own status to degenerate the processor module having the abnormal status (step S21). In this example, since there is no abnormal status, no processor module is degenerated.
[0085]
Next, each processor module checks the FRAM version number information. Since the version number of the processor module 12-3 is different from the version numbers of the processor modules 12-1 and 12-2, the processor module 12-3 degenerates itself (step S22).
[0086]
In this example, when the old version number and the new version number are mixed, the new version number is selected. Therefore, the remaining processor modules 12-1 and 12-2 constitute a multiprocessor system having a C-version initial operation program.
[0087]
Thus, even if the initial operation programs of different versions coexist, the configuration of the multiprocessor can be determined by the processor modules having the same version of the initial operation programs.
<Example 2>
Next, a second embodiment of the multiprocessor system of the present invention will be described. FIG. 10 is a configuration diagram of the multiprocessor system according to the second embodiment. In the second embodiment, the configuration of the first embodiment further includes a configuration mode information memory 20 connected to the system configuration determination unit 19 and a configuration mode setting processing unit 21 connected to the configuration mode information memory 20.
[0088]
The configuration mode setting processor 21 sets configuration mode information in the configuration mode information memory 20, and can set configuration mode information by recognizing switches of the apparatus, inputting by commands, and the like.
[0089]
The configuration mode information memory 20 stores configuration mode information for selecting logic for determining a system configuration.
Next, the operation of the configuration mode setting processing unit according to the second embodiment will be described. FIG. 11 is a flowchart illustrating the operation of the configuration mode setting processing unit according to the second embodiment. This process is performed before performing the system configuration determination process.
[0090]
First, the configuration mode setting processing unit 21 sets configuration mode information in the configuration mode information memory 20 (step S24a). Next, the system configuration determining unit 19 refers to the configuration mode information stored in the configuration mode information memory 20 and selects a logic for determining the system configuration (Step S24b).
[0091]
In this example, for example, the system configuration determination unit 19 selects any one of the first to third three system configuration determination logics. For example, when selecting the first system logic, the system configuration determining unit 19 configures a multiprocessor system with a new processor module of the FRAM version (step S25).
[0092]
Further, when selecting the second system logic, the system configuration determining unit 19 configures a multiprocessor system with processor modules having an old FRAM version (step S26). In this case, the FRAM operates so as to be used at the time of the level up operation.
[0093]
Further, when the third system logic is selected, the system configuration determining unit 19 specifies the FRAM version number and configures the multiprocessor system with the specified processor module (step S27). In this case, it can be used for a test system, fault investigation, development, emergency operation, and the like.
[0094]
After the above processing, the system configuration determination unit 19 performs the system configuration determination processing by checking the FRAM version number information, degenerating, and the like (step S7). The processing after S7 is the same as the processing of the first embodiment.
[0095]
As described above, since the configuration mode information can be easily set and changed by the configuration mode setting processing unit 21, the system configuration can be controlled according to the system status such as the operation state, the maintenance, and the test.
[0096]
Alternatively, only the configuration mode information memory 20 may be provided without providing the configuration mode setting processing unit 21. In this case, only limited configuration mode information may be selected by storing predetermined configuration mode information in the configuration mode information memory 20.
<Example 3>
Next, a third embodiment of the present invention will be described. In the third embodiment, a configuration as shown in FIG. 12 is further added to the configuration of the second embodiment. 12, the multiprocessor system includes a system version information section 23, a stored program data version information section 24, a system version comparison section 22, an external storage device 25 for storing FRAM initial operation program data 26, and a rewrite processing section 27. Prepare.
[0097]
The system version information section 23 stores system version information indicating the version of the initial operation program selected by the system configuration determining section 19 in the system configuration determining process.
[0098]
The stored program data version information section 24 stores stored program data version information indicating the version of the FRAM initial operation program data 26 in the external storage device 25. The stored program data version number information indicates the version number of the initial operation program data not selected in the system configuration determination processing.
[0099]
The system version comparison unit 22 compares the system version information with the stored program data version information. The system version information section 23 is provided, for example, in the system memory 8 or the like.
[0100]
The rewrite processor 27 rewrites the FRAM initial operation program as needed based on the comparison result of the system version number comparator 22. Here, when the system version information does not match the stored program data version information, the rewriting processing unit 27 rewrites the system version information to the stored program data version information, thereby rewriting all the processors. To the same version of the initial operation program.
[0101]
Next, a first process according to the third embodiment will be described with reference to FIG. In this example, the processor modules 12-1 and 12-2 have the B version of the initial operation program, and the processor module 12-3 has the A version of the initial operation program. The FRAM initial operation program data stored in the external storage device 25 is the B version.
[0102]
First, when the system control mechanism unit 18 executes a reset (step S1), each processor module recognizes the reset (step S2) and executes an initial operation (step S3a).
[0103]
Each processor module diagnoses and sets its own processor module, outputs the result (step S3c), and creates a normal or abnormal status (step S4). The status is set as initial operation state information 16-i in the system memory 8 (step S5).
[0104]
Next, each processor module sets the version number of its own initial operation program in the system memory 8 as FRAM version number information 17-i (step S6).
In this example, the normal status is set in the system memory 8 corresponding to the processor modules 12-1 and 12-2, and the FRAM version number (B version) is set (step S11). The normal status is set in the corresponding system memory 8 of the processor module 12-3, and the FRAM version number (A version) is set (step S12).
[0105]
Next, the system configuration determining unit 19 configures the system with logic for selecting a processor module having an older version number when determining the system configuration with reference to the configuration mode information stored in the configuration mode information memory 20 (step S7). In this example, the old A-version processor module 12-3 is left, and the new B-version processor modules 12-1 and 12-2 are degenerated.
[0106]
Then, the processor module 12-3 starts the multiprocessor system operation (Step S19).
Next, a second process according to the third embodiment will be described with reference to FIG. The processor module 12-3 stores the version (version A) of its own initial operation program in the system version information section 23 (step S28).
[0107]
Next, the processor module 12-3 reads the initial operation program data 26 stored in the external storage device 25, checks version information in the initial operation program data 26, and stores the version information in the storage program data version. The number information section 24 stores (step S29).
[0108]
Next, the system version comparison unit 22 compares the system version information with the stored program data version information and determines whether the versions are the same (step S30). If the version numbers are the same, the system is started (step S9).
[0109]
If the version numbers are different, the rewrite processing unit 27 executes a rewrite process (step S31). In this example, since the processor module 12-3 is the A version and the version number of the stored initial operation program data 24 is the B version, the initial operation program of the processor module 12-3 is changed from the A version to the B version. Rewritten.
[0110]
Further, after the rewriting is completed, the processor module 12-3 requests the system control mechanism unit 18 to reset the system (step S32).
The system control mechanism 18 executes a reset in response to a reset request (step S1). In this example, after the reset, the system is composed of three processor modules 12-1 to 12-3 having the B version of the initial operation program, and the operation is started by these three processor modules (step S19).
[0111]
Further, the B version information is stored in the system version information section 23 (step S33). Then, the system version comparison unit 22 compares the system version information with the version of the initial operation program data (step S34). In this case, since the version numbers are the same, the system normally starts without executing the rewriting process.
[0112]
Using the rewritable FRAM as described above, the system version number comparing unit 22 outputs the system version number information indicating the version number of the initial operation program (for example, the older version number) selected in the system configuration determination processing, The stored program data version number information indicating the version number of the initial operation program data not selected (for example, the version number is newer) in the configuration determination process is compared. If the system version information does not match the stored program data version information, the rewriting processing unit 27 rewrites the system version information (older version) to stored program data version information (new version). Thus, all processors are unified to the same version of the initial operation program.
[0113]
Therefore, even if there are a plurality of versions, all the versions can be activated with the same version.
<Example 4>
Next, a fourth embodiment of the present invention will be described. FIG. 15 is a diagram illustrating a main configuration of the multiprocessor system according to the fourth embodiment.
[0114]
If the process is interrupted for some reason during the rewriting process (for example, a power failure), the FRAM in which the rewriting process is being performed cannot perform necessary operations because a part of its own program is not guaranteed. In this case, at the time of the initial operation after the reset, an abnormal status, which is a diagnosis abnormality of the own program, is stored as initial operation state information.
[0115]
However, since this is a state in which recovery can be performed by executing the rewriting process again, it is necessary to distinguish it from other abnormal statuses. However, it is not possible to discriminate whether an abnormality of the FRAM due to rewriting or a mere abnormality of the FRAM by diagnosis only by diagnosis of the own processor module.
[0116]
Therefore, the configuration in FIG. 15 further includes a rewriting state information unit 28 in addition to the configuration shown in FIG. The rewriting state information section 28 stores, for example, rewriting state information indicating a rewriting state when the rewriting processing section 27 executes rewriting of the FRAM.
[0117]
FIG. 16 shows details of the rewrite state information. In FIG. 16, the rewrite state information is the state of the rewrite processing operation of the FRAM in which the rewrite is executed, and is set by a flag for each processor module. The rewriting state information includes, for example, a normal state of the FRAM, an erasing state (a state where the erasing operation is performed on the rewritable part), a writing state (a state where the writing process is being executed on the rewritable part), and the like. State information is set.
[0118]
Next, the operation of the fourth embodiment will be described with reference to FIG. Fourth Embodiment In the fourth embodiment, a case will be described in which, in the state of the processor module configuration of the third embodiment, an abnormality occurs in the processing of the rewrite processing execution operation (step S31) shown in FIG. 13 and the rewrite processing cannot be continued normally.
[0119]
First, before rewriting the FRAM of the processor module 12-3, the rewrite state information unit 28 sets the rewrite state information of the processor module 12-3. For example, as shown in FIG. 16, the rewriting state information unit 28 sets abnormal state information such as during the FRAM erase processing operation or the write processing operation in an area indicating the processing state of the processor module 12-3 (step S35). .
[0120]
During the execution of the rewriting process (step S31), if an abnormality occurs in which the rewriting process cannot be continued, for example, when the system power is turned off, the state of the FRAM is neither A version nor B version. It will be in a state.
[0121]
When the system control mechanism unit 18 recognizes the occurrence of the abnormality from the rewrite state information (step S36), the system controller 18 performs a reset (step S37). Each of the processor modules 12-1 to 12-3 starts an initial operation (step S3a). Since the rewritable portion of the initial operation program of the FRAM is in an abnormal state, the processor module 12-3 is detected as an abnormality of the FRAM by the initial operation (Step S4).
[0122]
Further, since the version number of the initial operation program of the FRAM of the processor module 12-3 is also undefined, the 0th version is set as the FRAM version number information in the system memory 8 (step S12). In this state, the system configuration determining unit 19 executes the system configuration determining process, and degenerates the processor module 12-3 in which the initial operation state information is abnormal.
[0123]
Next, the system configuration determination unit 19 refers to the rewrite state information set in the rewrite state information unit 28 during the rewrite processing. Then, the system configuration determining unit 19 recognizes that the abnormality of the FRAM of the processor module 12-3 has occurred due to the interruption during the rewriting process.
[0124]
Therefore, in order to restore the FRAM of the processor module 12-3, the system configuration determining unit 19 degenerates the processor modules 12-1 and 12-2 other than the processor module 12-3, and configures the system using only the processor module 12-3. Configure (step S37).
[0125]
Next, in the system configured by the processor module 12-3, the rewrite processing unit 27 immediately executes the rewrite process, writes the initial operation program data 26 of the external storage device 25 into the FRAM of the processor module 12-3, The FRAM is restored as the version (step S38).
[0126]
When the rewriting process is completed normally, the processor module 12-3 clears the rewriting state information in the rewriting state information section 28 (Step S39) and requests a reset (Step S40).
[0127]
Thereafter, all the processor modules 12-1 to 12-3 have the B version of the initial operation program, and all the processor modules are activated as a multiprocessor system of the selected three processor modules.
[0128]
As described above, when the initial operation program recognizes the abnormal processor, the system configuration determining unit 19 refers to the rewrite state information stored in the rewrite state information unit 28 to configure the system with the abnormal processor and start the system operation. I do. The rewriting processing unit 27 restores the abnormal initial operation program generated during the rewriting by retrying the rewriting process.
[0129]
Therefore, even if the FRAM is in an abnormal state due to an abnormality during the rewriting process, recovery of the abnormal FRAM can be easily realized by the next reset operation.
<Example 5>
Next, a fifth embodiment of the present invention will be described. FIG. 18 is a diagram illustrating a main configuration of the multiprocessor system according to the fifth embodiment. In the configuration in FIG. 18, a rewrite state information unit 28a is added to the configuration shown in FIG. The rewriting state information section 28a stores, for example, rewriting state information indicating a rewriting state when the rewriting processing section 27 executes rewriting of the FRAM.
[0130]
FIG. 19 shows details of the rewrite state information. In FIG. 19, the rewrite state information 28a includes, as the processing state information of each processor module, the state of the rewrite processing operation of the FRAM and the number of retries for limiting the specified number of retries for performing the recovery processing when an abnormality occurs. Information is set by a flag for each processor module.
[0131]
Next, a first process according to the fifth embodiment will be described with reference to FIG. First, in the processor module 12-3, the rewrite state information unit 28a simultaneously sets retry count information when setting rewrite state information (step S41). In this example, the number of retries is set to 1 to permit one retry.
[0132]
Next, an abnormality occurs while the processor module 12-3 is executing the rewriting process. Then, the system control mechanism unit 18 recognizes that an abnormality has occurred in the processor module 12-3, and executes a reset.
[0133]
Further, after performing the processing from step S2 to step S12, when performing the system configuration determination processing, the system configuration determining unit 18 refers to the rewriting state information set in the rewriting state information unit 28a and performs a retry. Check that the count information is not zero.
[0134]
In this example, since the retry count information of the processor module 12-3 is 1, the system configuration determining unit 18 selects the processor module 12-3.
[0135]
Then, the system configuration determining unit 18 updates the retry count information stored in the rewrite status information unit 28a, that is, subtracts the information (step S42). In this example, the retry count information is updated from 1 to 0. Next, the system operation is started only by the processor module 12-3 (step S19).
[0136]
A second process according to the fifth embodiment will be described with reference to FIG. After the processing in step S19, the rewrite processing unit 27 executes the FRAM rewrite processing on the processor module 12-3 (step S30). However, at this time, the rewrite state information stored in the rewrite state information section 28a is not updated.
[0137]
Further, when the processing cannot be completed normally due to the abnormality in step S30 of the processor module 12-3, the reset is executed as in the case of the first abnormality. Then, after the processes from step S2 to step S12 are performed, the system configuration determining unit 19 executes a system configuration determining process.
[0138]
The system configuration determining unit 19 recognizes that the number of retries of the processor module 12-3 in the rewrite state information stored in the rewrite state information unit 28a is zero.
[0139]
Then, the system configuration determination unit 19 degenerates the processor module 12-3 as an abnormal processor module, and executes a system configuration determination process on the other processor modules 12-1 and 12-2 (step S43). In this example, the processor modules 12-1 and 12-2 are configured as a B-version system.
[0140]
When the number of retries of the processor module 12-3 of the rewrite state information stored in the rewrite state information unit 28a is not zero, the system configuration determination unit 19 degenerates other than the processor module 12-3. The system configuration determination process is executed.
[0141]
By setting the number of retries in the rewrite state information in this way, it is possible to prevent the rewrite processing from being attempted more than necessary, execute the degeneration of the processor module, and continue the rewrite processing of the other processor modules to perform the rewrite processing. You can improve your own reliability.
<Example 6>
Next, a sixth embodiment of the present invention will be described. FIG. 22 is a diagram illustrating a main configuration of the multiprocessor system according to the sixth embodiment. In the configuration in FIG. 22, maximum update number information sections 29-1 to 29-3 connected to the rewrite information section 28a are added to the configuration shown in FIG.
[0142]
The maximum update count information sections 29-1 to 29-3 store the maximum update count information of the FRAM in each processor module. Each FRAM has a maximum number of updates, such as rewriting and erasing, which is guaranteed as hardware. If the number of times exceeds this number, there is no guarantee of operations such as rewriting and erasing, and the operation result. Therefore, the program rewriting of the FRAM must be executed within the number of times that does not exceed this number.
[0143]
The other configuration is the same as the configuration of the fifth embodiment.
Next, the operation of the sixth embodiment will be described with reference to FIG. First, information of the rewrite FRAM is set (step S41).
[0144]
Next, when the rewrite state information section 28a sets the retry count information, the rewrite state information section 28a stores the maximum update count information of the FRAM for rewriting stored in the maximum update count information sections 29-1 to 29-3. See
[0145]
The maximum update count information is set when the product is shipped. When setting the number of retries, the number of retries is set so as not to be larger than the maximum number of updates (step S44). For example, when the maximum number of updates is three, the number of retries is not set to four or more.
[0146]
Next, when executing the rewriting process, the rewriting processing unit 27 updates (subtracts) the maximum update count information each time the update operation such as the erase operation or the write operation is performed (step S45).
[0147]
Since the FRAM restoration process is performed in consideration of the maximum number of updates of the FRAM by such a process, it is not necessary to perform an extra restoration process for an abnormality that occurs when the maximum number of updates is exceeded.
[0148]
【The invention's effect】
According to the present invention, the deciding unit degenerates an abnormal processor based on the initial operation state information stored in the distributed shared memory, and degenerates processors having different versions of the initial operation program based on the version number information to thereby determine the same processor. Is determined to constitute a system with a processor having an initial operation program of the version number.
[0149]
That is, since the system is composed only of the initial operation programs having the same version number, the system can be started up in which the cooperative operation of the processors is guaranteed..
[Brief description of the drawings]
FIG. 1 is a principle diagram showing a multiprocessor system of the present invention.
FIG. 2 is a principle flowchart showing a multiprocessor system configuration method of the present invention.
FIG. 3 is a configuration diagram illustrating a multiprocessor system according to a first embodiment of the present invention.
FIG. 4 is a flowchart illustrating processing of the multiprocessor system according to the first embodiment.
FIG. 5 is a flowchart illustrating a system configuration determining process performed by a system configuration determining unit.
FIG. 6 is a flowchart illustrating a specific system configuration determination process in which the system control mechanism degenerates an abnormal processor module;
FIG. 7 is a flowchart illustrating a specific system configuration determination process in which a system control mechanism unit degenerates processor modules of different versions.
FIG. 8 is a flowchart illustrating a specific system configuration determination process in which each processor module degenerates an abnormal processor module.
FIG. 9 is a flowchart illustrating a specific system configuration determination process in which each processor module degenerates a different version of the processor module;
FIG. 10 is a configuration diagram illustrating a multiprocessor system according to a second embodiment of the present invention.
FIG. 11 is a flowchart illustrating processing of the multiprocessor system according to the second embodiment.
FIG. 12 is a diagram illustrating a main configuration of a multiprocessor system according to a third embodiment.
FIG. 13 is a flowchart illustrating a first process of the multiprocessor system according to the third embodiment.
FIG. 14 is a flowchart illustrating a second process of the multiprocessor system according to the third embodiment.
FIG. 15 is a diagram illustrating a main configuration of a multiprocessor system according to a fourth embodiment.
FIG. 16 is a diagram illustrating details of rewrite state information according to the fourth embodiment.
FIG. 17 is a flowchart illustrating processing of the multiprocessor system according to the fourth embodiment.
FIG. 18 is a diagram illustrating a main configuration of a multiprocessor system according to a fifth embodiment.
FIG. 19 is a diagram illustrating details of rewrite state information according to the fifth embodiment.
FIG. 20 is a flowchart illustrating a first process of the multiprocessor system according to the fifth embodiment.
FIG. 21 is a flowchart illustrating a second process of the multiprocessor system according to the fifth embodiment.
FIG. 22 is a diagram illustrating a main configuration of a multiprocessor system according to a sixth embodiment.
FIG. 23 is a flowchart illustrating processing of the multiprocessor system according to the sixth embodiment.
[Explanation of symbols]
6. Common bus
8. System memory
12-1 to 12-3: Processor module (PM)
13-1 to 13-3, 180 CPU
15-1 to 15-3 RAM
16-1 to 16-3: Initial operation state information
17-1 to 17-3 ... FRAM version number information
18. System control mechanism
19. System configuration decision unit
20 .. Configuration mode information memory
21. Configuration mode setting processing section
22 ・ ・ System version number comparison section
23-System version information section
24 ・ ・ Stored program data version information section
25 .. External storage device
26 FRAM program
27..Rewriting processing unit
28, 28a ··· Rewriting status information section
19-1 to 19-3 ... maximum update count information section

Claims (4)

In a multiprocessor system in which a plurality of processors execute parallel processing through a common bus,
An initial operation unit provided in each processor to diagnose whether the initial operation of its own processor is normal or abnormal by an initial operation program,
A distributed shared storage unit that stores initial operation state information indicating a diagnosis result of an initial operation diagnosed by an initial operation program for each processor and version number information indicating a version number of the initial operation program;
Based on the initial operation state information stored in the distributed shared storage unit, the abnormal processor is degenerated , and based on the version information, it is determined whether the versions of the initial operation programs of all processors are the same. And a determination unit that performs a system configuration determination process for determining which version of the initial operation program is to be used to configure the system when there are different versions of the initial operation program . When the different version of the initial operation program is present, comprising a configuration mode information unit that stores configuration mode information representing logic to determine which version of the processor having the initial operation program configures the system ,
When the different versions of the initial operation program exist, the determination unit determines which version of the processor having the initial operation program is to be configured based on the logic and the version number information. 2. The multiprocessor system according to 1. In a system configuration method for configuring a multiprocessor system by executing parallel processing by a plurality of processors through a common bus,
An initial operation step of diagnosing whether the initial operation of its own processor is normal or abnormal by an initial operation program,
A storage step of storing, in a distributed shared memory, initial operation state information indicating a diagnosis result of an initial operation diagnosed by an initial operation program for each processor and version information indicating a version number of the initial operation program;
Degenerate the processor that was abnormal based on the initial operation state information stored in the distributed shared memory, and based on the version number information, determine whether the versions of the initial operation programs of all processors are the same, A determining step of determining which version of the initial operation program is to be used to configure the system when there are different versions of the initial operation program . If there are different versions of the initial operation program,
Comprising a configuration mode information step of storing configuration mode information representing logic for determining whether to configure a system with a processor having an initial operation program ,
The determining step, when the initial operation programs of different versions exist, determines which version of the processor having the initial operation program is to be configured based on the logic and the version number information. 4. The method for configuring a multiprocessor system according to item 3 .

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