JP3429880B2 - Memory device and memory access method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a memory access method used in a digital signal processor or the like.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable improvement in the performance of a digital signal processor (hereinafter abbreviated as DSP), and the fields in which it is used are expanding more and more.

Therefore, there is an increasing need for a versatile DSP. That is, one DSP is required to be able to execute various applications by changing the instruction program.

Further, in digital signal processing, an arithmetic operation is mainly performed on array data. Therefore, a processing of reading out data stored in a memory device to perform an arithmetic operation and writing the arithmetic result to the memory device is frequently performed. Therefore, the performance of the memory device becomes a major point with respect to the processing capability of the DSP.

A conventional example of a memory device used in a DSP will be described with reference to the drawings.

FIG. 9 is an example of a block diagram of a conventional memory device. In FIG. 9, 500 is a data memory, 510
Is an address generation circuit, 520 is an address bus, and 530 is a data bus.

The operation of the memory device shown in FIG. 9 will be described. The data memory 500 stores operation data. The address generation circuit 510 generates an address signal indicating an address to be accessed inside the data memory 500 and outputs it to the address bus 520. Address bus 52
0 transfers this address signal. Data memory 500
Receives an address signal from the address bus 520, reads the data stored at the address indicated by the address signal, and outputs the data to the data bus 530. The data bus 530 transfers this data. An arithmetic circuit not shown in FIG. 9 inputs this data and performs arithmetic operations. Alternatively, an arithmetic circuit not shown in FIG. 9 outputs the arithmetic result to the data bus 530, the data memory 500 inputs this arithmetic result from the data bus 530, and the address bus 52
Write this operation result to the address indicated by the address signal input from 0 (for example, "TMS320C5x User's Guide"
June1991 TEXAS INSTRUMENT company).

FIG. 10 is a block diagram of a conventional memory device different from that of FIG. In FIG. 10, 600 and 602 are data memories, 610 is an address generation circuit, and 6
20 and 622 are address buses, 630 and 632
Is a data bus, 634 is an arithmetic circuit, and 640 is a data transfer data bus.

The operation of the memory device shown in FIG. 10 will be described. The data memories 600 and 602 store operation data. The address generation circuit 610 generates an address signal indicating an address to be accessed in the data memory 600 and outputs the address signal to the address bus 620, and also generates an address signal indicating an address to be accessed in the data memory 602 to generate an address. Output to the bus 622. Address buses 620 and 622 transfer address signals. The data memory 600 has an address bus 6
An address signal is input from 20 and the data stored at the address indicated by this address signal is read and output to the data bus 630. In addition, the data memory 602
Receives an address signal from the address bus 622, reads the data stored at the address indicated by the address signal, and outputs the data to the data bus 632. Data buses 630 and 632 transfer data. Arithmetic circuit 6
34 inputs data from the data buses 630 and 632 and performs an operation (for example, “DSP56000 / DSP56001 User's M
anual "1990 MOTOROLA company).

[0010]

However, the conventional memory device has the following problems.

Consider a case where two data stored in the data memory 500 are operated in the memory device shown in FIG. First, the first data is read from the data memory 500 and temporarily stored in a register inside the arithmetic circuit,
Next, the second data is read again from the data memory 500, and the calculation of the first data and the second data is performed. In other words, one step requires memory access in two steps, and the processing time increases accordingly. This poses a serious problem in order to efficiently execute the digital signal processing operation.

In order to solve the above problem, the memory device shown in FIG. 10 has a structure in which the data memory is divided into two and each data memory is provided with a dedicated address bus and data bus. With this configuration, at the same time as reading the first data from the data memory 600,
The second data can be read from the data memory 602. In other words, since only one step of memory access is required for one calculation, the processing time can be greatly shortened as compared with the memory device shown in FIG.

However, also in the memory device shown in FIG. 10, when the versatility of the DSP is taken into consideration, that is, when a plurality of applications are executed by one DSP,
New problems arise.

In the memory device shown in FIG. 10, since the storage capacities of the data memories 600 and 602 are fixed, when a plurality of applications are executed by one DSP, the operation data in each application are stored in the two data memories 600. It is extremely difficult to optimally allocate the data to 602 and 602. That is, the data used in a certain operation may often be stored in the same data memory. In this case, as in the calculation in the memory device shown in FIG.
Two-step memory access is required for each calculation, which increases the processing time.

Therefore, in the memory device shown in FIG. 10, the data transfer bus 640 is provided to enable the data transfer between the data memories, and the data transfer process is executed between the arithmetic processes so that the above-mentioned problem occurs. Trying to avoid.

However, in actuality, a waiting time occurs in the original arithmetic processing by executing the data transfer processing, so that the overall processing time increases. Further, since the data transfer process is a process that is not related to the arithmetic process itself, wasteful power consumption is required, which is not preferable.

If the data memory in the memory device shown in FIG. 10 is further divided to realize a memory device composed of a plurality of data memories, it is possible to arrange the arithmetic data so that the arithmetic processing can be efficiently performed in each application. In addition, the need for data transfer processing is reduced. However, in the conventional technique, when the number of data memories is increased, the amount of hardware such as an address bus and a data bus is increased accordingly, which is a big problem particularly when the DSP is used for small devices. .

In view of the above points, an object of the present invention is to provide a memory device and a memory access method capable of efficiently executing various applications of digital signal processing.

[0019]

According to a first aspect of the present invention, a means for solving the problems is directed to a memory device, and an address generating means for outputting an address signal for instructing an address of data, and the address generating means for outputting. An address bus for transferring an address signal, a first data memory and a second data memory connected to the address bus, each of which stores a plurality of data, and an address bus connected to the first data memory. A first data bus for transferring data input / output to / from the first data memory and a second data bus connected to the second data memory to transfer data input / output to / from the second data memory. Data bus,
Data is output from the first data memory and data is input to the second data memory, or data is input to the first data memory and data is output from the second data memory. Connected to the flag holding means, the first data memory and the second data memory for holding and outputting the flag information indicating whether or not (i) the read control signal input from the outside. When the data reading is instructed and the data writing is instructed by the write control signal input from the outside, the first data memory and the second data memory are based on the flag information input from the flag holding unit. While outputting a read signal for instructing the reading of data to the one of the data memories that outputs the data, Outputs a write signal for instructing writing of data into the data memory of the person who inputs the data, (i
i) Instruct to read data by the read control signal
And writing data by the write control signal
Is not instructed, a partial address signal
Of the first and second data memories according to
Select one of them, and read the read signal to the selected data memory.
Is output, and (iii) the read control signal
If the read control is not given and the write control signal is
If you are instructed to write data,
The first and second data according to some bits of the
Select one of the
And a control means for outputting the write signal, the first data memory, when the read signal from said control means is inputted, reads data from the address indicated address signal input from said address bus Output to the first data bus and a write signal is input from the control means, data is input from the first data bus and written to the address indicated by the address signal input from the address bus. When the read signal is input from the control means, the second data memory reads the data from the address indicated by the address signal input from the address bus to output the second data memory.
When the write signal is input from the control means, the data is input from the second data bus and written to the address indicated by the address signal input from the address bus. It is configured to be.

According to a second aspect of the present invention, there is provided a solving means for a memory device, wherein address generating means for outputting an address signal designating an address of data, and transferring an address signal outputted by the address generating means. A first address bus and a second address bus; a plurality of memory bank groups each including a plurality of memory banks connected to the first address bus and the second address bus; and the plurality of memory bank groups. A first data bus and a second data bus that are respectively connected to the plurality of memory banks that make up and transfer the data output from each memory bank; and the plurality of memory banks that make up the plurality of memory bank groups. A third data bus that is connected to each other and transfers data to be input to each memory bank, and a plurality of memory buses that configure each memory bank group. Flag holding means for holding and outputting flag information for instructing a first memory bank for outputting data and a second memory bank for inputting data, one for each memory bank group, Connected to the first address bus, the second address bus, flag holding means and a plurality of memory banks, (i)
When data read is instructed by a first read control signal input from the outside and data write is instructed by a first write control signal input from the outside, the data is input from the first address bus. Select one memory bank group from the plurality of memory bank groups based on some bits of the address signal, input flag information for the selected memory bank group from the flag holding means, and input the flag information. A first selection instructing to select the first memory bank and the second memory bank from a plurality of memory banks forming a memory bank group selected based on the above, and to select the first address bus Signal, a second selection signal instructing to select the first data bus, and a read signal instructing to read data. Is output to the first memory bank and a first select signal instructing to select the first address bus and a write signal instructing to write data are output to the second memory bank, ii) When the second read control signal input from the outside instructs the reading of the data and the second write control signal input from the outside instructs the writing of the data, the second address bus One memory bank group is selected from the plurality of memory bank groups based on a part of the bits of the address signal input from, and the flag information for the selected memory bank group is input from the flag holding means and input. The first memory bank and the second memory among a plurality of memory banks forming a memory bank group selected based on flag information Select the link,
A first instructing to select the second address bus
Output select signal, a second select signal instructing to select the second data bus, and a read signal instructing to read data to the first memory bank and selecting the second address bus. A plurality of memory banks that constitute the plurality of memory bank groups, and a control unit that outputs to the second memory bank a first selection signal for instructing to perform and a write signal for instructing to write data. Select one of the first address bus or the second address bus according to the first selection signal input from the control means, and select the remaining bit of the address signal from the selected address bus. And a plurality of pieces of data are stored, and (i) when a read signal is input from the control means. , The remaining bits of the address signal output from the selecting means are input to read data from the address indicated by the remaining bits, and the first data bus is operated in accordance with the second selecting signal input from the controlling means. Alternatively, when any one of the second data buses is selected and the read data is output to the selected data bus, (ii) when a write signal is input from the control means, the third data bus And a data memory for writing the data to the address indicated by the remaining bits of the address signal output from the selecting means.

According to a third aspect of the present invention, a solving means is directed to a memory access method, an address generating step of outputting an address signal indicating a data address, and an address transferring the address signal via an address bus. A signal transfer step, transferring data output from the first data memory and data input to the first data memory via the first data bus, and outputting data output from the second data memory; A data transfer step of transferring data input to the second data memory via a second data bus; outputting data from the first data memory and inputting data to the second data memory Or inputting data to the first data memory and outputting data from the second data memory. A flag setting step of setting a grayed information, if the write control signal from the outside is pointing to write data with instructs the reading of the read control signal data from (i) external, the flag information On the basis of the above, the one of the first data memory and the second data memory that outputs the data is selected, and the read signal instructing the reading of the data from the data memory is output while the first data memory is output. Of the second data memory and the data memory to which data is to be input, and a write signal for instructing writing of data to the data memory is output , and (ii) the reading
Read out data is instructed by the protrusion control signal and
Instruct to write data by the write control signal
If not, it follows some bits of the address signal.
Select either the first or second data memory.
The read signal is output to the selected data memory.
And (iii) read data by the read control signal.
Is not instructed and the write control signal causes a
If the writing of data is instructed, the address signal
The first and second data memos according to some bits of
Select one of the
A control step of outputting a read signal, and (i) when the read signal is output, the read signal reads data from an address indicated by an address signal from the address bus of the data memory instructing reading of data, When the data memory is the first data memory, the read data is output to the first data bus, and when the data memory is the second data memory, the read data is read to the second data bus. (Ii) when the write signal is output, the data is output from the first data bus when the data memory instructing the data write by the write signal is the first data memory. Is input, and when the data memory is the second data memory, data is input from the second data bus, and the data memory is input. It is an arrangement comprising a data input step of writing data inputted to the address indicated address signal input from the address bus.

According to a fourth aspect of the present invention, a means for solving the problems is directed to a memory access method, and an address generating step of outputting an address signal instructing a data address, and the address signal to the first address bus and the second address bus. Address signal transfer step of transferring the data through each address bus, and the data output from each of the plurality of memory banks forming the plurality of memory bank groups.
A data transfer step of transferring data input to each of the plurality of memory banks forming the plurality of memory bank groups via the third data bus, A flag setting step of setting flag information for instructing a first memory bank for outputting data and a second memory bank for inputting data, one for each memory bank group, among a plurality of memory banks constituting , (I) The first read control signal from the outside instructs the reading of data and the first read control signal from the outside.
Write control signal instructing to write data, one memory bank group is selected from the plurality of memory bank groups based on some bits of the address signal from the first address bus. The first of the plurality of memory banks forming the memory bank group selected based on the flag information for the selected memory bank group
Memory bank and a second memory bank, and a read signal instructing to read data from the first memory bank, a first select signal instructing to select the first address bus, and Outputting a second selection signal instructing to select the first data bus and instructing to select the first address bus and a write signal instructing to write data to the second memory bank. A second selection control signal from the outside is instructed to read data, and a second write control signal from the outside is instructed to write data. In this case, one memory bank group is selected from the plurality of memory bank groups based on some bits of the address signal from the second address bus, and the selected memory bank group is selected. The first memory bank and the second memory bank from among a plurality of memory banks forming the memory bank group selected based on the flag information for the memory bank group.
Memory bank is selected, a read signal instructing to read data from the first memory bank, a first select signal instructing to select the second address bus, and the second data bus are selected. A first selection signal which outputs a second selection signal instructing to select and a write signal instructing to write data to the second memory bank, and a first selection signal instructing to select the second address bus. And (i) when the read signal is output, one of the first address bus and the second address bus is selected and selected according to the first selection signal. The remaining bits of the address signal are input from the address bus, data is read from the address indicated by the remaining bits of the first memory bank, and the second selection is performed. According to a signal, either one of the first data bus or the second data bus is selected, and the read data is output to the selected data bus, and (ii) when the write signal is output, First
The first address bus or the second address bus according to the selection signal of
Selecting one of the address buses, inputting the remaining bits of the address signal from the selected address bus, inputting data from the third data bus, and inputting the remaining bits of the second memory bank. And a data input / output step of writing the data to the address indicated by the bit.

[0023]

According to the structure of the first or third aspect of the present invention, the flag information for setting which of the two data memories outputs the data and which of the data is input is set. A read signal and a write signal are output according to the flag information. When the read signal is output, the address signal is input from the address bus, and the data stored at the address designated by the address signal of the data memory designated by the read signal is read and output to the data bus. When the write signal is output, the address signal is input from the address bus, and the data input from the data bus is written to the address designated by the address signal in the data memory designated by the write signal. In this way, the operation of accessing two data memories according to one address designation, reading one data and writing one data can be executed in one step.

According to the second or fourth aspect of the present invention, flag information is set in each memory bank group, the flag information indicating a memory bank for outputting data and a memory bank for inputting data. One memory bank group is selected according to some bits of the address signal from the first address bus, two memory banks are selected according to flag information corresponding to the memory bank group, and a read signal and a write signal are output. It One memory bank is selected according to some of the bits of the address signal from the second address bus, and the read signal is output. When the read signal is output, the address bus is selected according to the instruction of the first selection signal input together with the read signal, the address signal transferred to the address bus is input, and the memory bank specified by the read signal is input. The data stored at the address indicated by the address signal is read, and the first data bus or the second data bus is selected according to the instruction of the second selection signal input together with the read signal, and read. Data is output. The first that is input together with the write signal when the write signal is output
The address bus is selected in accordance with the instruction of the selection signal, the address signal transferred to the address bus is input, and the address designated by the address signal of the memory bank designated by the write signal is input from the third data bus. Write the input data. In this way, three data memories are accessed according to two address specifications,
The operation of reading two data and writing one data can be executed in one step.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a memory device according to a first embodiment of the present invention.

In FIG. 1, 100, 102, 104 and 106 are data memories, 110 is an address generation circuit as an address generation means, 120 is a first address bus, 122 is a second address bus, and 130 is a first address bus. A first lower bit line for transferring a lower 10 bit signal of the address bus, 132 is a second lower bit line for transferring a lower 10 bit signal of the second address bus, 14
0 is a first upper bit line that transfers a signal of the upper 2 bits of the first address bus, 142 is a second upper bit line that transfers a signal of the upper 2 bits of the second address bus, 150, Reference numerals 152, 154 and 156 are multiplexers as selection means, 160, 162, 164 and 166 are selection signal lines for transferring selection signals, 170 is a control signal line for transferring a first read control signal, and 172 is a second read. A control signal line for transferring a control signal, 18
0, 182, 184 and 186 are read signal lines for transferring a read signal, 181 is a control circuit as control means,
Reference numeral 190 is a first data bus, 192 is a second data bus, 194 is an arithmetic circuit, and 196 is a register. One memory bank is constituted by the data memory 100 and the multiplexer 150, and similarly, the data memory 102, the multiplexer 152, and the data memory 10
4 and the multiplexer 154, and the data memory 106 and the multiplexer 156 respectively configure memory banks.

The data memories 100, 102, 104 and 106 each have a storage capacity of 1k (= 2 ¹⁰ = 1024) words. Since the memory device according to this embodiment holds four data memories, the total storage capacity is 4k (= 4 × 2 ¹⁰ = 2 ¹² = 4096) words. Therefore, the address data indicating the storage area is 12
The data memory 100 has an address x'0.
00 '(x' ... 'represents hexadecimal number) to address x'
Up to 3FF 'are allocated, address x'400' to address x'7FF 'are allocated to the data memory 102, and address x'8 is allocated to the data memory 104.
00 'to address x'BFF' are allocated,
Addresses x'C00 'to x'FFF' are assigned to the data memory 106.

The address generation circuit 110 outputs a 12-bit address signal to the first address bus 120 and the second address bus 120.
Address bus 122. The upper 2 bits of the 12 bits are used to select the data memory, and the lower 10 bits are used to indicate the address in the selected data memory. The first lower bit line 130 and the second lower bit line 132 are connected to the multiplexer 15
0, 152, 154 and 156. The first upper bit line 140 and the second upper bit line 142 are connected to the control circuit 181.

When the first read control signal is input through the control signal line 170, the control circuit 181 reads the signal from the first upper bit line 140, and based on the value, selects signal according to Table 1 (a). And output a read signal. Further, when the second read control signal is input through the control signal line 172, the signal is read from the second upper bit line 142, and the selection signal and the read signal are output based on the value according to Table 1 (b). . The selection signal is output to the multiplexer and the data memory, and the read signal is output to the data memory.

[0031]

[Table 1]

At this time, the multiplexer is the control circuit 1
When the selection signal input from 81 is "0", the signal input from the first lower bit line 130 is output to the data memory, and the selection signal input from the control circuit 181 is "0".
When it is "1", a signal is input from the second lower bit line 132 and output to the data memory.

When the read signal input from the control circuit 181 is "1", the data memory inputs the signal of the lower 10 bits of the address signal through the corresponding multiplexer and stores it at the address indicated by the signal. The stored data is read and output to the first data bus 190 or the second data bus 192. When the selection signal input from the control circuit 181 is "0", the data is output to the first data bus 190, and when the selection signal input from the control circuit 181 is "1", the data is output to the second data bus 192. Is output.

The arithmetic circuit 194 is connected to the first data bus 19
Data is input from 0 and the second data bus 192 to perform an operation. The register 196 holds the calculation result output by the calculation circuit 194.

The operation of the memory device configured as above will be described.

Here, the addresses x'001 'and x'4
An example will be described in which the data stored in No. 02 'is read and the calculation is executed. In the memory device according to the present embodiment, the address x'001 'is the address b'00000001' of the data memory 100.
(B '...' represents a binary number), the address x'4
02 'is the address b'0000 of the data memory 102.
It corresponds to 000010 '.

First, the address generation circuit 110 outputs x'001 'as an address signal to the first address bus 120.
X'402 'is output as an address signal to the second address bus 122.

At this time, since the signal output to the first upper bit line 140 is the upper 2 bits of the address signal output to the first address bus 120, b'00 '.
Since the signal output to the first lower bit line 130 is the lower 10 bits of the address signal output to the first address bus 120, b'00000000.
01 '. Also, the signal output to the second upper bit line 142 is the upper 2 bits of the address signal output to the second address bus 122, so it becomes b′01 ′ and is output to the first lower bit line 130. The output signal is
Since it is the lower 10 bits of the address signal output to the first address bus 120, b'00000001
It becomes 0 '.

At the same time, a first read control signal is sent from the instruction decoding means (not shown in FIG. 1) to the control circuit 181 through the control signal line 170 and a second read control signal is sent through the control signal line 172. Is output.

Since both the first read control signal and the second read control signal are input to the control circuit 181, the value of the signal input from the first upper bit line 140 and the second upper bit line 142. Thus, the selection signal and the read signal are output according to Tables 1 (a) and 1 (b). That is, the selection signal line 160 has a selection signal "
0 "is output, and the selection signal line 162 is supplied with"
1 ". Also, the read signal lines 180 and 18
"1" is output as a read signal to 2 and "1" is output to the read signal lines 184 and 186 as a read signal.
0 "is output.

Read signal through the read signal line 180
The data memory 100 to which "1" is input inputs the lower 10 bits of the address signal via the multiplexer 150. The multiplexer 150 receives the selection signal line 16
Since the selection signal "0" is input through 0, the first
The lower bit line 130 is selected, a signal is input, and the signal is output to the data memory 100. This signal, b'000
The data memory 100 to which 0000001 'is input is
Since the data stored in the address b'00000001 'is read and the selection signal "0" is input through the selection signal line 160, the first data bus 19
Select 0 to output this data.

At the same time, the data memory 102 to which the read signal "1" is input through the read signal line 182,
Lower 10 bits of the address signal via the multiplexer 152
Input the bit signal. Since the selection signal “1” is input through the selection signal line 162, the multiplexer 152 selects the second lower bit line 132, inputs the signal, and outputs the signal to the data memory 102. The data memory 102 to which this signal, that is, b'00000010 'is input, reads the data stored at the address b'00000010', and the selection signal "1" is input through the selection signal line 162. The data bus 192 is selected and this data is output.

That is, the data at the address x'001 'is output to the first data bus 190 and the data at the address x'402' is output to the second data bus 192 at the same time.

The arithmetic circuit 194 is connected to the first data bus 19
Data is input from 0 and the second data bus 192 to perform an operation, and the operation result is stored in the register 196.

By the above operation, the address x'001 '
And the data stored at the address x'402 'is calculated.

That is, according to the memory device of the first embodiment of the present invention, it is possible to execute an operation on two data stored in the data memory by one-step memory access.

(Second Embodiment) The memory device according to the first embodiment is dedicated to reading data, but the second embodiment has a data writing function added thereto.

FIG. 2 is a block diagram of a memory device according to the second embodiment of the present invention.

In FIG. 2, 120 is a first address bus, 122 is a second address bus, 130 is a first lower bit line, 132 is a second lower bit line, and 140 is a first lower bit line.
Upper bit line, 142 is the second upper bit line, 16
0, 162, 164 and 166 are selection signal lines for transferring selection signals, 170 is a control signal line for transferring a first read control signal, 172 is a control signal line for transferring a second read control signal, 180, 182 , 184 and 186
Is a read signal line for transferring a read signal, 190 is a first data bus, 192 is a second data bus, 194 is an arithmetic circuit, 196 is a register, 200, 202, 204 and 206 are data memories, and 210 is an address generator. An address generation circuit as means, 220 is a third address bus, 230 is a third lower bit line for transferring a signal of the lower 10 bits of the third address bus, and 240 is an upper 2 of the third address bus. Third bit signal transfer
High order bit lines, 250, 252, 254 and 256
Is a multiplexer as selecting means, 270 is a control signal line for transferring a write control signal, 280, 282, 28
4 and 286 are write signal lines for transferring write signals,
Reference numeral 281 is a control circuit as control means, and 290 is a third data bus. One memory bank is configured by the data memory 200 and the multiplexer 250, and similarly, the data memory 202 and the multiplexer 25.
2, the data memory 204 and the multiplexer 254, and the data memory 206 and the multiplexer 256 constitute memory banks.

The data memories 200, 202, 204 and 206 are the data memories 10 in the first embodiment.
1 for each of 0, 102, 104 and 106
It has a memory capacity of k (= 2 ¹⁰ = 1024) words,
Addresses are assigned in the same manner as in the above embodiment. The characteristic feature is that the data memory in the first embodiment has only the function of reading data, whereas the data memory in the second embodiment has the function of writing data.

The address generation circuit 210 outputs a 12-bit address signal to the first address bus 120, the second address bus 122 and the third address bus 220. The upper 2 bits of the 12 bits are used to select the data memory, and the lower 10 bits are used to indicate the address in the selected data memory.
First lower bit line 130, second lower bit line 132
And the third lower bit line 230 is
50, 252, 254 and 256.
The first upper bit line 140, the second upper bit line 142, and the third upper bit line 240 are connected to the control circuit 2.
It is connected to 81.

When the first read control signal is input through the control signal line 170, the control circuit 281 inputs a signal from the first upper bit line 140 and selects it according to Table 1 (a) based on the value. Output signal and read signal. In addition, when the second read control signal is input through the control signal line 172, a signal is input from the second upper bit line 142, and a selection signal and a read signal are output based on the value according to Table 1 (b). To do. Furthermore, when a write control signal is input through the control signal line 270, a signal is input from the third upper bit line 240, and a selection signal and a write signal are output according to Table 2 based on the value.
The selection signal is output to the multiplexer and the data memory, and the read signal and the write signal are output to the data memory.

[0053]

[Table 2]

At this time, the multiplexer is the control circuit 2
When the selection signal input from 81 is "0", the signal input from the first lower bit line 130 is output to the data memory, and the selection signal input from the control circuit 281 is "
When it is "1", a signal is input from the second lower bit line 132 and output to the data memory, and when the selection signal input from the control circuit 281 is "2", it is output from the third lower bit line 230. Input signals and output to data memory.

When the read signal input from the control circuit 281 is "1", the data memory inputs the lower 10-bit signal of the address signal through the corresponding multiplexer and stores it in the address indicated by the signal. The stored data is read and output to the first data bus 190 or the second data bus 192. When the selection signal input from the control circuit 281 is "0", the data is output to the first data bus 190, and when the selection signal input from the control circuit 281 is "1", the data is output to the second data bus 192. Is output.

When the write signal input from the control circuit 281 is "1", data is input from the third data bus 290 and the lower 10 bits of the address signal is input via the corresponding multiplexer. Then, the input data is written to the address indicated by the signal.

The arithmetic circuit 194 is connected to the first data bus 19
Data is input from 0 and the second data bus 192 to perform an operation. The register 196 temporarily holds the data of the calculation result output by the calculation circuit 194 and outputs it to the third data bus 290.

The operation of the memory device configured as described above will be described.

Here, in the state where the previous operation result has already been output from the register 196 to the third data bus, the operation result is written to the address x'805 'and at the same time, the addresses x'002' and x '. An example will be described in which the data stored in 403 ′ and 403 ′ is read out and the calculation is executed.

In the memory device according to this embodiment, the address x'805 'corresponds to the address b'0000000101' of the data memory 204, and the address x'0 '.
02 'is the address b'0000 of the data memory 200.
At the time of 000010 ', the address x'403' is the address b'00000001 of the data memory 202.
It corresponds to 1 '.

First, the address generation circuit 210 outputs x'002 'as an address signal to the first address bus 120.
X'403 'as an address signal to the second address bus 122 and x'805' as an address signal to the third address bus 220.

At this time, since the signal output to the first upper bit line 140 is the upper 2 bits of the address signal output to the first address bus 120, b'00 '.
Since the signal output to the first lower bit line 130 is the lower 10 bits of the address signal output to the first address bus 120, b'00000000.
10 '. Also, the signal output to the second upper bit line 142 is the upper 2 bits of the address signal output to the second address bus 122, so it becomes b'01 'and is output to the second lower bit line 132. The output signal is
Since it is the lower 10 bits of the address signal output to the second address bus 122, b'00000001
It becomes 1 '. Further, since the signal output to the third upper bit line 240 is the upper 2 bits of the address signal output to the third address bus 220, it becomes b′10 ′ and is output to the third lower bit line 230. The output signal is
Since it is the lower 10 bits of the address signal output to the third address bus 220, b'00000010
It becomes 1 '.

At the same time, an instruction decoding means (not shown in FIG. 2) sends to the control circuit 281 a first read control signal through the control signal line 170 and a second read control signal through the control signal line 172. , Control signal line 2
Write control signals are output through 70.

Since both the first read control signal and the second read control signal are input to the control circuit 281, the value of the signal input from the first upper bit line 140 and the second upper bit line 142. Thus, the selection signal and the read signal are output according to Tables 1 (a) and 1 (b). Further, since the write control signal is input, the third
Depending on the value of the signal input from the upper bit line 240 of
The selection signal and the write signal are output according to Table 2. That is, “0” is output as the selection signal to the selection signal line 160, “1” is output as the selection signal to the selection signal line 162, and “2” is output as the selection signal to the selection signal line 164. "1" is output as a read signal to the read signal lines 180 and 182, and "0" is output as a read signal to the read signal lines 184 and 186. Also,
"1" is output as a write signal to the write signal line 284, and "0" is output as a write signal to the write signal lines 280, 282 and 286.

Read signal through the read signal line 180
The data memory 200 to which "1" is input inputs the lower 10 bits of the address signal via the multiplexer 250. The multiplexer 250 receives the selection signal line 16
Since the selection signal "0" is input through 0, the first
The lower bit line 130 is selected, a signal is input and output to the data memory 200. This signal, b'000
The data memory 200 to which 0000010 'is input is
Since the data stored at the address b'00000010 'is read and the selection signal "0" is input through the selection signal line 160, the first data bus 19
Select 0 to output this data.

The data memory 202, to which the read signal “1” is input through the read signal line 182, inputs the lower 10 bits of the address signal via the multiplexer 252. Since the selection signal “1” is input through the selection signal line 162, the multiplexer 252 selects the second lower bit line 132, inputs the signal, and outputs the signal to the data memory 202. The data memory 202 to which this signal, that is, b'00000011 'is input, reads the data stored in the address b'00000011', and the selection signal "1" is input through the selection signal line 162. The data bus 192 is selected and this data is output.

Further, the data memory 204, to which the write signal “1” is input through the write signal line 284, inputs the lower 10 bits of the address signal via the multiplexer 254. Since the selection signal “2” is input through the selection signal line 164, the multiplexer 254 selects the third lower bit line 230, inputs the signal, and outputs the signal to the data memory 204. The data memory 204 to which this signal, that is, b'0000000101 'is input, receives the selection signal "2" via the selection signal line 164, so the data output from the register by selecting the third data bus 290. Is input, and the data is stored in the address b'0000000101 '.

That is, the data at the address x'002 'is output to the first data bus 190 and the data at the address x'403' is output to the second data bus 192, respectively, and at the same time input from the third data bus 290. The data thus stored is stored in the address x'805 '.

The arithmetic circuit 194 is connected to the first data bus 19
Data is input from 0 and the second data bus 192 to perform an operation, and the operation result is stored in the register 196.

By the above operation, the previous operation result is stored in the address x'805 'and at the same time the address x'00 is stored.
The data stored in 2'and the address x'403 'is calculated.

That is, according to the memory device of the second embodiment of the present invention, the operation for the two data stored in the data memory and the storage of the previous operation result can be executed by one-step memory access. You can

As a memory device having a data writing function, a memory device having an address bus for both reading and writing data can be realized instead of adding a data writing address bus as shown in FIG.

FIG. 3 is a block diagram of such a memory device. The basic structure and operation are similar to those of the memory device shown in FIGS. First address bus 12
0 and the second address bus 122 are data read / write address buses, and the control signal line 272 for transferring the second write control signal is the control circuit 2
It is newly connected to 81.

When the first write control signal is input through the control signal line 270, the first address bus 12
Data is written in the memory according to the address signal output to 0. When the second write control signal is input through the control signal line 272, the second address bus 1
Data is written to the memory according to the address signal output to 22. By such an operation, the data writing function is realized.

(Third Embodiment) In the filter calculation frequently used in digital signal processing, the processing shown in the following equation is often performed.

A ′ (n) = A (n−1) + α × B (n) (n = 1,
2, ..., N) where A ′ (n), A (n) and B (n) are array data, and α is a constant coefficient. The number of data N is usually a value of several hundreds.

When the filter operation shown in the above equation is processed by the DSP, the array data A (n-1) and B (n) are read from the memory device, the operation device performs the operation, and the operation result A '(n) is obtained. It is necessary to perform the operation of writing to the memory device several hundred times. In order to realize efficient processing, it is desirable that reading of two data and writing of one data can be executed by one-step memory access. For that purpose, like the memory device shown in FIG. 2, three systems of addressing means such as an address bus, an upper bit line and a lower bit line are required.

The address bus is composed of a dozen bit lines per system. Also, the lower bit lines need to be connected to multiple multiplexers. Therefore, a large amount of hardware is required for the address designating means, which poses a serious problem in downsizing the device. Further, since the voltage of the address bus constantly changes due to the change of the signal, the structure having a large number of address buses leads to an increase in current consumption and is not suitable for being incorporated in a battery-driven device such as a mobile phone. Therefore, the number of addressing means should be reduced as much as possible.

In the present invention, by providing the memory device with the flag holding means, the efficient processing of the filter operation can be performed.
This is achieved with fewer addressing means. Here, as a third embodiment, first, a simple memory device having a flag holding means and a single address designating means will be described.

FIG. 4 is a block diagram of a memory device according to the third embodiment of the present invention.

In FIG. 4, 300 is a first data memory, 302 is a second data memory, 310 is an address generation circuit as address generation means, 320 is an address bus, and 330 is the lower 10 bits of the address bus 320. Lower bit line for transferring signals, 340 is address 32
A high-order bit line that transfers a high-order 2 bit signal of 0,
Reference numeral 370 is a control signal line for transferring a read control signal, and 37
Reference numeral 2 is a control signal line for transferring a write control signal, 378 is a flag as flag holding means, 381 is a control circuit as control means, 380 and 382 are read signal lines for transferring read signals, 385 and 387 are write signals. The write signal line to be transferred, 390 is the first data bus, 3
Reference numeral 92 is a second data bus.

The data memories 300 and 302 each have a storage capacity of 1k (= 2 ¹⁰ = 1024) words. The address data indicating the storage area is 12 bits, addresses x'000 'to x'3FF' are assigned to the data memory 300, and addresses x'400 'to x'are assigned to the data memory 302.
Up to 7FF 'are allocated.

The address generation circuit 310 outputs a 12-bit address signal to the address bus 320. The upper 2 bits of the 12 bits are used to select the data memory, and the lower 10 bits are used to indicate the address in the selected data memory. Lower bit line 3
30 is connected to the first data memory 300 and the second data memory 302, and the upper bit line 340
Are connected to the control circuit 381.

When a read control signal is input through the control signal line 370, the control circuit 381 inputs a signal from the upper bit line 340 and outputs a read signal based on the value. When the signal value is b'00 ', "1" is output to the read signal line 380, and "0" is output to the read signal line 382. When the signal value is b'01', the read signal line 38 is output.
“0” is output to 0 and “1” is output to the read signal line 382. When a write control signal is input through the control signal line 372, a signal is input from the upper bit line 340 and a write signal is output based on that value. Signal value is b'0
When it is 0 ', "1" is output to the write signal line 385 and "0" is output to the write signal line 387, and the signal value is b'01'.
In this case, “0” is output to the write signal line 385 and “1” is output to the write signal line 387.

When both the read control signal and the write control signal are input, the control circuit 381 inputs the signal from the upper bit line 340, and if the value is b'00 'or b'01', The control is performed according to the flag information of the flag 378.

The flag 378 is "0" when the operation of outputting the data from the first data memory and inputting the data to the second data memory is instructed, and when the data is input to the first data memory, When instructing the operation of outputting data from the second data memory, "1" is held as flag information.

The flag information is set before the control signal is input to the control circuit 381. FIG. 5 shows an example of a flag information setting method. FIG. 5A shows a method of setting flag information from the data bus according to an instruction of a write signal, and FIG. 5B shows a method of setting flag information using a set signal and a reset signal.

Therefore, if the flag information is "0", the read signal line 380 and the write signal line 387 have "0".
1 "is output, and" 0 "is output to the read signal line 382 and the write signal line 385. If the flag information is" 1 ", the read signal line 382 and the write signal 385 are output.
1 "is output, and" 0 "is output to the read signal line 380 and the write signal line 387.

The first data memory 300 includes the control circuit 3
When the read signal input from 81 is “1”, the signal of the lower 10 bits of the address signal is input from the lower bit line 330, the data is read from the address indicated by the signal and output to the first data bus 390. To do. When the write signal input from the control circuit 381 is "1",
Data is input from the first data bus 390, and the input data is written to the address indicated by the lower 10-bit signal of the address signal input from the lower bit line 330.

The second data memory 300 includes the control circuit 3
When the read signal input from 81 is "1", the signal of the lower 10 bits of the address signal is input from the lower bit line 330, the data is read from the address indicated by the signal and output to the second data bus 392. To do. When the write signal input from the control circuit 381 is "1",
Data is input from the second data bus 392, and the input data is written to the address indicated by the lower 10 bits of the address signal input from the lower bit line 330.

The operation of the memory device configured as described above will be described.

Here, a case will be described as an example where the data is read from the address x'002 'and at the same time the data is written to the address x'402'.

In this memory device, the address x'00
2'is the address b'000000 of the data memory 300
At the time of 0010 ', the address x'402' corresponds to the address b'00000010 'of the data memory 302. That is, the lower one indicating the address in the data memory
The 0-bit signal is common.

First, the flag 378 is set as "flag information".
Set to 0 ".

The address generation circuit 310 uses the address bus 3
It outputs x'002 'to 20. At this time, since the signal output to the upper bit line 340 is the upper 2 bits of the address signal output to the address bus 320, b'0.
The signal that becomes 0 ′ and is output to the lower bit line 330 is
Lower one of the address signals output to the address bus 320
Since it is 0 bit, it becomes b'00000010 '.

At the same time, a read control signal and a write control signal are output from the instruction decoding means (not shown in FIG. 4) to the control circuit 381 through the control signal line 370 and the control signal line 372, respectively.

The control circuit 381 inputs both the read control signal and the write control signal, and since the value of the signal input from the upper bit line 340 is b'00 ', it inputs the flag information from the flag 378. Control is performed based on that value. Now, since the value of the flag information is "0", the read signal line 380 and the write signal line 387 are
Is output to the read signal line 382 and the write signal line 385.

The data memory 300 has a read signal line 38.
Since the read signal “1” is input through 0, the signal of the lower 10 bits of the address signal is input from the lower bit line 330, the address indicated by this signal, that is, the data of the address b′0000000010 ′ is read out, and the first
Data bus 390.

The data memory 302 has a write signal line 38.
Since the write signal “1” is input through 7, the data is input from the second data bus 392 and the lower bit line 3
The address indicated by the lower 10-bit signal of the address signal input from 30, that is, the address b'00000000
The input data is written in 10 '.

By the above operation, the address x'002 '
Is output to the first data bus 390, and the data of the second data bus 392 is output to the address x'4.
It is stored in 02 '.

That is, according to the memory device of the third embodiment of the present invention, although the address bus has only one system, reading and writing of data can be executed by one-step memory access. it can.

(Fourth Embodiment) In the fourth embodiment, the function of the flag information explained in the third embodiment is added to the memory device shown in FIG.

FIG. 6 is a block diagram of a memory device according to the fourth embodiment of the present invention.

In FIG. 6, 120 is a first address bus, 122 is a second address bus, 130 is a first lower bit line, 132 is a second lower bit line, and 140 is a first lower bit line.
Upper bit line, 142 is the second upper bit line, 16
0, 162, 164 and 166 are selection signal lines for transferring selection signals, 180, 182, 184 and 186 are read signal lines for transferring read signals, 190 is a first data bus, 192 is a second data bus, 194 is an arithmetic circuit, 196 is a register, 200, 202, 204 and 206 are data memories, 250, 252, 254 and 256 are multiplexers as selection means, 280 and 2
82, 284 and 286 are write signal lines for transferring write signals, 290 is a third data bus, 410 is an address generating circuit as an address generating means, 470 is a control signal line for transferring a first read control signal, 472. Is the second
Control signal line 475 for transferring a read control signal of 475, a control signal line 475 for transferring a first write control signal, a control signal line 477 for transferring a second write control signal, 478
Is a first flag, 479 is a second flag, and 481 is a control circuit as control means. The first flag 478 and the second flag 479 form a flag holding unit. Further, the data memory 200 and the multiplexer 250 form one memory bank, the data memory 202 and the multiplexer 252 form one memory bank, and the two memory banks form a first memory bank group. There is. The data memory 204 and the multiplexer 254 form one memory bank, the data memory 206 and the multiplexer 256 form one memory bank, and the two memory banks form a second memory bank group.

The data memories 200, 202, 204 and 206 each have a storage capacity of 1k (= 2 ¹⁰ = 1024) words. Since the memory device according to this embodiment holds four data memories, the total storage capacity is 4k (= 4 × 2 ¹⁰ = 2 ¹² = 4096) words. Therefore, the address data indicating the storage area is 12
The data memory 200 has an address x'0.
00 'to address x'3FF' are assigned,
Address x'400 'to address x'7FF' are assigned to the data memory 202, and the data memory 2
04 has address x'800 'to address x'BF
Addresses up to F'are assigned, and addresses x'C00 'through x'FFF' are assigned to the data memory 206.

Address generation circuit 410 outputs a 12-bit address signal to first address bus 120 and second address bus 122. The upper 2 bits of the 12 bits are used to select the data memory, and the lower 10 bits are used to indicate the address in the selected data memory. The first lower bit line 130 and the second lower bit line 132 are connected to the multiplexer 25.
0, 252, 254 and 256. The first upper bit line 140 and the second upper bit line 142 are connected to the control circuit 481.

The first flag 478 holds flag information about the first memory bank group, and the second flag 479 holds flag information about the second memory bank group. The first flag 478 and the second flag 479 are connected to the control circuit 481.

When the first read control signal is input through the control signal line 470 and the first write control signal is not input through the control signal line 475, the control circuit 481 outputs from the first upper bit line 140. A signal is input, and a read signal and a selection signal are output according to Table 1 (a) based on the value. When the second read control signal is input through the control signal line 472 and the second write control signal is not input through the control signal line 477, a signal is input from the second upper bit line 142 and its value is set. Based on Table 1, the read signal and the selection signal are output according to Table 1.

When the first read control signal is not input and the first write control signal is input, a signal is input from the first upper bit line 140, and based on the value, Table 3 ( The write signal and the selection signal are output according to a). When the second read control signal is not input and the second write control signal is input, a signal is input from the second upper bit line 142, and based on the value, Table 3 (b)
The write signal and the selection signal are output in accordance with.

Further, when both the first read control signal and the first write control signal are input, the signal is input from the first upper bit line 140 and the value of this signal is b'00 'or When b'01 ', the first flag 47
The flag information regarding the first memory bank group is input from 8 and the read signal, the write signal, and the selection signal are output according to Table 4 (a). When the value of the signal input from the first higher-order bit line 140 is b'10 'or b'11', the flag information about the second memory bank group is input from the second flag 479, and Table 4 (b) According to the lead signal,
It outputs a write signal and a selection signal.

When both the second read control signal and the second write control signal are input, the signal is input from the second upper bit line 142 and the value of this signal is b '.
When 00 'or b'01', the flag information regarding the first memory bank group is input from the first flag 478,
The read signal, the write signal, and the selection signal are output according to Table 5 (a). When the value of the signal input from the second upper bit line 142 is b'10 'or b'11', the second
The flag information about the second memory bank group is input from the flag 479 of FIG. 4 and the read signal, the write signal, and the selection signal are output according to Table 5 (b).

[0112]

[Table 3]

[0113]

[Table 4]

[0114]

[Table 5]

At this time, each multiplexer inputs the signal from the first lower bit line 130 when the selection signal input from the control circuit 481 is "0", and outputs it to the connected data memory, When the selection signal input from the control circuit 481 is “1”, the second lower bit line 132
The signal is input from and output to the connected data memory.

When the read signal input from the control circuit 481 is "1", each data memory inputs the signal of the lower 10 bits of the address signal via the connected multiplexer, and outputs the address indicated by the signal. Data is read and output to the first data bus 190 or the second data bus 192. When the selection signal input from the control circuit 481 is "0", the data is output to the first data bus 190, and the selection signal input from the control circuit 481 is "0".
When it is 1 ", the data is output to the second data bus 192.

When the write signal input from the control circuit 481 is "1", data is input from the third data bus 290 and the lower 10 bits of the address signal input via the connected multiplexer. The input data is written to the address indicated by the signal.

The arithmetic circuit 194 is connected to the first data bus 19
Data is input from 0 and the second data bus 192 to perform an operation. The register 196 temporarily holds the data of the calculation result output by the calculation circuit 194 and outputs it to the third data bus 290.

The operation of the memory device configured as described above will be described. Here, the case where the filter calculation process as shown in the following equation is performed is taken as an example.

A ′ (n) = A (n−1) + α × B (n) (n = 1,
2, 3, ...) (1) A ′ (n), A (n) and B (n) are array data, α
Is a constant coefficient. FIG. 7A shows the contents of the data memory before execution of the calculation. The array data A (n) is already stored in the data memory 200, and the array data B (n) is already stored in the data memory 204. Further, the constant coefficient α is assumed to be held by a register inside the arithmetic circuit 194.

When n = 1, the equation (1) becomes the following equation. A '(1) = A (0) + α × B (1) (2)

At this time, the following operation is performed.
Data A (0) is read from the address x'000 'and output to the first data bus 190. The data B (1) is read from the address x'801 'and output to the second data bus 192. The arithmetic circuit 194 uses the data A (0) input from the first data bus 190, the data B (1) input from the second data bus 192, and the constant coefficient α held in the internal register to obtain the equation (2). The calculation result A ′ (1) is stored in the register 1
Output to 96.

When n = 2, the equation (1) becomes the following equation. A ′ (2) = A (1) + α × B (2) (3)

At this time, the following operation is performed.
The data A (1) is read from the address x'001 'and output to the first data bus 190. The data B (2) is read from the address x'802 'and output to the second data bus 192. In addition, the register 196
Data A '(1) held by the third data bus 290
Is written to the address x'401 'via. The arithmetic circuit 194 uses the data A (1) input from the first data bus 190, the data B (2) input from the second data bus 192, and the constant coefficient α held in the internal register to obtain the equation (2). Is calculated and the calculation result A '(2)
Is output to the register 196.

The operation in the case of performing the calculation of equation (3) will be described in more detail.

In the memory device according to this embodiment, the address x'001 'is the address b'of the data memory 200.
Address x'80 for 0000000001 '
2'is the address b'000000 of the data memory 204
At the time of 0010 ', the address x'401' corresponds to the address b'0000000001 'of the data memory 202. That is, the address in which the data A (1) is stored and the address in which the data A ′ (1) is written have a common lower 10 bits indicating the address inside the data memory.

First, "0" is set as the flag information in the first flag 478.

Next, the address generation circuit 410 outputs x'001 'as an address signal to the first address bus 120.
X'802 'is output as an address signal to the second address bus 122.

At this time, since the signal output to the first upper bit line 140 is the upper 2 bits of the address signal output to the first address bus 120, b'00 '.
Since the signal output to the first lower bit line 130 is the lower 10 bits of the address signal output to the first address bus 120, b'00000000.
01 '. In addition, the signal output to the second upper bit line 142 is the upper 2 bits of the address signal output to the second address bus 122, so that it becomes b′10 ′ and the second lower bit line 130. The output signal is
Since it is the lower 10 bits of the address signal output to the second address bus 122, b'00000001
It becomes 0 '.

At the same time, an instruction decoding means (not shown in FIG. 6) controls the control circuit 481 to control the first read control signal through the control signal line 470 and the second read control signal through the control signal line 472. The first write control signal is input through the signal line 475. The second write control signal is not input.

Since the first read control signal and the first write control signal are both input to the control circuit 481,
A signal is input from the first upper bit line 140, and since this signal is b'00 ', the flag information regarding the first memory bank group is input from the first flag 478. Since this flag information is "0", "1" is output to the read signal line 180 and the write signal line 282 and "0" is output to the read signal line 182 and the write signal line 280 according to Table 4 (a), and the selection signal is output. Output "0" on lines 160 and 162.

Further, since the second read control signal is input and the second write control signal is not input,
A signal is input from the second higher-order bit line 142, and since this signal is b'10 ', "1" is output to the read signal line 184 and "1" to the selection signal line 164 according to Table 1 (b).
Is output.

The data memory 200 has the read signal line 18
Since the read signal “1” is input through 0, the lower 10 bits of the address signal is input through the multiplexer 250. Since the selection signal “0” is input through the selection signal line 160, the multiplexer 250 selects the first lower bit line 130, inputs the signal, and outputs the signal to the data memory 200. Data memory 2 to which this signal, namely b'00000001 'is input
00 reads the data stored at the address b'0000000001 ', and since the selection signal "0" is input through the selection signal line 160, selects the first data bus 190 and outputs this data.

The data memory 202 has the write signal line 28.
Since the write signal "1" is input through 2, the lower 10 bits of the address signal is input through the multiplexer 252. Since the selection signal “0” is input through the selection signal line 162, the multiplexer 252 selects the first lower bit line 130, inputs the signal, and outputs the signal to the data memory 202. Data memory 2 to which this signal, namely b'00000001 'is input
02 inputs data from the third data bus and writes this data to the address b'0000000001 '.

The data memory 204 has the read signal line 18
Since the read signal “1” is input through 4, the lower 10 bits of the address signal are input through the multiplexer 254. Since the selection signal “1” is input through the selection signal line 164, the multiplexer 254 selects the second lower bit line 132, inputs the signal, and outputs the signal to the data memory 204. Data memory 2 to which this signal, that is, b'00000010 'is input
Reference numeral 04 reads the data stored at the address b'00000010 '. Since the selection signal "1" is input through the selection signal line 164, the second data bus 192 selects the second data bus 192 and outputs this data.

That is, the data A (1) at the address x'001 'is transferred to the first data bus 190 at the address x'8.
The data B (2) of 02 'is supplied to the second data bus 192,
Each is output and at the same time, the third data bus 29
Data A '(1) input from 0 is address x'40
It is stored in 1 '.

The arithmetic circuit 194 is connected to the first data bus 19
Data A (1) input from 0, second data bus 19
The data B (2) input from 2 and the constant coefficient α held in the internal register are used to perform the operation of Expression (3), and the operation result A ′ (2) is output to the register 196.

After n = 3, the same calculation as in the case of n = 2 is performed. FIG. 7B shows the contents of the data memory after execution of the calculation. Array data A'which is the calculation result
(N) is stored in the data memory 202.

FIG. 8 is a timing chart at the time of executing the filter calculation process as shown in the equation (1) in the memory device according to the fourth embodiment of the present invention. The operation of reading the array data A (n-1) and B (n) from the memory and the operation of writing the previous calculation result A '(n-1) to the memory are realized in one step.

As described above, according to the memory device of the fourth embodiment of the present invention, the reading of two data and the writing of one data are performed in one step memory by the addressing means of two systems. It can be executed by access.

In the first, second and fourth embodiments, the memory device in which the number of data memories is four has been described. However, the present invention is not limited to this, and the number of bits of address data can be changed. By appropriately setting, a memory device having an arbitrary number of data memories can be realized.

Further, the storage capacity of the data memory is not limited to 1 k word, and the storage capacities of the data memories do not have to be all equal, and the data memories may have different storage capacities.

[0143]

As described above, according to the memory device of the first aspect of the invention and the memory access method of the third aspect of the invention, one data read and one data write are performed by one address. Since it can be executed by designation, the number of address buses can be reduced, and the amount of hardware and power consumption can be suppressed. Further, reading of one data and writing of one data can be executed in one step, so that the processing time required for digital signal processing can be significantly shortened.

A memory device and a contract according to the invention of claim 2
According to the memory access method of the invention of claim 4 , it is possible to read two pieces of data and write one piece of data in one step, so that it is possible to greatly reduce the processing time required for digital signal processing. it can. In addition, since multiple memory banks are used, optimal memory placement can be realized for various applications. Moreover, even if the number of memory banks is increased, only two address buses and three data buses are required. Since it is sufficient, the versatility of the DSP can be improved by using the present invention without increasing the amount of hardware and power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a memory device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a memory device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a method of setting flag information.

FIG. 6 is a configuration diagram of a memory device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing the contents of a data memory of a memory device according to a fourth embodiment of the present invention, (a) before execution of arithmetic processing and (b) after execution of arithmetic processing.

FIG. 8 is a timing chart during execution of arithmetic processing in the memory device according to the fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional memory device.

FIG. 10 is a configuration diagram of a conventional memory device.

[Explanation of symbols]

100, 102, 104, 106 data memory 110 address generation circuit 120 First address bus 122 Second address bus 130 First lower bit line 132 second lower bit line 140 First high-order bit line 142 Second upper bit line 150, 152, 154, 156 multiplexer 160, 162, 164, 166 Selection signal line 170, 172 control signal line 180, 182, 184, 186 Lead signal line 181 control circuit 190 First data bus 192 Second data bus 194 arithmetic circuit 196 register 200, 202, 204, 206 data memory 210 address generation circuit 220 Third Address Bus 230 Third Lower Bit Line 240 Third upper bit line 250, 252, 254, 256 multiplexers 270, 272 Control signal line 280, 282, 284, 286 write signal line 281 Control circuit 290 Third data bus 300 First data memory 302 Second data memory 310 address generation circuit 320 address bus 330 Lower bit line 340 upper bit line 370, 372 Control signal line 378 flag 381 control circuit 380,382 Lead signal line 385, 387 write signal line 390 First data bus 392 Second data bus 410 address generation circuit 470, 472, 475, 477 Control signal line 478 and 479 flags 481 control circuit 500 data memory 510 address generation circuit 520 address bus 530 data bus 600,602 data memory 610 Address generation circuit 620, 622 address bus 630 and 634 data buses 634 arithmetic circuit 640 Data transfer data bus

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-5-100948 (JP, A) JP-A-2-83618 (JP, A) JP-A-5-313884 (JP, A) JP-A-1- 311319 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16 G06F 9/30-9/34

Claims (4)

(57) [Claims] 1. An address generating means for outputting an address signal for instructing an address of data, an address bus for transferring an address signal output by the address generating means, and a plurality of data connected to the address bus. A first data memory and a second data memory in which is stored; and a first data bus that is connected to the first data memory and that transfers data input to and output from the first data memory, A second data bus that is connected to the second data memory and transfers the data that the second data memory inputs and outputs; and a second data memory that outputs data from the first data memory Whether to input data to the first data memory or to output data from the second data memory A flag holding means for holding the flag information indicating output, the flag holding unit is connected to the first data memory and the second data memory, the data by the read control signal input from (i) outside When the reading is instructed and the writing control signal inputted from the outside is instructed to write the data, based on the flag information inputted from the flag holding means, the first data memory and the second data While outputting a read signal instructing to read the data to the data memory that outputs the data among the memories, outputting a write signal instructing to write the data to the data memory that inputs the data , (ii) Read data by read control signal
Data is instructed to be output and is written by the write control signal.
If it is not instructed to write the
According to some bits of the signal, the first and second data
Select one of the
A read signal is output, and (iii) the read control signal is output.
The above-mentioned writing without being instructed to read the data
If data writing is instructed by the control signal,
Wherein the first and in accordance with some bits of the address signal
Select one of the second data memories and select
Control means for outputting the write signal to a data memory, and the first data memory, when a read signal is input from the control means, reads data from an address indicated by an address signal input from the address bus. Is read out and output to the first data bus, and a write signal is input from the control means,
It has a function of inputting data from the first data bus and writing to an address indicated by an address signal input from the address bus, and the second data memory receives a read signal from the control means. In this case, when the data is read from the address indicated by the address signal input from the address bus and output to the second data bus, and the write signal is input from the control means,
A memory device having a function of inputting data from the second data bus and writing to an address indicated by an address signal input from the address bus. 2. An address generating means for outputting an address signal indicating a data address, a first address bus and a second address bus for transferring the address signal output by the address generating means, and the first address bus. A plurality of memory bank groups each including a plurality of memory banks respectively connected to the address bus and the second address bus, and the plurality of memory banks forming the plurality of memory bank groups are respectively connected to each memory bank. A first data bus and a second data bus for transferring output data, and a third data bus connected to the plurality of memory banks forming the plurality of memory bank groups, respectively, for transferring data input to the respective memory banks. Data bus and a first memory bank that outputs data among the plurality of memory banks that make up each memory bank group. Flag holding means for holding and outputting flag information for instructing a memory and a second memory bank for inputting data, one for each memory bank group, the first address bus, the second address bus, Connected to a flag holding means and a plurality of memory banks,
(i) When data reading is instructed by a first read control signal externally input and data writing is instructed by a first write control signal externally input, the first address One memory bank group is selected from the plurality of memory bank groups based on some bits of the address signal input from the bus, and flag information for the selected memory bank group is input from the flag holding means and input. Selecting a first memory bank and a second memory bank from a plurality of memory banks forming a memory bank group selected based on the flag information, and instructing to select the first address bus. 1 selection signal, a second selection signal instructing to select the first data bus, and a read instructing to read data Outputting a signal to the first memory bank and outputting to the second memory bank a first selection signal instructing to select the first address bus and a write signal instructing to write data, (ii) The second read control signal input from the outside instructs the reading of data and the second input from the outside.
When data writing is instructed by the write control signal of, one memory bank group is selected from the plurality of memory bank groups based on some bits of the address signal input from the second address bus. The flag information for the memory bank group selected from the flag holding means is input, and the first memory bank and the second memory bank are selected from a plurality of memory banks forming the memory bank group selected based on the input flag information. A first selection signal instructing to select a memory bank and selecting the second address bus, a second selection signal instructing to select the second data bus, and an instruction to read data. A first select signal and a first select signal for outputting a read signal to the first memory bank and instructing to select the second address bus. And a control means for outputting a write signal for instructing the writing of data to the second memory bank, wherein each of the plurality of memory banks forming the plurality of memory bank groups is input from the control means. Either the first address bus or the second address bus is selected in accordance with the first selection signal, the remaining bits of the address signal are input from the selected address bus, and the remaining bits are output. (I) When a read signal is input from the control unit, the remaining bits of the address signal output from the selection unit are input and the remaining bits are stored. The data is read from the address shown, and the first data bus or the second data is read according to the second selection signal input from the control means. Select one of the two, output the read data to the selected data bus, and (ii) input the data from the third data bus when a write signal is input from the control means. A memory device comprising: a data memory for inputting the remaining bits of the address signal output from the selecting means and writing the data to an address indicated by the remaining bits. 3. An address generating step of outputting an address signal indicating an address of data, an address signal transferring step of transferring the address signal via an address bus, data output from a first data memory and the Data input to the first data memory is transferred via the first data bus, and data output from the second data memory and data input to the second data memory are transferred to the second data bus. A data transfer step of transferring via the first data memory and outputting data from the first data memory and inputting data to the second data memory, or inputting data to the first data memory and A flag setting step of setting flag information indicating whether to output data from the second data memory, and (i) a read control signal from the outside. If the signal indicates reading of data and the write control signal from the outside indicates writing of data, one of the first data memory and the second data memory is selected based on the flag information. One of the first data memory and the second data memory that receives data is selected while the data memory that outputs the data is selected and a read signal that instructs reading of the data from the data memory is output. Select a data memory and output a write signal instructing the writing of data to the data memory, and (ii) reading the data.
Control signal to read data, and
Do is instructed to write data by the write control signal
If yes, according to some bits of the address signal
Select one of the first and second data memories
Output the read signal to the selected data memory,
(iii) Read data by the read control signal.
Data not instructed and by the write control signal
When instructed to write, one of the address signals
Of the first and second data memories according to the partial bits
Select one and write to the selected data memory.
A control step of outputting a signal , (i) when the read signal is output, the read signal reads data from an address indicated by an address signal from the address bus of the data memory instructing reading of data, and When the data memory is the first data memory, the read data is output to the first data bus, and when the data memory is the second data memory, the read data is read to the second data bus. Outputting data, and (ii) outputting the data from the first data bus when the write signal is output and the data memory instructing the write of the data by the write signal is the first data memory. When the data memory is the second data memory, the data is input from the second data bus, Memory access method is characterized in that a data output step of writing data inputted to the address indicated by the address signal input from the serial address bus. 4. An address generating step of outputting an address signal instructing an address of data, an address signal transferring step of transferring the address signal via a first address bus and a second address bus, and a plurality of memories. Data output from each of the plurality of memory banks forming the bank group is transferred via a first data bus and a second data bus, and is transferred to each of the plurality of memory banks forming the plurality of memory bank groups. A data transfer step of transferring input data via the third data bus, a first memory bank for outputting data and a second memory bank for inputting data among a plurality of memory banks forming each memory bank group. A flag setting step of setting flag information indicating a memory bank for each memory bank group one by one; Of the address signal from the first address bus when the first read control signal from the outside indicates the data write and the first write control signal from the outside instructs the data write. One memory bank group is selected from the plurality of memory bank groups based on the above, and the first memory bank group is selected from the plurality of memory banks forming the memory bank group selected based on the flag information for the selected memory bank group. A read signal for selecting a memory bank and a second memory bank and for instructing reading of data from the first memory bank, a first select signal for instructing to select the first address bus, and the first and second select signals. Outputting a second selection signal instructing to select one data bus and instructing writing of data to the second memory bank. A write signal to be shown and a first selection signal instructing to select the first address bus, and (ii) a second read control signal from the outside instructing data read If the second write control signal from the memory controller instructs to write data, one memory bank is selected from the plurality of memory bank groups based on some bits of the address signal from the second address bus. Selecting a group, selecting the first memory bank and the second memory bank from a plurality of memory banks forming the memory bank group selected based on the flag information for the selected memory bank group, and selecting the first memory bank. Signal for instructing reading of data from the memory bank, a first selection signal for instructing to select the second address bus, and the second signal. A second select signal for instructing to select the second data bus and a write signal for instructing to write data to the second memory bank and a second for instructing to select the second address bus. A control step of outputting one selection signal, and (i) selecting one of the first address bus and the second address bus according to the first selection signal when the read signal is output, The remaining bits of the address signal are input from the selected address bus, the data is read from the address indicated by the remaining bits of the first memory bank, and the first data bus or the first data bus is read according to the second selection signal. When one of the second data buses is selected and the read data is output to the selected data bus, (ii) the write signal is output. Then, either the first address bus or the second address bus is selected according to the first selection signal, and the remaining bits of the address signal are input from the selected address bus, and the third bit is input. A data input / output step of inputting data from the data bus and writing the data to an address indicated by the remaining bit of the second memory bank.