JP3428200B2 - Defective cell repair analysis apparatus and repair analysis method - Google Patents

Description

Detailed Description of the Invention

[0001]

[Industrial application] When a memory device having a large number of spare cells formed on a wafer and having a plurality of spare cells corresponding to X and Y lines is measured by an IC tester, defective cells are found and spare cells are used. The present invention relates to a defective cell repair analysis device that obtains information for repairing.

[0002]

2. Description of the Related Art In recent years, as memory devices have become larger in capacity, the decrease in yield due to defective cells has become a major problem. In order to improve the yield due to defective cells, spare cells provided in advance in the device and defective cells are required. Various methods for replacing cells and repairing defective cells have been considered.

Next, FIG. 9 shows the configuration of an IC test apparatus according to the prior art. In FIG. 9, 1 is a sample to be measured, 2 is a measuring portion, and 3
Is a fail memory unit, 4 is a measurement information processing unit, and 6 is a measurement result. In FIG. 9, the measuring unit 2, the fail memory unit 3, and the measurement information processing unit 4 constitute an IC test apparatus. Conventionally, when performing defective cell repair, defective cell repair analysis for determining a replacement position of a defective cell and a spare cell is performed in a fail memory unit of an IC test apparatus.

Next, FIG. 10 shows a state of the fail memory section 3 in which a defective cell is taken in by measuring a memory IC which is a sample to be measured with an IC test apparatus. In FIG. 10, 11 is a fail memory, 12 is a Y line fail flag, 13 is an X line fail flag, 14 is a Y line mask flag, 15
Is an X line mask flag, 16 is an X side spare cell, and 17 is a Y side spare cell. In FIG. 10, the fail memory 11 is a memory that holds the defective cell cell plate information of the sample to be measured, and the defective cell cell plate information is indicated by “*”.

In FIG. 10, first, when there is one or more defective cell information on one address line of each of X and Y by the defective cell information fetched in the fail memory 11, the XY line fail flag 12 ... The line fail flag is set at the same address of 13.

Next, using the information of the X / Y line fail flags 12 and 13, in order to replace the defective cell with the spare cell, the X / Y line is sequentially set to the address where the line fail flag is set from the upper address. The mask flags 14 and 15 are set for the number of spare cells.

By setting the X and Y line mask flags 14 and 15, the fail information of the defective cell existing on the fail memory of the set address line is masked and is not recognized as a fail. In this way, the fail count of the fail memory 11 is performed with the mask flag set, and when the fail count number is "0", it is judged that the measured sample can be rescued. When the fail count number is other than “0”, it is determined that the rescue is impossible.

[0008]

However, in the configuration of FIG. 9, in the case where, for example, the defective cell taken into the fail memory section 3 is in the state shown in FIG. 10, the X side spare cell 16 is actually used.
Also, there is a problem that the Y-side spare cell 17 makes it impossible to make a relief although it can make a relief, and the yield does not increase. In addition, it cannot be determined whether or not repair is possible without analysis, and even if repair is not possible, analysis is performed, resulting in a problem that throughput is lowered. Further, when there is only one defective cell, two spare cells are used, such as the X side and the Y side, even though one spare cell can repair the spare cell. There is a problem that cell replacement is necessary.

On the other hand, as a semiconductor memory as a sample to be measured, as shown in FIGS. 11A to 11C, there is a sample having a complicated structure in which a plurality of spare cell groups and a plurality of cell plates are combined. 11A to 11C show one analysis unit of the semiconductor memory by the arrangement of the cell plate which is a group of memory cells and the spare cells.

In FIG. 11A, memory cells are divided into two groups, a cell plate 31 and a cell plate 32. Here, the defective cell existing in the cell plate 31 can be replaced and repaired by the X side spare cell 42A or the Y side spare cell 41A. Further, the defective cell existing in the cell plate 32 can be replaced and repaired by the X side spare cell 42B or the Y side spare cell 41A. here,
If the cell plate 31 and the cell plate 32 have the same Y address, the Y side spare cell 41A can be replaced and repaired by one cell.

Similarly, in FIG. 11B, the cell plate 3
The defective cell existing in No. 1 is the X side spare cell 42C or Y
In the side spare cell 41B, the defective cell existing in the cell plate 32 can be replaced and repaired by the X side spare cell 42C or the Y spare cell 41C.

In FIG. 11C, the defective cell existing in the cell plate 31 is the X side spare cell 42D or the Y side spare cell 41D, and the defective cell existing in the cell plate 32 is X.
Side spare cell 42E or Y side spare cell 41D, the defective cell existing in the cell plate 33 is the X side spare cell 42D.
Alternatively, in the Y-side spare cell 41E, defective cells existing in the cell plate 34 can be replaced and repaired by the X-side spare cell 42E or the Y-side spare cell 41E, respectively.

Further, the X-side spare cell 42D can be replaced and repaired by a single cell when the cell plate 31 and the cell plate 33 have the same X address, and the X-side spare cell 42E can be replaced by the cell plate 32 and the cell plate. In the case of the same X address of 34, the Y side spare cell 41D has the same Y address of the cell plate 31 and the cell plate 32, and the Y side spare cell 41E has the same Y address of the cell plate 33 and the cell plate 34. In addition, it is possible to replace and repair each one.

However, in the configuration of FIG. 9, A to C of FIG.
There is a problem in that it is difficult to analyze a sample having a complicated configuration in which a plurality of spare cell groups and a plurality of cell plates are combined as shown in FIG.

The present invention analyzes a replacement of a defective cell of a sample to be measured with a spare cell on the basis of the measurement result of the sample to be measured obtained by an IC test apparatus, and repairs the defective cell by a defective cell repair analysis. The purpose is to provide a device.

[0016]

To achieve this object, the present invention provides a plurality of redundant spare cells corresponding to X and Y address lines, comprising at least one cell plate consisting of a plurality of memory cells. The measuring section 2 for measuring the sample 1 to be measured, the fail memory section 3 for receiving the output of the measuring section 2 and the output of the fail memory section 3 and the measuring section 2 for inputting the rescue analysis result as the measurement result 6 In the defective cell repair analysis apparatus including the measurement information processing unit 4 for outputting to the secondary fail memory unit 5a that holds the defective cell information of the fail memory unit 3 and the address of the spare cell, the secondary fail memory unit 5a is generated. The output of the repair address generating section 5c and the output of the secondary fail memory section 5a, which are input to the memory cell, are input to determine whether the DUT 1 can be repaired by the spare cell. Repair analysis result determination unit 5b to force
The defective cell repair analysis unit 5 including the repair analysis determination unit 5b and the control unit 5d for controlling the repair address generation unit 5c is provided, and the secondary fail memory unit 5a is represented by a two-dimensional matrix image of X and Y. Secondary fail memory 2
1 and the actual fail memory address registers 24 and 25 for holding the address of the defective cell information acquired in the fail memory unit 3 as the actual address of the acquired defective cell information in the secondary fail memory 21 and the secondary fail memory 21. Fail cell plate register 2 that holds cell plate information of defective cell information acquired for each address
6.27, spare cell mask registers 28 and 29 for holding masked information by replacing a defective cell address with a spare cell during analysis, and a fail for holding the number of defective cells for each address of the secondary fail memory 21. Counter 2a
The X and Y address widths of the secondary fail memory 21 having 2b are determined from the arrangement of the spare cells of the sample to be measured 1 by the number of X side spare cells for each cell plate and the Y side spare cell for each cell plate. The number of cells is y, the number of spare cell groups on the X side is a, the number of spare cell groups on the Y side is b, the number of cell plates corresponding to the X side spare cells is α, and the number of cell plates corresponding to the Y side spare cells is β. x (βby + a), Y
Side address width = y (αax + b). As for the operation, the defective cell repair analysis unit 5 acquires necessary defective cell information from the fail memory unit 3 of the IC test apparatus in the secondary fail memory unit 5a, and based on the acquired defective cell information in the secondary fail memory unit 5a. , The repair analysis information of the fail cell plate number of X and Y, the spare cell mask number, and the fail count number is created, and the first combination of the spare cell rescue addresses is generated from the rescue address generating unit 5c.
In the mask side processing, the relief address generated by the relief address generation unit 5c is calculated by the relief address generation unit 5c from the total number of fail addresses written in the secondary fail memory unit 5a for the number of spare cells. The spare cell mask information is created in the spare cell mask register 28 on the mask side by using the combination of the determined relief addresses on the mask side, and the mask side address of the secondary fail memory unit 5a is created based on the created information in the spare cell mask register 28. The defective cell cell plate information in each defective cell cell plate register 26 is masked, and the repair analysis result determination unit 5b determines whether the defective cell of the semiconductor memory can be repaired by the repair address generated from the repair address generation unit 5c.
The secondary fail memory unit 5a includes a secondary fail memory 21 represented by a two-dimensional matrix image of X and Y.
And the actual fail memory address registers 24 and 25 for holding the address of the defective cell information acquired in the fail memory unit 3 as the actual address of the defective cell information acquired in the secondary fail memory 21, and each of the secondary fail memory 21. Fail cell plate register 26 that holds cell plate information of defective cell information acquired for each address
27, spare cell mask registers 28 and 29 for holding masked information by replacing a defective cell address with a spare cell during analysis, and a fail counter for holding the number of defective cells for each address of the secondary fail memory 21. 2a
2b, the X and Y address widths of the secondary fail memory 21 are determined by arranging the number of X side spare cells for each cell plate based on the arrangement of the spare cells of the DUT 1 and the number of Y side spare cells for each cell plate. Where y is the number of spare cell groups on the X side, b is the number of spare cell groups on the Y side, α is the number of cell plates corresponding to the X side spare cells, and β is the number of cell plates corresponding to the Y side spare cells, the X side address width = x (Βby + a), Y side address width = y (αax + b), and the residual defective cell cell plate information generated from the secondary fail memory 5a masked by the masking process is taken into the spare cell mask register 29 on the analyzing side. , The information of the spare cell mask register 29 fetched on the analysis side is masked by the cell plate information corresponding to the spare cell on the analysis side, and all spare cell mask information on the analysis side is masked. If did not remain, it is determined that can be relieved, if possible relief, spare cells mask register 2
The information of the real fail memory address registers 24 and 25 corresponding to the mask information of 8.29 is output as the spare cell relief address, the relief analysis is completed, and if the relief is impossible, the relief address of the next combination is set. Generate and analyze until it can be repaired. Further, according to the present invention, the secondary fail memory unit 5A is initialized, the defective cell search of the fail memory unit 3 is started, and the fail memory unit 3 is started.
If a defective cell is found above, the defective cell search is stopped, the secondary fail memory section 5A is searched for the actual fail memory address register, and the secondary fail memory 21 of the secondary fail memory section 5A is previously marked with X. Or Y
Search whether the information of the same address of is set,
When there is no defective cell information at the same X or Y address of the secondary fail memory unit 21, the secondary fail memory unit 2
If the defective cell number is set to an address near the lower address of 1 and the defective cell information is not set, and the defective cell information is previously set to the same address of either X or Y, that address is set. If the defective cell information is newly set on the line extension and the secondary fail memory section 21 is searched and the address width on the X side or the Y side of the secondary fail memory 21 is exceeded, the measured sample 1 It is judged that the defective cell repair of
If it does not exceed the number of spare cells of Y on the same X address in the cell plate corresponding to the spare cells of Y, it is judged whether or not there is a defective cell, and at the same time the spare of X is spared. It is determined whether or not there is a line fail in which the number of defective cells exceeds the number of X spare cells on the same Y address in the cell plate corresponding to the cell, and the defective cell acquired in the secondary fail memory 21 becomes the line fail. In the case of a defective cell not corresponding to, the cell plate number of the defective cell is written in the position indicated by the address of the set secondary fail memory 21, and the defective cell address information is written in the corresponding actual fail memory address register.
If the defective cell obtained by incrementing the XY fail counter and acquired in the secondary fail memory 21 is a defective cell corresponding to the line fail, is the determined number of X line failures exceeded the number of Y spare cells? , Or the number of Y line failures exceeds the number of X spare cells, and if so, a line failover occurs and it is determined that the defective cell of the measured sample cannot be relieved. If it is not over, the spare cell mask register corresponding to the address of the secondary fail memory 21 which has become the X or Y line fail,
The cell plate number of the defective cell is written and the X and Y line mask flags 14 corresponding to the X or Y address of the defective cell on the secondary fail memory 21.
A flag is set to 15, the process for one defective cell information found by the fail memory search is ended, the fail memory search is performed again, and if a defective cell is found, the same process is repeated. , A secondary fail memory 21 for ending the creation. Furthermore, when there are a plurality of spare cell groups, a combination is generated for each group, and the groups are also combined. At this time, the address of the secondary fail memory unit 5A determined to be replaced by the line fail is the target of the combination. Remove from

[0017]

Next, the configuration of the defective cell repair analysis apparatus according to the present invention is shown in FIG. Reference numeral 5 in FIG. 1 is a defective cell repair analysis unit, and the others are the same as in FIG. That is, FIG. 1 shows I of FIG.
This is a configuration in which a defective cell repair analysis unit 5 is added to the configuration of the C test device, and the output of the fail memory unit 3 is used as an input to operate asynchronously to perform processing.

In FIG. 1, the defective cell repair analysis section 5 judges whether the secondary fail memory section 5a holding the defective cell information of the fail memory section 3 and the DUT 1 can be repaired by the spare cell, and the judgment result Is provided to the measurement result 6, a repair analysis result determination unit 5b, a repair address generation unit 5c that generates an address of a spare cell for repair, and a control unit 5d that controls them.

Next, the configuration of the secondary fail memory section 5a is shown in FIGS. In FIG. 2A, the secondary fail memory unit 5a includes a secondary fail memory 21 represented by a two-dimensional matrix image of X and Y, real fail memory address registers 24 and 25 of X and Y, and fail cells. Plate registers 26 and 27, spare cell mask registers 28 and 29, and fail counters 2a and 2
b.

Next, the operation of the secondary fail memory unit 2a in the case of the measurement result shown in the fail memory unit 3 of FIG. 10 will be described with reference to FIGS. In FIG. 2A, the secondary fail memory 21 of the secondary fail memory unit 5a has
Of the defective cell information of the fail memory unit 0 of 0, only the portion necessary for analysis is acquired, and the defective cell information is indicated by "*".

At this time, if there is a plurality of cell plates as in the case of the structure of the sample 1 to be measured as shown in A of FIG. 11, it is recognized which of the cell plates 31 and 32 corresponds to the defective cell information. The cell plate number for doing this is added as acquisition information.

Real fail memory address register 24
25 stores the address of the defective cell information acquired in the fail memory unit 3 as the real address of the defective cell information acquired in the secondary fail memory 21. The fail cell plate registers 26 and 27 hold the cell plate information of the defective cell information acquired for each address in the secondary fail memory 21. In FIG. 2A, since there is only one cell plate, there is only “1”.

The spare cell mask registers 28 and 29 hold information masked by replacing the address of a defective cell with a spare cell during analysis. Fail counters 2a and 2b
Holds the number of defective cells for each address of the secondary fail memory 21.

X of the secondary fail memory 21 required for analysis
The address width of Y and Y depends on the arrangement of spare cells, and x
Is the number of X side spare cells for each cell plate, y is the number of Y side spare cells for each cell plate, a is the number of X side spare cell groups, b is the number of Y side spare cell groups, and α is the cell plate corresponding to the X side spare cells. If the number β is the cell plate number corresponding to the Y side spare cell, it is determined by the following relational expression. X side address width = x (βby + a) ... Equation 1 Y side address width = y (αax + b) ...... Equation 2

For example, in FIG. 10, the number of X side spare cells x for each group is 2 for the X side spare cells 16, and the number y of Y side spare cells is 2 for the Y side spare cells 17. Further, the number a of spare cell groups on the X side is 1 because there is only one group of spare cells on the X side, and the number b of spare cell groups on the side of Y is 1 because there is only one group.

The cell plate number α corresponding to the X side spare cell is 1 because the X side spare cell 16 corresponds to the fail memory 11 in a one-to-one manner, and the cell plate number β corresponding to the Y side spare cell corresponds to the Y side spare cell 17. It is 1 because there is a one-to-one correspondence. When the data for each condition is determined in this way, the calculation formula (1)
From (2), the X-side address width and the Y-side address width of the secondary fail memory 21 can be calculated to be 6 and 6, respectively. In FIG. 2, the X-side address width and the Y-side address width of the secondary fail memory 21 are shown as 5 for simplification.

In the case of a complicated device design, for example, in FIG. 11A, the number x of X side spare cells for each group is 2 for the X side spare cell 42A and 2 for the X side spare cell 42B, and Y side spare cell. The number y of the Y side spare cells 41A is three. Further, the number a of X side spare cell groups is 2, since the X side spare cells are divided into two groups of X spare cells 42A and 42B, and the number of Y side spare cell groups b is Y side spare cells 4
It is 1 because 1A has only one group.

The cell plate number α corresponding to the X side spare cell is 1 for the cell plate 31 and the cell plate 32 for the X side spare cell 42A and the X side spare cell 42B, respectively.
Since the pair corresponds to 1, the cell plate number β corresponding to the Y side spare cell is 1 in common for the cell plate 31 and the cell plate 32 corresponding to the Y side spare cell 41A.
It is 2 because it corresponds to pair 2. When the data for each condition is determined in this manner, the X-side address width and the Y-side address width of the secondary fail memory can be calculated as 16 and 15 from the calculation formulas (1) and (2). Similarly, in FIG. 11B, the X-side address width is determined to be 15, and the Y-side address width is determined to be 10,
In C of FIG. 11, the X-side address width is 20 and the Y-side address width is 20.

Next, as an example, the operation of creating the secondary fail memory 21 of FIG. 2A will be described with reference to the flowcharts of FIGS. 1 and 3. First, step 61 in FIG.
Then, the information of the actual fail memory address register, fail cell plate register, spare cell mask register, and fail counter of the secondary fail memory unit 5a of FIG. 1 is initialized.

Next, in step 62, the defective cell search of the fail memory unit 3 of FIG. 1 is started, and if a defective cell is found in the fail memory unit 3 in step 63, the defective cell search is stopped in step 65. Then, the cell plate number is set as the defective cell information found by the fail memory search in the secondary fail memory unit 5a, and the actual fail memory address register is searched.

Next, at step 69, it is searched whether or not the information of the same address of X or Y is set in the secondary fail memory 21 of the previous secondary fail memory section 5a, and X or Y of the secondary fail memory section 21 is searched. If there is no defective cell information at the same address of Y, the defective cell number is set at an address near the lower address of the secondary fail memory unit 21 and the defective cell information is not set at step 6p. If the defective cell information is previously set to the same address of either X or Y, the defective cell information is newly set on the extension of the address line in step 6r.

Here, in the previous stage of step 6a, that is, in step 6p or step 6r, the fail memory unit 3 is
When attempting to set the defective cell information from, the secondary fail memory unit 21 is searched in step 6a of FIG.
If the address width on the X side or the Y side of the secondary fail memory 21 is exceeded, it is determined in step 68 that the defective cell of the DUT 1 cannot be repaired, and the process is terminated.

If the X / Y address width of the secondary fail memory 21 is not exceeded, in step 6b of FIG. 3, in the defective cell information of the fail memory unit 3, the same data in the cell plate corresponding to the Y spare cell is identified. On the X address of
The number of spare cells is exceeded and it is determined whether or not there is a line fail, and at the same time, the number of defective cells exceeds the number of spare cells X on the same Y address in the cell plate corresponding to the spare cells of X. It is determined whether or not there is an existing line fail.

When the defective cell acquired in the secondary fail memory 21 is a defective cell which does not correspond to the line fail, it is indicated by the address of the secondary fail memory 21 set in steps 69.6p and 6r in step 6e of FIG. The cell plate number of the defective cell is written in the position, the defective cell address information is written in the corresponding real fail memory address register, and the XY fail counter is incremented.

On the other hand, when the defective cell acquired in the secondary fail memory 21 is a defective cell corresponding to the line fail,
In step 6c of FIG. 3, whether the number of X line failures determined in step 6b does not exceed the number of Y spare cells, and whether the number of Y line failures exceeds the number of X spare cells. Judge each. If it exceeds the threshold, line failover occurs, it is determined that the defective cell of the measured sample cannot be repaired, and the process proceeds to step 68.

In the case of no line failover, FIG.
In step 6d of step 6, the cell plate number of the defective cell is written in the spare cell mask register corresponding to the address of the secondary fail memory 21 that has become the X or Y line fail, and the defective cell on the secondary fail memory 21 is written. A flag is set in the X and Y line mask flags 14 and 15 of FIG. 10 corresponding to the X or Y address. As a result, even if there is defective cell information that has not been searched for at the set address on the fail memory, it is ignored and the secondary fail memory 21 is not set.

In this way, the processing for one piece of defective cell information found by the fail memory search is completed, and FIG.
Returning to step 62, the fail memory search is performed, and if a defective cell is found, the same processing is repeated. If no defective cell is found in step 63 of FIG. 3, the creation of the secondary fail memory 21 is terminated and the repair analysis is performed.

Next, the operation of the IC test apparatus of FIG. 1 will be described with reference to the flowchart of FIG. First, in step 51 of FIG. 4, the measuring unit 2 of the IC test apparatus measures the sample 1 to be measured under specified conditions, and stores defective cell information in the fail memory unit 3.
Write in. When all the defective cell information is written in the fail memory section 3, the IC tester instructs the defective cell repair analysis section 5 to start repair analysis in step 52. The above processing is performed on the IC test apparatus side.

Next, at step 53, the defective cell repair analysis section 5 obtains necessary defective cell information from the fail memory section 3 of the IC test apparatus as shown in FIG. 2A, for example, as a secondary fail memory section 5a. To get to. Then, step 54
Then, based on the defective cell information acquired in the secondary fail memory unit 5a, the repair analysis information of the fail cell plate number of X and Y, the spare cell mask number, and the fail count number is created.

Step 55 is a repair analysis process. First, the repair address generator 5c of FIG. 1 generates the first combination of spare cell repair addresses. As for the combination to be generated, the combination processing is performed with the mask having the smaller total number of combinations of replacement of the spare cells of either X or Y as the mask side. The other one is set as the analysis side. In the mask-side processing, the repair address generated by the repair address generation unit 5c is obtained by combining the number of spare cells from the total number of fail addresses written in the secondary fail memory unit 5a.

If there are a plurality of spare cell groups, a combination is generated for each group and the groups are combined. At this time, since the address of the secondary fail memory unit 5a, which has been determined to be replaced by the line fail, is fixed as the relief address, it is excluded from the combination target.

In order to increase the probability of a combination that can be repaired at an early stage, a combination of repair addresses is generated in the order of the number of defective cells in each address line of the secondary fail memory section 5a.

At step 56, the relief address generator 5c
The spare cell mask information is created in the spare cell mask register 28 on the mask side, as shown in FIG. When there are a plurality of cell plates, this information is created by adding the cell plate number corresponding to the determined spare cell group of the combination. In B of FIG. 2, the spare cell mask information is indicated by “◯”.

The information in the prepared spare cell mask register 28 is used to mask the defective cell cell plate information in each defective cell cell plate register 26 at the mask side address of the secondary fail memory section 5a. In FIG. 2B, masked defective cell cell plate information is indicated by diagonal lines. Then, the repair analysis result determination unit 5b of FIG. 1 determines whether the defective cell of the semiconductor memory can be repaired with the repair address generated from the repair address generation unit 5c.

At step 57, the defective cell repairable judgment is made on the analysis side of the secondary fail memory section 5a. Step 5
Residual defective cell cell plate information generated from the secondary fail memory 5a masked by the processing on the mask side of No. 6 is taken into the spare cell mask register 29 of FIG. 2B on the analysis side. In FIG. 2B, residual defective cell cell plate information is indicated by "●".

The information stored in the spare cell mask register 29 on the analysis side is masked by the cell plate information corresponding to the spare cell on the analysis side. At this time, if all the spare cell mask information on the analysis side does not remain, it can be determined that the repair is possible.

When the repair is possible, the information of the real fail memory address registers 24 and 25 corresponding to the mask information of the spare cell mask registers 28 and 29 of FIG. finish. If the repair is impossible, the process returns to step 55 of FIG. 4 to generate the next combination of repair addresses to determine whether the repair is possible. By repeating this, analysis is performed until repair becomes possible.

[0048]

Next, the operation of the embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 6 and 7. FIG. 5 shows the relationship between the arrangement of the semiconductor memory and the spare cells. The cell plates 71 and 72 of the semiconductor memory, the Y-side spare cell 73,
The state is shown in which defective cell information “*” is stored in the cell plates 71 and 72 by preliminarily measuring the semiconductor memory of the sample to be measured with the IC test device, which is provided with the X side spare cells 74 and 75. .

In FIG. 5, the X spare cell 74 is the cell plate 7
Only the defective cells in the range 1 can be replaced, and the X spare cells 75 can replace only the defective cells in the range of the cell plate 72. Further, the two Y spare cells 73 in FIG. 5 can be replaced with defective cells in the range of the cell plate 71 and the cell plate 72.

6 and 7 show the states of the secondary fail memory section at each stage, where 81 is the secondary fail memory, 82 and 83 are actual fail memory address registers, and 84 and 85 are Fail cell plate register, 86/87 are spare cell mask registers, 88/89
Is a fail counter, and 8a and 8b are combination generation orders.

Next, the operation of creating the secondary fail memory 81 will be described with reference to FIGS. 6 and 7. First, in order to create the basic information, the defective cell information stored in the fail memory unit 3 is searched and set in the secondary fail memory unit 5a of FIG. At this time, a search is performed for each cell plate and a repair analysis is performed. In FIG. 6, the address widths on the X side and the Y side of the secondary fail memory 81 are expressed by the formula 1
-Equation 2 is calculated as "6".

Next, the defective cell search set in the fail memory of the cell plate 71 of FIG. 5 is performed in the X address direction. In FIG. 5, the first defective cell (X: 4,
Y: 3) is found, the secondary fail memory 81 shown in FIG.
The information is set at the position [x: 0, y: 0] of. The information to be set is cell plate information (01) obtained by assigning a number to each cell plate and converting it into bit information according to the number.
At the same time, the real fail memory address register 82 of FIG.
The actual addresses (X: 4, Y: 3) of the defective cells are set in 83, and the setting of one piece of defective cell information is completed.

Again, the defective cell search of the cell plate 71 of FIG. 5 is performed. Next, a defective cell of (X: 4, Y: 6) is found and set in the secondary fail memory 81 of FIG. At this time, the real address (X:
4) is set, cell plate information is set to [x: 0, y: 1] on the line of the secondary fail memory address [x: 0]. At the same time, the real address information of Y (Y:
6) is also set.

Next, a defective cell (X: 2, Y: 9) is found, cell plate information is set in [x: 1, y: 2] of the secondary fail memory, and (X : 2, Y: 9).

Next, a defective cell of (X: 6, Y: 9) is found. This defective cell has a defective cell at the same (Y: 9) address before. Also, since there is only one X-side spare cell 74 in FIG. 5, this (Y: 9) address line is
Only the Y-side spare cell 73 in FIG. 5 can be replaced and repaired. Therefore, it can be determined that the address (Y: 9) is a line fail.

When the line fail is confirmed, the defective cell information is not set in the secondary fail memory. Instead, the information that the (Y: 9) address is determined to be line fail is set in the secondary fail memory 81. In FIG. 6, this information is indicated by “☆”.

Further, the line mask flag is set to the address of the fail memory where the line fail is confirmed. As a result, even if there is a defective cell at the (Y: 9) address thereafter, it is ignored.

The line fail flag is set at the address (Y: 9) of the secondary fail memory 81, and the search is continued. If the line fail flag is not set,
A defective cell of (X: 8, Y: 9) is found, but since the line fail flag is set, the defective cell of the line fail address is ignored and the secondary fail memory 81
Not set to. When all the defective cell searches of the cell plate 71 of FIG. 5 are completed, the line mask flag set in the line fail address is released and the process ends.

Subsequently to the cell plate 71, the defective cell search of the cell plate 72 is started, and the defective cell information is similarly set. Here, the defective cell information set in the secondary fail memory corresponds to the cell plate 72.
Use the cell plate information (02).

Here, similarly to the cell plate 71, fail memory search and secondary fail memory setting are performed to create basic information for the secondary fail memory 81 in FIG.

Next, based on the information set in the secondary fail memory 81, it is determined whether the defective cell can be rescued or not.
Judgment is based on two criteria. First, when the cell plate information of the defective cell is set in each of X / Y exceeding the size of the secondary fail memory address width determined in FIG. 6,
It can be judged that the defective cell cannot be repaired, and the subsequent analysis is not performed.

Further, in each X / Y group, if the number of spare cells exceeds the number of spare cells and the address line of the line fail is determined, it can be determined that the defective cell cannot be repaired, and the subsequent analysis is not performed. . Here, the cell plate information of the defective cell set in FIG. 6 does not reach either criterion, and it can be determined that the defective cell can be relieved.

Next, the information necessary for analysis is created based on the basic information for the secondary fail memory 81 of FIG. 6 in which the defective cell information is acquired from the fail memory unit 3.
An explanatory diagram for creating information necessary for analysis is shown in A of FIG.
In A of FIG. 7, first, the spare cell bit information similar to that of the cell plate is set for each of the X / Y spare cells corresponding to the cell plate bit information of the DUT 1. In FIG. 7A, fail cell plate information is created in the fail cell plate registers 84 and 85. The fail cell plate registers 84 and 85 have a secondary fail memory 81.
For each X / Y address of, the cell plate bit information of the defective cell is "ORed".

The spare cell mask registers 86 and 87 are set by clearing "0". However, the spare cell bit information of the confirmed spare cell is set to the line fail confirmed address, that is, the address to which "*" is set. In A of FIG. 7, (Y: of the secondary fail memory 81).
2) Set bit (03) in the spare cell mask register 86 of the address. The fail counters 88 and 89 have
The defective cells are counted and set for each X / Y address of the secondary fail memory 81.

Whether or not relieving can be performed by defective cell relief analysis is determined by masking the X-side address line and using the information on the Y-side address line, or by masking the Y-side address line and the X-side address line. Judgment based on information. Of the two, in order to finish the analysis in a short time, the repair analysis is executed by the method with the smallest maximum number of times of analysis.

Here, the maximum number of times of analysis on each of the X side and the Y side of A of FIG. 7 is obtained with reference to FIG. First, X in FIG.
The number of times of analysis for the side spare cell 74 is two because the number of spare cells for two addresses is one. Similarly, the number of times of analysis for the X side spare cell 75 is two, and the maximum number of times of analysis on the X side is 2 × 2 = 4. Times.

The maximum number of times of analysis on the Y side is 6 when a combination of two Y side spare cells 73 for 4 addresses is used. However, one of the spare cells on the Y side is defined as a line fail. Therefore, one combination is made for three addresses, which is three times.

From the above processing, the maximum number of analyzes on the X side is 4
The maximum number of times of analysis on the Y side becomes three times, and it is determined whether the repair analysis can be performed by setting the Y side address line on the mask side and the X side on the analysis side address line.

Next, as a preparation for starting the repair analysis, the spare cell mask information 86 on the mask side is created using the spare cell bit information of FIG. 8 as shown in FIG. 7B. Y in FIG.
Since the side spare cell 73 is defined by one line fail, the mask data for the remaining one cell is created.

The masked address is the Y address "1" of the secondary fail memory having the largest number of defective cells on the Y address side. Spare cell mask information 86 of this address
The Y spare cell bit information (03) is set to. In B of FIG. 7, "03" with diagonal lines is set in the spare cell mask register 86, and the spare cell mask setting address is shown by "-". As described above, the mask address combination for the first two Y spare cells is determined.

Next, in order to confirm whether the repair is possible, the secondary fail memory 81 is masked with the spare cell mask information 86. The masked address is the secondary fail memory 8
The Y-side address of 1 is "1" or "2", and the secondary fail memory 8 is the bit data of the spare cell mask information 86.
The cell plate bit information set to 1 is masked.

As a result, the defective cell information remaining in the secondary fail memory 81 is set to [x: 0, y: 0] and the defective (X: 4, Y: 3) of the cell plate 71 of FIG. Information on the cell and (X: 88, Y: 8) of the cell plate 72 set to [x: 2, y: 3]. The cell plate bit information of each of the two defective cell information is set in the spare cell mask information 87 of FIG. 7B on the analysis side.

Next, using the information in the spare cell mask register 87 on the analysis side and the X side spare cell bit information, it is judged whether or not the repair can be performed with the present combination address. First, the X side spare cell 74 of FIG. 5 will be examined. X side spare cell 7
The bit information of 4 is (01), and the number is 1. In the information of the spare cell mask register 87 of FIG. 7B, (0
There is only one bit information corresponding to 1), and the cell plate 71 can be replaced by the X side spare cell 74.

Next, the X side spare cell 75 of FIG. 5 will be examined. The bit information of the X side spare cell 75 is (02), and the number is one. In the information of the spare cell mask register 87 of FIG. 7B, there is only one bit information corresponding to (02), and the cell plate 72 can be replaced by the X side spare cell 75.

As for the defective cells set in the secondary fail memory 81, the X side spare cell 74 is replaced with X address = 4, the X side spare cell 75 is replaced with X address = 88, and two Y side spare cells are used. It can be judged that it is possible to repair the defective cell of the sample to be measured by replacing Y with Y address = 6, 9, and the analysis is completed. If it is not determined that the repair is possible, the mask side masks the address line having the next largest number of defective cells, and the analysis is repeated until the repair becomes possible.

[0076]

According to the present invention, the defective cell information of the fail memory is processed by the secondary fail memory so that if the defective cell can be actually repaired, it can be repaired without fail, and the yield in IC manufacturing can be improved. Can be raised. Also, because the analysis is performed with the minimum defective cell information,
High speed relief is possible. Furthermore, since the number of spare cells used is the minimum necessary, it is possible to deal with defective relief by retesting, and it is also possible to deal with complicated spare cell arrangements, so that free device design is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a defective cell repair analysis apparatus according to the present invention.

FIG. 2 is a state diagram of a secondary fail memory unit 5a.

FIG. 3 is a flowchart illustrating an operation of creating the secondary fail memory 21 of FIG.

FIG. 4 is a flowchart illustrating an operation of a defective cell repair analysis section 5.

FIG. 5 shows an arrangement of a semiconductor memory and spare cells.

FIG. 6 shows a state of a secondary fail memory unit at each stage.

FIG. 7 shows a state of a secondary fail memory unit at each stage.

FIG. 8 is a diagram showing the relationship between spare cell bits and cell plate information.

FIG. 9 is a configuration diagram of an IC test apparatus according to a conventional technique.

FIG. 10 is a state diagram of the fail memory unit 3 in which a defective device is taken in by measuring a memory device with an IC test apparatus.

FIG. 11 is a diagram showing one analysis unit of a semiconductor memory by arranging a cell plate, which is a group of memory cells, and a spare cell.

[Explanation of symbols]

1 sample to be measured 2 measuring section 3 Fail memory section 4 Measurement information processing unit 5 Bad cell repair analysis section 5a Secondary fail memory section 5b Remediation analysis result determination unit 5c Relief address generator 5d control unit 6 measurement results

Claims (6)

(57) [Claims] 1. A sample to be measured, which comprises at least one cell plate comprising a plurality of memory cells, and a plurality of redundant spare cells corresponding to X and Y address lines.
Measuring unit (2) that measures (1), fail memory unit (3) that receives the output of measuring unit (2), and fail memory unit (3)
In the defective cell repair analysis device including the measurement information processing unit (4) that outputs the repair analysis result to the measurement result (6), the defective cell information of the fail memory unit (3) is input. And a secondary fail memory unit (5a) that holds the
Using the output of the repair address generator (5c) and the secondary fail memory (5a) input to a) as input, it is judged whether the DUT (1) can be repaired by the spare cell, and the measurement result
The repair analysis result determination unit (5b) output to (6), and the defective cell repair analysis unit (5) including the repair analysis determination unit (5b) and the control unit (5d) that controls the repair address generation unit (5c). The secondary fail memory unit (5a) is provided with a secondary fail memory (21) represented by a two-dimensional matrix image of X and Y.
And an actual fail memory address register (24/25) that holds the address of the defective cell information acquired in the fail memory unit (3) as the actual address of the defective cell information acquired in the secondary fail memory (21). The fail cell plate register (26/27) that holds the cell plate information of the defective cell information acquired for each address in the next fail memory (21) and the masked information by replacing the defective cell address with the spare cell during analysis. Spare cell mask register (2
9) and a fail counter (2a, 2b) that holds the number of defective cells for each address of the secondary fail memory (21), and the X and Y address width of the secondary fail memory (21) is
From the arrangement of the spare cells of the sample to be measured (1), the number of X side spare cells for each cell plate is x, the number of Y side spare cells for each cell plate is y, the number of X side spare cell groups is a, and the Y side spare cell is The number of groups is b, the number of cell plates corresponding to the X side spare cells is α, and the number of cell plates corresponding to the Y side spare cells is β, and is determined by X side address width = x (βby + a), Y side address width = y (αax + b) A defective cell repair analysis device characterized by the above. 2. The defective cell repair analysis unit (5) obtains necessary defective cell information from the fail memory unit (3) of the IC test apparatus in the secondary fail memory unit (5a), and the secondary fail memory unit (5a). ), The repair analysis information of the fail cell plate number, the spare cell mask number, and the fail count number of X and Y is created based on the defective cell information acquired, and the repair address generation unit (5c) generates the first spare cell repair address. The relief address generated by the relief address generation unit (5c) in the mask side processing is generated from the total number of fail addresses written in the secondary fail memory unit (5a) by the number of spare cells. Then, the spare cell mask information is created in the spare cell mask register (28) on the mask side by using the combination of the repair addresses on the mask side determined by the repair address generation unit (5c). The information Bei cell mask register (28), 2
Next, the defective cell cell plate information in each defective cell cell plate register (26) at the mask side address of the fail memory unit (5a) is masked, and the repair analysis result determination unit (5b) generates it from the repair address generation unit (5c). The repair address determines whether the defective cell of the semiconductor memory can be repaired, and the secondary fail memory unit (5a) displays the secondary fail memory (21) represented by a two-dimensional X and Y matrix image.
And an actual fail memory address register (24/25) that holds the address of the defective cell information acquired in the fail memory unit (3) as the actual address of the defective cell information acquired in the secondary fail memory (21). The fail cell plate register (26/27) that holds the cell plate information of the defective cell information acquired for each address in the next fail memory (21) and the masked information by replacing the defective cell address with the spare cell during analysis. Spare cell mask register (2
9) and a fail counter (2a, 2b) that holds the number of defective cells for each address of the secondary fail memory (21), and the X and Y address width of the secondary fail memory (21) is
From the arrangement of the spare cells of the sample to be measured (1), the number of X side spare cells for each cell plate is x, the number of Y side spare cells for each cell plate is y, the number of X side spare cell groups is a, and the Y side spare cell is The number of groups is b, the number of cell plates corresponding to the X side spare cells is α, and the number of cell plates corresponding to the Y side spare cells is β, and is determined by X side address width = x (βby + a), Y side address width = y (αax + b) , Secondary fail memory (5a) masked by masking process
Residual defective cell cell plate information generated from the analysis side is stored in the spare cell mask register (29) on the analysis side, and the spare cell mask register (29) information captured on the analysis side is stored in the cell plate corresponding to the spare cell on the analysis side. When masked with information and all spare cell mask information on the analysis side does not remain, it is judged that it can be repaired, and when repairable, the actual fail memory address register corresponding to the mask information of the spare cell mask register (28 ・ 29)
The information of (24 ・ 25) is output as the spare cell relief address as a result, the relief analysis is ended, and if the relief is impossible, the next combination of relief addresses is generated and analysis is performed until the relief becomes possible. And a defective cell repair analysis method. 3. The secondary fail memory unit (5a) is initialized, the defective cell search of the fail memory unit (3) is started, and when a defective cell is found on the fail memory unit (3), the defective cell search is performed. Stop and search the secondary fail memory section (5a) for the actual fail memory address register, and the information of the same X or Y address is entered in the secondary fail memory (21) of the previous secondary fail memory section (5a). Is set, and if there is no defective cell information at the same X or Y address of the secondary fail memory section (21), the secondary fail memory section (2
If the defective cell number is set to an address near the lower address of 1) and the defective cell information is not set, and the defective cell information was previously set to the same X or Y address, If defective cell information is newly set on the extension of the address line, the secondary fail memory section (21) is searched, and if the address width on the X side or the Y side of the secondary fail memory (21) is exceeded, When it is judged that the defective cell of the sample to be measured (1) cannot be relieved, the processing is terminated, and if it is not exceeded, the Y cell is placed on the same X address in the cell plate corresponding to the Y spare cell.
The number of spare cells is exceeded and it is determined whether or not there is a line fail, and at the same time, the number of defective cells exceeds the number of spare cells X on the same Y address in the cell plate corresponding to the spare cells of X. If the defective cell acquired in the secondary fail memory (21) is a defective cell that does not correspond to the line fail, it is determined whether or not there is an existing line fail, and the defective cell is located at the position indicated by the address of the set secondary fail memory (21). The cell plate number of the defective cell is written, the defective cell address information is written to the corresponding real fail memory address register, the XY fail counter is incremented, and the bad cell acquired in the secondary fail memory (21) becomes a line fail. In the case of the corresponding defective cell, whether the determined number of X line failures exceeds the number of Y spare cells,
Alternatively, it is judged whether or not the number of line fail of Y exceeds the number of spare cells of X, and if it exceeds, line failover occurs, it is judged that the defective cell of the measured sample cannot be relieved, and line failover occurs. If not, the cell plate number of the defective cell is written to the spare cell mask register corresponding to the address of the secondary fail memory (21) that has failed the X or Y line, and the defect on the secondary fail memory (21) is detected. A flag is set in the X and Y line mask flags (14, 15) corresponding to the X or Y address of the cell, the processing for one defective cell information found in the fail memory search is completed, and the fail memory is again set. A search is performed. If a defective cell is found, the same processing is repeated. Defective cell relief analysis apparatus according to claim 1, characterized in that it comprises a Rumemori (21). 4. The secondary fail memory unit (5a) is initialized, the defective cell search of the fail memory unit (3) is started, and when a defective cell is found on the fail memory unit (3), the defective cell search is performed. Stop and search the secondary fail memory section (5a) for the actual fail memory address register, and the information of the same X or Y address is entered in the secondary fail memory (21) of the previous secondary fail memory section (5a). Is set, and if there is no defective cell information at the same X or Y address of the secondary fail memory section (21), the secondary fail memory section (2
If the defective cell number is set to an address near the lower address of 1) and the defective cell information is not set, and the defective cell information was previously set to the same X or Y address, If defective cell information is newly set on the extension of the address line, the secondary fail memory section (21) is searched, and if the address width on the X side or the Y side of the secondary fail memory (21) is exceeded, When it is judged that the defective cell of the sample to be measured (1) cannot be relieved, the processing is terminated, and if it is not exceeded, the Y cell is placed on the same X address in the cell plate corresponding to the Y spare cell.
The number of spare cells is exceeded and it is determined whether or not there is a line fail, and at the same time, the number of defective cells exceeds the number of spare cells X on the same Y address in the cell plate corresponding to the spare cells of X. If the defective cell acquired in the secondary fail memory (21) is a defective cell that does not correspond to the line fail, it is determined whether or not there is an existing line fail, and the defective cell is located at the position indicated by the address of the set secondary fail memory (21). The cell plate number of the defective cell is written, the defective cell address information is written to the corresponding real fail memory address register, the XY fail counter is incremented, and the bad cell acquired in the secondary fail memory (21) becomes a line fail. In the case of the corresponding defective cell, whether the determined number of X line failures exceeds the number of Y spare cells,
Alternatively, it is judged whether or not the number of line fail of Y exceeds the number of spare cells of X, and if it exceeds, line failover occurs, it is judged that the defective cell of the measured sample cannot be relieved, and line failover occurs. If not, the cell plate number of the defective cell is written to the spare cell mask register corresponding to the address of the secondary fail memory (21) that has failed the X or Y line, and the defect on the secondary fail memory (21) is detected. A flag is set in the X and Y line mask flags (14, 15) corresponding to the X or Y address of the cell, the processing for one defective cell information found in the fail memory search is completed, and the fail memory is again set. A search is performed. If a defective cell is found, the same processing is repeated. Defective cell repair analysis method according to claim 2, characterized in that it comprises a Rumemori (21). 5. If there are multiple spare cell groups,
A combination is generated for each group, and combinations are also made between groups. At this time, the address of the secondary fail memory unit (5a) determined to be replaced by a line fail is excluded from the combination target.
Alternatively, the defective cell repair analysis device described in 3. 6. When there are a plurality of spare cell groups,
The combination is generated for each group, and the combination is also performed between the groups. At this time, the address of the secondary fail memory unit (5a) determined to be replaced by the line fail is excluded from the combination target.
Alternatively, the defective cell repair analysis method described in 4 above.