JP3487628B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to a technique for reducing power consumption in a standby state.

[0002]

2. Description of the Related Art Liquid crystal display devices are thinner and lighter than CRTs and have low power consumption, and are therefore widely used in portable information equipment and the like that operate on the power supplied by a battery. .

However, it is desired to extend the operable time of such a portable information device by a battery. On the other hand, further miniaturization of portable information equipment is desired, and for this purpose, it is necessary to miniaturize the battery as well.

In order to realize such a proposition, it is desirable to reduce the power consumption of the liquid crystal display device used in the information equipment.

Here, as a conventional technique for reducing the power consumption of a liquid crystal display device, for example, a personal computer is used.
When you do not operate the keyboard, etc. for a long time,
There is known a technique of cutting off the power supply of the device when it is in a standby state.

Although not related to a liquid crystal display device, as described in NIKKEI ELECTRONICS NO590 (published on September 13, 1993), a display device using a CRT is in a standby state, There is known a technique for reducing the power consumption of the device by cutting off the power supply to the deflection circuit and the high voltage circuit.

[0007]

According to the respective techniques for reducing the power consumption in the standby mode, the display of the display device is not displayed in the standby mode, so that the state of the information equipment at that time cannot be visually recognized. There are points.

Therefore, an object of the present invention is to provide a liquid crystal display device capable of displaying with low power consumption in the standby state.

[0009]

[Means for Solving the Problems] To achieve the above object,
According to the present invention, the pixel data and the timing different from the non-standby state are displayed in the display control unit during the standby instruction period.
Signal to generate the pixel data and timing signals
Of the power consumption of the liquid crystal display device characterized by outputting
Provide reduction technology.

In order to achieve the above object, the present invention provides
During the period when the standby is instructed , the voltage controller does not wait
Generates less grayscale voltage than the number of grayscale voltages generated in each state.
Power consumption reduction of liquid crystal display devices characterized by
Provide technology.

[0011]

According to the power consumption reduction method of the present invention, the current flowing in and out of the liquid crystal matrix panel is increased by lengthening the change period of the signal voltage applied to the liquid crystal matrix panel or decreasing the voltage level of the signal voltage. By reducing the power consumption, the power consumption is reduced. In addition, even if the change period of the signal voltage is lengthened or the voltage level of the signal voltage is reduced in this way, a display that can be visually recognized by the user is ensured, and thus the user can display information more than this display. You can visually check the status of the equipment. In this case, although the display quality is deteriorated in the standby state period, the standby state is a period in which the user is not using, so that there is no problem in use.

[0012]

EXAMPLES Examples of information equipment according to the present invention will be described below.

First, the configuration and operation of the information equipment and liquid crystal display device common to each of the embodiments presented below will be described.

FIG. 1 shows the external appearance of the information device according to this embodiment.

In the figure, 1000 is an information device, 2 is a display unit of a liquid crystal display device, 3000 is a floppy disk insertion port of a floppy disk driver, 4000 is an input pen, and 50
00 is a key switch group, 6000 is a power save switch, and 7000 is a power switch. As illustrated, the liquid crystal display device is incorporated in the information device 1000.

FIG. 2 shows the internal configuration of the information equipment 1.

In the figure, 1001 is a CPU and 1002 is a CP.
ROM storing a program executed by U1, 1003
Is a RAM used for executing a program, 1004 is a battery, 10 is a liquid crystal display device, 1005 is a liquid crystal display device for controlling the display of the liquid crystal display device, and 1006 is V for storing data defining display contents to be displayed on the display device. -RA
M and 1007 are interface circuits between the power save switch 6000 and the key switch group 5000.
Reference numeral 08 is an interface circuit with the floppy disk drive, 1009 is an interface circuit for the control signal 2003 with the display controller 10, and 1010 is an interface circuit with the input pen 4000.

The liquid crystal display device 10 also includes a display unit 2, a light source 4, and a drive control circuit 2005.

Now, in such a configuration, when the input pen 4000 is placed on the display unit 2, it detects the coordinates on the display unit 2, for example, the voltage applied to the display unit 2, etc. To detect.

Further, the CPU 1001 uses the input pen 400
The program is executed according to the detected coordinates of 0 or the key input of the key switch group 5000, and the contents to be displayed on the display unit 2 of the liquid crystal display device 10 are determined according to the execution result,
The image data defining the display content is written in the V-RAM 1006. The display control device 1005 is a V-RAM 100.
6 is stored in the liquid crystal display device 10.
Together with the synchronization signal group 2001 necessary for the display in FIG.

The CPU 1001 detects the fact that the power save switch 6 is turned on via the interface circuit 1007, or the input pen 4 for a certain period or longer.
When it detects that no coordinates have been input or that no key has been input to the key switch group 5000, it outputs the power save control signal 2003 for instructing the shift to the power save mode. It is sent to the liquid crystal display device 10 via the scanning circuit 1009.

When the power switch is turned on, the battery 1004 supplies electric power of a predetermined voltage to each part of the information equipment 1000 including the liquid crystal display device 10.

Next, FIG. 3 shows the internal structure of the liquid crystal display device 10.

As shown in the drawing, the signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, the light source 4,
It is composed of an interface circuit 7 and a display unit 2.
The signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, and the interface circuit 7 correspond to the drive control circuit 2005 shown in FIG.

In this embodiment, a liquid crystal matrix panel is assumed as the display unit 2. As shown in FIG. 4, in the liquid crystal matrix panel 2, one pixel is composed of a TFT (thin film transistor) 13 and a liquid crystal 14. Also, T
The scanning lines 12a to 12d are connected to the gate electrode of the FT 13, and the signal lines 11a to 11c are connected to the drain electrode.

In the interface circuit 7, the image data 2 to be displayed on the display unit 2 is displayed by the display control device 1005.
002 is input. Further, as the synchronizing signals included in the synchronizing signal group 2001, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal synchronized with the image data 2002 are input,
The power save control signal 2003 is the interface circuit 1
It is input from the CPU 1001 via 009. Here, the image data 2002 is input in the order according to the raster scan method. The vertical synchronizing signal is a pulse signal output for each frame period of an image to be displayed, and the horizontal synchronizing signal is a pulse signal output for each line scanning period.

The interface circuit 7 passes these signals to the display control circuit 5.

The display control circuit 5 uses the image data 2002,
Based on the sync signal 2001 and the power save control signal 2003, image data DATA, a vertical sync signal VSYNC, and a horizontal sync signal H, which are internal signals corresponding to these signals.
SYNC, a power save control signal PS are generated, and the generated vertical synchronizing signal VSYNC, horizontal synchronizing signal HSYNC, clock signal DCLK, and image data DATA are sent to the signal driving circuit 1, and the scanning driving circuit 3 is horizontally synchronized. Signal HS
YNC and a vertical synchronizing signal VSYNC are sent to the voltage control circuit 6, a synchronizing signal (one or both of VSYNC and HSYNC) and a clock signal DCLK necessary for realizing a polarity inversion driving method described later are sent to the voltage control circuit 6, A power control signal PS is supplied to the signal drive circuit 1, the scan drive circuit 3, and the light source 4.
To send.

However, in some embodiments, it is not necessary to send some signals.

FIG. 5 shows the normal mode (non-power).
The correspondence between the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the clock signal DCLK, the timing of the image data DATA (FIG. 5a) in the save operation mode) and the display screen (FIG. 5b) defined thereby are shown. Keep it. Figure 5
The timing shown in a coincides with the timing of the vertical synchronizing signal, the horizontal synchronizing signal, the clock signal, and the image data input to the interface circuit 7.

Now, the voltage control circuit 6 is connected to the battery 100.
The power supply 4 supplies a scan driving voltage to the scan driving circuit 3. Further, a signal driving voltage is generated and sent to the signal driving circuit 1.

As shown in FIG. 6, the scanning driving circuit 3 is for scanning driving, which is sent from the voltage control circuit 6 to the different scanning lines 12a to 12d sequentially in synchronization with the horizontal synchronizing signal HSYNC. Scanning voltages Vg1 to Vg according to voltage
n is applied. Also, every time the vertical synchronization signal VSYNC is input, the above-mentioned operations from the first scanning line 12a are repeated. That is, the scanning voltage is sequentially set to the value Vg for each line.
As a result, the TFT is turned on every line.

On the other hand, the signal drive circuit 1 includes two groups of latches capable of storing image data for one line. Further, the signal lines 11a to 11c are provided with the same number of output circuits as the number of image data for one line, which are respectively connected.
The first latch group sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and synchronizes the latched image data DATA for one line to the second latch group in synchronization with the horizontal synchronization signal HSYNC. The image data for one line is transferred in parallel, the transferred image data for one line is held until the image data for the next line is transferred, and the image data is output to different output circuits in parallel. During this period, the first latch group sequentially takes in the image data of the next line in the same manner as the previous line. As a result, as shown in FIG. 6, the signal voltages Vd1 to Vdm are applied.

Each output circuit applies the signal voltages Vd1 to Vdm to the connected signal lines according to the value of the received image data and the signal driving voltage sent from the voltage control circuit 6.

The configuration and operation of the information equipment and the liquid crystal display device common to each embodiment presented in this embodiment have been described above. Hereinafter, in the liquid crystal display device 10 having such a configuration, each embodiment for reducing power consumption while ensuring display will be described.

First, the first embodiment will be described.

In the first embodiment, when the display controller 5 receives the power save signal from the interface circuit 7, it outputs the horizontal synchronizing signal HSYNC in the normal mode.
In addition to double the power saving mode, the power save signal PS instructs the scan drive circuit 3 and the signal drive circuit 1 in the power save operation mode. Note that such a horizontal synchronization signal HSY
The NC cycle is changed by changing the display control circuit 8 as described later.
A frequency dividing circuit for dividing the frequency of the horizontal synchronizing signal HSYNC to be output to 1/2 of the frequency of the horizontal synchronizing signal input from the interface circuit 7 when the power save signal PS is ON. Can be realized by providing. Alternatively, when the power save signal PS is ON, it is phase-synchronized with the horizontal synchronizing signal input from the interface circuit 7, and a signal having a frequency of 1/2 of this is output as the horizontal synchronizing signal HSYNC. An oscillator may be provided.

As shown in FIG. 7, the scan drive circuit 3 sequentially outputs two scan signals such as Vg1 and Vg2 and Vg3 and Vg4 at every cycle of the horizontal synchronizing signal HSYNC output from the display control circuit 3. The scanning voltage value Vgh is applied one by one. The application of the scanning voltage for each of the two scanning signals is
For example, the scan drive circuit 3 includes output circuits for the number of scan signals connected to different scan signal lines, and HSYNC.
The counter that counts C and is reset by VSYNC and the count value of the counter are used as the power save signal PS.
And a decoder for decoding the output circuit in accordance with the decoder value and sequentially enabling the output circuits in accordance with the decoder's decoder value. Here, the output circuit is a circuit that outputs the scanning voltage supplied from the voltage control circuit 6 to the corresponding scanning signal line when activated.

On the other hand, in the signal drive circuit 1, when the first latch group becomes full by taking in the image data of the odd-numbered lines, the operation of discarding the image data of the even-numbered lines to be input is performed. repeat. The image data of the odd-numbered lines fetched by the first latch group is
It is taken into the second latch group by the horizontal synchronizing signal HSYNC input at the end of inputting the image data of the next even-numbered line, held until the input of the next horizontal synchronizing signal HSYNC, and output to the output circuit. As a result, the voltage applied to each signal line is updated at a cycle twice that of the normal mode.

By doing so, the period for turning on the TFTs of the liquid crystal matrix 2 is doubled. Further, in accordance with this, the cycle in which the levels of the signal voltages Vd1 to Vdm change is doubled. Therefore, the power consumption of the liquid crystal matrix 2, the signal drive circuit, the voltage control circuit 6 and the like can be reduced.

On the other hand, the resolution of the image displayed on the liquid crystal matrix 2 is half of that in the normal mode in the vertical direction, but in the power save mode, the user works. This is a period that has not been set, so there is no problem in practical use.

The display control circuit 8 uses the vertical synchronizing signal V
SYNC, operation clock DCLK, image data DATA
With respect to, the interface circuit 7 outputs the input signal as it is.

By the way, as shown in FIG.
The scan voltages Vg1, Vg2. ． Is applied in the same manner as in the normal mode, and the display control circuit 5 doubles only the cycle of the horizontal synchronizing signal HSYNC given to the signal drive circuit 1 to change the level of only the signal voltage every two lines. You may do it. Even in this case, the cycle in which the level of the signal voltage changes can be doubled, and an effect similar to that of the first embodiment can be achieved.

Further, the period of the clock signal DCLK is further doubled, and in the signal drive circuit 1, the image data is taken into the first latch group every other pixel data, and the image data is transferred from the nth latch of the first latch group. 2n− of the second latch group
Data may be transferred in parallel to the first and 2nth latches in synchronization with the horizontal synchronization signal HSYNC. The frequency of the clock signal DCLK is changed by inputting the frequency of the clock signal DCLK output from the interface circuit 7 to the display control circuit 8 when the power save signal PS is ON. It can be realized by providing a frequency dividing circuit for dividing the frequency of the operating clock signal to ½. Of course, 1/2 the frequency of the operation clock signal input from the interface circuit 7
An oscillator may be provided to generate a clock having a frequency of 3 in synchronization with the operation clock signal input from the interface circuit 7.

In this way, the horizontal resolution of the display is also halved, but as described above, the power save mode is used.
When it is off, it is a period during which the user is not working, so there is no practical problem. Further, the operating frequency of the first latch group of the signal drive circuit 1 is half that in the normal mode, so that the power consumption can be reduced.

In this embodiment, the driving / operating frequency of the scanning drive circuit 3 and the signal drive circuit 1 is changed to 1/2 in the power save mode, but this is 1/4, etc. Other ratios may be used.

The second embodiment will be described below.

In the first embodiment, the scan drive circuit 3,
By reducing the driving / operating frequency of the signal drive circuit 1 and reducing the resolution of the image displayed by the image data input to the interface circuit 7, the power consumption is reduced. In this embodiment, a predetermined image is generated by the built-in pattern generator without using the image data input to the interface circuit 7 in the power save mode.
Display this.

FIG. 9 shows the configuration of the display control circuit 5 according to the second embodiment.

As shown in the drawing, in the second embodiment, the display control circuit 5 includes a selection circuit group 19 including selection circuits 19a to 19d, an oscillation circuit 22, a pattern generator 20,
A control circuit 21 is provided.

The control circuit 21 uses the basic clock output from the oscillation circuit 22 and has three frequency ratios equal to the frequency ratio of the direct sync signal, the horizontal sync signal, and the operation clock input from the interface circuit. Signal VSYNC
(IN), HSYNC (IN), and DCLK (IN) are generated. The pattern generator 20 is actually a memory that stores image data, and outputs image data indicating a predetermined image pattern as shown in FIG. 10, for example, in synchronization with DCLK (IN). To do.

The selection circuits 19a to 19d are provided with vertical synchronizing signals input from the interface circuit 7 in the normal mode.
The horizontal synchronizing signal, the operation clock, and the image data are output as they are as VSYNC, HSYNC, DCLK, and DATA, and the timing signal VSYNC (I) input from the control circuit 21 in the power save mode.
N), HSYNC (IN), DCLK (IN) to VS
DATA (IN) output from the pattern generator 20 is output as YNC, HSYNC, and DCLK.
Output as TA.

Here, VSYNC (IN), HSYNC (IN), DCLK output from the control circuit 21.
The frequency of (IN) can be smaller than the frequencies of the direct sync signal, the horizontal sync signal, and the operation clock input from the interface circuit, to the extent that the visibility of the display of the liquid crystal matrix 2 is not significantly impaired. Therefore, the driving / operating frequency of each unit can be made smaller than that in the normal mode, so that the power consumption can be reduced.

The V output from the control circuit 21
SYNC (IN), HSYNC (IN), DCLK (I
Of N), the horizontal synchronizing signal input from the interface circuit 7 of HSYNC (IN) and DCLK (IN) and the frequency ratio to the operation clock are the vertical synchronizing signal input from the interface circuit 7 of VSYNC (IN). If the scanning drive circuit 3 drives every two scanning signal lines in the same manner as in the first embodiment (see FIG. 7), the vertical resolution will be the normal mode. Although it is 1/2 as compared with the time, the driving / operating frequency of the scanning drive circuit 3 and the signal drive circuit 1 can be further reduced, and power consumption can be further reduced, as in the case shown in FIG. In this case, the pattern generator 20 displays an image to be displayed in advance in half in the vertical direction.
The reduced image data is stored.

Alternatively, in power-save mode, HSYNC (IN) and DCLK (I
(N) the horizontal synchronizing signal input from the interface circuit 7 and the frequency ratio to the operating clock are VSYNC (I
If the frequency ratio to the vertical synchronizing signal input from the interface circuit 7 in (N) is set to, for example, 1/2, driving / driving of the signal driving circuit 1 is performed in the same manner as that shown in FIG. 8 in the first embodiment. The operating frequency can be slowed down and the power consumption can be reduced. In this case as well, the pattern generator 20 stores in advance image data in which the image to be displayed is reduced by 1/2 in the vertical direction.

Further, the frequency ratio of DCLK (IN) to the operation clock input from the interface circuit 7 is set to, for example, 1 of the frequency ratio of the horizontal sync signal input from the HSYNC (IN) interface circuit 7. / 2, as described above, in the signal drive circuit 1, the image data is fetched into the first latch group every other pixel data, and the nth latch of the first latch group to the second latch group 2n. If the data is transferred in parallel to the -1st and 2nth latches in synchronization with the horizontal synchronizing signal HSYNC (IN), both the horizontal direction and the resolution become half of those in the normal mode. The drive / operating frequency of the signal drive circuit 1 can be further lowered, and the power consumption can be further reduced. In this case, the pattern generator 20 also displays an image to be displayed in advance in the horizontal direction.
The image data reduced to / 2 is stored.

As described above, in the second embodiment,
In the power save operation mode, a predetermined image pattern as shown in FIG. 10 is displayed, but the pattern generation
Timing signals HSYNC (IN), VSYNC for the timing of reading the image pattern from the printer 20.
The image pattern may be moved on the display screen by sequentially shifting the generation timings of (IN) and DCLK (IN). By doing so, the user can perform power control. -It is possible to easily recognize the bleeding state. Further, it is possible to reduce the deterioration of the image quality such as the change in brightness and the afterimage caused by the characteristic change of the film forming the TFT or the characteristic change of the liquid crystal material, which is caused by the display at the same position for a long time.

In the second embodiment, in the display control circuit shown in FIG. 9, switching between VSYNC, HSYNC and DCLK in the normal mode and the power save operation mode is performed by the oscillator. Control circuit 21 and selection circuit group 19
This is realized by providing a horizontal synchronizing signal input from the interface circuit 7 in the power save mode without performing frequency division in the normal mode as shown in FIG. The operating clock may be realized by providing a frequency dividing circuit group 23 including frequency dividing circuits 23a, 23b, and 23c that divide the operating clock by a predetermined frequency dividing ratio.

The third embodiment of the liquid crystal display device will be described below.

In the third embodiment, the liquid crystal matrix panel 2 is driven by the polarity inversion driving method for each line. That is, as shown in FIG. 12, the polarity of the signal voltage is inverted every horizontal line and applied to the pixels of the liquid crystal matrix panel. The application of such a signal voltage is realized in the voltage control circuit 6 by inverting the polarity of the voltage supplied to the signal drive circuit for each horizontal line by using the input HSYNC and DCLK.

In the third embodiment, a liquid crystal matrix panel 2 capable of gradation display is used. The display gradation of each pixel is controlled by the value of the signal voltage supplied from the signal drive circuit 1. The configuration of the liquid crystal matrix panel 2 is the same as that shown in FIG.

In FIG. 13, the signal voltage Vd corresponding to each gradation applied to the signal line by the polarity inversion driving method for each line is shown.
And the waveform of the voltage Vcom applied to the common electrode. As shown in the figure, the voltage Vcom applied to the common electrode is inverted in polarity for each line,
The polarity of d is also inverted so that the absolute value of the voltage difference with the voltage Vcom is maintained. The OFF voltage of the scanning voltage is
It is in phase with the common voltage Vcom and has the same amplitude value. Further, the polarities of the signal voltages corresponding to the five gradations from black to white are inverted with the halftone 2 as the boundary.

In the liquid crystal matrix panel 2 shown in FIG. 4, the potential difference between the signal electrode (drain electrode) and the common electrode is minimum, the potential difference between the signal electrode and the scanning electrode (gate electrode) is minimum, and The power consumption is lowest when the three conditions in which the potential difference between the common electrode and the signal electrode is minimized are satisfied. This is because a transient current flows through the parasitic capacitance due to the parasitic capacitance between the electrodes.

Here, as understood from FIG. 13, such a transient current is minimized in the case of white display. Therefore, it is desirable that the entire screen be displayed in white in the power save operation mode. However, this makes it impossible to visually recognize the operating state of the device. Therefore, in this embodiment, a predetermined pattern is displayed as shown in FIG. 14 in the power save operation mode. And on that, the brightness of the background is displayed in white or a halftone close to white,
The pattern part should be displayed in halftone with a darker gradation than the background part. The display of such a pattern can be performed in the same manner as in the second embodiment.

In this case, since the background looks bright, the voltage applied to the light source 4 may be reduced, or the current flowing through the light source may be limited to reduce the brightness. As a result, the power consumption of the display device can be further reduced. Further, in particular, when the liquid crystal matrix panel 2 is of a reflective type and a transmissive type, the power source of the light source 4 may be cut off.

In the third embodiment, the normally white mode is the brightest when no voltage is applied to the liquid crystal.
The liquid crystal matrix panel 2 of
When a normally black mode liquid crystal matrix panel 2 which becomes darkest when no voltage is applied to the liquid crystal is used, conversely, the background brightness is black or halftone display close to black, and the pattern part is the background. It is only necessary to display halftones with gradations lighter than the area.

When the liquid crystal matrix panel 2 capable of color display is used, the pattern may be a halftone display which is brighter than the background portion for one of the three RGB colors.

Further, in the third embodiment, not only the polarity inversion driving method for each line but also the driving method for inverting the polarity for each pixel as shown in FIG. 15 and the polarity inversion for each pixel as shown in FIG. Further, the same can be applied to a driving method of reversing the polarity for each line, a driving method of reversing the polarity for each frame, or a driving method combining these.
Further, the liquid crystal matrix panel 2 can be similarly applied even if the number of gradations is not five.

The fourth embodiment of the present invention will be described below.

In the fourth embodiment, as in the third embodiment, a liquid crystal matrix panel 2 capable of gradation display is used.

FIG. 17 shows the voltage control circuit 6 according to this embodiment.
As shown in the figure, the voltage control circuit 6 includes selection circuits 24 and 25, and a gradation circuit 26.

In power-save mode operation, the selection circuit 24
When the power save control signal PS is input from the display control circuit 5, switches the power supply voltage of the power supply VDR supplied to the gradation circuit 26 from VN1 to VS1. Similarly, the selection circuit 25 switches the power supply to the signal drive circuit 1 from VN2 to VS2. The relationship of power supply voltage is VN1
> VS1 and VN2> VS2. That is, during the power save mode operation, the gradation circuit 26 and the signal drive circuit 1
Reduce the voltage applied to. Note that only one of the grayscale circuit 26 and the signal circuit 1 may be powered down without powering down at the same time.

The gradation circuit 26 divides the power supply voltage supplied from the selection circuit at a predetermined ratio and outputs the voltages V1 to Vk. Since VN1> VS1, the voltages V1 to Vk are
During power-save mode operation, the ratio becomes smaller at the ratio of VS1 / VN1. The gradation voltages V1 to Vk are set at constant intervals in accordance with the driving method of the liquid crystal matrix panel 2 (line-by-line polarity inversion driving method, pixel-by-pixel polarity inversion driving method, frame-by-frame polarity inversion driving method). The polarity may be inverted.

Next, FIG. 18 shows the configuration of the signal circuit 1 according to the fourth embodiment.

As shown in the figure, as described above, the signal circuit 1 outputs the latched group for sequentially latching the image data DATA for one line in synchronization with the clock signal DCLK and the transferred image data for one line as follows. It has a logic circuit section 27 including a second latch group which holds the image data of the line until it is transferred and outputs the image data in parallel to the output circuit 28, and the output circuit 28.

Further, as shown in FIG. 19A, each output circuit 28 is responsive to a decoder 2810 for decoding the value of the image data sent from the logic circuit section 27 and the decoded value. Of the voltages V1 to Vk sent from the gradation circuit 26,
A selector unit 2800 having an analog selector that selects one of them and a power supply voltage VDR supplied from a selection circuit 24 with the voltage selected by the analog selector 2800.
It has a driver circuit 2801 which amplifies using (VN2 or VS2) and supplies it to the corresponding signal electrode.

The selector section of the output circuit 28 of the signal circuit 1 is, as shown in FIG. 19B, the decoder 2 for decoding the value of the image data sent from the logic circuit section 27.
810, a voltage dividing circuit 2890 which divides the voltages V1 to Vk sent from the gradation circuit 26 according to the decoding value, and an analog selector 2800 which selects one of the divided voltages. It may be configured.

The output circuit 28 can be constructed in various ways, and as shown in FIG.
Decoding to decode the value of image data sent from 7
Every clock signal D according to the decoder 2810 and the decoding value.
A sample-hold circuit 2820 that holds the power supply voltage VDR at the timing of CLK, and a voltage V1 sent from the gradation circuit 26 using the held power supply voltage VDR as a control input (for example, a gate voltage). To Vk to selectively output any of the transistors (for example, FET) 283.
It can be configured by 0 or the like.

In any case, if the image data values are the same, the output voltage of the output circuit 28 is determined by the voltages V1 to Vk sent from the gradation circuit 26 and the power supply voltage VDR.

With the above-described structure, the waveforms of the signal voltage Vd applied to the signal electrode and the power supply voltage VDR applied to the signal circuit 1 are in the non-power save operation mode and the power mode. It changes as shown in FIG. 20 in the save operation mode.

In the figure, (a) represents the non-power save operation mode, and (b) represents the power save operation mode.

As shown in the figure, in the power save operation mode, the influence of the gradation voltages V1 to Vk and the power supply voltage VDR is lowered as compared with the non-power save operation mode. , A low signal voltage is applied to the signal electrode. Therefore, the power consumption is lower than that in the non-power save operation mode.

In this case, in the power save operation mode, a display with lower or higher brightness is performed as compared with the non-power save operation mode.
In the save operation mode, there is no problem because the user is not working.

Incidentally, since the scan drive circuit 3 is usually provided with a driver circuit for sequentially driving the scan lines by using the supplied power source, this driver circuit is operated during the power save mode operation. Even if the power supply voltage to be supplied is lowered, the power consumption can be reduced as in the case of the fourth embodiment.

The fifth embodiment of the liquid crystal display device according to the present invention will be described below.

FIG. 17 shows the configuration of the voltage control circuit 6 according to the fifth embodiment. As shown in the figure, the voltage control circuit 6 is shown.
Includes a gradation circuit 26, and the gradation circuit 26 includes gradation voltage generation circuits 26a to 26e.

Each of the gradation voltage generating circuits 26a to 26e has V1 to V1 shown in FIG. 22A in the non-power save operation mode.
A gradation voltage of Vk is generated. Further, power - Se - Bed operating mode - the time of de generates gradation voltages of V1～V 2 shown in FIG. 22 (b).

That is, only V1 and V2 are changed, and other output voltages are set to constant voltages (Vc) so as not to change.

The drawing shows the case where the polarity of the voltage is changed every horizontal scanning time ta by the line polarity reversal drive method.

Further, in the fifth embodiment, as shown in FIG.
The display control circuit 5 having the pattern generator 20 displays a predetermined pattern on the liquid crystal matrix panel.

Then, for example, in the output circuit 28 shown in FIG. 19A, the portion displaying the pattern is V
1, the voltage of V2 is selected, the other part is V3 ~ V
The value of the image data output by the pattern generator 20 is given in advance so that any voltage of k can be selected.

As a result, when the pattern shown in FIG. 23 is displayed, as shown in FIG. 24, the background portion 2300 is driven at a constant voltage level, and the portion 2 for displaying the pattern is displayed.
301 is driven by the voltages of V1 and V2.

The voltage control circuit 6 according to the fifth embodiment.
May be configured as shown in FIG.

As shown in the figure, the voltage control circuit 6 includes a gradation circuit 26, a gradation circuit 41, a gradation control circuit 42, and a switch circuit 35.

The gradation circuit 26 generates gradation voltages V1 to Vk whose polarities are inverted every horizontal scanning period, as shown in FIG. 22A, from the supplied power supply voltage and the horizontal synchronizing signal HSYNC, and the gradation is generated. The circuit 41 generates gradation voltages V1 to Vk whose polarities are inverted every horizontal scanning period shown in FIG. 22B from the supplied power supply voltage and the horizontal synchronizing signal HSYNC.

The gradation control circuit 42 controls the switch circuit 35 so that the gradation circuit 2 is operated during non-power save mode operation.
The output voltage of 6 is selected and given to the signal drive circuit 1,
During the save mode operation, the output voltage of the gradation circuit 41 is selected and given to the signal drive circuit 1.

Further, the gradation control circuit 42 is a non-power
During the boost mode operation, the operation of the gradation circuit 41 is stopped, and during the power save mode operation, the operation of the gradation circuit 26 is stopped. The operation can be stopped, for example, by stopping the supply of power or stopping the supply of the horizontal synchronization signal HSYNC and the clock signal DCLK used for inverting the polarity of the generated voltage.

In the fifth embodiment, V1 and V2
Only the output voltage may be changed so that the other output voltages have a smaller amplitude than V1 and V2.

Alternatively, only V1 may be changed, other output voltages may be constant or have a voltage amplitude smaller than V1, and characters or the like may be simply driven by V1 and the background may be driven by another voltage. .

By doing so, it is possible to reduce the power consumption of the gradation circuit which is generally composed of a differential amplifier and resistors and capacitors. Furthermore, by making the voltage input to the signal drive circuit 1 constant or reducing the amplitude, the current due to the stray capacitance in the signal drive circuit 1 and the liquid crystal matrix panel 2 can be reduced, and the power consumption can be reduced.

As described above, according to each embodiment of the liquid crystal display device according to the present invention, the power saving is performed while performing a constant display.
The power consumption in the operation mode can be reduced.

In the above embodiments, the liquid crystal display device in which the signal drive circuit 1 drives the liquid crystal matrix panel according to the image data which is digital data has been described.
In the device in which the signal drive circuit 1 drives the liquid crystal matrix panel directly according to the analog image signal,
The signal drive circuit 1 in the embodiment may be configured as shown in FIG.

That is, the input analog image signal 28
Reference numeral 50 denotes sample hold circuits 2803 corresponding to the number of signal electrodes that sample hold in synchronization with the sample clock signal 2804 corresponding to the data clock, and the respective sample hold circuits are cyclically and sequentially based on the sample clock signal. A logic circuit portion 2805 which gives a sampling operation permission signal of the circuit 2803 and a sample-hold voltage provided for each sample-hold circuit are used by using the power supply voltage (VN2 or VS2) supplied from the selection circuit 24. A driver circuit 2801 that amplifies and applies to the corresponding signal electrode
You may make it comprised further. When the signal drive circuit 1 drives the liquid crystal matrix panel directly according to the analog image signal as described above, each line or frame is driven.
When driving by inverting the polarity for each frame, the polarity of the analog image signal given to the driving method signal drive circuit 1 is inverted and the analog image signal voltage is equivalent to the common voltage in synchronization with the timing of this polarity inversion. A circuit that shifts by an amount may be provided.

Further, in the sixth embodiment, when the signal drive circuit 1 shown in FIG. 26 is used and the signal drive circuit 1 drives the liquid crystal matrix panel directly in response to the analog image signal, it is shown in FIG. The pattern generator 20 may be configured to generate an analog image signal such that the signal drive circuit 1 outputs the signal voltage.

In the above embodiments, the liquid crystal display device 1 is used.
0 is a power save control signal 200 from the CPU 1001.
When 3 is received, the mode shifts to the power save operation mode, but the liquid crystal display device itself judges the usage status of the information equipment 1000 and automatically enters the power save operation mode. You may make it shift. For example, by providing a frame buffer for storing one frame of image data in the liquid crystal display device 10 and determining whether the image data in the frame buffer and the input image data are coincident with each other, two consecutive frames can be detected. -The change between frames is sequentially obtained, and if there is no change in the predetermined number of frames, it is judged that it is not being used by the user at present, and the power save operation mode is automatically set. This can be realized by making a transition. Also,
Alternatively, the state of the power switch may be directly read to shift to the power save operation mode.

[0106]

As described above, according to the present invention, the present invention can provide a liquid crystal display device capable of displaying with low power consumption in the standby state.

[Brief description of drawings]

FIG. 1 is a diagram showing an external appearance of an information device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an information device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a liquid crystal matrix panel.

FIG. 5 is a normal mode of a liquid crystal display device according to an embodiment of the present invention.
It is a figure which shows operation | movement at the time of switching.

FIG. 6 is a normal mode of a liquid crystal display device according to an embodiment of the present invention.
FIG. 6 is a timing chart showing a drive voltage waveform during driving.

FIG. 7 is a timing chart showing a first drive voltage waveform in the power save mode of the liquid crystal display device according to the embodiment of the present invention.

FIG. 8 is a timing diagram showing a second drive voltage waveform in the power save mode of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a first display control circuit according to a second embodiment of the present invention.

FIG. 10 is a power saver according to a second embodiment of the present invention.
It is the figure which showed the appearance of the pattern display at the time of reading.

FIG. 11 is a block diagram showing a configuration of a second display control circuit according to the second embodiment of the present invention.

FIG. 12 is a diagram showing the polarities of voltages applied to pixels by a line-by-line polarity inversion driving method.

FIG. 13 is a timing diagram showing a signal voltage corresponding to each gradation applied to a signal line by a polarity inversion driving method for each line.

FIG. 14 is a power save mode according to a third embodiment of the present invention.
It is the figure which showed the appearance of the pattern display at the time of reading.

FIG. 15 is a diagram showing a polarity of a voltage applied to a pixel by a pixel polarity inversion driving method.

FIG. 16 is a diagram showing the polarities of the voltages applied to the pixels by a driving method combining a pixel-by-pixel polarity inversion driving method and a line-by-line polarity inversion driving method.

FIG. 17 is a block diagram showing a configuration of a voltage control circuit according to a fourth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a signal drive circuit according to a fourth embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of an output circuit according to a fourth example of the present invention.

FIG. 20 is a timing diagram showing signal drive voltage waveforms according to the fourth embodiment of the present invention.

FIG. 21 is a block diagram showing a first configuration of the voltage control circuit according to the fifth exemplary embodiment of the present invention.

FIG. 22 is a timing chart showing an output voltage waveform of the voltage control circuit according to the fifth embodiment of the present invention.

FIG. 23 is a power save mode according to a fifth embodiment of the present invention.
It is the figure which showed the appearance of the pattern display at the time of reading.

FIG. 24 is a timing chart showing a driving voltage waveform in the power save mode of the liquid crystal display device according to the fifth embodiment of the present invention.

FIG. 25 is a block diagram showing a second configuration of the voltage control circuit according to the fifth exemplary embodiment of the present invention.

FIG. 26 is a block diagram showing another configuration of the output circuit according to the example of the present invention.

[Explanation of symbols]

1 signal drive circuit 2 Liquid crystal matrix panel 3 Scan drive circuit 4 light sources 5 Display control circuit 6 Voltage control circuit 7 Interface circuit

Front page continuation (72) Inventor Soshiro Katsuruki 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-5-145872 (JP, A) JP-A 3-221984 (JP, A) JP 5-344371 (JP, A) JP 63-261229 (JP, A) JP 3-182793 (JP, A) JP 7-84238 (JP, A) JP 4-32383 (JP, A) JP 4-284490 (JP, A) JP 61-92952 (JP, A) Actual flat 3-8349 (JP, U) Actual 63 -45587 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/20-3/36 G09G 3/18 G02F 1/13-1/141

Claims (3)

(57) [Claims] 1. A liquid crystal matrix panel having a plurality of pixels each provided with a thin film transistor in a horizontal direction and a vertical direction intersecting with the pixels, and the liquid crystal matrix panel provided in each group of the plurality of pixels arranged in the vertical direction. A signal driver that sends pixel data to the thin film transistor, a scan driver that applies a scan voltage to the scan electrodes of the thin film transistors provided in each group of the plurality of pixels arranged in the horizontal direction, and the pixel data, And an interface for receiving from the external circuit a timing signal for fetching the pixel data into the signal drive unit or outputting the pixel data to the liquid crystal matrix panel from the signal drive unit, and a display control unit provided in a subsequent stage of the interface, The display control unit generates pixel data different from the pixel data received from the interface. Pattern cell
A generator, a control circuit for generating a timing signal different from the timing signal received from the interface, and pixel data and timing signal sent to the signal drive unit by an external signal, pixel data received from the interface And a timing signal, or a selection circuit for setting either the pixel data generated by the pattern generator or the timing signal generated by the control circuit, the timing signal including a clock signal, and the control circuit 2. The liquid crystal display device according to claim 1, wherein the clock signal generated in step 1 has a lower frequency than the clock signal received from the interface. 2. The liquid crystal display device according to claim 1, wherein the pixel data generated by the pattern generator has a lower resolution than the pixel data received from the interface. 3. The liquid crystal display device according to claim 1, wherein the external signal is a signal for instructing the liquid crystal display device to enter a standby period.