JP3476383B2 - Semiconductor laminated package - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor stacked package <br/> cage, more particularly, capable semiconductor multilayer to improve the packaging density of semiconductor packages package
About the.

[0002]

2. Description of the Related Art In recent years, demands for downsizing and weight reduction of semiconductor devices have been increasing. On the other hand, DRAM (Dynamic Random Access Memory)
In such a semiconductor memory device, the area of the semiconductor integrated circuit chip is increasing with the increase in capacity. Under such circumstances, various methods have been conventionally proposed in order to improve the mounting density of the mounting substrate of the semiconductor package. Specifically, there are a method of mounting individual semiconductor packages in close proximity to each other in a two-dimensionally high-density mounting manner, and a method of mounting a semiconductor package on both sides of a mounting substrate using a double-sided mounting substrate. In addition, regarding the structure of the semiconductor package itself, the QFP (Quad Flat
Package) and the CSP (Ch
ip Size Package) is proposed.

FIG. 12 is a schematic sectional view showing an example of a conventional semiconductor package. A conventional semiconductor package will be described with reference to FIG.

Referring to FIG. 12, semiconductor package 10
Reference numeral 0 includes a semiconductor integrated circuit chip 101, an interposer substrate 103, a mold resin 104, and solder balls 105. The semiconductor integrated circuit chip 101 is connected to the interposer substrate 103 using wires 102. The semiconductor integrated circuit chip 101 and the wire 102 are sealed with a mold resin 104. Then, solder balls 105 that are electrically connected to the semiconductor integrated circuit chip 101 and that act as electrodes are arranged on the back surface of the interposer substrate 103. Here, a flexible substrate can be used as the interposer substrate 103. Then, such a semiconductor package 100 is mounted on the mounting substrate 160 by connecting the electrodes 161 formed on the mounting substrate 160 and the solder balls 105.

[0005]

As described above, various attempts have heretofore been made to improve the packaging density of semiconductor packages. However, in the conventional semiconductor package as shown in FIG.
At 60, the semiconductor package can be mounted only two-dimensionally. As a result, since the area of the mounting substrate is limited, there is a limit in improving the mounting density depending on the semiconductor package as shown in FIG.
Therefore, it has become difficult to meet the demands for downsizing and weight reduction, which have become stronger and stronger in recent years.

Therefore, conventionally, if the area for mounting the semiconductor package is still insufficient even when double-sided mounting is performed on the mounting board, another mounting board has been prepared. The use of such another mounting board not only hinders downsizing, weight reduction, and thinning of a product using this mounting board, but also causes a cost increase.

Further, in the conventional semiconductor package as shown in FIG. 12, it is necessary to form the bonding pad electrode on the interposer substrate 103 outside the region where the semiconductor integrated circuit chip 101 is mounted. Therefore, the interposer substrate 10 having an area larger than the area occupied by the semiconductor integrated circuit chip 101.
It was necessary to use 3. Further, since it is necessary to provide a mold die contact region for forming the mold resin 104 on the peripheral portion of the interposer substrate 103, the size of the interposer substrate 103 is the semiconductor integrated circuit chip 10.
It was necessary to make it larger than 1. Therefore, it has been difficult to sufficiently satisfy the requirements for downsizing and weight reduction as described above.

Furthermore, such an interposer substrate 1
Therefore, there is also a problem that the material cost of the semiconductor package becomes high. Therefore, it is difficult to provide an inexpensive semiconductor package.

Further, when the semiconductor package as shown in FIG. 12 is formed, it is necessary to package the semiconductor integrated circuit chips 101 cut out from the semiconductor wafer one by one. Therefore, the process of manufacturing the semiconductor package becomes complicated, and it is difficult to improve the productivity in the process of manufacturing the semiconductor package.

Further, in Japanese Unexamined Patent Publication No. 9-102561, a semiconductor integrated circuit chip is die-bonded to a rough frame material in which thin plate-shaped leads are embedded in the peripheral portion thereof, and the electrodes of the semiconductor integrated circuit chip and the above-mentioned thin plate-shaped material. There is proposed a semiconductor package in which a semiconductor integrated circuit chip is resin-molded after connecting the lead and the lead by wire bonding. According to the semiconductor package proposed in Japanese Patent Laid-Open No. 9-102561, it is possible to stack a plurality of semiconductor packages and mount them on a mounting board. As a result, the mounting density can be improved.

However, in the semiconductor package proposed in Japanese Unexamined Patent Publication No. 9-102561, a rough frame material (interposer substrate) having an area larger than the area of the semiconductor integrated circuit chip, like the semiconductor package shown in FIG. Is used. In addition, a complicated processing step of embedding thin plate-shaped leads in this rough frame material is performed. Therefore, although the packaging density can be improved, the material cost is high and it is difficult to provide an inexpensive semiconductor package. Also, since the semiconductor integrated circuit chip is packaged after being cut out from the semiconductor wafer,
Similar to the semiconductor package shown in FIG. 12, it is difficult to realize high productivity because the manufacturing process of the semiconductor package is complicated.

The present invention has been made to solve the above problems, and one object of the present invention is to:
An object of the present invention is to provide a semiconductor laminated package which can improve the packaging density and can realize low manufacturing cost and high productivity in the manufacturing process.

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A semiconductor laminated package according to the present invention comprises a laminated body including first and second semiconductor package units. The first semiconductor package unit includes a semiconductor integrated circuit chip, a first sealing resin body, and a first external connection terminal. The semiconductor integrated circuit chip has a main surface and sidewalls and includes a bonding pad electrode formed on the main surface. The first sealing resin body is formed on the main surface of the semiconductor integrated circuit chip so as to cover the bonding pad electrode, and has a side wall located substantially flush with the side wall of the semiconductor integrated circuit chip. The first external connection terminal is electrically connected to the bonding pad electrode and is formed on the side wall of the first sealing resin body. The second semiconductor package unit includes a semiconductor integrated circuit chip, a second sealing resin body, and a second external connection terminal. The semiconductor integrated circuit chip has a main surface and sidewalls and includes a bonding pad electrode formed on the main surface. The second sealing resin body is formed on the main surface of the semiconductor integrated circuit chip so as to cover the bonding pad electrode, and has a side wall located substantially flush with the side wall of the semiconductor integrated circuit chip. Second
The external connection terminal is electrically connected to the bonding pad electrode and is formed on the side wall of the second sealing resin body. In the stacked body, the second semiconductor package unit is stacked on the first semiconductor package unit such that the side wall of the second sealing resin body is located substantially flush with the side wall of the first sealing resin body. Tei Ru.

As described above, according to the semiconductor laminated package including the laminated body in which the first and second semiconductor package units are laminated, a plurality of semiconductor package units are mounted on the mounting substrate in an area occupied by one semiconductor package unit. Can be implemented. That is, it becomes possible to mount a plurality of semiconductor integrated circuit chips on the mounting substrate without increasing the area occupied by the semiconductor laminated package on the mounting substrate. As a result, the mounting density of the semiconductor circuit chips on the mounting board can be improved.
Moreover, since the number of stacked semiconductor package units in the stacked body can be set arbitrarily, the mounting density of the semiconductor stacked packages can be increased by increasing the number of stacked semiconductor package units.

Further, since the laminated body is formed by directly laminating the first and second semiconductor package units, it is necessary to prepare an interposer substrate larger than the semiconductor integrated circuit chip for each semiconductor integrated circuit chip as in the conventional case. Absent. As a result, the occupied area of the semiconductor laminated package can be made smaller than that of the conventional semiconductor laminated package. Moreover, the number of components of the semiconductor laminated package can be reduced. As a result, downsizing and weight reduction of the semiconductor laminated package can be achieved.

Further, since it is not necessary to prepare an interposer substrate for each semiconductor integrated circuit chip, the material cost can be reduced as compared with the conventional case.

Further, in the conventional semiconductor package, after the semiconductor integrated circuit chips are separated, steps such as forming a sealing resin body and wire bonding are performed for each semiconductor integrated circuit chip. However, in the semiconductor package unit used for the semiconductor laminated package according to the present invention, as shown in the method of manufacturing the semiconductor package unit described later, the sealing resin body is not removed from the semiconductor integrated circuit chip before cutting the semiconductor integrated circuit chip from the semiconductor wafer. Therefore, the packaging process can be simplified as compared with the conventional case. Therefore, the productivity of the manufacturing process of the semiconductor package unit can be improved, and as a result, the productivity of the manufacturing process of the semiconductor laminated package can be improved.

The upper SL semiconductors stacked package is not good also comprise at least one electrically connected to an external connection means of the first and second external connection terminals.

In this case, the mounting substrate and the semiconductor laminated package can be easily electrically connected via the external connecting means. As a result, the semiconductor laminated package can be easily mounted on the mounting substrate.

[0049] In the above SL semiconductors stacked package may laminate have a laminate sidewall including a sidewall of the first sidewall and the second sealing resin of the resin portion, an external connection means May include a flexible substrate, a connecting wire, and a lead wire. The flexible substrate may be arranged so as to face the side wall of the laminate. The connection line may be formed on the surface of the flexible substrate and may be electrically connected to at least one of the first and second external connection terminals.
Leads but it may also be electrically connected to the connection line.

In this case, since the flexible substrate arranged so as to face the side wall of the laminated body is used as the external connection means, the occupied area of the semiconductor laminated package can be made smaller than in the case where the conventional interposer substrate is used. You can As a result, the mounting density when mounting the semiconductor laminated package on the mounting substrate can be further increased.

[0051] In the above SL semiconductors stack package, and at least one a connecting line of the first and second external connection terminals may be electrically connected by the anisotropic conductive adhesive.

In this case, an anisotropic conductive adhesive is previously arranged on the side wall of the laminated body, and the flexible substrate as described above is heated and pressure-bonded to the side wall of the laminated body.
At least one of the first and second external connection terminals can be easily connected to the connection line on the surface of the flexible substrate. As a result, the semiconductor laminated package can be easily formed.

[0053] In the above SL semiconductors stack package, and at least one a connecting line of the first and second external connection terminals may be electrically connected by soldering.

[0054] In the above SL semiconductors stacked package, the surface of the flexible substrate, a region other than the connection line portion to be connected to the first and second external connection terminals may be covered with an insulator. A resist may be used for this insulator.

In this case, it is possible to prevent the occurrence of a defect such that a region other than the region originally connected to the external connection terminal on the flexible substrate is short-circuited with the external connection terminal of the semiconductor package unit or the semiconductor integrated circuit chip.

[0056] In the above SL semiconductors stacked package, connecting lines and the lead wire may include a nickel plating layer and a gold plating layer.

In this case, it is possible to improve the reliability of the electrical connection between the external connection terminal and the connection line of the semiconductor package unit and the electrical connection between the lead wire and the electrode formed on the mounting substrate. it can.

[0058] In the above SL semiconductors stacked package, at least the connecting line portion or connected one with the first and second external connection terminals, projecting laminate sidewall side than a region other than the connection line portion It may include parts. Further, the protruding portion may include at least one layer selected from the group consisting of a copper plating layer, a nickel plating layer and a gold plating layer.

In this case, since the connecting line portion electrically connected to at least one of the first and second external connecting terminals includes the protruding portion, at least one of the first and second external connecting terminals is included. The electrical connection between one of them and the connection line can be made more reliably.

[0060] In the above SL semiconductors stacked package may tip portion of the lead wire protrude below the bottom surface of the laminate.

Here, consider a case where the semiconductor laminated package is mounted on the mounting substrate so that the bottom surface of the laminated body faces the surface of the mounting substrate. In this case, by adjusting the position of the semiconductor laminated package with respect to the mounting board, the tip of the lead wire connected to the electrode on the mounting board can be pressed by the electrode of the mounting board. Therefore, the solder reflow connection can be used in the connection between the tip of the lead wire and the electrode of the mounting board, as in the case of a normal plastic package. Further, since the tip portion of the lead wire is pressed by the electrode of the mounting board as described above, the reliability of the electrical connection between the tip portion of the lead wire and the electrode of the mounting board is improved. be able to.

[0062] In the above SL semiconductors stacked package, the distal end portion of the lead wire may be curved so as to be located below the bottom of the stack.

In this case, the area occupied by the semiconductor laminated package can be made smaller than that of the semiconductor laminated package having a structure in which the tips of the lead wires are spread outside the region occupied by the laminated body. As a result, the mounting density when mounting the semiconductor laminated package on the mounting substrate can be further increased.

[0064] In the above SL semiconductors stacked package, the external connection means may comprise an insulator film and a conductive film. The conductor film may be electrically connected to at least one of the first and second external connection terminals and may be formed to extend from above the sidewall of the laminate to above the bottom surface of the laminate. Insulation film, and between the conductor film and the laminate sidewall conductive film and but it may also be formed so as to be interposed and between the bottom of the stack.

In this case, the conductor film formed on the side wall of the laminated body and the bottom surface of the laminated body can electrically connect the semiconductor laminated package and the mounting substrate. The area occupied by the package can be reduced. As a result,
The mounting density when mounting the semiconductor laminated package on the mounting substrate can be further increased.

[0066] In the above SL semiconductors stacked package, part of which is formed on the bottom surface of the laminate conductive film is electrically connected to at least one of the plurality of electrodes arranged in a matrix form on the bottom surface of the stack It may have been done.

[0067] In the above SL semiconductors stacked package may include a solder ball electrodes.

In this case, the electrical connection between the semiconductor laminated package and the electrodes formed on the mounting substrate can be easily performed.

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BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a schematic sectional view showing Embodiment 1 of a semiconductor package unit according to the present invention. The semiconductor package unit will be described with reference to FIG.

Referring to FIG. 1, a semiconductor package unit 10 according to the present invention comprises a semiconductor chip 11 as a semiconductor integrated circuit chip, wires 13a and 13b made of gold, and a sealing resin body 15. Bonding pad electrodes 12a and 12b are formed on the main surface of the semiconductor chip 11 on which the semiconductor integrated circuit is formed. Wires 13 are formed on the bonding pad electrodes 12a and 12b, respectively.
a and 13b are connected by wire bonding. Bonding pad electrodes 12a and 12b and wires 13a and 13 are formed on the main surface of the semiconductor chip 11.
A sealing resin body 15 is formed so as to cover b. The wires 13a and 13b are bonded pad electrodes 12a,
It is formed so as to extend from above 12b to the side wall of the sealing resin body 15. The cross sections of the wires 13 a and 13 b are exposed on the side wall of the sealing resin body 15. The exposed cross sections of the wires 13a and 13b serve as side wall electrodes 14a and 14b as external connection terminals.

At this time, on the side wall of the sealing resin body 15, the side wall electrodes 14a and 14b are located substantially at the center in the thickness direction of the sealing resin body 15. Here, it is preferable that the side wall electrodes 14a and 14b are arranged at a sufficient distance from the upper surface of the semiconductor chip 11. this is,
This is to prevent a short circuit between the semiconductor chip 11 and the side wall electrodes 14a and 14b when configuring a semiconductor laminated package described later. Therefore, the distance L1 between the upper surface of the semiconductor chip 11 and the sidewall electrodes 14a and 14b is 50.
It is preferably at least μm. This can be realized by setting the loop height of the wires 13a and 13b to 50 μm or more.

Similarly, the distance L2 between the side wall electrodes 14a and 14b and the upper surface of the sealing resin body 15 is preferably 50 μm or more in order to secure sufficient insulation.

Here, in such a semiconductor package unit 10, since there is no protruding portion on the side wall of the sealing resin body 15, the handling property is improved as compared with the conventional plastic package. Also, handling problems in conventional plastic packages, such as QF
It is possible to prevent an accident such as a lead portion deformation accident at P or the like, or a solder ball missing accident at the time of handling in CSP or the like. It should be noted that the semiconductor package unit 10 as shown in FIG. 1 is not normally mounted on the mounting board in the same form.

As will be described later, a plurality of semiconductor package units 10 can be stacked to obtain a semiconductor stacked package that can be mounted on a mounting board.
It is also possible to obtain the semiconductor package unit 10 having the form as shown in (1) and set and use the number of stacked semiconductor package units 10 in the semiconductor stacked package according to the required function of the product.

Next, a method of manufacturing the semiconductor package unit shown in FIG. 1 will be described. 2 to 4 are schematic perspective views for explaining a method for manufacturing the semiconductor package unit shown in FIG.

As shown in FIG. 2, semiconductor integrated circuit forming regions 11a to 11d to be semiconductor chips 11 (see FIG. 1) are formed on the main surface of semiconductor wafer 20. In each of the semiconductor integrated circuit forming regions 11a and 11b, the bonding pad electrode 12 is formed on the main surface of the semiconductor wafer 20.
a, 12b, 12d and 12e are formed. In addition,
Bonding pad electrodes are similarly formed in the semiconductor integrated circuit formation regions 11c and 11d. Also,
Dummy bonding pad electrodes 12c and 12f are formed on the main surface of the semiconductor wafer 20 in regions located on the outer peripheral side of the semiconductor integrated circuit forming regions 11a to 11d. Then, the semiconductor integrated circuit forming region 11
A dicing line 21 is formed in the boundary region of a to 11d. The semiconductor integrated circuits and the bonding pad electrodes 12a to 12f inside the semiconductor integrated circuit formation regions 11a to 11d are formed by the same method as the conventional method for manufacturing a semiconductor device.

Then, as shown in FIG. 2, the bonding pad electrode 12 is formed so as to cross the dicing line 21.
The wires a to 12f are connected by wires 13a to 13c made of gold. A conventional wire bonding device can be used in this connection step.

Here, as for the bonding pad electrodes formed on the semiconductor wafer 20, as shown in FIG. 5, in addition to the bonding pad electrode group 19 capable of inputting and outputting a common signal, semiconductor package units are laminated. At this time, a chip select bonding pad electrode group 17 for selecting each of the stacked semiconductor package units may be formed. Here, FIG. 5 is a schematic plan view for explaining the bonding pad electrode formed on the main surface of the semiconductor wafer 20 and its peripheral structure in the first step of the method for manufacturing the semiconductor package unit shown in FIG. Is.

Referring to FIG. 5, the semiconductor wafer 20 (see FIG.
A bonding pad electrode group 19 capable of inputting / outputting a common signal and a chip selecting bonding pad electrode group 17 are formed on the main surface (see FIG. 3) so as to face each other with the dicing line 21 interposed therebetween. A bonding pad electrode group 19 capable of inputting / outputting a common signal is composed of bonding pad electrodes 12b and 12d. And
The bonding pad electrodes 12b and 12d are the wires 1
It is connected by 3b. Therefore, after the semiconductor wafer 20 is separated into the semiconductor package units, in the semiconductor integrated circuit forming region in which the bonding pad electrodes 12b are formed and in the semiconductor integrated circuit forming region in which the bonding pad electrodes 12d are formed, the respective bonding pads are formed. The side wall electrodes 14b (see FIG. 1) connected to the electrodes 12b and 12d can be arranged substantially at the same side wall of the sealing resin body.

Further, on the main surface of the semiconductor wafer 20,
As described above, the chip select bonding pad electrode group 17 is arranged so as to face each other across the dicing line 21.
Are formed. The chip select bonding pad electrode group 17 includes chip select bonding pad electrodes 17a to 17c. The chip select bonding pad electrode group 17 is used to select individual stacked semiconductor package units when the semiconductor package units are stacked. Here, three sets of chip select bonding pad electrodes 17a to 17c are formed with the dicing line 21 interposed therebetween. However, by changing the position of the wire 13d by forming the same number of pairs of chip select electrodes as the number of stacked semiconductor package units, the position of the side wall electrode which is the cross section of the wire 13d can be changed. You can Therefore, it is possible to form the same number of types of semiconductor package units as the above-mentioned number of stacked layers, in which the positions of the side wall electrodes are different. As a result, when a plurality of semiconductor package units are stacked to form a semiconductor stacked package, it is possible to easily send a signal individually to each stacked semiconductor package unit. This is for the following reasons.

That is, when the side wall electrodes 14a and 14b (see FIG. 1) of the stacked semiconductor package units are all located at the same horizontal position on the side wall of the sealing resin body,
In order to individually transmit a signal to each of the stacked semiconductor package units 10, a connection line corresponding to the side wall electrode of each semiconductor package unit in a one-to-one correspondence is formed in the semiconductor stacked package using a complicated pattern. Had to do. However, regarding the semiconductor package units stacked in this way, by changing the chip select bonding pad electrodes 17a to 17c to which the wire 13d is connected for each semiconductor package unit, the cross section of the wire 13d which becomes the sidewall electrode of the semiconductor package unit is changed. The horizontal position of can be changed. As a result, it is possible to individually send a signal to each semiconductor package unit by using a flexible substrate having only parallel connection lines without forming a complicated circuit pattern as described above. As a result, since it is not necessary to form a complicated connection line pattern on the flexible substrate used in the semiconductor laminated package, it is possible to reduce the manufacturing cost of the semiconductor laminated package.

More specifically, for example, with reference to FIG. 5, of the semiconductor package units stacked in the semiconductor stacked package, the semiconductor package unit arranged in the first stage is bonded to the chip select bonding pad electrode. 17a are connected by wire 13d,
In the semiconductor package unit stacked in the second stage, the chip select bonding pad electrodes 17b are connected by the wire 13d. In this way, for the stacked semiconductor package units, if the chip select bonding pad electrodes to be connected by the wires 13d are determined in accordance with the number of stacked layers, the wire 1 is connected to each of the stacked semiconductor package units.
The position of 3d, that is, the position of the side wall electrode on the side wall of the sealing resin body of the semiconductor package unit in the horizontal direction can be changed. Note that the wire 13d
The chip select bonding pad electrode not connected to is a bonding pad electrode not connected to the side wall electrode which is the external connection terminal in the semiconductor package unit.

Then, a plurality of parallel connection lines extending substantially parallel to the stacking direction of the semiconductor package units are prepared at positions corresponding to the regions where the chip select electrode group 17 is formed. As a result, if these parallel connection lines and the side wall electrode which is the cross section of the wire 13d are electrically connected,
By selecting these parallel connection lines, signals can be individually transmitted to the stacked semiconductor package units.

As shown in FIG. 6, in the chip select bonding pad electrode group 18, dummy bonding pad electrodes 18a to 18c are provided at positions facing the chip select bonding pad electrode 16 with the dicing line 21 interposed therebetween. You may form. FIG. 6 is a schematic plan view showing a modified example of the bonding pad electrode formed on the main surface of the semiconductor wafer 20 shown in FIG. 5 and its peripheral structure. Here, it is preferable to prepare the same number of bonding pad electrodes 18a to 18c as the dummy as the number of stacked semiconductor package units in the semiconductor stacked package similar to the chip select electrode shown in FIG. Then, for each of the stacked semiconductor package units, by selecting the bonding pad electrodes 18a to 18c connected to the chip select electrode 16 and the wire 13e, each of the stacked semiconductor package units is stacked similarly to the case shown in FIG. It becomes possible to individually transmit signals to the semiconductor package unit.

Then, following the steps as shown in FIG. 2, the semiconductor wafer 20 is placed inside the molding die,
The sealing resin body 15 is arranged on the main surface of the semiconductor wafer 20 on which the bonding pad electrodes 12a to 12f are formed. Then, the sealing resin body 15 is cured. As a result, a structure as shown in FIG. 3 is obtained.

At this time, in the sealing process using the molding die, since the film thickness of the sealing resin body 15 formed can be easily controlled, the semiconductor package unit 10
The thickness of the sealing resin body 15 (see FIG. 1) can be controlled to be the minimum necessary thickness. As a result, the height of the semiconductor package unit 10 can be made smaller. Further, since the upper surface of the sealing resin body 15 can be easily flattened, the film thickness of the sealing resin body 15 can be made uniform. As a result, the sealing resin body 15 having the required film thickness can be reliably formed, so that the reliability of the semiconductor package unit can be improved.

In this encapsulation step, instead of using the molding die, a frame for damming the encapsulating resin body is formed on the peripheral edge of the semiconductor wafer 20, and then the liquid resin is applied to the semiconductor wafer. The liquid resin may be poured onto the main surface of 20, and the liquid resin may be cured. In this case, it is not necessary to add a release agent to the sealing resin body 15. As a result, the semiconductor wafer 20 and the sealing resin body 1
The adhesion strength with No. 5 can be improved. For this reason,
The reliability of the semiconductor package unit 10 can be improved.

Further, in order to further improve the flatness of the upper surface of the sealing resin body 15, the upper surface of the sealing resin body 15 is polished before the dicing step described below, whereby The top surface may be planarized.

Next, as shown in FIG. 4, a dicing step of cutting the semiconductor wafer 20 and the sealing resin body 15 at the position of the dicing line 21 (see FIG. 2) using the dicing blade 22 is carried out. At this time, the wires 13a to 1 formed so as to cross the dicing line 21.
3c is also cut at the same time.

By thus separating the semiconductor integrated circuit formation regions 11a to 11d, the semiconductor package unit 10 (see FIG. 1) can be obtained. And such a semiconductor package unit 10
On the side wall of the sealing resin body 15, the cross-sections of the wires 13a to 13c made of gold are exposed and become the side wall electrodes 14a and 14b for external connection as shown in FIG.

Here, in order to make the outer diameter dimension of the semiconductor package unit 10 uniform, the surface of the semiconductor package unit 10 may be polished after the dicing step, if necessary.

The dicing line 21 (see FIG. 2)
If any position on the outer periphery of the semiconductor wafer 20 is used as a reference point for determining the position of the dicing line 21 after the encapsulating resin body 15 is formed.
Since the position of can be detected, accurate dicing can be performed. In addition, the dicing line 2 is used for the molding die used when forming the sealing resin body 15.
If the index mark is formed in advance so as to match the position of 1, the position of the dicing line 21 on the semiconductor wafer 20 and the position of the index mark on the molding die are aligned when the sealing resin body 15 is formed. be able to. In this way, since the index mark can be formed on the surface of the sealing resin body 15 after the sealing resin body 15 is formed, the dicing line can be engraved with the index mark as a reference point. . Accurate dicing can also be performed by such a method.

Next, a semiconductor laminated package according to the present invention obtained by laminating the semiconductor package units 10 shown in FIG. 1 will be described. FIG. 7 is a schematic sectional view showing Embodiment 1 of the semiconductor laminated package according to the present invention.

Referring to FIG. 7, a semiconductor laminated package 30 according to the present invention is a laminated body composed of laminated semiconductor package units 10a to 10c and an external connecting means arranged on the side wall of the laminated body. The flexible substrates 40a and 40b are provided. In the stacked body, the semiconductor package units 10a to 10c are stacked in the vertical direction using the adhesive 31. As a result, on the side wall of the stacked body, the semiconductor package units 10a-1
The sidewall electrodes 14a are arranged at equal intervals at a pitch substantially equal to the height of 0c.
~ 14f is present.

The flexible substrates 40a and 40b have substantially the same structure, and the polyimide substrate 42
a, 42b, connecting wires 41a, 41b, resists 44a, 44b as insulators, and mounting lead wires 43a, 43b.
With. Connection lines 41a and 41b are formed on the polyimide base materials 42a and 42b. Connection lines 41a, 4
Resists 44a and 44b are formed on 1b.
The mounting lead wires 43a and 43b are connection wires 41a and 41b.
Electrically connected to.

The connection lines 41a and 41b are respectively connected to the sidewall electrodes 14a to 14f and the anisotropic conductive adhesive 50a.
It is electrically connected using 50b. Here, the anisotropic conductive adhesives 50a and 50b are the conductive particles 51a and 5a.
1b and resins 52a and 52b. The side wall electrodes 14a to 14f are electrically connected to the connection lines 41a and 41b via the conductive particles 15a and 15b. The mounting lead wires 43 a and 43 b, which are the tip portions of the connection wires 41 a and 41 b, are the electrodes 6 formed on the mounting substrate 60.
It is a terminal for connecting to 1a and 61b. This electrode 6
1a, 61b and the mounting lead wires 43a, 43b are connected by solder 62.

At this time, the flexible substrates 40a, 40
In b, the regions other than the regions electrically contacting the side wall electrodes 14a to 14f of the laminated body are formed into the resists 44a, 44.
It is preferable to coat with b. By doing so, it is possible to prevent the problem that the connection lines 41a and 41b are short-circuited with a region of the semiconductor chip 11 (see FIG. 1) other than the sidewall electrodes 14a to 14f.

In the flexible boards 40a and 40b, the connecting wires 41a and 41b and the mounting lead wires 43 are provided.
It is preferable to apply nickel plating and gold plating to the surfaces of a and 43b. In this way, the connection line 41
It is possible to improve the reliability of the electrical connection between the a and 41b and the sidewall electrodes 14a to 14f and the electrical connection between the mounting lead wires 43a and 43b and the electrodes 61a and 61b.

Here, as the connection lines 41a and 41b,
A connecting wire made of copper can be used. Then, the connection lines 41a and 41b connected to the sidewall electrodes 14a to 14f.
In the region (2), it is preferable to form a portion protruding toward the side wall electrodes 14a to 14f. In this way, the side wall electrodes 14a to 14f and the connection line 41 can be more reliably formed.
It is possible to make an electrical connection between a and 41b.
In addition, the connection lines 41a and 41b and the sidewall electrodes 14a to 1
It is also possible to easily perform the step of electrically connecting to 4f.

In addition, the sidewall electrodes 1 of the connection lines 41a and 41b.
4a to 14f, copper plating,
It is preferable to apply nickel plating and gold plating.
With this configuration, the protrusion can be easily formed, and at the same time, the connection lines 41a and 41b and the side wall electrodes 14a to 14a.
The reliability of the electrical connection with 14f can be improved.

As described above, in the semiconductor laminated package 30 according to the present invention, three semiconductor package units 10 are provided.
Since it has a laminated body in which a to 10c are laminated, a plurality of semiconductor package units 10a to 10a
10c can be mounted on the mounting substrate 60. As a result, the mounting density of the semiconductor chips 11 (see FIG. 1) on the mounting board 60 can be improved.

Further, the semiconductor package units 10a ...
Since the laminated body is formed by directly laminating 10c, it is not necessary to prepare an interposer substrate larger than the semiconductor chip for each semiconductor chip as in the conventional case. As a result, the occupied area of the semiconductor laminated package 30 can be made smaller than that of the conventional semiconductor laminated package.

Further, the number of constituent parts of the semiconductor laminated package 30 can be reduced as compared with the conventional one. As a result, downsizing and weight reduction of the semiconductor laminated package 30 can be achieved.

Since it is not necessary to prepare an interposer substrate for each semiconductor chip, the material cost can be reduced as compared with the conventional case.

Next, a method of manufacturing the semiconductor laminated package according to the present invention shown in FIG. 7 will be described.

First, the semiconductor package units 10a to 10c having the same structure as the semiconductor package unit 10 shown in FIG. 1 are vertically stacked with the adhesive 31. At this time, the stacked semiconductor package units 1
In order to align the position of the side wall of the laminated body composed of 0a to 10c (the laminated body side wall), the laminated body side wall may be polished.

Next, as shown in FIG.
A film-shaped anisotropic conductive adhesive (ACP) 50a made of conductive particles 51a and resin 52a is attached on the side wall of the laminated body where a, 14c, and 14e are exposed. And
The flexible substrate 40 is placed on the anisotropic conductive adhesive 50a.
Place a. At this time, the position of the side wall electrodes 14a, 14c, 14e in contact with the side wall electrodes 14a, 14c, 14e in the connection line 41a of the flexible substrate 40a is aligned. Here, FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor laminated package shown in FIG.

Next, the laminated body on which the flexible substrate 40a is arranged is set on the bonding stage 81. Then, the flexible substrate 40a is pressed against the stacked body while being heated using the bonding tool 80. In this manner, the electrodes 14a, 14c, 14e and the connection line 41a are electrically connected via the conductive particles 51a, and at the same time, the resin 52a is thermally cured to mechanically bond the laminate and the flexible substrate 40a. Connecting. By performing such a process on the side surface of the stacked body where the sidewall electrodes 14a to 14f are exposed, the semiconductor stacked package 30 as shown in FIG. 7 can be obtained.

Since the resist 44a as an insulator such as a solder resist is previously formed on the flexible substrate 40a in a region other than the region in contact with the side wall electrodes 14a, 14c, 14e, the flexible substrate 40a is laminated. In the step of fixing to, it is possible to prevent the occurrence of the problem that the semiconductor chips of the semiconductor package units 10a to 10c and the connection line 41a are short-circuited.

Next, the lead wires 43a and 43b for mounting are lead-formed into a gull wing type as shown in FIG. Then, as shown in FIG. 7, the adhesive 70 is applied in advance to the mounting substrate 60 at the position where the semiconductor laminated package 30 is mounted. Then, the mounting lead wires 43a and 43b of the semiconductor laminated package 30 and the electrodes 61a and 61b of the mounting substrate 60 are aligned with each other, and the semiconductor laminated package 30 is placed on the adhesive 70. Then, the mounting substrate 60 and the semiconductor laminated package 30 are mechanically bonded by curing the adhesive 70. With this configuration, the semiconductor laminated package 30 can be firmly fixed to the mounting substrate 60 using the adhesive 70, and thus the mounting substrate 60 including the semiconductor laminated package 30 has durability against mechanical shock such as vibration. Can be increased.

After that, the electrodes 61a and 61b to which the solder 62 has been supplied in advance and the mounting lead wires 43a and 43b are heated and pressed by a lead bonding tool to perform solder connection. In this way, the semiconductor laminated package 30 can be mounted on the mounting substrate 60 as shown in FIG.

Here, if the mounting lead wires 43a and 43b are shaped so as to project below the bottom surface (bottom surface of the semiconductor package unit 10a) of the stacked body as shown in FIG. 7, the semiconductor stacked package 30 is mounted. When mounted on the substrate 60, the mounting lead wires 43a and 43b are connected to the electrodes 61a,
It is in a state of being pressed to 61b. As a result, the mounting lead wires 43a and 43b and the electrodes 61a and 61 are formed by using the solder reflow connection as in the ordinary plastic package.
b can be connected.

In the laminated body of the semiconductor laminated package 30 according to the present invention, three semiconductor package units 1 are used.
Although 0a to 10c are stacked, a stacked body may be configured by stacking three or more semiconductor package units. By doing so, it is possible to realize higher mounting density in a limited mounting area. As a result, downsizing and weight reduction of the semiconductor device can be easily achieved.

Further, the mounting board 60 as an external connecting means.
In the connecting means for connecting to the laminated body, since the thin flexible substrates 40a and 40b arranged so as to face the side wall of the laminated body are bonded to the laminated body, the semiconductor laminated package is further improved as compared with the case where the conventional interposer substrate is used. Downsizing and weight reduction of 30 can be achieved. Further, since no interposer substrate is required for each of the semiconductor chips 10a to 10c, the material cost can be reduced as compared with the conventional case. As a result, it is possible to provide an inexpensive semiconductor laminated package.

Since the encapsulating resin body 15 of the semiconductor package unit 10 (see FIG. 1) is formed before cutting the semiconductor chip 11 from the semiconductor wafer 20,
Encapsulating resin 1 for each semiconductor chip as before
It is not necessary to separately perform the steps of forming 5 and forming electrodes. As a result, the semiconductor package unit 10
The manufacturing process of can be simplified. Therefore, it is possible to improve the productivity in the manufacturing process of the semiconductor package unit 10.

In the first embodiment of the present invention,
Although the film-shaped anisotropic conductive adhesives 50a and 50b are used, a liquid anisotropic conductive adhesive may be used. In addition, if necessary, the surfaces of the flexible substrates 40a and 40b and the sidewall electrodes 14 of the semiconductor package units 10a to 10c may be used.
The surface of a to 14f may be plated. And
Connection lines 41a, 41 of the flexible substrates 40a, 40b
As an electrical connection method between the b and the side wall electrodes 14a to 14f, a connection method using solder or a connection method by pressure contact may be used. In addition, the material of the connecting wires 41a and 41b and 4
By changing the material of the plating layer formed on the surfaces of 1a and 41b, the side wall electrodes 14a to 14f and the connecting wire 41 are formed.
a, 41b are connected to Au-Sn connection, Au-Al
A connection or an Au-Au connection may be used. In this case, in place of the anisotropic conductive adhesive, a liquid thermosetting resin, a film-shaped thermosetting resin, or a thermoplastic resin can be used if necessary.

(Second Embodiment) FIG. 9 is a schematic sectional view showing a second embodiment of a semiconductor laminated package according to the present invention. The semiconductor stacked package will be described with reference to FIG.

Referring to FIG. 9, the semiconductor laminated package basically has the same structure as the semiconductor laminated package shown in FIG. However, in the semiconductor laminated package shown in FIG. 9, the semiconductor package unit 10a
10c, the wires 13a and 13b are made of copper. Further, the wires 13a and 13b made of copper, which are exposed on the side wall of the sealing resin body, are nickel-plated and gold-plated on their cross sections. As a result,
The side wall electrodes 23a to 23f are the semiconductor package unit 1
It includes a convex portion protruding from the side wall of the sealing resin body of 0a to 10c.

Therefore, in the semiconductor laminated package shown in FIG. 9, in addition to the effect obtained by the semiconductor laminated package according to the first embodiment of the present invention shown in FIG. 7, the semiconductor package units 10a to 10c are bonded by the adhesive 31. When stacking using the semiconductor package units 10a to 1
When the stacking position of 0c is displaced, the electrical connection between the side wall electrodes 23a to 23f and the connection lines 41a and 41b can be surely realized. This is the side wall electrodes 23a-2
When connecting the connection lines 41a and 41b to 3f, the convex portion of the side wall electrodes 23a to 23f is deformed due to the influence of the variation in the position of the side wall of the sealing resin body due to the displacement of the stacking position of the semiconductor package units 10a to 10c. This is because it can be absorbed. Therefore, it is not necessary to perform a polishing process or the like to align the positions of the side walls of the stacked body including the semiconductor package units 10a to 10c. As a result, the manufacturing process of the semiconductor laminated package can be simplified.

Further, in the semiconductor laminated package shown in FIG. 9, the mounting lead wires 43a and 43b are processed so as to be curved toward the lower side of the laminated body (below the semiconductor package unit 10a). Therefore, the occupied area of the semiconductor laminated package 30 can be made smaller than that of the semiconductor laminated package shown in FIG. As a result, it is possible to increase the mounting density of the semiconductor laminated packages 30 on the mounting board. The tip ends of the mounting lead wires 43a and 43b are polyimide base materials 42 fixed to the bottom surface of the laminate with adhesives 31a and 31b.
It is in contact with a and 42b.

As described above, according to the semiconductor laminated package shown in FIG. 9, in addition to the effect selected by the semiconductor laminated package according to the first embodiment of the present invention shown in FIG. Can be simplified, and at the same time, the area occupied by the semiconductor laminated package can be reduced.

The semiconductor laminated package shown in FIG. 9 can be basically manufactured by the same manufacturing method as that of the semiconductor laminated package shown in FIG.

In the semiconductor laminated package shown in FIG. 9, a liquid anisotropic conductive adhesive is used instead of the film-shaped anisotropic conductive adhesive as in the semiconductor laminated package shown in FIG. May be. If necessary, the surfaces of the flexible substrates 40a and 40b and the surfaces of the side wall electrodes 23a to 23f of the semiconductor package units 10a to 10c may be plated. In addition, the sidewall electrode 23a
In the connection between ~ 23f and the connection lines 41a, 41b,
Pressure contact or solder connection may be used.

(Third Embodiment) FIG. 10 is a schematic sectional view showing a third embodiment of a semiconductor laminated package according to the present invention. The semiconductor stacked package will be described with reference to FIG.

Referring to FIG. 10, semiconductor laminated package 32 functions as a laminated body in which semiconductor package units 10a to 10c are laminated, insulator films 90a and 90b, conductor films 91a and 91b as connection lines, and electrodes. Mounting solder balls 92a to 92d. Here, the semiconductor package units 10a to 10c basically have the same structure as the semiconductor package unit 10 shown in FIG. And this semiconductor package unit 1
The laminated body including 0a to 10c has the same structure as the laminated body in the semiconductor laminated package 30 illustrated in FIG. 7. Then, the semiconductor laminated package 32 shown in FIG.
Then, as the external connection means, the flexible substrate 4 in the semiconductor laminated package 30 as shown in FIGS.
Instead of 0a and 40b, conductor films 91a and 91b are formed on the sidewalls 34a and 34b and the bottom surface 35 of the stacked body. Specifically, the insulator films 90a and 90b are formed on the sidewalls 34a and 34b and the bottom surface 35 of the stacked body in regions other than the regions where the sidewall electrodes 14a to 14f are located. As the insulating films 90a and 90b, an organic insulating film such as polyimide, or silicon oxide, silicon nitride, silicon carbide or the like can be used. Then, conductor films 91a and 91b are formed on the sidewall electrodes 14a to 14f and the insulator films 90a and 90b. A thin film of copper, aluminum, gold, or the like can be used as the conductor films 91a and 91b. This conductor film 91
a and 91b are electrically connected to the side wall electrodes 14a to 14f, and are conductor film portions 36a to 36, which serve as mounting electrodes arranged in a matrix on the bottom surface 35 of the laminated body.
Including c. Mounting solder balls 92a to 92d are formed on the conductor film portions 36a to 36c. In this way, the semiconductor laminated package 32 is constructed.
The mounting solder balls 92 a to 92 d are electrically connected to the electrodes 61 a to 61 d formed on the mounting substrate 60, so that the semiconductor laminated package 32 is mounted on the mounting substrate 60.

Therefore, in the semiconductor laminated package 32 shown in FIG. 10, the same effect as the semiconductor laminated package shown in the first embodiment of the present invention can be obtained, and at the same time, the semiconductor laminated package 32 is occupied. The area can be reduced. As a result, the mounting density of the semiconductor laminated package on the mounting substrate can be further increased.

Next, a method of manufacturing the semiconductor laminated package shown in FIG. 10 will be described. First, the first embodiment of the present invention
By using the same method as the method for manufacturing the semiconductor laminated package 30 (see FIG. 7) in the above, a laminated body including the semiconductor package units 10a to 10c is formed.

Next, in the side walls 34a and 34b on which the side wall electrodes 14a to 14f of the laminated body are formed and the bottom surface 35,
Insulator films 90a and 90b are formed in regions other than the regions where the sidewall electrodes 14a to 14f are formed. As the insulating films 90a and 90b, an organic insulating film such as polyimide can be used as described above. Alternatively, silicon oxide, silicon nitride, or silicon carbide may be formed as the insulator films 90a and 90b by a sputtering method or a CVD method. Further, ceramics that can be fired at a low temperature may be formed as the insulating films 90a and 90b.

Next, conductor films 91a and 91b are formed in a predetermined pattern on the sidewall electrodes 14a to 14f and the insulator films 90a and 90b. This conductor film 91
The a and 91b may be thin films of copper, aluminum, gold or the like formed by using a sputtering method. Then, as described above, the conductor film portions 36a to 36c located on the bottom surface 35 of the laminated body of the conductor films 91a and 91b.
Serves as a mounting electrode. The conductor film portions 36a to 36c are arranged in a matrix on the bottom surface of the stacked body. The solder balls 92 for mounting are mounted on the conductor film portions 36a to 36c arranged in a matrix.
a to 92d are arranged. In this way, the semiconductor laminated package 32 can be obtained.

Next, the semiconductor laminated package 32 as described above is connected to the mounting substrate 60. In this case, the mounting board 6
On the electrodes 61a to 61d formed on the surface 0, plating or solder paste is previously supplied by printing. Such electrodes 61a to 61d and the semiconductor laminated package 32
The semiconductor laminated package 32 is arranged on the mounting substrate 60 so as to be aligned with the mounting solder balls 92a to 92d. Then, the mounting substrate 60 and the semiconductor laminated package 32 are heated in a solder reflow furnace. As a result, the solder is melted on the electrodes 61a to 61d, so that the conductor film portion 3 of the semiconductor stacked package 32 is melted.
6a to 36c and the electrodes 61a to 61d of the mounting substrate 60 are electrically connected, and at the same time, the semiconductor laminated package 32 can be fixed to the mounting substrate 60. In this way, the semiconductor laminated package 32 can be mounted on the mounting substrate 60.

Here, a nickel thin film may be formed on the conductor film portions 36a to 36c by a plating method or a sputtering method, and a gold thin film may be formed on the nickel thin film. In this case, the conductor film 91 is formed in the conductor film portions 36a to 36c during the heat treatment in the solder reflow furnace.
The material of a and 91b is the solder balls 92a to 92d for mounting.
It is possible to prevent the heat diffusion to. As a result, the reliability of the semiconductor laminated package 32 can be improved.

Further, in the semiconductor laminated package 32, it is preferable to form a coating film such as a resist on the surface other than the region where the mounting solder balls 92a to 92d are present. By doing so, the moisture resistance of the semiconductor laminated package 32 can be improved. Further, the semiconductor laminated package 32 can be protected from mechanical shock, and at the same time, the mounting solder balls 92a to 92d.
It is also possible to maintain a proper volume.

Also, as shown in FIG. 11, unlike the semiconductor laminated package shown in FIG. 10, a semiconductor laminated package 33 having a structure not using mounting solder balls is similar to the semiconductor laminated package 32 shown in FIG. The effect of can be obtained. Here, FIG. 11 is a schematic sectional view showing a modified example of the semiconductor laminated package shown in FIG. The semiconductor stacked package will be described with reference to FIG.

Referring to FIG. 11, semiconductor laminated package 33 basically has the same structure as semiconductor laminated package 32 shown in FIG. However, in the semiconductor laminated package 33 shown in FIG. 11, the conductor film portions 36a and 36b which are the mounting electrodes of the semiconductor laminated package 33 are directly connected to the electrodes 61a and 61b of the mounting electrode 60 by using solder 62. . Here, the conductor film portions 36a and 36b to be the mounting electrodes are formed to have a substantially rectangular shape at the peripheral portion of the bottom surface of the stacked body.

The semiconductor laminated package 3 having such a configuration
According to 3, the effect similar to that of the semiconductor laminated package shown in FIG. 10 can be obtained, and the structure of the semiconductor laminated package can be further simplified. As a result, the manufacturing cost of the semiconductor laminated package can be reduced, and at the same time, the manufacturing process can be simplified.

Here, the solder is used for the connection between the semiconductor laminated package 33 and the electrodes 61a and 61b of the mounting substrate 60, but a conductive adhesive or an anisotropic conductive adhesive is mounted on the mounting electrodes 61a and 61b. May be disposed, and the conductive film portions 36a and 36b and the electrodes 61a and 61b may be connected using this conductive adhesive or anisotropic conductive adhesive.

The insulator films 90a and 90b and the conductor films 91a and 91b in the semiconductor laminated package 33 shown in FIG. 11 are plated, sputtered, CVD, etc. as in the semiconductor laminated package shown in FIG. Can be formed by using. In the semiconductor laminated package shown in FIGS. 10 and 11, the film thickness of the insulator films 90a and 90b and the conductor films 91a and 91b can be set arbitrarily. In addition, the insulator film 90
Although polyimide and silicon oxide are used as a and 90b, the same effect can be obtained if other insulators are used. Although thin films such as copper are used as the conductor films 91a and 91b, the same effect can be obtained by using other conductive materials as the conductor films 91a and 91b.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiments but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

[0149]

As described above, according to the present invention, it is possible to obtain a semiconductor laminated package in which an arbitrary number of semiconductor package units can be laminated. As a result,
It is possible to increase the mounting density of the semiconductor package unit in a limited mounting area.

Further, since an interposer substrate having a size larger than that of a semiconductor chip, which has been conventionally required for each semiconductor package unit, is not required,
The occupied area of the semiconductor laminated package can be further reduced, and at the same time, the material cost can be reduced. Also,
As the external connection means of the semiconductor laminated package, since the flexible substrate arranged on the side wall of the laminated body where the semiconductor package units are laminated or the conductor film formed on the surface of the laminated body is used, the area occupied by the semiconductor laminated package can be reduced. At the same time, the manufacturing cost can be reduced.

[0151]

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor package unit according to the present invention.

FIG. 2 is a perspective schematic view for explaining the first step of the method for manufacturing the semiconductor package unit shown in FIG.

FIG. 3 is a schematic perspective view for explaining a second step of the method for manufacturing the semiconductor package unit shown in FIG.

FIG. 4 is a schematic perspective view for explaining a third step of the method for manufacturing the semiconductor package unit shown in FIG.

5 is a schematic plan view for explaining the bonding pad electrode formed on the main surface of the semiconductor wafer and its peripheral structure in the first step of the method for manufacturing the semiconductor package unit shown in FIG.

6 is a schematic plan view showing a modified example of a bonding pad electrode formed on the main surface of the semiconductor wafer shown in FIG. 5 and its peripheral structure.

FIG. 7 is a schematic sectional view showing the first embodiment of the semiconductor laminated package according to the present invention.

FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor laminated package shown in FIG.

FIG. 9 is a schematic sectional view showing a second embodiment of the semiconductor laminated package according to the present invention.

FIG. 10 is a schematic sectional view showing a third embodiment of the semiconductor laminated package according to the present invention.

FIG. 11 is a schematic cross-sectional view showing a modified example of the semiconductor laminated package shown in FIG.

FIG. 12 is a schematic sectional view showing an example of a conventional semiconductor package.

[Explanation of symbols]

10, 10a to 10c Semiconductor package unit 11 Semiconductor chips 11a to 11d Semiconductor integrated circuit forming regions 12, 12a to 12f Bonding pad electrodes 13a to 13e Wires 14a to 14f, 23a to 23f Side wall electrode 15 Sealing resin body 16, 17a to 17c Bonding pad electrodes 17 and 18 for chip select Bonding pad electrode groups 18a to 18c for chip select Bonding pad electrode 19 as a dummy Bonding pad electrode group 20 capable of inputting a common signal 20 Semiconductor wafer 21 Dicing line 22 Dicing blades 30, 32, 33 semiconductor laminated packages 31, 31a, 31b, 70 adhesives 34a, 34b side walls 35 bottom surfaces 36a to 36c conductor film portions 40a, 40b flexible substrates 41a, 41b connection lines 42a 42b Polyimide base material 43a, 43b Mounting lead wires 44a, 44b Resists 50a, 50b Anisotropic conductive adhesives 51a, 51b Conductive particles 52a, 52b Resin 60 Mounting substrate 61a, 61d Electrode 62 Solder 80 Bonding tool 81 Bonding stage 90a , 90b Insulator films 91a, 91b Conductor films 92a to 92d Mounting solder balls

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 2000-200859 (JP, A) JP 10-340974 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23 / 12,25 / 04-25/13 H01L 25/18

Claims (4)

(57) [Claims] 1. A laminated body including first and second semiconductor package units, wherein the first semiconductor package unit has a main surface and a side wall, and a bonding pad electrode formed on the main surface. A first integrated circuit chip including a semiconductor integrated circuit chip including: and a sidewall formed on the main surface of the semiconductor integrated circuit chip so as to cover the bonding pad electrode and located substantially flush with the sidewall of the semiconductor integrated circuit chip. And a second external connection terminal that is electrically connected to the bonding pad electrode and that is formed on a sidewall of the first sealing resin body. A semiconductor integrated circuit chip having a surface and a sidewall and including a bonding pad electrode formed on the main surface, and a main surface of the semiconductor integrated circuit chip A second encapsulating resin body formed to cover the bonding pad electrode and having a sidewall located substantially in the same plane as the sidewall of the semiconductor integrated circuit chip; electrically connected to the bonding pad electrode; And a second external connection terminal formed on the side wall of the second sealing resin body, wherein in the laminate, the side wall of the second sealing resin body is substantially the same as the side wall of the first sealing resin body. A semiconductor stacked package in which the second semiconductor package unit is stacked on the first semiconductor package unit so as to be located on the same plane. 2. The semiconductor laminated package according to claim 1 , further comprising an external connection unit electrically connected to at least one of the first and second external connection terminals. 3. The laminated body has a laminated body side wall including a side wall of the first encapsulating resin body and a side wall of the second encapsulating resin body, and the external connection means includes the laminated body. A flexible substrate arranged to face the side wall; a connection line formed on a surface of the flexible substrate and electrically connected to at least one of the first and second external connection terminals; The semiconductor laminated package according to claim 2 , further comprising a connecting wire and a lead wire electrically connected to the connecting wire. 4. The external connection means is electrically connected to at least one of the first and second external connection terminals and extends from above the side wall of the laminate to above the bottom surface of the laminate. An insulator film formed so as to be interposed between the conductor film and the sidewall of the laminate, and between the conductor film and the bottom surface of the laminate. The semiconductor laminated package according to claim 2 , comprising: