JP3371070B2 - Semiconductor switching device, semiconductor stack device and power conversion device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching device having a gate electrode and a gate driver for supplying a turn-off current between a gate electrode and a cathode electrode of the semiconductor switching device via a current path. The present invention relates to a switching device, a semiconductor stack device and a power conversion device using the semiconductor switching device.

[0002]

2. Description of the Related Art FIG. 40 shows an example of a circuit configuration of a conventional semiconductor switching device. In the figure, reference numeral 3
P is a semiconductor switching element, here it is a GTO (gate turn-off thyristor). GT
A gate driver 4P that generates a gate turn-on control current I _GP is connected between the gate and the cathode of O3P, and the driver 4P applies the gate turn-on control current I _GP to the gate of the GTO 3P, thereby allowing GT
Turn on O3P. Furthermore, the driver 4P is
A gate reverse current I _GQP given with a current change rate dI _GQP / dt of 20 to 50 A / μs is applied from the gate to the cathode. The gate reverse current I _GQP is a shunt of the anode current I _AP . At this time, the turn-off gain has a value within the range of 2 to 5, and the GTO 3P turns off.

Further, the voltage V between the anode electrode and the cathode electrode
_A snubber circuit is generally used to suppress the rate of increase in _AKP (dV _AKP / dt) and the surge voltage. Here, the snubber circuit is configured as follows. That is, the snubber capacitor Cs and the snubber diode D _S are connected in parallel to the GTO 3P, and the snubber resistor R _S causes the snubber diode R _S to discharge the charge stored in the snubber capacitor Cs when the GTO 3P is turned off. It is connected in parallel to D _S.

Further, the inductance 1P is the rate of increase dI of the anode current I _AP flowing when the GTO 3P is turned on.
_AP / dt is to be suppressed to 1000 A / μs or less, and the free wheeling diode 2P connected in parallel with the inductance 1P is to return the energy generated in the inductance 1P when the GTO 3P is turned off.

The inductance Ls is the stray inductance of the wiring of the snubber circuit.

A measured waveform obtained by performing a turn-off test on the circuit of the semiconductor switching device described above is
It shows in FIG. In the figure, waveforms C1P, C2P, and C3P are waveforms showing the anode current I _AP , the voltage V _AKP between the anode electrode and the cathode electrode, and the gate reverse current I _GQP , respectively, and the horizontal axis is the time axis.

In FIG. 41, at time tP1, GTO3
P is in the turn-on state and the gate reverse current I _GQP is in the 0 state. At this time, the rate of increase d of the gate reverse current I _GQP
The gate reverse current I _GQP is raised with the absolute value of I _GQP / dt set to 20 to 50 A / μs, and the turn-off gain (absolute value of the ratio given by the anode current I _AP / gate reverse current I _GQP ) of the GTO3P itself is measured. When the turn-off gain reaches the threshold value (time tP2), the anode current I _AP begins to decrease, and the voltage V between the anode electrode and the cathode electrode of the GTO 3P becomes V.
_AKP begins to rise. At this time, the current I _S also flows out to the snubber circuit side described above, and a voltage is generated by the rate of increase of this current I _S and the inductance (snubber inductance) Ls of the snubber circuit. This voltage is generated between the anode electrode and the cathode electrode. As a result of being superimposed on the voltage V _AKP , a spike voltage V _DSP is generated (time tP3). This spike voltage V _DSP causes power loss. For example, about 40
When a current of 00A flows, the power loss becomes several MW. Therefore, it is necessary to suppress this spike voltage V _DSP to a value as low as possible, and efforts have been continued to reduce the snubber inductance L _S than before.

Further, the rate of increase dV _AKP / d of the voltage V _AKP between the anode electrode and the cathode electrode after the spike voltage V _DSP is generated.
t changes abruptly, the maximum value is generated in the anode current I _AP (time tP4), and after that, the tail current is generated. Therefore, by the product of this tail current and the voltage V _AKP ,
Further power loss occurs. The voltage V _AKP is
At time tP5, the peak voltage is reached. After that,
The voltage V _AKP reaches the power supply voltage V _DD .

Therefore, such a rate of increase dV _AKP / dt
In order to suppress the above, the snubber capacitor C _{S described} above is required. The capacitance value is represented by I _AP / (dV _AKP / dt), and is usually selected so as to satisfy the relational expression of dV _AKP / dt ≦ 1000 V / μs.

42 and 43 show the GTO3P used in the conventional semiconductor switching device shown in FIG.
(The structure is roughly divided into a GTO element package and two stack electrodes), and both figures are shown including a gate driver 4P. 42 shows a side view of the GTO 3P viewed from the arrow direction DP2 shown in FIG. 43, but only a part of the GTO 3P is shown in a sectional view form. Also, FIG.
FIG. 43 is a plan view of a portion excluding the stack electrode 27Pa when viewing the GTO 3P from the arrow direction DP1 shown in FIG. 42.

42 and 43, each reference numeral indicates the following member. That is, 20P is a GTO element, 4PL is an internal inductance of the gate driver 4P, and 21P and 22P are a gate external lead (gate lead-out wire) and a cathode external lead (gate lead wire) each of which is a coaxial shield wire or twisted lead wire. (Cathode extraction line). Then, the gate terminal 25P of the GTO element 20P and one end of the gate external lead 21P are welded or soldered to the metallic connecting member 23P or are fitted to each other to integrate the two 25P and 21P, and The cathode terminal 26P and one end of the cathode external lead 22P are welded, soldered, or fitted to the metallic connecting member 24P to integrate the two 26P and 22P. As a result, both terminals 25P and 26P are connected to the gate driver 4P via the leads 21P and 22P, respectively.

Reference numerals 27Pa and 27Pb are stack electrodes for pressing the GTO element 20P.

Reference numeral 28P is a semiconductor substrate on which a GTO segment is formed, and the gate electrode 2 of A1 (aluminum) is formed on the outermost peripheral portion of the upper surface of the semiconductor substrate 28P.
9 Pa is formed, and a cathode electrode 29Pb is formed corresponding to each segment on the upper surface inside the gate electrode 29Pa. Also, 30P and 31P
Are cathode strain buffer plates and cathode post electrodes, which are sequentially stacked and arranged on the upper surface of the cathode electrode 29Pb on the upper surface of the semiconductor substrate 28P, respectively,
32P and 33P are anode electrodes (not shown) formed on the back surface of the semiconductor substrate 28P (in the back surface,
The cathode electrode 29Pb is an anode strain buffer plate and an anode post electrode, which are sequentially stacked on a surface located on the opposite side).

Further, 34P is a ring-shaped gate electrode which is in contact with the upper surface of the gate electrode 29Pa of the semiconductor substrate 28P and 3
5P is a ring-shaped gate electrode 3 via an annular insulator 36P.
Disc spring for pressing 4P against the gate electrode 29Pa, 37P
The ring-shaped gate electrode 34P to the cathode strain buffer plate 30.
38P is an insulating sheet for insulating from P and the post electrode 31P. One end of 38P is the ring-shaped gate electrode 34.
P is a gate lead fixed to P by brazing or welding and the other end is electrically connected to the gate terminal 25P. One of 39P is fixed to the cathode post electrode 31P and the other end is the cathode terminal 26P. 40P is a second flange whose one end is fixed to the anode post electrode 33P, and 41P is a projection in which the gate terminal 25P is arranged on the inner surface of the opening. Both ends 43P are insulating cylinders having a portion 42P and projecting from the upper and lower surfaces of the insulating cylinder 41P.
a and 43Pb are the first and second flanges 39P, respectively.
And 40P are airtightly fixed, which allows GTO
The element 20P has a sealed structure.

[0015]

The conventional semiconductor switching devices are roughly divided into two problems.

(1) First, as shown in FIG. 43, the first is that the lead 21P for extracting the gate reverse current is taken out from a local portion of the ring-shaped gate electrode 34P. is there. Therefore, the gate reverse current is taken out in one direction. As a result, at turn off,
The non-uniformity of the cathode current occurs, and the power loss such as the spike loss and the loss due to the tail current described above is locally concentrated on a part of the cathode surface inside the GTO, and the local temperature rise causes each element of the GTO. Also, there is a high probability that each segment will be destroyed and brought into conduction, resulting in a failure in turn-off, resulting in a problem with the reliability of the device.

This point is schematically explained with a plan view of the GTO element of FIG. 44 and a sectional view of the GTO element of FIG. 45. 45 is a vertical cross-sectional view taken along the line CSA-CSB shown in FIG. That is, in each of the GTO elements formed in the cylindrical wafer, the ring-shaped gate electrode 34P is formed.
Closer to, for example, a region formed in the region REO, the gate reverse current thereof is more inward than the region REI.
It will be pulled out much sooner than in the case of the GTO element in and will therefore be turned off sooner. On the other hand, the segment of the GTO formed in the region REC in the central portion of the wafer requires the longest time to be turned off most, and the segment of the GTO in the central region REC toward the cathode electrode Since the cathode current I _K will flow in from each of the surrounding segments, current concentration will occur in a part of the inside of the GTO wafer.

(2) The second problem is due to the presence of the snubber circuit, especially the snubber capacitor. That is, as described above, the snubber capacitor Cs is turned off at the time of turn-off.
It is necessary to completely discharge the electric charge charged up in (FIG. 40) by the next turn-off. Therefore, when the GTO 3P is turned on, the charges are discharged through the snubber resistor R _S , which causes a large power loss. At this time, the capacity of the power consumption generated in the snubber resistor R _S is PW = 1/2 * Cs * f (V _DD ² + (V
_DM- V _DD ) ² ). Here, V _DD is a power supply voltage, and V _DM is a voltage when the snubber capacitor CS is charged up at turn-off. Therefore, it becomes necessary to provide a cooling device for cooling the entire device.

When a snubber resistor having such a power capacity is connected, only the amount of power generated by the snubber resistor becomes a loss in the power that should be originally transmitted, resulting in a decrease in efficiency and the above-mentioned. This requires the installation of a cooling device, which is a very big problem in simplifying and downsizing the entire device.

Therefore, in order to solve these problems, the first electrode has the first, second and third electrodes, and when it is turned on in response to the turn-on control current applied to the third electrode, the first electrode is turned on. Is connected between the semiconductor switching element for directly flowing a main current flowing into the first electrode to the second electrode and the third electrode and the second electrode, and generates the turn-on control current to generate the turn-on control current. Drive control means for applying to three electrodes, and at the time of turn-off, all of the main current is commutated from the first electrode to the drive control means via the third electrode in a direction opposite to the turn-on control current. We devised a semiconductor switching device that allowed us to solve the problem. However, as a result of further study in order to commercialize the actual product, when supplying the turn-off current from the gate driver to the semiconductor switching element via the current path,
It has been found that how the current can be applied to the gate terminal in a uniform distribution is an extremely important issue for the semiconductor switching device to exhibit its full performance.

The present invention has been made to solve the above problems, and prevents power loss from locally concentrating on a part of semiconductor switching elements in a semiconductor wafer to prevent element destruction. In a semiconductor switching device or the like for preventing the above and improving the reliability of the device, a semiconductor switching device in which current is uniformly supplied to a gate terminal, a semiconductor stack device and a power conversion device using the same are provided. The purpose is to get.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor switching device comprising a gate terminal extending in the circumferential direction of a semiconductor switching element, and a current path is provided at a plurality of places where the turn-off current is the gate terminal. It is a parallel current path that flows in parallel with.

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, a current path is formed by a conductor region and an insulating region, and the turn-off current is the gate terminal. Is a parallel current path that flows in parallel at a plurality of locations.

A semiconductor switching device according to a third aspect of the present invention is the semiconductor switching device according to the second aspect, wherein the current path includes a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. Is formed of a wiring board laminated via an insulating layer, the conductive layers are used as conductor areas, and slits having a predetermined pattern are formed in the wiring board to form an insulating area.

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, and a turn-off current flows in parallel in a current path in a plurality of positions of the gate terminal. And a means for reducing the impedance difference between the gate terminal and the gate driver in each current path of the parallel current path.

According to a fifth aspect of the present invention, there is provided a semiconductor switching device comprising a semiconductor switching element having a gate terminal extending in a circumferential direction, and a turn-off current flows in parallel in a current path in a plurality of positions of the gate terminal. And the gate driver is composed of a plurality of gate drivers, and the voltage applied to the semiconductor switching element of each gate driver is a different voltage so as to reduce the difference in current in each current path of the parallel current paths. It is what

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, and the gate driver is composed of a plurality of gate drivers. The gate driver is disposed before and after the switching element, and the gate driver close to the semiconductor switching element is located far from the gate terminal, and the gate driver far from the semiconductor switching element is located near the gate terminal via current paths. Connected.

A semiconductor switching device according to a seventh aspect is the semiconductor switching device according to the sixth aspect, wherein the current path includes a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. And a turn-off current that flows through the current path in parallel at a plurality of positions of the gate terminal by forming a slit of a predetermined pattern on the wiring board A gate driver near the semiconductor switching element is a current path, and a gate driver far from the semiconductor switching element is connected to a location near the gate terminal via a current path connected to a location far from the gate terminal. Are connected to each other.

According to an eighth aspect of the present invention, there is provided a semiconductor switching device according to the sixth aspect, wherein the current path includes a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. A plurality of pairs, the wiring board is formed by alternately laminating both conductive layers with an insulating layer interposed therebetween, and the gate driver close to the semiconductor switching element has the gate terminal through the some conductive layers of the plurality of pairs. The gate driver farther from the semiconductor switching element is connected to a portion farther away from the semiconductor switching element to a portion closer to the gate terminal through the remaining conductive layers of the pairs.

A semiconductor stack device according to a ninth aspect uses the semiconductor switching device according to any one of the first to eighth aspects, and includes a semiconductor switching element and a cooling member for radiating heat generated from the semiconductor switching element. Are arranged in a stacking mounting frame.

A power converter according to a tenth aspect uses the semiconductor switching device according to any one of the first to ninth aspects, and comprises a gate control device for controlling the gate of the semiconductor switching element to perform power conversion. It is a thing.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor switching device or semiconductor switching element of the present invention is used in various power conversion devices such as a vehicle power conversion device, a UPS (Uninterruptible Power System), and an industrial power conversion device. , A power device.

The core of the novel method for controlling a semiconductor switching element proposed by the present invention is that all of the main current flowing through the semiconductor switching element in the ON state is diverted to the drive circuit. The point is to turn off.

In the following, as such a semiconductor switching element, a gate turn-off thyristor (hereinafter, referred to as G
An example using (TO) will be shown. In this case, GTO
The first, second and third electrodes of the anode electrode,
It corresponds to the cathode electrode and the gate electrode. The semiconductor switching element is not limited to the one having a four-layer structure such as GTO, and a transistor having a three-layer structure can be used as the semiconductor switching element of the present invention. In this case, when using the NPN transistor, the first, second, and third electrodes correspond to the collector electrode, the emitter electrode, and the base electrode, respectively.
When using a PNP transistor, the first, second and third electrodes correspond to an emitter electrode, a collector electrode and a base electrode, respectively.

Embodiment 1. FIG. 1 shows a circuit configuration of a semiconductor switching device 10 according to the first embodiment of the present invention. In the figure, each reference numeral indicates the following circuit element. That is, 3 is a GTO as a semiconductor switching element, and the gate driver 4 is provided between the gate electrode 3G of the GTO 3 and the node 13 of the cathode electrode 3K.
(Drive control means) is connected.

The gate driver 4 has its driving power source 4a.
(Power supply voltage V _GD (for example, 20 V)), capacitor 4b,
It is composed of an inductance 4C and a transistor 4d. still,
The detailed configuration is shown in FIG. 2 described later.

The gate driver 4 generates a turn-on control current I _G for turning on the GTO 3, and applies this current I _G to the gate electrode 3G via the wiring path or the line L1. In response to this, the GTO 3 is turned on. Reference numeral 11 is a node, and 9 is a power supply for driving the device 10, that is, a main circuit power supply (power supply voltage V _DD ) of the device 10.

On the other hand, 1 is the rate of increase dI _A / dt of the main current or anode current I _A flowing when the GTO 3 is turned on.
Is an inductance for suppressing the
This is a free-wheeling diode for freeing the energy generated in the inductance 1 when 3 is turned off.

Reference numeral 5 is connected in parallel to the GTO 3 between the node 11 of the anode electrode 3A and the node 12 of the cathode electrode 3K, and when the GTO 3 is turned off, the voltage V _AK between the anode and the cathode electrode rises. It is a peak voltage suppression circuit for suppressing only the peak voltage generated due to. As will be described later, the circuit 5 has a function of holding or clamping the voltage V _AK at a predetermined voltage value determined according to the voltage blocking capability of the GTO 3 for a predetermined time when the voltage V _AK is turned off.

Here, at turn-off, the rate of change or rate of rise (gradient) dI _GQ / of the gate reverse current I _GQ , which has conventionally been shunted from the main current I _A and flowed into the gate driver 4 side.
Make the absolute value of dt as large as possible (ideally, |
dI _GQ / dt | is ∞), and all of the main current I _A is passed to the node 12 via the gate driver 4 as the gate reverse current I _GQ . That is, the turn-off gain G (= | I _A / determined by the absolute value of the ratio of the main current I _A and the gate reverse current I _GQ
I _GQ |) is set to 1 or less (G ≦ 1), so that all of the main current I _A flows in the opposite direction to the turn-on control current I _G from the anode electrode 3A through the gate electrode 3G. And the commutation to the node 12 side, thereby turning off the GTO 3. At this time, the cathode current I _K flowing directly inside the GTO 3 from the anode electrode 3A toward the cathode electrode 3K immediately stops flowing at all. In that sense, this method, rather than the shunt of the main current I _A, with each other to achieve a "commutation of the main current I _A."

Here, the value of the rate of increase dI _GQ / dt can be changed according to the relationship between the power supply voltage value V _GD of the driving power supply (main power supply) 4a of the gate driver 4 and the inductance value of the loop R1. Therefore, by appropriately setting the values of both 4 (4a) and R1, by setting the increase rate | dI _GQ / dt | to an extremely large value close to the infinite value,
All of the main current I _A can be commutated to the gate driver 4 side in an extremely short time.

On the other hand, it is easy to realize such commutation of the gate reverse current I _GQ by the gate driver 4 alone because the power supply voltage V _GD that the drive power supply 4a of the driver 4 can have is limited. However, on the other hand, on the other hand, the absolute value of the rate of increase dI _GQ / dt necessary to set the gate turn-off gain G to 1 or less is set by setting the driving power supply voltage V _GD of the gate driver 4 to a practical value that can be set. Possible loop R
It is actually possible to set the value of the internal inductance of 1.

Therefore, the line L1 from the gate electrode 3G to the gate driver 4, the gate driver 4, the line L2 from the gate driver 4 to the cathode electrode 3K via the node 13, and the GTO3 between the gate and the cathode electrode.
It is required to reduce the value of the (floating) internal inductance in the loop consisting of the internal path or the path R1 to a value necessary for setting the turn-off gain G to 1 or less.

However, the gate driver 4 must be set so as to have a capacitance enough to allow the gate reverse current I _GQ having a value equal to or higher than the main current I _A to flow.

For example, when the power supply voltage V _GD of the main power supply 4 _a of the gate driver 4 is set to 20 V and the absolute value of the rate of increase dI _GQ / dt is set to about 8000 A / μs, the inductance of the loop R1 is set. The value is preferably 2.5 nH or less, and the internal inductance value of the gate driver 4 is preferably 1 nH or less.

A specific circuit diagram of the gate driver 4 having such capacitance is shown in FIG. In the figure, a drive power source 50 is a main power source for driving the gate driver 4, a sub power source 51 is a power source for a turn-on gate current, and a sub power source 52 is a turn-on transistor Tr.
1, a power supply for a drive circuit 56 for driving Tr2, a sub power supply 53 is a power supply for a turn-off gate current, a sub power supply 54
Is a power supply for the drive circuit 57 for driving the turn-off transistor Tr3, and the sub power supply 55 is a circuit section 58 for generating a turn-on signal and a turn-off signal from the control signal 62.
The transistor Tr1 is a switch for supplying the turn-on high gate current I _G1 shown in FIG. 3, the transistor Tr2 is a switch for supplying the turn-on / steady gate current I _G2 , and the transistor Tr3. Is a switch for supplying a turn-off gate current I _GQ (gate reverse current). The currents I _G1 and I _G2 are collectively referred to as the turn-on control current I _G. C1 is a capacitor for the turn-on gate current I _G , and C2 is a capacitor for the turn-off gate current I _GQ .

In the above gate driver circuit 4, when the control signal 62 is given from the outside, the noise cut circuit 59 is provided.
Removes a noise component included in the control signal 62 from the control signal 62, receives the noise-removed control signal, and outputs the turn-on signal generation circuit 60 and the turn-off signal generation circuit 61.
Respectively generate a turn-on signal 63 and a turn-off signal 64 and supply the signals 63 and 64 to the corresponding drive circuits 56 and 57.

The drive circuits 56 and 57 which have received the signals 63 and 34 operate as follows. That is, at the time t ₀₁ , the drive circuit 56 generates a signal that can drive the transistor Tr1 and supplies it to the base of the transistor Tr1. Where both capacitors C1 and C2
Are charged by the sub power source 51 and the sub power source 53, respectively, so that the turn-on high gate current I _G1 flows from the capacitor C1 to the GTO3 through the transistor Tr1. Then, at time t ₀₂ , the drive circuit 56 stops the supply of the base current of the transistor Tr1 and this time,
A base current that can drive the transistor Tr2 is generated and supplied to the base of the transistor Tr2. As a result, the transistor Tr1 is turned off, the transistor Tr2 is turned on instead, and the turn-on / steady gate current I _G2 flows from the capacitor C1 to the GTO3 through the transistor Tr2.

At time t ₁ , the drive circuit 56 stops the supply of the base current of the transistor Tr2, and the drive circuit 5
7 generates a base current required to turn on the transistor Tr3 according to the signal 64 and supplies the base current to the base of the transistor Tr3. As a result, the transistor Tr2 is turned off, and instead the transistor Tr3 is turned on. As a result, the electric charge charged in the capacitor C2 is discharged to the GTO3 side via the transistor Tr3, and thus the turn-off gate current I _GQ is generated. GTO3
Through the transistor Tr3 to the node 13 of the cathode electrode 3K of GTO3. Moreover, this current I _GQ becomes equal to or greater than the absolute value of the main current I _{A in} a very short time, and conversely, the cathode current decreases to 0 value in a very short time.

As described above, in order to realize the rate of increase dI _GQ / dt such that the turn-off gain G is 1 or less, the loop R1 including the wiring route inside the gate driver 4 is used.
It is necessary to reduce the overall inductance value.
It is desired to realize this point by improving the mechanical parts such as the wiring of the GTO element or the package structure.

However, since the package structure of the conventional GTO 3P has the structure as shown in FIGS. 42 and 43, the internal inductance (lead 21P-ring-shaped gate electrode 34P-cathode electrode 30P) of the GTO element 20P. ~ Inductance of the path to the lead 22P)
Was a large value, for example, about 50 nH. At this value, the rate of increase dI _GQ / d is about 8000 A / μs.
t cannot be achieved. Therefore, in order to reduce the internal inductance value of the GTO element 20P to a desired value such as 2 nH or less, the gate-side connecting portion 23P and the cathode-side connecting portion 24P, the gate terminal 25P of the GTO element 20P, and the like. Loss caused by each coupling with the cathode terminal 26P and the gate external lead 2
1P and cathode external lead 22P and gate driver 4
Loss caused by each coupling with P and gate lead 3
It is necessary to reduce the inductance value of 8P, and further, the inductance value of each of the external lead wires 21P and 22P of the gate and the cathode which occupy 90% of the total inductance value in the loop R1.

Therefore, the applicant of the present application studied the package structure of the GTO element from the above viewpoint and decided to improve it. As a result, the pressure contact type semiconductor element having the following structure was realized.

That is, FIG. 4 shows a pressure contact type GTO element 20,
Stack electrodes 27a, 27 for pressing it from above and below
5 is a cross-sectional view showing the GTO element 20 in the direction of the arrow D1 shown in FIG. 4 (excluding the stack electrode 27a). Therefore, the line SA-S in FIG.
FIG. 4 is a vertical cross-sectional view of B.

In both FIGS. 4 and 5, each reference numeral indicates the following member. That is, 20 is a pressure contact type semiconductor element, that is,
Here, the entire GTO element is shown, and 28 is a semiconductor substrate on which each GTO segment is formed.
A gate electrode 29a of A1 (aluminum) is formed on the surface located on the outer peripheral side of the upper surface of 8, and each segment is formed on the upper surface of the semiconductor substrate 28 inside the gate electrode 29a. Each cathode electrode 29b is formed corresponding to the position. The structure of each segment or the wafer structure of the GTO element is similar to the structure shown in the sectional view of FIG.

Reference numerals 30 and 31 respectively denote the semiconductor substrate 28.
On the upper surface of the cathode electrode 29b are the cathode strain buffer plate and the cathode post electrode, which are sequentially stacked on the upper surface of the cathode electrode 29b, while 32 and 33 are the semiconductor substrate 8 respectively.
An anode strain buffer plate and an anode post electrode, which are sequentially stacked on the surface (a surface opposite to the cathode electrode 29b) of an anode electrode (not shown) formed on the back surface of
Reference numeral 34 is a ring-shaped gate electrode that is in contact with the upper surface of the gate electrode 29a of the semiconductor substrate 28, and 38 is a ring-shaped gate terminal made of an annular metal plate, and an inner peripheral plane 25 thereof.
Are slidably contacted with and arranged on the ring gate electrode 34. Reference numeral 35 is an elastic body such as a disc spring or a wave spring for pressing the ring-shaped gate electrode 34 against the gate electrode 29a together with the ring-shaped gate terminal 38 through the annular insulator 36, and 37 is
An insulator made of an insulating sheet or the like for insulating the ring-shaped gate electrode 34 from the cathode strain buffer plate 30 and the cathode post electrode 31, and 26 is a first flange whose one end is fixed to the cathode post electrode 31. And
40 is a second flange whose one end is fixed to the anode post electrode 33, 41 is an insulating cylinder which is made of ceramic or the like and is divided into upper and lower parts with the ring-shaped gate terminal 38 in between and which has a protrusion 42. is there. The outer peripheral portion 23 of the ring-shaped gate terminal 38 projects outward from the side surface of the insulating tube 41, and a plurality of mounting holes 21 are provided at a predetermined interval at a position closer to the inner peripheral side than the other end 38E. . The portion 43 a protruding upward from the upper surface of the upper insulating cylinder 41 is the other end portion 2 of the first flange 26.
6E is airtightly fixed, and the portion 43b protruding downward from the back surface of the lower insulating cylinder 41 is airtightly fixed to the other end of the second flange 40, whereby the pressure contact type semiconductor element 20 is hermetically sealed. It has a package structure.
The inside is replaced with an inert gas.

FIG. 6 is a plan view showing the mechanical portion of the gate driver 4, and FIG. 7 shows the GTO element 20 (stack electrodes 27a and 27b in the gate driver 4 having the structure shown in FIGS. 4 and 5). It is a longitudinal cross-sectional view showing a state in which (pressurized) is mounted. In both FIGS. 6 and 7, reference numeral 4A
Shows a case for covering the gate driver main body 4C, 4B shows a case which becomes a seat of the gate driver main body 4C, and 70 shows the gate driver main body 4 and the GTO.
The whole board | substrate in which the circuit pattern for electrically connecting with the element 20 was formed is shown. The substrate 70 is just the gate lead wires 21P and 22P of the conventional package.
(FIG. 42) and has a strength enough to support the weight of the GTO element 20. Reference numeral 71 denotes a cathode electrode connected by pressure contact with the cathode electrode 29b of the GTO element 20, and corresponds to the stack electrode 27a. 21
A is a substrate 7 for connecting the GTO element 20 through the mounting hole 21 corresponding to the substrate 70 of the gate driver 4.
The mounting holes are provided at 0, and in order to connect the gate driver 4 and the GTO element 20, for example, about 6 mounting holes 21A are required.

The above-mentioned substrate 70 has the following two circuit pattern substrates facing each other with the insulator interposed therebetween. That is, the substrate 70 includes a gate lead substrate 72, a cathode lead substrate 73, and an insulator 74 for insulating the two substrates 72 and 73.
And have. The multilayer substrate structure is provided in order to reduce the internal inductance on the gate driver 4 side. The GTO element body 20 has screws 75 and 76.
Alternatively, it is connected to the gate driver main body 4C by welding, caulking or the like.

As described above, the airtight package of this GTO 3 has the internal gate electrode 29 formed on the semiconductor substrate.
It has a ring-shaped or disk-shaped gate electrode 38 extending from the side a toward the side of the gate driver body 4C,
Moreover, in the package (20), the outer peripheral portion of the ring-shaped gate electrode 38 is directly connected to the main body 4C of the gate driver 4.
Connected to the extended board 70 via the mounting hole 21A.
It is connected to the gate driver 4 only by fixing it. Therefore, no gate lead wire is used for the connection. Therefore, all the problems in the conventional configuration are improved. That is, the coupling loss that has conventionally been caused by the coupling between the internal gate lead portion of the GTO element and the gate terminal and cathode terminal of the GTO element is
As described above, by taking out the gate lead with the disk-shaped structure, it is significantly reduced, and the power loss corresponding to the coupling loss conventionally generated by the coupling between the external gate lead wire and the gate driver is reduced by the present invention. In this case, since the entire disc-shaped gate lead portion or the gate electrode 38 is directly connected to the gate current conducting substrate 70 of the gate driver 4, it is significantly reduced. Furthermore, the inductance of the external gate leads themselves, which conventionally occupied 90% of the total inductance of the loop R1, does not exist because they are not used in the present invention.

As described above, it is possible to reduce the internal inductance of the GTO element 20 (3) and the internal inductance of the gate driver 4. In addition to these improvements, the connection between the GTO element 20 and the gate driver 4 is further devised as described above (FIG. 7), so that the GTO element 3 is provided with a turn-off gain G ≦ 1. Rate of rise d that can be turned off
It has become possible to actually generate the I _GQ / dt region.

The gate current may be taken out in two directions or four directions diagonally located by using the substrate 70A shown in the plan view of FIG. You may make it take out an electric current.

The operation of the semiconductor switch device having the above circuit structure and mechanism will be described with reference to FIGS. 9 and 10. Note that FIG. 9 shows operation waveforms, and FIG.
An equivalent model in which TO3 is replaced with a circuit configuration including a PNP transistor 80 and an NPN transistor 81 is shown.

In FIG. 9, when the GTO 3 is turned on and the anode current I _A is flowing (time t ₁ ), the gate driver 4 rapidly changes the gate reverse current I _GQ in response to the control signal 62 (FIG. 2). If the gate reverse current I _GQ reaches a current value whose absolute value is equal to the absolute value of the anode current I _A in an extremely short time (I _GQ =
-I _A) (time T _2). In this state, all the anode current I _A flowing into the anode electrode 3A of the GTO 3 is the gate electrode 3
G, commutated to the gate driver 4 via the wiring path L1,
The relational expression of anode current I _A | ≦ | gate reverse current I _GQ | of | GTO 3 is established, and the cathode current I _K = 0.
After that, the gate reverse current I _GQ continues to maintain the state of | I _A | ≦ | I _GQ | until the GTO 3 is completely turned off.

The current difference ΔI _GQ shown in FIG. 9 is considered to be the recovery current of the NPN transistor 81 shown in FIG. This is caused by the following phenomenon. That is, in FIG. 10, when the GTO 3 is turned on and the anode current I _A is flowing in the semiconductor substrate, the current I _A is separated from the anode electrode 3A of the GTO 3 into the loop 82 and the loop 83, and the cathode electrode 3K. Is flowing to. From this state, when GTO3 is turned off,
All of the anode current I _A is strongly pulled by the gate driver 4 and flows to the loop 84 and the loop 85. At this time, the base current of the NPN transistor 81 is inverted from the positive direction to the negative direction, the NPN transistor 81 is suddenly turned off, and its internal carrier becomes a recovery current and flows in a superimposed manner. The increase in the recovery current is expressed as the above-mentioned current difference ΔI _GQ, and at this time, | gate reverse current I _GQ |> | anode current I _A |.

In this way, the gate reverse current | I _GQ |> | anode current I _A | results and the NPN transistor 8 of FIG.
When 1 is turned off, PNP transistor 80
The base current becomes zero (I _B = 0), PNP transistor 80 will shift to the turn-off.

When the voltage blocking function of the PNP transistor 80 starts to recover (time T ₃ ), the anode-cathode electrode voltage V _AK shown in FIG. 9 starts to rise, and the anode-cathode electrode voltage V _AK becomes the power supply voltage. When the value equal to V _DD is reached (time T ₄ ), the anode current I _A begins to decrease and GTO3
Turns into a turn-off state. At this time, the rising rate dV _AK / dt of the voltage V _AK between the anode and the cathode electrode is G
It is determined only by the speed at which the voltage blocking function of TO3 is restored, not by the external connection circuit or the like. In this respect, the present invention is clearly different from the prior art in which the increase rate of the voltage between the anode and the cathode electrode is determined depending on the snubber capacitor C _S.

In FIG. 9, the peak voltage (surge voltage) V _P of the present invention means the main circuit (loop from the power supply 9 to the node 11, GTO 3, node 12 to the power supply 9) when the GTO 3 is turned off. Stray inductance L
Electromotive force generated due to (the energy is E = 1 /
2 * L * I ² ) is a voltage obtained by superimposing it on the power supply voltage V _DD . If this peak voltage V _P is GTO
If the voltage blocking capability of 3 is exceeded, the GTO 3 will be destroyed. Therefore, the peak voltage suppressing circuit 5 that suppresses the anode-cathode electrode voltage V _AK that continues to increase toward the peak voltage V _P when the GTO 3 is turned off so as not to exceed the voltage blocking capability of the GTO 3 is provided at the node 1 of the GTO 3.
It is necessary to connect GTO3 between 1 and 12 in parallel. The peak voltage suppression circuit 5 of FIG. 1 has such a function, and is a voltage clamp circuit including, for example, a Zener diode, a varistor, a celestor, and an arrester. After the voltage V _AK that continues to rise when the GTO is turned off reaches a predetermined voltage value V _SP set within a range that does not exceed the voltage blocking capability of the GTO 3, the circuit 5 is
If If there is no same circuit 5 the voltage V _AK reaches the peak voltage V _P, a predetermined time Delta] t (Fig. 9) is the time required for the returns to a predetermined voltage value V _SP, the voltage V _AK The peak voltage after suppression is kept at V _SP . Therefore, the peak voltage V _P is not generated, and the GTO3 element is never destroyed.

As described above, in the present invention, at the time of turn-off, the GTO 3 is turned off by controlling the GTO 3 in the region RA of the rate of increase dI _GQ / dt shown in FIG. In the figure, the point PA on the curve CA is the main current I _A.
Is a commutation point where commutation of the
In this case, it is in an ideal state when it is considered that there is no recovery current described above. In reality, since the recovery current is superimposed on the commutated main current, the turn-off gain G <1
The turn-off of GTO3 is realized in the area of.

FIG. 12 and FIG. 13 are diagrams relatively showing the flow of the main current I _A at turn-off in the prior art and the present invention, respectively. Prior art, for example, Japanese Patent Laid-Open No. 5-
No. 111262 (Swiss application number 9110619)
19) and Japanese Patent Application Laid-Open No. 6-188411 (German application No. P4227063).
As shown in, the cathode current I _K is flowing in the GTO 3P even at turn-off. That is, the main current I _A is
At the time of turn-off, the cathode current is _{divided into} I _K and I _GQP . However, in this case, even if the cathode current I _K flowing through each segment is a small value, they will intensively flow into some of the segments, so the GTO
The problem of element destruction is inherent.

On the other hand, in the present invention, as shown in FIG. 13, at the time of turn-off, the cathode current I _K does not flow at all, and all the main current I _A commutates to the path on the side of the gate driver 4 to generate the recovery current. Gate reverse current I _GQ
Is the sum of the absolute value of the main current I _{A and} the absolute value of the recovery current, and the relational expression | I _GQ | ≧ | I _A | holds (in the prior art, | I _GQP | <| I _A |).

As described above, according to the present invention, the novel gate commutation system in which | anode current I _A | ≦ | gate reverse current I _GQ | is employed during the turn-off mode period is adopted. The current I _K = 0,
The cathode current does not flow into the cathode surface inside the GTO 3P at all, and localized current concentration on the cathode surface, which has conventionally been a cause of turn-off failure, cannot occur at all. Therefore, in the present invention, there is no possibility of element destruction due to turn-off failure, and the reliability of the device is significantly improved. It can be said that this effect is the core effect of the present invention and is an advantage that cannot be obtained even by the combination of the techniques shown in the above-mentioned respective documents.

In addition, the voltage V between the anode and cathode electrodes
_{Since the} circuit 5 for suppressing the rise in _AK and suppressing the surge voltage is provided, the spike voltage is cut by the circuit 5 and is not generated at all. Therefore, the snubber capacitor C _S , which was conventionally required to discharge the electric charge accumulated at the time of turn-off, can be eliminated. That is, the snubber circuit, which is indispensable in the prior art, can be dispensed with, and the device can be made compact, simple, low cost, and highly efficient.

FIG. 14 shows a circuit configuration of a semiconductor switching device which employs a peak voltage protection circuit different from that of FIG. In the figure, the same reference numerals as those in FIG. 1 denote the same components. As the package structure of the GTO 3 and the mechanism of the gate driver 4, those described in FIG. 1 are used. Each of the reference numbers 6 to 8 is G
It is an element that constitutes a protection circuit that suppresses or reduces power loss due to a spike voltage or a peak voltage (surge voltage) that occurs when TO3 is turned off, and shows a diode, a resistance element, and a capacitor in order. In particular,
Here, one end 15 of the capacitor 8 (capacitance element) included in the bypass line BL arranged in parallel with the GTO 3 between the node 11 and the node 12 includes the resistance element 7 and is connected to the power supply 9 at the node 14. It is characterized in that it is connected to the power supply 9 through the formed wiring route R4.

The semiconductor switching device 10A as described above.
Or, the operation of the GTO 3 will be described with reference to FIG.

The operation of the GTO 3 in this case is shown in FIG.
1 is the same as the operation in the device of FIG. 1, and only the peak voltage suppressing operation of the voltage V _AK between the anode and the cathode electrode is different from the case of FIG. The measured waveform of FIG. 15 is I _A = 1000 (A /
d), V _AK = 1000 (V / d), I _GQ = 1200 (A
/ D), V _GD = 20 (V / d), and t = 2 (μs / d). In the figure, curves C1, C2, C3,
C4 shows the measured waveforms of the anode current I _A , the anode-cathode electrode voltage V _AK , the gate reverse current I _GQ , and the gate voltage V _G , respectively.

In FIG. 14, the capacitor 8 is constantly charged to the power supply voltage V _DD through the resistance element 7, and during the turn-off operation, the generated spike voltage V _DSP and peak voltage V _P exceed the power supply voltage V _DD . Only the current due to the voltage portion (V _DSP −V _DD , V _P −V _DD ) is absorbed by the capacitor 8 through the diode 6. Therefore, only the excess portion is newly charged to the capacitor 8 for the excess time.

The above points will be described with reference to FIG.
The capacitor 8 does not function until the voltage V _AK between the anode and the cathode electrode reaches the power supply voltage V _DD , and this period (t ₂
The rate of increase dV _AK / dt of −t ₁ ) is determined by the capability of the GTO 3 (at this time, the total main current I _A is commutated to the gate driver 4 side). Then, when the anode-cathode voltage V _AK reaches the power supply voltage V _DD and the anode current I _A starts to decrease (time t ₂ ), at the same time, the node 1
The main current flowing into 1 starts flowing to the capacitor 8 side through the diode 6, that is, to the bypass path BL. At this time, the rate of increase di / dt of the bypass current i flowing in and G
An electromotive voltage is generated by the closed circuit composed of TO3, the diode 6 and the capacitor 8 or the inductance (L _f1 ) floating in the first loop R2. This is
Is the spike voltage V _DSP shown at (time t ₃ ). After that, until time t ₅ , the voltage V between the anode and the cathode electrode is
The difference between the peak voltage V _{P of AK} and the power supply voltage V _DD is absorbed by the capacitor 8. At that time, the amount of overcharge absorbed by the capacitor 8 should be equal to or lower than the voltage blocking capability of the GTO 3.
The capacitance value of the capacitor 8 is appropriately determined. That is, it is determined by the capacitance value of the capacitor 8 so that the peak value V _{P of} the anode-cathode electrode voltage V _AK that rises from the time t ₄ to the time t ₅ becomes equal to or lower than the voltage blocking ability of the GTO 3.

The overcharged portion of the peak voltage absorbed by the capacitor 8 is discharged through the resistance element 7 to the power source 9 side by the next turn-off. On the other hand, even when the GTO 3 is turned on, the voltage or charge charged in the capacitor 8 is blocked by the diode 6 even if it tries to discharge, so that it is not discharged. Therefore, the capacitor 8 is always charged to a voltage equal to the power supply voltage V _DD .

The peak voltage V _P from time t ₄ to time t ₅ is based on the electromotive force generated due to the stray inductance (L _A2 ) in the second loop R3 and the capacitance value of the capacitor 8.

As described above, the energy stored in the capacitor 8 of the peak voltage suppression circuit or the protection circuit of the semiconductor switching device 10A is entirely reduced to zero by the snubber resistance like the snubber capacitor in the prior art. Instead of being discharged, only the overcharged portion is discharged, and the discharge loss of the snubber circuit, which has been a problem in the past, can be significantly reduced. Moreover, this semiconductor switching device 10A
Then, by simply using the members used in the snubber circuit of the related art and directly connecting the wiring of the resistance element used as the snubber resistance to the node 14 of the power supply 9 as the wiring route R4, Since the structure can be simplified, that is, the conventional snubber circuit can be used as it is to sufficiently reduce the discharge loss, there is an advantage that a highly realizable device can be realized. Of course, also in the device 10A, like the device 10 of FIG. 1, it is possible to completely prevent the element breakdown of the GTO 3 at the time of turn-off.

As mentioned in the previous section, the semiconductor switching device described with reference to FIGS.
Although the conventional problems are basically solved, in order to achieve actual commercialization, in addition to the structure, workability at the time of manufacturing and maintenance, as well as implementation of peripheral devices and parts It is necessary to consider it, and it is necessary to solve the problems raised in these embodiments.

That is, when the turn-on current is supplied to the ring-shaped gate terminal, it is necessary to make the current distribution in the circumferential direction uniform. In the examples shown in FIGS. 6 and 7, the gate driver and the gate are used. The terminals are connected by a board 70 which is a wide plate-shaped conductor. Therefore, the distance to the gate driver changes depending on the position of the gate terminal in the circumferential direction, and because of the arrangement of the gate driver, a good and uniform current distribution cannot always be obtained. In the following, a semiconductor switching device that solves the above-mentioned problems newly appearing when embodying these products will be described. In the following, since the contents described with reference to FIGS. 1 to 15 are different from the main points of interest, the same or corresponding parts will be described with new reference numerals.

Here, since the current path to the gate driver and the semiconductor switching element is the center, attention is focused on them and moreover, the following FIG.
16 will be described in a simplified manner. In the figure, GCT is a flat semiconductor switching element which is on / off controlled by gate control of a gate turn-off thyristor or transistor having the ring-shaped gate terminal RG shown in FIGS. 4 and 5, A is its anode electrode, K
Is the cathode electrode. GD is a gate driver, G
TF is a turn-off gate driver, GTN is a turn-on gate driver, VDN and VDP are turn-off and turn-on power supplies, CF
And CN are turn-off and turn-on capacitors, TrF is a turn-off transistor,
Tr1 and R1 are transistors and resistors for turn-on high gates, and Tr2 and R2 are transistors and resistors for turn-on steady gates.

Although a detailed description of the operation is omitted, the transistors Tr1, Tr2, and TrF are sequentially turned on / off in a series of timing sequences determined by the one-shot circuit and the buffer by the input of the control signal, for example, as shown in FIG. The turn-on high gate current, the turn-on steady gate current, and the turn-off gate current are supplied between the gate terminal RG and the cathode electrode K.

Now, FIG. 17 is a plan view showing a semiconductor switching device according to the first embodiment of the present invention, which solves the above-mentioned new problem. In the figure, the newly appearing codes will be described below. That is, BG is a plurality of output terminals P of this gate driver GD.
1, P2, ... Straight part BGD extending toward
It consists of and. An annular current path RP that surrounds the gate terminal RG is formed between the annular portion BGR and the gate terminal RG. K is the above-mentioned cathode electrode, which is located on the back side of the anode electrode A in FIG.

In is a turn-off gate current flowing from the gate terminal RG into the gate driver GD to turn off the semiconductor switching element GCT. These turn-off gate currents i1, i2 ,.
in is configured to flow in a number of parallel circuits between the gate driver GD and the ring-shaped gate terminal RG. That is, the current path width IW of the linear portion BGD of the plate-shaped connecting conductor BG is made larger than the diameter D of the gate terminal RG of the semiconductor switching element GCT, and the current path width I of the linear portion BGD is set.
W and the length GDTL of the current take-in end GDT from the gate terminal RG of the gate driver GD are substantially the same. Therefore, the turn-off gate current at the end of the straight portion BGD of the plate-shaped connecting conductor BG, for example, i1 and i2, flows out from the portion of the gate terminal RG far from the gate driver GD via the annular current path RP. is there. That is, the turn-off gate current in the ring-shaped gate terminal RG does not flow out from the whole outer circumference of the gate terminal RG and intensively flows out from one lead wire unlike the conventional one, and the turn-off gate current in the gate terminal RG does not flow. Are distributed over the entire area of the internal gate electrode, and the current per unit area is small, so that a large turn-off gate current can flow, and as a result, the turn-off time is about 1/10 of that of the conventional one. Becomes extremely short. Further, the life of the gate region of the semiconductor switching element GCT, that is, the life of the semiconductor switching element GCT is extended, and the reliability is improved.

FIG. 18 is a circuit configuration diagram for realizing the parallel current path shown in FIG. That is, in order to form a large number of parallel current paths, the gate driver GD is composed of n transistors and capacitors, respectively, which are sequentially arranged along the direction of the current path width IW. In the figure, this n
Of the individual pieces, only the first, second and n-th ones are extracted and shown. In the figure, C1, C2 and Cn are capacitors, TrF1, TrF2 and TrFn are turn-off transistors, P1, P2 and Pn are turn-off gate current output terminals from the respective transistors, G1P, G2P and G.
nP is each parallel current path on the gate side in the plate-shaped connecting conductor BG of FIG. 17, and K1P, K2P, KnP are each parallel current path on the cathode side of the plate-shaped connecting conductor BG of FIG.

Incidentally, in FIG. 18 (the same applies to drawings of the same type described later), the turn-on gate driver GT is shown.
Although the illustration of N is simplified, in the semiconductor switching device targeted by the present invention, the turn-on gate current is usually several tenths of the turn-off gate current, and there is no particular problem with the current supply. This is because the description is omitted. However, since both gate drivers GTF and GTN supply current to the gate terminal RG via a common current path, the presence of the turn-on gate driver GTN adversely affects the current distribution in the parallel current path of the turn-off gate current. However, as shown in the figure, the turn-on gate driver G
Since the resistor R is inserted on the output side of the TN, there is no fear of that.

FIG. 19 shows capacitors C1, C2, Cn and turn-off transistor TrF in the circuit diagram of FIG.
1, TrF2, TrFn, semiconductor switching element GC
FIG. 6 is a plan view showing an example of mounting arrangement of T on the plate-shaped connecting conductor BG and a configuration of connection to the plate-shaped connecting conductor BG in plan view. Note that the turn-on gate driver GTN is not shown in FIG.

FIG. 20 shows capacitors C1, C2, Cn and turn-off transistor TrF in the circuit diagram of FIG.
1, TrF2, TrFn, semiconductor switching element GC
It is sectional drawing which showed the example of mounting arrangement | positioning to T-shaped connection conductor BG, and the structure of the connection to T-shaped connection conductor BG by the cross section.
In the figure, GR1 is a gate pressing ring, KR1 is a cathode spacer ring, B1 is a conductor plate, and the gate pressing ring GR1 and the conductor plate B are formed by a screw mechanism (not shown), for example.
The gate-side conductive layer (gate-side current path) GP formed on the surface of the plate-shaped connection conductor BG with the gate terminal RG sandwiching the plate-shaped connection conductor BG and the cathode spacer ring KR1 therebetween by pressure contact. , And the cathode electrode K is electrically connected to the cathode side conductive layer (cathode side current path) KP formed on the back surface of the plate-shaped connecting conductor BG. The part (1) in the figure shows the connection structure between the transistor Tr and the capacitor C, which form a unit unit of the gate driver, and the plate-like connection conductor BG. The part (2) in the figure includes the power supply VDN. The circuit diagram is shown. Further, an enlarged view of the portion (1) of FIG. 20 is shown in FIG.
22 (1) and 22 (2) respectively show a cross section along line X1-X1 and a cross section along line X2-X2.

The cathode side terminal CK of the capacitor C is electrically insulated from the gate side conductive layer GP and the through hole H1.
Is electrically connected to the cathode side conductive layer KP on the lower surface. In addition, the gate side terminal TG of the transistor Tr
Are electrically insulated from the cathode side conductive layer KP and are electrically connected to the gate side conductive layer GP on the upper surface by a through hole H4. The negative side terminals CN and TN of the capacitor C and the transistor Tr are connected to through holes H2 and H3, respectively, which are electrically insulated from both the gate side conductive layer GR and the cathode side conductive layer KP. The leads of the terminals CK, CN, TN, and TG are inserted into the through holes H1 to H4 from the upper surface side and joined by soldering or the like from the lower surface side.

As can be seen from FIGS. 20 to 22, the gate side conductive layer GP (current paths G1P, G2P shown in FIG. 18,
GnP) and the cathode-side conductive layer KP (corresponding to the current paths K1P, K2P, and KnP shown in FIG. 18) are
Since the plate-shaped connecting conductor BG is formed on the front and back sides through the thin insulating layer, the turn-off gate currents become currents that flow in the current paths on the front and back sides in opposite directions, and the inductance in this portion can be suppressed to an extremely small value. In combination with the above-described measures for forming a plurality of parallel current paths in a plane, it is possible to easily and surely supply a desired steep turn-off gate current based on the above-mentioned principle.

FIG. 23 shows the ring-shaped gate terminal R for the turn-off gate current in the embodiment shown in FIGS.
The detection is performed at 16 locations around G, and the horizontal axis in the figure indicates each of the 16 locations around the gate terminal RG.
The vertical axis is the detected value, i is the turn-off gate current (however, the scale is the relative ratio), and Z is the time differential value di / dt of the turn-off gate current (however, the scale is the relative ratio). As shown in FIG. 23, it can be seen that the turn-off gate current i flows from the entire circumference of the gate terminal RG toward the gate driver GD. Therefore,
It can also be seen that the turn-off gate current at the gate terminal RG is distributed to the entire area of the internal gate electrode, and the current per unit area becomes small.

Embodiment 2. FIG. 24 shows a device for further reducing the turn-off gate current value in the vicinity of the central portion in FIG. 23, that is, in the vicinity of the side closest to the gate driver GD of the gate terminal RG. FIG. 6 is a plan view of the embodiment shown in FIG.
That is, the insulating region S is provided. This insulating region S is
It may be a long hole penetrating the straight portion BGD across the front and back, may be a groove with a bottom, or may be one in which an insulator is embedded in the slit. In any case, the insulating region S is, for example, a pair of linear insulating regions SD extending in a straight line in parallel from the gate driver GD toward the semiconductor switching element GCT, and from the tip of the linear insulating region SD. Furthermore, semiconductor switching element GCT
And an inclined insulating region SE that extends obliquely along the outer periphery of the gate terminal RG. The pair of insulating regions S is near the central portion in FIG. 24, that is, the gate driver GD of the gate terminal RG.
Since the turn-off gate current in the vicinity of the side closest to is attracted from the wide current path GCWP between the pair of inclined insulating regions SE to the narrow current path GCNP between the pair of linear insulating regions SD, the current becomes difficult to flow. 24, the current value of the central current path GCP decreases, and
The current values of P and GRP increase, and the distribution of the turn-off gate current flowing in the gate terminal RG is more homogenized.

FIG. 25 is an example in which the insulating region S is only a simple linear shape, and the distance between the pair of insulating regions S, S is such that it becomes narrower as it gets closer to the gate terminal RG.
Since the insulating region S has a simple shape, it can be manufactured at low cost. Note that, also in the example of FIG. 25, the central current path G
The current value of CP decreases, and the current paths GLP, GR other than the center
The current value of P rises, and the distribution of the turn-off gate current flowing in the gate terminal RG is more homogenized.

Embodiment 3. FIG. 26 is a device for further reducing the turn-off gate current value in the vicinity of the central portion in FIG. 23, that is, in the vicinity of the side closest to the gate driver GD of the gate terminal RG. 3 is a connection diagram showing another embodiment, in which three gate side current paths GLP, GCP, GRP equivalently extending from the gate terminal RG to the gate driver GD are provided, and these gate side current paths GLP, GCP, GRP are provided. Inductances LL, LC, LR and resistance R that compose the impedance
The sizes of L, RC and RR are set to the central portion G of the gate terminal RG.
Both ends GL and GR of the gate terminal RG, which are separated from the gate driver GD, by the gate side current path GCP connected to C
The gate-side current paths GLP and GRP connected to are made smaller. The inductance LC and resistance RC of the gate side current path GCP connected to the central portion GC of the gate terminal RG are the inductances L of the gate side current paths GLP and GRP connected to the end portions GL and GR other than the central portion GC.
Since L, LR, and resistors RL, RR are larger, the vicinity of the central portion in FIG. 23, that is, the vicinity of the gate terminal RG closest to the gate driver GD, that is, the central current path G
The turn-off gate current value of CP can be further reduced. Therefore, the current values of the current paths GLP and GRP other than the center are increased, and the distribution of the turn-off gate current flowing in the gate terminal RG is further homogenized.

In the figure, KP is a cathode side current path connecting between the cathode electrode K and the gate driver GD. Actually, it is shown separately from KLP, KCP and KRP. Therefore, it is displayed as a single KP. CL, CC and CR are capacitors and S
L, SC, and SR are turn-off transistors whose illustration is simplified in the form of a single-pole switch.
As shown in FIG. 7, n capacitors and transistors are divided into three groups corresponding to the current paths GLP, GCP, and GRP.

FIG. 27 shows a specific example in which the circuit shown in FIG. 26 is mounted on the plate-shaped connecting conductor BG, and the turn-on gate driver is not shown. Six transistors TrF from the first to the n-th (n = 6 in this example)
1 to TrF6 and the like are arranged. Then, the first and second driver outputs are connected to the current path GLP via the resistor RL and the inductance LL, and the third and fourth driver outputs are connected to the current path GCP via the resistor RC and the inductance LC and the fifth. And the sixth driver output are respectively sent to the current path GRP via the resistor RR and the inductance LR.

Fourth Embodiment FIG. 28 is devised in order to further reduce the turn-off gate current value in the vicinity of the central portion in FIG. 23, that is, in the vicinity of the side closest to the gate driver GD of the gate terminal RG, and therefore to increase the current values in other portions. FIG. 3 is a connection diagram showing another embodiment, in which a gate terminal R
Equivalently, three gate side current paths GLP, GCP, GRP from G to the gate driver GD are provided, and respective power supply voltages of these respective gate side current paths GLP, GCP, GRP are connected to the central portion GC of the gate terminal RG. The gate side current path GCP connected to both ends GL and GR of the gate terminal RG which are separated from the gate driver GD.
It is a higher version of LP and GRP. In the figure,
CL, CC, and CR are capacitors, SL, SC, and SR are turn-off transistors, which are simplified in the form of single-pole switches, VDN1 is, for example, -18V turn-off DC power supply, and VDN2 is, for example, -2V turn-off DC power supply. , KP are cathode-side current paths that connect the cathode electrode K and the gate driver GD, and are shown in a simplified manner as in FIG.

The voltage between the gate side current path GCP connected to the central portion GC of the gate terminal RG and the cathode side current path KP is 18 V, and the gate side current path GLP connected to both ends GL and GR, The voltage between GRP and the cathode side current path KP is 18 + 2 = 20V. Thus, the voltage between the gate side current path GCP connected to the central portion GC of the gate terminal RG and the cathode side current path KP is the gate side current path GLP connected to both ends GL, GR. G
Since the voltage is lower than the voltage between RP and the cathode side current path KP, the vicinity of the central portion in FIG. 23, that is, the vicinity of the side closest to the gate driver GD of the gate terminal RG, that is,
The turn-off gate current value of the central current path GCP can be further reduced. Therefore, the current paths GLP and GRP other than the center
Of the turn-off gate current flowing in the gate terminal RG is further homogenized.

FIG. 29 shows a specific example in which the circuit shown in FIG. 28 is mounted on the plate-shaped connecting conductor BG, and the turn-on gate driver is not shown. Six transistors TrF from the first to the n-th (n = 6 in this example)
1 to TrF6 and the like and DC power supplies VDN1 and VDN2 are arranged. The first and second drivers are connected to the power source V
The turn-off gate current output by the sum voltage (20V) of DN1 and VDN2 is output to the current path GLP, and the third and fourth drivers output the turn-off gate current output by the voltage (18V) of the power supply VDN1 to the current path GCP. The fifth and sixth drivers send a turn-off gate current, which is output by the sum voltage (20 V) of the power supplies VDN1 and VDN2, to the current path GRP, respectively.

Embodiment 5. FIG. 30 shows a semiconductor switching device GCT having a gate driver for flowing a turn-off gate current between a gate terminal RG and a cathode electrode K via current paths GLP, GRP, GCP. Driver GT
F1 and GTF2, and each of these gate drivers GT
F1 and GTF2 are arranged before and after the semiconductor switching element GCT, and the semiconductor switching element GC is provided.
The gate driver GTF2 near T has current paths GLP and GR.
The semiconductor switching element G is provided at a portion (left part, right part, tip part in the drawing) far from the gate terminal RG via P.
The gate driver GTF1 far from CT is located near the gate terminal RG via the current path GCP (the central portion in the figure).
Are connected to each other.

In the figure, C1, C2 and S1, S2
Is a turn-off transistor expressed by a capacitor and a single-pole switch of the gate driver GTF1, C
L1, CL2, CR1, CR2 and SL1, SL2,
SR1 and SR2 are turn-off transistors represented by a capacitor and a single-pole switch of the gate driver GTF2, respectively. In the figure, for convenience, the turn-on gate driver is omitted except for the power supply VDP.

FIG. 31 shows a concrete example in which the circuit shown in FIG. 30 is mounted on the plate-shaped connecting conductor BG, and the turn-on gate driver is not shown. FIG. 1A is its plan view, and FIG. 2B is its side view. 32 is a sectional view taken along line X3-X3 of FIG. 31, and FIG. 33 is X4- of FIG.
It is sectional drawing of a X4 line. Here, it is assumed that the first conductive layer CC1 forming the gate side current path as the plate-shaped connecting conductor BG and the second conductive layer CC2 forming the cathode side current path are alternately stacked via the insulating layer, Furthermore, this first
The two conductive layers CC1 and the second conductive layer CC2 are provided, that is, two pairs of conductive layers are provided.

Then, as shown in FIG. 31 (1), as shown in FIG.
The slit S described in 4 and the like is provided so that the gate driver GTF1 supplies the turn-off gate current to the central portion GC of the gate terminal RG, and the gate driver GTF2 turns off the left portion GL and the right portion GR. The current paths are separated in plane so that the gate current is supplied. Further, as shown in FIG. 32, the gate driver GTF
Among the four conductive layers of the plate-shaped connecting conductor BG, the uppermost layer and the second conductive layer are used as the first conductive layer CC1-2 and the second conductive layer CC2-2, respectively. To the gate side terminal TG and the cathode side terminal CK. Then, the second conductive layer CC2-2 and the fourth conductive layer CC2-2 and the fourth conductive layer CC2-2 are formed by the through hole TH1 formed in the portion far from the gate terminal RG.
Electrically connects the conductive layer of the layer. As a result, the gate driver GTF2 close to the semiconductor switching element GCT is pressed against and electrically connected to the gate terminal RG and the cathode electrode K, which are located far from the gate terminal RG.

In addition, as shown in FIG. 33, the gate driver GTF1 includes the third conductive layer and the fourth conductive layer of the four conductive layers of the plate-like connecting conductor BG, which are respectively the first conductive layer CC1.
-1 and the second conductive layer CC2-1, and their gate side terminal TG and cathode side terminal CK, respectively.
Connect. Then, the first conductive layer CC1- is formed by the through hole TH2 formed in the portion close to the gate terminal RG.
1 and the first conductive layer are electrically connected. As a result,
The gate driver GTF1 far from the semiconductor switching element GCT has a gate terminal RG located near the gate terminal RG.
And the cathode electrode K are pressed and electrically connected.

32 and 33, the gate drivers GTF1 and GTF2 are arranged such that the conductive layers used by the plate-shaped connecting conductors BG are used as upper and lower pairs. Of the gate drivers GTF1 and GTF2
In both cases, four conductive layers may be used to connect the gate terminal RG to the near portion and the far portion, respectively.

As described above, in the fifth embodiment, the slits S are formed in the plate-shaped connecting conductor BG to form the parallel current paths GCP, GLP, GRP, and the gate driver close to the semiconductor switching element GCT. The GTF2 passes through the current paths GLP and GRP, and the gate terminal R
Since the gate driver GTF1 far from the semiconductor switching element GCT is connected to the portion near the gate terminal RG via the current path GCP to the portion far from G, the vicinity of the central portion in FIG. Near the side closest to the gate driver GD, that is,
The turn-off gate current value of the central current path GCP can be further reduced. Therefore, the current paths GLP and GRP other than the center
Of the turn-off gate current flowing in the gate terminal RG is further homogenized.

Sixth Embodiment FIG. 34 shows the fifth embodiment.
Similarly to the above, the gate driver is composed of two gate drivers GTF1 and GTF2 arranged in front and rear, respectively connected to a portion near the gate terminal RG and a portion far from the gate terminal RG. Is different from the form 5. That is, in the sixth embodiment, the parallel current paths are formed by distinguishing the used conductive layers of the plate-shaped connecting conductor BG, which will be described below with reference to FIGS.

FIG. 35 shows a concrete example in which the circuit shown in FIG. 34 is mounted on the plate-shaped connecting conductor BG, and the turn-on gate driver is not shown. FIG. 1A is its plan view, and FIG. 2B is its side view. 36 is a sectional view taken along line X5-X5 of FIG. Here, the first conductive layer CC1 forming the gate side current path as the plate-shaped connecting conductor BG and the second conductive layer CC forming the cathode side current path.
2 and 2 are alternately stacked via an insulating layer, and further, the first conductive layer CC1 has two layers and the second conductive layer CC has two layers.
2 is provided with two layers, that is, two pairs of conductive layers.

As shown in FIG. 36, the gate driver GT
The gate side terminal TG of F2 is electrically connected to the first conductive layer CC1-2 of the second layer of the plate-like connecting conductor BG, and the cathode side terminal CK of the gate driver GTF2 is the second conductive layer of the third layer. It is electrically connected to CC2-2. And the first
Conductive layer CC1-2 is connected to the first conductive layer through a through hole TH3 formed at the tip of gate terminal RG, and this first conductive layer is connected to semiconductor switching element G.
The gate terminal RG of CT is pressure-contacted and electrically connected. Although not shown, the first and fourth conductive layers are electrically isolated from each other near the line connecting the left portion GL and the right portion GR of the semiconductor switching element GCT.

The second conductive layer CC2-2 is connected to the fourth conductive layer through the through hole TH4 formed at the tip of the gate terminal RG, and the fourth conductive layer is the semiconductor switching element GCT. Is pressed and electrically connected to the cathode electrode K of.

On the other hand, the gate side terminal TG of the gate driver GTF1 is the first conductive layer C of the first layer of the plate-like connecting conductor BG.
Gate driver GTF1 electrically connected to C1-1
The cathode side terminal CK of the second conductive layer CC2- of the fourth layer.
Electrically connected to 1. And both conductive layers CC1-1
And CC2-1 are directly pressed and electrically connected to the gate terminal RG and the cathode electrode K, respectively.

As described above, in the sixth embodiment, a plurality of pairs of conductive layers on the gate side and the cathode side are divided without providing the slit S and the like. In this example, among the four conductive layers, , The current paths FP for the gate driver GTF1 are formed by the outer conductive layers of the first layer and the fourth layer, and the current paths B for the gate driver GTF2 are formed by the inner conductive layers of the second layer and the third layer.
The gate driver GTF2, which forms P and is close to the semiconductor switching element GCT, passes through the current path BP and then the gate terminal RG.
Since the gate driver GTF1 farther from the semiconductor switching element GCT is connected to the nearer part of the gate terminal RG via the current path FP, the farther part of the gate terminal RG is located near the central part in FIG. 23, that is, the gate of the gate terminal RG. The turn-off gate current value of the current path GCP in the vicinity of the side closest to the driver GD, that is, the central current path GCP can be further reduced. Therefore, the current values of the current paths GLP and GRP other than the center are increased, and the distribution of the turn-off gate current flowing in the gate terminal RG is further homogenized.

The method of forming a parallel current path group by providing the slit of the fifth embodiment and the method of dividing a plurality of stacked conductive layers of the sixth embodiment are used in combination. The current distribution may be homogenized.

Seventh Embodiment In FIG. 37 (1), the turn-off gate current value in the vicinity of the central portion in FIG. 23, that is, in the vicinity of the side closest to the gate driver GD of the gate terminal RG is further reduced, and therefore the current values of other portions are increased. A plan view showing another embodiment devised for that purpose, FIG. 2B is a side view of the same, and two turn-off gate drivers GTF1 and GTF2 are provided, and these gate drivers G are provided.
A semiconductor switching element GCT is provided between TF1 and GTF2.
And a turn-off gate current flowing through the gate terminal RG is generated by the gate drivers GTF1 and GT2.
Divide and flow into F2. In addition, FIG. 24 shows the configuration between the gate terminal RG and the one gate driver GTF1 and between the gate terminal RG and the other gate driver GTF2.
An insulating region S similar to that of the embodiment of FIG. 25 is provided. Therefore, the current value of the gate terminal central portion GC on either side of the gate drivers GTF1 and GTF2 is suppressed, and the turn-off gate current is reduced by the gate drivers GTF1 and GTF of both gate drivers.
The distribution of the turn-off gate current flowing in the gate terminal RG is more surely equalized in combination with the shunting into two. The turn-on gate driver GTN1,
The GTN2 is also the gate drivers GTF1 and GTF2 described above.
The arrangement is similar to the arrangement.

Eighth Embodiment FIG. 38 shows a structure in which a plurality of semiconductor switching devices described above are used and are assembled together with other peripheral components as a semiconductor stack device. FIG. 1A is its structural diagram, and FIG. 2B is its circuit block diagram. In the figure, GCT is a semiconductor switching element, GD is a gate driver, FD is a freewheeling diode, SD is a snubber diode, FIN is a cooling fin as a cooling member, ST is a stack electrode, and IS is an insulating spacer. Of these, the water cooling pipe PW is installed in the cooling fin FIN.
Are connected to radiate heat generated from the semiconductor switching element GCT and the freewheeling diode FD to the cooling water. The FLM is a mounting frame that stacks the above-mentioned components and tightens them from the top and bottom, and stores the components in a pressure contact state. Although the gate terminal RG in each of the above-described embodiments has been described as having a ring shape extending in the circumferential direction of the semiconductor switching element GCT, as shown in FIG. 39, in the circumferential direction of the semiconductor switching element GCT. A plurality of terminal strips TS are provided at equal intervals along the gate terminal RG1, which is, so to speak, discontinuously extending in the circumferential direction. It is effective. Further, by applying the semiconductor switching elements according to the present invention and further including a gate control device for controlling the gates of these semiconductor switching elements to perform power conversion, as described above, the distribution of the turn-off gate current flowing to the gate terminal is uniform. Thus, it is possible to obtain a high-performance power converter such as an inverter that can pass a large turn-off gate current.

[0117]

As described above, the semiconductor switching device according to the first aspect of the invention is provided with the gate terminal extending in the circumferential direction of the semiconductor switching element, and the current path has a plurality of turn-off currents having the gate terminals. Since the parallel current paths that flow in parallel to the points are provided, the turn-off current can flow in an even distribution over the circumferential direction of the gate terminal.

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, a current path is formed of a conductor region and an insulating region, and the turn-off current is the gate terminal. Since the parallel current paths that flow in parallel to a plurality of points are formed, the parallel current paths can be formed easily and reliably.

In the semiconductor switching device according to a third aspect of the present invention, the current path of the semiconductor switching device includes the first conductive layer forming the gate side current path and the second conductive layer forming the cathode side current path via the insulating layer. Since it is composed of a wiring board formed by stacking the conductive layers, the conductive layers are used as conductor areas, and slits having a predetermined pattern are formed in the wiring board to serve as an insulating area, so that a parallel current path of low impedance can be obtained easily and surely. To be

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, and a parallel current in which a turn-off current flows in parallel at a plurality of locations of the gate terminal is provided in a current path. Since a means for reducing the impedance difference between the gate terminal and the gate driver in each current path of this parallel current path is provided as a path, the turn-off current of each parallel current path flowing in parallel to the gate terminal can be more reliably achieved. It can be in a uniform state.

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, and a turn-off current flows in parallel in the current path in parallel at a plurality of positions of the gate terminal. And the gate driver is composed of a plurality of gate drivers, and the voltage applied to the semiconductor switching element of each gate driver is a different voltage so as to reduce the difference in current in each current path of the parallel current paths. Therefore, the turn-off current of each parallel current path flowing in parallel to the gate terminal can be more surely made uniform.

According to another aspect of the semiconductor switching device of the present invention, the semiconductor switching element is provided with a gate terminal extending in the circumferential direction, and the gate driver is composed of a plurality of gate drivers. The gate driver is disposed before and after the switching element, and the gate driver close to the semiconductor switching element is located far from the gate terminal, and the gate driver far from the semiconductor switching element is located near the gate terminal via current paths. Since they are connected in parallel, the turn-off currents of the parallel current paths flowing in parallel to the gate terminals can be more surely made uniform.

According to a seventh aspect of the semiconductor switching device of the present invention, a current path of the semiconductor switching device is a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path via an insulating layer. And a parallel current path in which the turn-off current flows in parallel to a plurality of places of the gate terminal by forming slits of a predetermined pattern on the wiring board. A gate driver close to the semiconductor switching element is via a current path connected to a part far from the gate terminal, and a gate driver far from the semiconductor switching element is via a current path connected to a part close to the gate terminal,
Since they are connected to each other, the impedance of each parallel current path becomes substantially uniform, and the current distribution is more surely uniform.

Further, in the semiconductor switching device according to an eighth aspect, a plurality of pairs of the current paths are formed by a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. Both conductive layers are alternately laminated to form a wiring board that is laminated via an insulating layer, and the gate driver close to the semiconductor switching element is located at a distant portion of the gate terminal through a part of the conductive layers of the plurality of pairs, Since the gate driver far from the semiconductor switching element is connected to the portion close to the gate terminal via the remaining conductive layers of the plurality of pairs, the impedance of each parallel current path is substantially uniform without providing a slit. Therefore, the distribution of the current becomes more surely uniform.

The semiconductor stack device according to the ninth aspect and the power conversion device according to the tenth aspect are provided with the above semiconductor switching elements, and in particular, the distribution of the turn-off current flowing to the gate terminal is uniform and a large turn-off current can flow. It is possible to obtain a high-performance semiconductor stack device and a power conversion device that can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor switching device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a gate driver circuit.

FIG. 3 is a diagram showing a waveform of a current flowing to the gate side.

FIG. 4 is a cross-sectional view showing a GTO device package of the present invention.

FIG. 5 is a plan view showing the appearance of a GTO device package of the present invention.

FIG. 6 is a plan view showing the external appearance of the gate driver of the present invention.

FIG. 7 is a cross-sectional view showing a method for connecting a GTO element package of the present invention to a gate driver.

FIG. 8 is a plan view showing a gate driver when gate reverse currents are taken out from multiple directions.

FIG. 9 is a diagram showing an operation of the semiconductor switching device according to the first embodiment of the present invention.

FIG. 10 is a diagram showing an equivalent model of GTO.

FIG. 11 is a diagram showing the relationship between the increase rate of the voltage between the anode and the cathode electrode and the turn-off gain.

FIG. 12 is a diagram showing a flow of a main current at the time of turn-off in a conventional technique.

FIG. 13 is a diagram showing a main current flow at turn-off in the present invention.

FIG. 14 is a circuit diagram of a semiconductor switching device according to the first embodiment of the present invention, which is different from FIG.

FIG. 15 is a diagram showing measured waveforms in the apparatus of FIG.

FIG. 16 is a diagram showing a gate driver circuit of the present invention, which is a simplified version of FIG. 2.

FIG. 17 is a diagram showing a schematic configuration of a semiconductor switching device according to a first embodiment of the present invention.

FIG. 18 is a circuit configuration diagram for realizing the parallel current path shown in FIG.

FIG. 19 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 18 on a plate-shaped connecting conductor.

20 is a cross-sectional view showing an example of mounting arrangement of the circuit configuration of FIG. 18 on a plate-shaped connecting conductor.

FIG. 21 is an enlarged view showing a portion (1) of FIG. 20.

22 is a sectional view taken along line X1-X1 and X2-X2 of FIG. 21.

FIG. 23 is a diagram showing an actual measurement result of a turn-off gate current in the circumferential direction of a gate terminal.

FIG. 24 is a configuration diagram showing a semiconductor switching device according to a second embodiment of the present invention.

FIG. 25 is a configuration diagram showing a semiconductor switching device different from that of FIG. 24 in the second embodiment of the present invention.

FIG. 26 is a circuit diagram showing a semiconductor switching device according to a third embodiment of the present invention.

FIG. 27 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 26 on a plate-shaped connecting conductor.

FIG. 28 is a circuit diagram showing a semiconductor switching device according to a fourth embodiment of the present invention.

FIG. 29 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 28 on a plate-shaped connecting conductor.

FIG. 30 is a circuit diagram showing a semiconductor switching device according to a fifth embodiment of the present invention.

31 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 30 on a plate-shaped connecting conductor.

32 is a cross-sectional view taken along line X3-X3 of FIG.

33 is a cross-sectional view taken along line X4-X4 of FIG.

FIG. 34 is a circuit diagram showing a semiconductor switching device according to a sixth embodiment of the present invention.

FIG. 35 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 34 on a plate-shaped connecting conductor.

36 is a cross-sectional view taken along line X5-X5 of FIG.

FIG. 37 is a configuration diagram showing a semiconductor switching device according to a seventh embodiment of the present invention.

FIG. 38 is a configuration diagram showing a semiconductor stack device according to an eighth embodiment of the present invention.

FIG. 39 is a view showing a modified example of the gate terminal RG extending in the circumferential direction.

FIG. 40 is a diagram showing a circuit of a conventional device.

FIG. 41 is a diagram showing measured waveforms of a conventional circuit.

FIG. 42 is a cross-sectional view of a conventional GTO device package.

FIG. 43 is a plan view showing the appearance of a conventional GTO device package.

FIG. 44 is a diagram for pointing out a conventional problem.

FIG. 45 is a diagram for pointing out a conventional problem.

[Explanation of symbols]

3 GTO, 3A anode electrode, 3K cathode electrode, 3G gate electrode, 4 gate driver, 5 peak voltage suppression circuit, R1 path, I _A main current, I _G turn-on control current, I _GQ gate reverse current, GCT semiconductor switching device, RG, RG1 gate terminal, A anode electrode, K cathode electrode, GD gate driver, GTF turn-off gate driver, VDN1,
VDN2 DC power supply, BG, plate-like connecting conductor as wiring board, CC1 first conductive layer, CC2 second conductive layer,
S slit, GLP, GCP, GRP, FP, BP
Current path, FIN cooling fins, FLM mounting frame, TS
Terminal piece.

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-9-201039 (JP, A) JP-A-8-330572 (JP, A) JP-A-61-227661 (JP, A) JP-A-8- 331835 (JP, A) Actual development Sho 55-67685 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02N 1/06

Claims (10)

(57) [Claims] 1. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. A semiconductor switching device comprising a semiconductor switching element having a gate terminal extending in a circumferential direction, and the current path being a parallel current path in which the turn-off current flows in parallel to a plurality of locations of the gate terminal. . 2. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. A semiconductor switching device is provided with a gate terminal extending in the circumferential direction, the current path is formed by a conductor region and an insulating region, and the turn-off current flows in parallel at a plurality of positions of the gate terminal. A semiconductor switching device characterized in that 3. A first current path forming a gate side current path
Of the conductive layer and the second conductive layer forming the cathode side current path are laminated with an insulating layer in between, and both conductive layers are used as conductor regions, and a predetermined pattern is formed on the wiring board. The semiconductor switching device according to claim 2, wherein a slit is formed to form an insulating region. 4. A semiconductor switching device comprising a semiconductor switching element having a gate electrode, and a gate driver supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching device is provided with a gate terminal extending in the circumferential direction, and the current path is a parallel current path in which the turn-off current flows in parallel to a plurality of locations of the gate terminal, and each current path of the parallel current path. 2. A semiconductor switching device comprising means for reducing a difference in impedance between the gate terminal and the gate driver in. 5. A semiconductor switching device comprising a semiconductor switching element having a gate electrode, and a gate driver supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. A semiconductor switching device is provided with a gate terminal extending in the circumferential direction, the current path is a parallel current path in which the turn-off current flows in parallel to a plurality of locations of the gate terminal, and a plurality of gate drivers are provided. The semiconductor switching device is characterized in that the voltage applied to the semiconductor switching element of each of the gate drivers is a different voltage so as to reduce the difference between the currents in the current paths of the parallel current paths. . 6. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching element is provided with a gate terminal extending in the circumferential direction, the gate driver is composed of a plurality of gate drivers, and each of these gate drivers is arranged in front of and behind the semiconductor switching element. The gate driver near the semiconductor switching element is located far from the gate terminal, and the gate driver far from the semiconductor switching element is located near the gate terminal.
A semiconductor switching device, characterized in that each is connected through the current path. 7. A first current path forming a gate side current path
And a second conductive layer forming a cathode side current path are laminated on each other with an insulating layer in between, and a slit having a predetermined pattern is formed on the wiring substrate to form the current. The path is a parallel current path in which the turn-off current flows in parallel to a plurality of locations of the gate terminal,
The gate driver close to the semiconductor switching element, through the current path connected to the far part of the gate terminal,
7. The semiconductor switching device according to claim 6, wherein the gate driver far from the semiconductor switching element is connected via a current path connected to a portion near the gate terminal. 8. A first current path forming a gate side current path
A plurality of pairs of conductive layers and a second conductive layer forming the cathode side current path, and a wiring board formed by alternately stacking the conductive layers with an insulating layer interposed therebetween, and a gate close to the semiconductor switching element. The driver is distant from the gate terminal through a part of the conductive layers of the plurality of pairs, and the gate driver far from the semiconductor switching element is near the gate terminal through the remaining conductive layers of the plurality of pairs, 7. The semiconductor switching device according to claim 6, wherein they are connected to each other. 9. A semiconductor switching element and a cooling member for radiating heat generated from the semiconductor switching element are stacked and arranged in a mounting frame.
9. A semiconductor stack device using the semiconductor switching device according to any one of 8 to 8. 10. A power conversion device using the semiconductor switching device according to claim 1, further comprising a gate control device that gate-controls the semiconductor switching element to perform power conversion.