JP3355511B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (in particular, a dynamic RA having a stacked cell capacitor, for example).
M).

[0002]

2. Description of the Related Art There are a number of manufacturing processes for memory cells of a stack type dynamic RAM of the COB (Cell Over Bitline) type.
Called WL. ) And a bit line (hereinafter, referred to as BL) after the formation of an interlayer insulating film, the following two representative methods are employed.

[0003] The first representative method is the following steps 1 to
It consists of nine. 1. 1. Photo process of bit line contact (hereinafter, referred to as BLCT) for connecting BL to a substrate 2. BLCT etching step 3. BL material deposition process 4. BL photo process BL etching process 6. BL and storage node (hereinafter, referred to as SN)
6. Formation of interlayer insulating film for separating from 7. Photo step of storage node contact (hereinafter, referred to as SNCT) for connecting SN to substrate 8. SNCT etching step SN material deposition process

[0004] A second representative technique is to provide an intermediate conductor layer (hereinafter, referred to as "between") between BL and a substrate, between SN and a substrate, or both.
It is called BLPAD or SNPAD. ), And takes the following steps 1 to 15 (in the following example, BL
Both PAD and SNPAD are used). 1. Bit line contact 1 (hereinafter, referred to as BLCT1) for connecting BLPAD to the substrate, and SN
1. Photo process of storage node contact 1 (hereinafter referred to as SNCT1) for connecting the PAD to the substrate 2. BLCT1, SNCT1 etching step 3. BLPAD, SNPAD material deposition process 4. BLPAD, SNPAD photo process BLPAD, SNPAD etching process (Step 1
Method 5 may be performed independently of BLPAD and SNPAD. ) 6. 6. Formation of interlayer insulating film for separating BLPAD and BL 7. Photo process of bit line contact 2 (hereinafter, referred to as BLCT2) for connecting BL and BLPAD 8. BLCT2 etching step BL material deposition process 10. BL photo process 11. BL etching step 12. 12. Formation of interlayer insulating film for separating BL and SN 13. Photo process of storage node contact 2 (hereinafter referred to as SNCT2) for connecting SN and SNPAD SNCT2 etching step 15. SN material deposition process

[0005] The first representative method described above is illustrated in FIGS. 61 to 69.

First, as shown in FIG. 62, after a field SiO ₂ film 2 is selectively formed on one principal surface of a P ⁻ type silicon substrate 1 by a known LOCOS method, a gate oxide film 5 is formed.
Is formed by a thermal oxidation method, a first layer of polysilicon is deposited by a CVD method, and this is patterned by a photoetching method to form a polysilicon word line WL. Further, using the word line WL as a mask, an N-type impurity ( For example, arsenic or phosphorus) is implanted into the silicon substrate 1 by an ion implantation method,
An N ⁺ type semiconductor region (drain and source region) is formed by a self-alignment method to form a transfer gate TR.

Although not shown, an insulating layer (for example, an SiO ₂ layer) deposited on the entire surface by a known CVD technique is etched back, and an SiO ₂ sidewall is formed on the side surface of the word line WL. Thereafter, an N-type impurity (for example, arsenic or phosphorus) is ion-implanted into the N-type region formed in advance at a low concentration using the word lines WL and sidewalls as a mask, and is implanted relatively deeply. The N ⁺ -type drain region 3 and the N ⁺ -type source region 4 (storage node) are formed in a self-aligned manner, whereby the transfer gate TR
May be configured.

Next, although a single layer 7 is shown in the drawings for simplicity, an SiO ₂ layer for passivation, a Si ₃ N ₄ layer for protecting an underlayer, and the like are laminated on the surface of the silicon substrate 1. Then, an interlayer insulating film 7 is formed.

Then, a mask material 8 made of a photoresist or polysilicon is formed on the interlayer insulating film 7 and selectively exposed and developed to form a bit line contact B.
A non-mask portion (opening) 8a for LCT is formed.

Next, as shown in FIG. 63, the interlayer insulating film 7 is selectively etched down to the silicon substrate 1 using the mask 8 to form a bit line contact hole BLCT.

Next, as shown in FIG. 64, a bit line material BL 'is deposited by sputtering or the like, and
As shown in FIG. 65, etching is performed using the mask 9 having a predetermined pattern to form a bit line BL as shown in FIG.

Next, as shown in FIG. 67, after forming an interlayer insulating film 10 for separating BL and SN, as shown in FIG. 68, a mask 11 is formed, and this is selectively exposed and developed. Unmasked part (opening) for storage node contact
11a is formed.

Next, as shown in FIG. 69, the interlayer insulating film 10, and furthermore, 7 are selectively etched down to the silicon substrate 1 using a mask 11, thereby forming a storage node contact hole SNCT.

Next, as shown in FIG. 70, polysilicon 12 as a storage node material is deposited. After this,
Patterning of this polysilicon layer, formation of dielectric film 100 by surface oxidation, nitridation or deposition, upper electrode
Through the formation of 101, a stacked capacitor is manufactured.

FIGS. 71 to 79 show another example of the first representative method.

In this example, when an oxide film is used for the interlayer insulating film 7 in order to make the SNCT a self-aligned structure with respect to the BL, a nitride film 20 is formed around the BL as shown in FIG. Cover, an interlayer insulating film 7 and an opening 18
A mask 18 having a is formed.

Next, as shown in FIG. 72, a bit line contact hole BLCT is formed in the interlayer insulating film 7.

Next, as shown in FIG. 73, a bit line material BL 'and a nitride film 13 are stacked, and a mask 19 is formed as shown in FIG.
The bit line BL is formed in a predetermined pattern as shown in FIG.

Next, as shown in FIG. 76, after forming a sidewall 14 of a nitride film on the side surface of the bit line BL,
As shown in FIG. 77, the mask 21 is formed by a photo process.

Next, as shown in FIG. 78, the interlayer insulating film 7
Is etched to form storage node contact holes SNCT reaching silicon substrate 1.

Next, as shown in FIG. 79, a polysilicon layer 22 as a storage node material is deposited.

However, FIGS. 62 to 70 and FIGS. 71 to 79
The problems with the first method described in (1) can be summarized as follows. (1) The opening process for contacts is performed by BLCT,
Since there are two times of SNCT, the number of steps is large. (2) When the SNCT does not have a self-aligned structure with respect to the BL (FIGS. 62 to 70), a space for aligning the SNCT with the BL is required, so that it is difficult to reduce the cell size.

(3) When the SNCT has a self-aligned structure with respect to the BL (FIGS. 71 to 79), highly selective etching of the oxide film and the nitride film is required in the opening etching process. Such a process requires a special device and uses a nitride film having a high dielectric constant for an oxide film around the BL, thereby increasing the parasitic capacitance of the BL, reducing the circuit operation speed, and reducing power consumption. Tends to increase.

On the other hand, the second representative method described above is shown in FIGS.
FIG. 94 will be described.

As shown in FIG. 80, each diffusion region and word lines WL, Si
An O ₂ layer 31 ′ and a side wall 30 are formed. The mask 38 is formed for forming a hole between the word lines WL.

Next, as shown in FIG. 81, a bit line contact hole BLCT1 and a storage node contact hole SNCT1 are respectively formed by etching.

Next, as shown in FIG. 82, materials BLPAD ′ and SNPAD ′ of each intermediate conductor layer for the bit line BL and the storage node SN are deposited.

Next, as shown in FIG. 83, a mask 30 is formed, and the PAD material is selectively etched using the mask 30 to form respective intermediate conductor layers BLPAD and SNPAD as shown in FIG. I do.

Next, as shown in FIG. 85, the interlayer insulating film 31 is formed.
Are formed, and the intermediate conductor BL is formed using the mask 32 shown in FIG.
Selectively etching up to PAD, as shown in FIG. 87,
A bit line contact through hole BLCT2 is formed.

Next, as shown in FIG. 88, after a bit line material BL ′ is deposited by sputtering or the like,
By etching with a mask 39 having a predetermined pattern shown in 89, a bit line BL as shown in FIG. 90 is formed.

Next, as shown in FIG. 91, after forming an interlayer insulating film 40 for separating BL and SN, as shown in FIG. 92, a mask 41 is formed, and this is selectively exposed and developed. Unmasked part (opening) for storage node contact
41a is formed.

Next, as shown in FIG. 93, the interlayer insulating film 40, and furthermore, 31 are selectively etched using a mask 41 to form a through hole SNCT2 for a storage node contact.
To form

Next, as shown in FIG. 94, polysilicon 42 as a storage node material is attached. After this,
A stacked capacitor is manufactured through patterning of the polysilicon layer, formation of a dielectric film by surface oxidation or the like, and formation of an upper electrode.

As described above, the second method as shown in FIGS. 80 to 94 is most problematic in that the number of steps is large.

[0035]

As described above, conventionally, there has been a method of solving one or two of the problems of the increase in the number of steps, the difficulty in reducing the size of the cell, and the deterioration of the characteristics. There was no way to solve everything. It is an object of the present invention to provide a method that can solve all of those problems simultaneously.

[0036]

A first semiconductor device according to the present invention is provided.
The method of manufacturing the transistor
One diffusion area is for the bit line and the other diffusion area is for the key line.
Semiconductor device having memory cell connected to capacitor
In manufacturing the device, a capacitor for connecting to the bit line is used.
Tact hole and contact for connection to the capacitor
Forming holes and forming bit lines
When patterning material to form bit lines
The contact hole for connection to the bit line and the key
The contact hole for connection to the capacitor and a conductive material
And then the bit line forming material
And pattern this bit line forming material.
Forming a bit line by using
In the contact hole for connection to the side and the capacitor
The upper surface of the conductive material was oxidized and then formed over the entire surface
Etch back the insulating film and update it to the side of the bit line.
Forming a thick sidewall on the substrate.

Further, a method of manufacturing the second semiconductor device of the present invention
The method is defined by the field insulating film on the main surface of the semiconductor substrate
Over the semiconductor layer of the first conductivity type via a gate insulating film.
Forming a second word line and the semiconductor
A layer of said first word line and said field insulating film;
Between the first word line and the second word line.
Between the second word line and the field.
The first, second and third conductive types of the second conductive type
Forming semiconductor regions, respectively, and the semiconductor substrate
Forming a first insulating film on the field insulating film,
The first and second word lines, and the first and second word lines;
Covering the third semiconductor region and the first insulating film
Is selectively removed, and the first semiconductor region reaching the first semiconductor region is removed.
Storage node contact, the second semiconductor region
Bit line contact, as well as the third half
A second storage node contact reaching the conductive area
Forming each, and a first conductive layer on the semiconductor substrate.
Forming an electrical material to cover the first insulating film and
1 storage node contact, the bit line connector
Contact and the second storage node contact
A step of filling the conductive material,
And selectively removing the bit lines on the first insulating film.
Forming the first and second storage node cores;
Contacts the first and second storage node plugs.
Forming a second insulating layer on the semiconductor substrate.
Forming a film to form the bit line, the first insulating film,
Cover the first and second storage node plugs
And etching back the second insulating film to form the bit.
Forming sidewalls on the side surfaces of the train and
Exposing the first and second storage node plugs
And forming a second conductive material on the semiconductor substrate.
And selectively removing the second conductive material to remove the first conductive material.
And the second storage node plug, respectively.
Forming the first and second strade nodes.
Have.

Further , according to the second method for manufacturing a semiconductor device,
In the method, the first conductive material is formed and then the first conductive material is formed.
Forming a third insulating film on the conductive material of
The third insulating film and the first conductive material have the same pattern.
Is patterned on the bit line and the third
An insulating film is formed.

[0039]

[0040]

In the above, the storage node material can be applied after the formation of the sidewall.

[0042]

Embodiments of the present invention will be described below.

FIGS. 1 to 17 show a first embodiment in which the present invention is applied to a COB type dynamic RAM. Here, FIGS. 1 to 8 are sectional views taken along line XX of FIG.
16 to 16 show cross sections taken along line YY of FIG.

The manufacturing process of the memory cell of the dynamic RAM according to the present embodiment will be described. First, as shown in FIGS.
Then, each diffusion region and a word line WL are formed.

Then, after forming an interlayer insulating film 51 made of SiO ₂ on the word line WL, a mask 58 made of polysilicon is applied, and a bit line contact B
A non-mask portion (opening) 58A for simultaneously patterning the LCT and the storage node contact SNCT;
58B are respectively formed.

Then, as shown in FIG. 2 and FIG. 10, the bit line contact hole B
LCT and storage node contact hole SNCT
Are formed by etching the interlayer insulating film 51, respectively. These contact holes may be etched simultaneously or separately (in this case, separate masks may be used).

Next, as shown in FIGS. 3 and 11, a bit line material BL 'is deposited by sputtering or the like, and a SiO ₂ insulating layer 60 is formed thereon.

Next, as shown in FIGS. 4 and 12, a mask made of polysilicon is used to form a bit line.
After forming a 59 to a predetermined pattern, then used to etch, as shown in FIGS. 5 and 13, SiO ₂ layer on top 60
Is formed, and the bit line material BL ′ is also applied to the contact holes SNCT by SNCT.
Leave as plug.

Next, as shown in FIGS. 6 and 14, after an interlayer insulating film 40 for separating BL and SN is formed, as shown in FIGS. 7 and 15, the sides of the bit line BL are etched back. While covering with the side wall 54, SN
Expose the CT PLUG.

Next, as shown in FIGS. 8 and 16, polysilicon 22 as a storage node material is attached. Thereafter, adjacent storage nodes are separated by patterning the polysilicon layer, and a stacked capacitor is manufactured through formation of a dielectric film 100 by surface oxidation or the like and formation of an upper electrode 101. FIG. 17 shows a layout corresponding to FIGS. 8 and 16 (the bit line BL is formed in a wave shape).

As described above, the method according to the present embodiment includes:
It is characterized mainly by the following four points.

1. BLCT and SNCT are simultaneously patterned (FIGS. 1 and 9) and etched using a common mask (FIG. 2). 2. Substrate-SN in SNCT at the same time as BL etching
A connection conductive portion (SNCT PLUG) between them is formed using a part of the BL constituent material (FIGS. 5 and 13). 3. The insulating film between the SN and the SNCT PLUG should be removed at the same time as the sidewall etching for insulating between the BL and the SN (FIGS. 7 and 15). 4. Then, immediately deposit the material that will be the SN (FIGS. 6 and 16).

Therefore, the problems can be solved in the following various points with respect to the above-described first and second methods.

<Regarding Problems of First Method> (1) The opening process is performed only once since the BLCT and the SNCT are simultaneously formed, and the number of steps is small. Nine steps (FIG. 62)
70) to eight steps. (2) Even if the SNCT does not have a self-aligned structure with respect to the BL, since the SNCT is completed before the BL is formed, there is no need to take a space for the SNCT and the BL not to contact. Therefore, the cell can be reduced in size.

(3) When the SNCT has a self-aligned structure with respect to the BL, since the SNCT is completed before the BL is formed, it is not necessary to make the SNCT and the BL self-aligned. Accordingly, there is no need to cover the periphery of the BL with a nitride film and perform a high-selective etching of the oxide film and the nitride film in the opening etching process, so that a special device for this step is not required. Further, since it is not necessary to use a nitride film having a high dielectric constant for the oxide film around BL,
There is no increase in the parasitic capacitance of L, no decrease in circuit operation speed, and no increase in power consumption.

<Regarding Problems of the Second Method> The number of steps, which was the most serious, was reduced to 15 steps (FIGS. 80 to 94).
Is reduced to eight steps.

Other effect 1: When there is a capacity between adjacent BLs, the effective storage node capacity is reduced due to line noise between the BLs unless a technique such as BL twist is used. In the example cell, as clearly shown in FIG. 16, the height position P1 of the BL bottom coincides with (or is located at) the height position P2 of the SN bottom or the bottom of the cell plate on the SN, and the adjacent BL The number of insulating layers between the adjacent BLs can be reduced (refer to FIG. 70), and there is no capacitance between adjacent BLs (see FIG.
A part 16).

Other Effect 2: BL, SN, or the capacity between cell plates, which accounts for a large proportion of the BL capacity,
Oxide film 60 on BL and sidewall oxide film 54 beside BL
The thickness can be reduced by increasing the thickness (part B in FIG. 16).

Other Effect 3: In general, it is necessary to perform a layout in which the BLCT and the BL have an appropriate overlap amount so that the BLCT and the BL are not misaligned and the substrate is not etched during the BL etching. is there. In the present embodiment, BLCT and BCT are left in order to leave the SNCT PLUG at the time of simultaneous etching of BLCT and SNCT.
The substrate is not etched even if L is misaligned. Therefore, there is no need to perform a layout in which the overlap amount is large between the BLCT and the BL, and the cell can be reduced (C in FIG. 13).

FIGS. 18 to 41 show a second embodiment in which the present invention is applied to a COB type dynamic RAM. Here, FIGS. 18 to 29 are sectional views taken along line XX of FIG.
41 to 41 correspond to the cross section taken along line YY of FIG.

The manufacturing process of the memory cell of the dynamic RAM according to the present embodiment will be described first with reference to FIGS.
As shown in FIG. 30, the silicon substrate 1
Then, each diffusion region and a word line WL are formed.

Then, after forming an interlayer insulating film 51 made of SiO ₂ on the word line WL, a mask 58 is attached,
Non-mask portions (openings) 58A and 58B for simultaneously patterning the bit line contact BLCT and the storage node contact SNCT are formed thereon.

Then, as shown in FIGS. 19 and 31, the bit line contact hole B is
LCT and storage node contact hole SNCT
Are formed by etching the interlayer insulating film 51, respectively. These contact holes may be etched simultaneously or separately.

Next, as shown in FIGS. 20 and 32, a bit line material BL 'is deposited by sputtering or the like.

Next, as shown in FIGS. 21 and 33, the BL material is etched by etch-back, and is selectively left as a BLCT plug in the BLCT and an SNCT plug in the SNCT.

Next, as shown in FIGS. 22 and 34, after slightly etching the insulating film 51, an SiO ₂ insulating film 60 is formed as shown in FIGS. 23 and 35. In this example, as shown in FIGS. 22 and 34, the SNCT plug and the BLCT plug are formed to protrude from the interlayer insulating film. However, such shapes are not necessarily required.

Next, as shown in FIGS. 24 and 36, a mask 59 is formed in a predetermined pattern in order to form a bit line, and is then etched using the mask. As shown in FIGS. The bit line BL having the SiO ₂ layer 60 is formed. At this time, the upper part of the SNCT plug slightly projects.

Next, as shown in FIG. 26 and FIG. 38, the side of the bit line BL is
Cover with 54. Further, as shown in FIG. 27 and FIG. 39, FIG. 28 and FIG. 40, an insulating film 64 is deposited on the entire surface, and a sidewall is formed by etch back. In addition, the oxide film by thermal oxidation
The reason for forming 54 is to remove polysilicon (bit line material) adhering to unnecessary portions, or to form an oxide film by thermal oxidation having a relatively high withstand voltage on the bit line (BL).
This is because it is provided on the side wall.

Next, as shown in FIGS. 29 and 41, polysilicon 22 as a storage node material is attached. Thereafter, a stacked capacitor is manufactured through patterning of the polysilicon layer, formation of a dielectric film by surface oxidation or the like, and formation of an upper electrode.

In this embodiment, since the BLCT and the SNCT are formed using a common mask in the same manner as in the first embodiment, the same operation and effect as those described above can be obtained. Also, since the SN material is slightly projected in the step of FIG. 25 to apply the SN material, it is possible to prevent the oxidation in FIG. 26 from being unnecessarily oxidized. Since the walls are overlapped, the insulating properties of the bit lines are sufficient.

FIGS. 42 to 59 show a third embodiment in which the present invention is applied to a COB type dynamic RAM. Here, FIGS. 42 to 50 are sectional views taken along line XX of FIG.
To FIG. 59 correspond to a cross section taken along line YY of FIG. However, the final shape of the storage node (SN) in this example is shown in FIG.
It will be apparent to those skilled in the art that this will be different from 17.

The process for fabricating the memory cell of the dynamic RAM according to the present embodiment will be described first with reference to FIGS.
As shown in 51, the silicon substrate 1
Then, a diffusion region and a word line WL are formed, and a nitride film 30 'is formed on the word line WL.

Then, the word line W covered with the nitride film
After forming an interlayer insulating film 51 made of SiO ₂ on L, a mask 58 made of photoresist is applied, and a non-mask portion (opening) for patterning the bit line contact BLCT and the storage node contact SNCT at the same time. Form 58A and 58B respectively.

Then, as shown in FIGS. 43 and 52, the bit line contact hole B is
LCT and storage node contact hole SNCT
Are formed by etching the interlayer insulating film 51, respectively. These contact holes may be etched simultaneously or separately.

Next, as shown in FIGS. 44 and 53, a bit line material BL ′ is deposited by sputtering or the like, and a SiO ₂ insulating layer 60 is further formed thereon.

Next, as shown in FIGS. 45 and 54, a mask 59 is formed in a predetermined pattern in order to form a bit line, and is etched using the mask. The bit line BL having the SiO ₂ layer 60 is formed. At this time, the conductive material of the SNCT plug is also etched.

Next, as shown in FIGS. 47 and 56, an insulating film 64 is deposited on the entire surface and then etched back to form a sidewall on the side surface of the bit line BL as shown in FIGS. 48 and 57. leave. At this time, the conductive material is exposed around the bit line BL, and the nitride film is exposed around the word line WL.

Next, as shown in FIGS. 49 and 58, a thin conductive material 70 such as polysilicon as a storage node material is grown on the entire surface, and further, as shown in FIGS. A conductive material such as polysilicon is removed by CMP (Chemical Mechanical Polishing).

Next, patterning of the polysilicon layer 70, formation of the dielectric film 100 by surface oxidation, etc., and the upper electrode 10
Through the formation of 1, a stacked capacitor is manufactured.

In this embodiment, since the BLCT and the SNCT are formed using a common mask in the same manner as in the first embodiment, the same operation and effect as those described above can be obtained. Since the storage node (storage electrode) is formed at a lower position, a step between the memory cell forming portion and a peripheral circuit portion such as a sense amplifier is reduced, and the depth of the contact to the substrate is reduced. This facilitates formation and formation of contact holes. Further, in the step of FIG.
By making the T plug protrude, the surface area of the storage node increases, and the capacitance of the capacitor increases.

FIG. 60 shows a fourth embodiment in which the present invention is applied to a trench type dynamic RAM.

In this example, a field plate 83, a dielectric film 84, and a storage node 86 are sequentially provided in a trench 80 formed in a P ⁻ type silicon substrate 1 with an insulating film 85 interposed therebetween.
Storage node 86 is connected to N ⁺ type source region 3 through polysilicon conductive layer 102. Note that 3 in the figure
1 ', 71, 72, and 73 are insulating films.

The conductive layer 102 and the bit line BL can be formed by the same process as that shown in FIGS. 1 to 16 in the first embodiment.

That is, the contact holes BLCT and SNCT are opened for the insulating layer 71 using a common mask, and after the bit line material is deposited on the entire surface, the bit line material is left in the SNCT together with the bit line patterning. Used as the conductive layer 102.

Thus, the number of steps can be reduced, and the BL and the conductive layer 102 can be formed by a process other than the self-alignment method.

Although the embodiments of the present invention have been described above, the above embodiments can be further modified based on the technical idea of the present invention.

For example, the order and combination of the steps described above may be changed in various ways, and the materials and patterns used may also be changed.

As shown in FIG. 61, the lower portion of bit line BL may be filled with another plug material PLUG, or PLUG and BL may be formed in separate steps (FIG. The material and BL are formed of the same material in the same step).

In the step of FIG. 3, the bit line may be patterned by first closing the SNCT with a conductive material other than the bit line material, and then applying the bit line material. As long as the contact holes for the bit lines and the storage nodes are formed by a common mask, the arrangement of the holes and the layout of the memory cells are not limited to the above-described example.

The materials of the word lines, bit lines, insulating films, dielectric films and the like are not limited to those described above. For example, polysilicon, W-Si (tungsten silicide), W, Al, Ti, SiO ₂ , Si
₃ N _4, other may be suitably selected conductor or insulator from conventionally known materials that will be apparent to those skilled in the art. Further, a structure in which a plurality of the conductors or the insulators are stacked may be employed. Also, it will be apparent to those skilled in the art that the method of formation can be variously selected, such as thermal oxidation, nitridation, silicidation, and deposition. Further, the mask members 58 and 59 may be, for example, a photoresist, a nitride film, or the like in addition to the above-described polysilicon.

The present invention is not limited to the dynamic RAM having the above-described stacked cell capacitor, and may be, for example, Si
The above-mentioned stack cell capacitor may be provided on the O ₂ film, the lower electrode of the capacitor may be extended to connect to the source region of the transfer gate, or the conductivity type of the above-described semiconductor region may be changed, or The present invention can be applied to other parts of the semiconductor memory and other devices.

[0092]

As described above, according to the present invention,
Not only can the cell be reduced, but also the tolerance around the bit line
The properties and characteristics can also be improved. Also, the number of manufacturing processes
Can also be reduced.

In addition, since there is no need to form a film structure in consideration of the etching rate around the bit line, it is advantageous in the parasitic capacitance and operation speed of the bit line. Also, the bit line and the storage node can be positioned at the same height, and the parasitic capacitance between adjacent bit lines is reduced.

[Brief description of the drawings]

FIG. 1 is an enlarged cross-sectional view (cross-section taken along line XX of FIG. 17; the same applies hereinafter) of a process step of a method for manufacturing a memory cell of a dynamic RAM according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 3 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 4 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 5 is an enlarged cross-sectional view of another process step of the memory cell manufacturing method.

FIG. 6 is an enlarged cross-sectional view of another process step of the memory cell manufacturing method.

FIG. 7 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 8 is an enlarged cross-sectional view of yet another process step of the method for manufacturing the memory cell.

9 is an enlarged cross-sectional view (a cross-section taken along line YY in FIG. 17; the same applies hereinafter) of one step of a method of manufacturing the memory cell;

FIG. 10 is an enlarged sectional view of another process step of the memory cell manufacturing method.

FIG. 11 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 12 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 13 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 14 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 15 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 16 is an enlarged cross-sectional view of yet another process step of the memory cell manufacturing method.

FIG. 17 is a plan view of the memory cell.

FIG. 18 shows a dynamic RAM according to another embodiment of the present invention.
FIG. 11 is an enlarged cross-sectional view of one step in a method for manufacturing the memory cell of FIG.

FIG. 19 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 20 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 21 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 22 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 23 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 24 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 25 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 26 is an enlarged cross-sectional view of another manufacturing step of the same memory cell.

FIG. 27 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 28 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 29 is an enlarged cross-sectional view of yet another process step of the memory cell manufacturing method.

FIG. 30 is an enlarged cross-sectional view of one step in a manufacturing method of the memory cell.

FIG. 31 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 32 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 33 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 34 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 35 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 36 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 37 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 38 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 39 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 40 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 41 is an enlarged cross-sectional view of yet another process step of the method for manufacturing the memory cell.

FIG. 42 shows a dynamic RAM according to another embodiment of the present invention.
FIG. 11 is an enlarged cross-sectional view of one step in a method for manufacturing the memory cell of FIG.

FIG. 43 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 44 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 45 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 46 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 47 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 48 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 49 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 50 is an enlarged cross-sectional view of yet another process step of the memory cell manufacturing method.

FIG. 51 is an enlarged cross-sectional view of one step in a method of manufacturing the memory cell.

FIG. 52 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 53 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 54 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 55 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 56 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 57 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 58 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 59 is an enlarged cross-sectional view of yet another process step of the manufacturing method of the memory cell.

FIG. 60 shows a dynamic RAM according to another embodiment of the present invention.
It is an expanded sectional view of the principal part of.

FIG. 61 shows a dynamic R according to still another embodiment of the present invention.
It is an expanded sectional view of the important section of AM.

FIG. 62 is an enlarged cross-sectional view of one step in a method of manufacturing a memory cell of a dynamic RAM according to a conventional example.

FIG. 63 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 64 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 65 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 66 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 67 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 68 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 69 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 70 is an enlarged cross-sectional view of yet another process step of the method for manufacturing the memory cell.

FIG. 71 is an enlarged cross-sectional view of one process step of a method for manufacturing a memory cell of a dynamic RAM according to another conventional example.

FIG. 72 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 73 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 74 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 75 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 76 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 77 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 78 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 79 is an enlarged cross-sectional view of yet another process step of the memory cell manufacturing method.

FIG. 80 is an enlarged cross-sectional view of one step in a method for manufacturing a memory cell of a dynamic RAM according to still another conventional example.

FIG. 81 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 82 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 83 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 84 is an enlarged cross-sectional view of another process step of the manufacturing method of the memory cell.

FIG. 85 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 86 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 87 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

FIG. 88 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 89 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell.

90 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell; FIG.

FIG. 91 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 92 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 93 is an enlarged cross-sectional view of another step of the manufacturing method of the memory cell;

FIG. 94 is an enlarged cross-sectional view of yet another process step of the memory cell manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 3 ... N ⁺ type drain region 4 ... N ⁺ type source region 22 ... Polysilicon layer (lower electrode) 40, 60 ... Insulating film 51 ... Interlayer insulating film 54, 64: Side wall 58, 59: Mask 58A, 58B: Opening WL: Word line BL: Bit line BL ': Bit line material TR: Transfer gate SN ..Storage node BLCT: bit line contact (hole) SNCT: storage node contact (hole) SNCT PLUG: storage node contact plug

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masayuki Moroi 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Inside Texas Instruments Co., Ltd. (72) Inventor Katsuji Park 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texas Instruments Inside (72) Inventor Yoshihiro Ogata 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture Inside Texas Instruments Co., Ltd. Inside (72) Yasuhiro Okumoto 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Inside Texas Instruments Inc. (56) References JP-A-3-64964 (JP, A) JP-A-4-287967 (JP, A) JP-A-6-268175 (JP, A) JP-A-8-1662619 (JP, A) ( 58) Surveyed fields (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 27/108

Claims (3)

(57) [Claims] 1. A transistor having a word line.
One diffusion region is for the bit line and the other diffusion region is for the bit line.
Half with memory cells respectively connected to the capacitor
In manufacturing a conductor device, a contact hole for connection to the bit line,
Form contact holes for connection to capacitors
And forming the bit line by patterning the bit line forming material
When forming the
Contact hole for connection to the hole and capacitor
With a conductive material, and then the bit
Apply the line forming material and apply this bit line forming material
Patterning to form a bit line; and connecting the side surface of the bit line and a capacitor to a capacitor.
Oxidize the top surface of the conductive material in the contact hole,
The insulating film formed later on the entire surface is etched back to
Work to form thicker sidewalls on the sides of the train
And a method of manufacturing a semiconductor device. 2. A semiconductor device comprising a field insulating film on a main surface of a semiconductor substrate.
A gate insulating film is interposed on the partitioned first conductive type semiconductor layer.
Forming first and second word lines, and forming the first word line and the field of the semiconductor layer.
Between the first word line and the second word line.
Between the first word line and the second word line.
A first conductivity type, a second conductivity type,
Forming a first insulating film on the semiconductor substrate and forming the first insulating film on the semiconductor substrate.
Field insulating film, the first and second word lines, and
A step of covering the first, second, and third semiconductor regions, and selectively removing the first insulating film;
A first storage node contact reaching the area,
Bit line contact reaching the second semiconductor region,
And a second storage node reaching the third semiconductor region.
Forming a first conductive material on the semiconductor substrate and forming the first conductive material on the semiconductor substrate.
And the first storage node capacitor.
Tact, the bit line contact and the second switch.
Filling the storage node contact with the above conductive material
And selectively removing the first conductive material and removing the first insulating material.
A bit line is formed on the film and the first and second
First and second storage
Forming a second insulating film on the semiconductor substrate , and forming a second insulating film on the semiconductor substrate.
Line, the first insulating film, and the first and second insulating films.
Covering the storage node plug; etching back the second insulating film to form the bit line
Forming side walls on the side surfaces of
Exposing a second storage node plug ; forming a second conductive material on the semiconductor substrate; and selectively removing the first and second conductive materials by removing the second conductive material.
The first connected to each of the two storage node plugs
And a method of manufacturing a semiconductor device having a step of forming a second scan Trade node. 3. The method according to claim 1, wherein said first conductive material is formed after said first conductive material is formed.
Forming a third insulating film on the first conductive material;
The third insulating film and the first conductive material have the same pattern.
Pattern on the bit line and
3. The method according to claim 2, wherein a third insulating film is formed .