JP3355573B2 - Asynchronous transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal transmission in an asynchronous transfer mode (hereinafter referred to as "ATM"). In particular, the synchronous transfer mode (Sync
hronous Transfer Mode (hereinafter referred to as “STM”), a circuit that converts a signal into an ATM signal, and a circuit that performs the reverse conversion, ie, a cell / decell circuit (CLA)
D).

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional asynchronous transmission apparatus having a cell / decell circuit. Here, an example in which a plurality of input terminals are provided, the STM signal input from each terminal has a multi-channel structure of one channel, and the multi-frame phase of each terminal matches will be described. The asynchronous transmission device includes a cell conversion circuit 21 and a cell overhead provision circuit 22 as cellization circuits, and a cell synchronization circuit 2 through an ATM network 23.
4 and a cell inversion circuit 25. The output of the cell inverse conversion circuit 25 is output via the multi-frame phase synchronization circuit 26. Cell conversion circuit 2
1, cell overhead providing circuit 22, cell synchronization circuit 2
4. The cell inverse conversion circuit 25 and the multi-frame phase synchronization circuit 26 are provided for each channel, and a common timing generation circuit 27 is connected to the multi-frame phase synchronization circuit 26 for each channel.

[0003] A cell conversion circuit 21 decomposes a main information portion called a payload, which is obtained by removing frame synchronization information and other control information from an input STM signal (hereinafter referred to as an "input STM signal"), into 48 bytes. The cell overhead giving circuit 22 gives a header of 5 bytes to each of the 48 bytes (this is called “cell overhead”), and 53
It is a byte cell. The 53-byte signal block is called a "cell" and is transmitted to the ATM network 23. FIG. 7 shows an example of cell conversion by the cell conversion circuit 21 and the cell overhead provision circuit 22. At the time of cell conversion, input terminal #
1 to #n, the multi-frame (M
F1 to MF4) No phase is considered at all. In the figure, a specific multi-frame phase point is represented by a black triangle so that the multi-frame phase is clear.

The cell synchronization circuit 24 establishes cell synchronization, recognizes a 53-byte cell, decodes the overhead of each cell, and verifies whether the destination described therein is addressed to itself. If it is addressed to itself, the cell inverse conversion circuit 2
5 deletes the 5-byte cell overhead and adds frame information and outputs the same STM signal as the input signal. Cell synchronization circuit 24 and cell inverse conversion circuit 2
FIG. 8 shows an example of decellularization according to No. 5. At this point, no multi-frame phase of the cell is considered.

The output of the cell reverse conversion circuit 25 is input to a multi-frame synchronization circuit 26, and outputs an STM signal in accordance with a timing signal from a common timing generation circuit 27. That is, the multi-frame synchronization circuit 26 detects the multi-frame phases of all the channels, and the multi-frame phase synchronization is established. FIG. 9 shows an example of the operation of establishing multi-frame phase synchronization.

[0006] By converting the STM signal into an ATM signal and transmitting it in this manner, the ATM signal is unified regardless of the transmission parameters of the input signal such as the transmission speed and the frame synchronization method.
Transmission within the TM network becomes possible.

[0007]

Generally, in an ATM network, cell fluctuation and cell drop occur.
It is necessary to take measures for these phenomena on the receiving side of the ATM network. If the input STM signal is composed of multiple channels with the same multi-frame phase, the multi-channel phase of the multiple channels must be matched against the cell fluctuation in addition to the buffer normally required on the receiving side of the network. Therefore, a multi-frame phase synchronization circuit is required to perform the synchronization. In addition, in order to prevent the multi-frame phase synchronization from being lost in the STM signal after the cell reverse conversion (hereinafter referred to as “output STM signal”), the cell conversion circuit and the cell reverse conversion circuit are provided with a cell counter. (For example, ATM adaptation layer, type 1: AAL type 1) is newly required.

As described above, since a multi-frame phase synchronization circuit is required for cell fluctuation, the circuit scale and the processing time have been increased. In addition, since a function for managing a cell sequence is newly required for a cell conversion circuit and a cell reverse conversion circuit when a cell is dropped, the circuit scale is increased, the transmission efficiency is reduced, and the processing time is increased. I was

[0009] The present invention solves the above problems, and when an input signal is composed of a plurality of channels having the same multi-frame phase, asynchronous transfer with improved circuit scale, transmission efficiency, and processing time is achieved. It is intended to provide a device.

[0010]

The most important object of the present invention is to convert an input signal into cells by using a multi-frame phase and accommodate one or more multi-frame period signals in one cell. Features. That is, the asynchronous transmission device of the present invention comprises: cell conversion means for converting a signal in the synchronous transfer mode into a cell signal in the asynchronous transfer mode and outputting the signal to the asynchronous transfer mode network; and a cell input from the asynchronous transfer mode network. An asynchronous transmission device comprising: a decelerating unit for converting the converted signal into a signal in a synchronous transfer mode;
The input synchronous transfer mode signal is a plurality of series of signals having the same multi-frame structure and having the same multi-frame phase, and the cellifying means includes means for detecting the multi-frame phase of the plurality of signals, Means for accommodating one or a plurality of pieces of multi-frame information in one cell based on the obtained multi-frame phase, wherein the decellularizing means includes means for detecting a cell phase of a cell signal, Means for inversely converting to a synchronous transfer mode signal having a required multi-frame phase timing based on the obtained cell phase.

[0011] A plurality of signals in the synchronous transfer mode are input from separate input terminals, respectively, and the accommodating means includes means for individually converting the signals input from the separate input terminals into cells, respectively. Means for generating a plurality of series of signals having the same multi-frame phase from separately cellized signals may be included. Also, a plurality of signals may be a signal obtained by time-division multiplexing a plurality of channels having the same multi-frame structure, and the accommodating means may include means for cellizing the time-division multiplexed signal without separation. it can. Further, by combining these, a plurality of series of signals are input from a plurality of input terminals, and a plurality of channels each having the same multi-frame structure are time-division multiplexed signals, and the accommodating means is input from a plurality of input terminals. The means for individually transforming the signals into cells may be included, and the means for performing the inverse transform may include means for generating a plurality of series of signals having the same multi-frame phase from the signals separately formed as cells.

In the present invention, by utilizing the multi-frame phase of the input STM signal, m frames of n channels of the input STM signal (n and m are each an integer of 1 or more) in one cell.
Accommodates information. Therefore, when the cell synchronization is established, the multi-frame phase of the channel is obtained at the same time, and the multi-frame phase synchronization of all the channels can be established without using the multi-frame phase synchronization circuit. Further, when a cell drop occurs, information for m multi-frames may be lost. Therefore, even if there is no function to manage the sequence of cells, multi-frame synchronization is not lost in the output STM signal. Therefore, it is possible to solve the problems of an increase in circuit scale, a decrease in transmission efficiency, and an increase in processing time.

[0013]

FIG. 1 is a block diagram showing an asynchronous transmission apparatus according to an embodiment of the present invention. This device uses STM
The signal is converted into an ATM signal which is converted into a cell, and the ATM network 13
A cell synchronizing circuit 14, a cell inverse converting circuit 15 and a cell converting means 11 for converting an ATM signal input from an ATM network 13 into an STM signal. A timing generator 17 is provided. The input STM signals input to the cell conversion circuit 11 are a plurality of series of signals having the same multi-frame structure and having the same multi-frame phase, and corresponding to each cell conversion circuit 11, the cell overhead adding circuit 12, the cell synchronization A plurality of circuits 14 and a plurality of cell inverse conversion circuits 15 are provided, and a multi-frame phase detection circuit 16 is provided as means for detecting a multi-frame phase of a plurality of series of signals. The cell conversion circuit 11 stores one or a plurality of pieces of multi-frame information in one cell based on the detected multi-frame phase,
The cell synchronization circuit 14 detects the cell phase of the ATM signal, and the cell inverse conversion circuit 15 inversely converts the cell phase into a synchronous transfer mode signal having a required multi-frame phase timing based on the detected cell phase.

FIG. 2 shows a cell conversion circuit 11, a cell overhead provision circuit 12, and a multi-frame phase detection circuit 16.
FIG. 7 is a diagram for explaining a cell operation by the STA. The multi-frame phase detection circuit 16 detects the multi-frame phase of all STM signals input to the input terminals # 1 to #n. Cell conversion circuit 11, participated the detected multiframe phase
By dividing the STM signal by comparing
The signal is decomposed into 48 bytes each corresponding to the information of one cycle of the multiframe , and the cell overhead adding circuit 12 adds the cell overhead (“O” in the figure) to the 48 bytes of information.
H ”) and sends it out to the ATM network 13.

FIG. 3 is a diagram for explaining a decelling operation by the cell synchronizing circuit 14, the cell inverting circuit 15, and the timing generating circuit 17. The cell synchronization circuit 14 recognizes the cell, and the cell inversion circuit 15 removes the 5-byte overhead of the cell. The aforementioned cell conversion circuit 11 detects
STM signal with reference to the obtained multi-frame phase
The top of the cell with overhead removed
It will always have the same multi-frame phase. did
Therefore, it is possible to detect the multi-frame phases of all the channels at the output point of the cell inverse conversion circuit 15 .
As in the conventional example described in the section of “Prior Art”, the cell reverse
The output of the conversion circuit 15 is supplied to a common timing generation circuit 17.
Output as an STM signal according to the timing signal from
It is. As a result, multi-frame phase synchronization can be established. In the conventional example shown in FIG.
25 outputs are synchronized every multiframe
Although (see the upper side of each series in FIG. 9), the multiframe phase
Is not taken into account for certain multi-frames
The phase points (points indicated by black triangles in FIG. 9) are different for each series.
In order to synchronize this, the cell inverse conversion circuit 2
5, a multi-frame phase synchronization circuit 26 is required.
Was. On the other hand, in this embodiment, overhead is taken.
The head signal of the removed cell is used as the cell timing generation circuit 17.
Just synchronize with the timing signal from
Because it corresponds to a specific multi-frame phase point,
In the output of the cell inverse conversion circuit 25 for each stream,
Frame phase synchronization is established. Even if a cell is dropped, information for exactly one multi-frame is lost. Therefore, even if there is no function for managing a cell sequence, multi-frame synchronization is not lost in an output STM signal.

In the above description, the case where an STM signal having a frame structure of one channel is input from each input terminal has been described. However, a plurality of channels having the same multi-frame structure are time-division multiplexed to each input terminal. The present invention can be implemented in the same manner even when input is made by the user. FIG. 4 shows an example of cell formation in such a case. Here, input terminal #
This will be described using i as an example. In this example, four multi-frames each composed of three frames are time-division multiplexed. These multi-frames have a time slot shift, but the multi-frame phases match from the viewpoint of multiplexing unit. Even in such a case, the cell conversion circuit 11 and the cell overhead provision circuit 12
This time-division multiplexed signal is formed into cells without separation. In the cell synchronization circuit 14 and the cell reverse conversion circuit 15,
A plurality of series of STM signals having the same multiframe phase are generated from the ATM signals separately formed for each input terminal. Similarly, when there is one input terminal, a plurality of channels having the same multi-frame structure are time-division multiplexed.
The TM signal can be converted to an ATM signal and transmitted.

FIG. 5 is a diagram showing the flow of the entire operation.
The transmitting side detects the multi-frame phase of the STM signal input from the input terminal, and uses the multi-frame phase information to generate n multi-frames of n channels (n and m are 1 or more) in the same cell. The cell is converted into a cell accommodating the information, and the cell overhead is added to the cell for output to the ATM network. On the receiving side, the cell phase of the input ATM signal is detected,
Using the cell phase information, the signal is inversely converted into an STM signal having a required multi-frame phase timing.

If the information for m multi-frames of n channels is less than 48 bytes, an appropriate byte is inserted so as to be 48 bytes and input to the cell conversion circuit 11. The deleted byte may be deleted.

With such a configuration, on the receiving side,
The multi-frame phase synchronization of the channel can be established without using the multi-frame phase synchronization circuit. Further, it is possible to prevent occurrence of loss of multiframe synchronization without using a function of managing a sequence of cells. Therefore, it is possible to reduce the circuit scale, improve the transmission efficiency, and shorten the processing time as compared with the conventional technology.

[0020]

As described above, the asynchronous transmission apparatus of the present invention utilizes the multi-frame phase of an input signal to
One cell accommodates information of m multi-frames of n channels (n and m are both 1 or more). Therefore, at the receiving side, it is possible to establish a multi-frame phase synchronization of all channels simultaneously when the cell synchronization is established, the multi-frame phase synchronization circuit that Do not required. Also,
Even when a cell drop occurs, it is possible to prevent the occurrence of loss of multiframe synchronization in an output STM signal without using a function for managing a cell sequence. Therefore, there is an effect that the circuit scale can be reduced, the transmission efficiency can be improved, and the processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an asynchronous transmission device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a cell operation.

FIG. 3 is a diagram illustrating a decelerating operation.

FIG. 4 is a diagram showing an example of cell formation when a plurality of channels having the same multiframe structure are input to individual input terminals in a time-division multiplexed manner.

FIG. 5 is a diagram showing a flow of an entire operation.

FIG. 6 is a block diagram showing a conventional asynchronous transmission apparatus.

FIG. 7 is a diagram illustrating a conventional example of cell formation.

FIG. 8 is a diagram illustrating deceleration in a conventional example.

FIG. 9 is a diagram illustrating an operation of establishing multi-frame phase synchronization in a conventional example.

[Explanation of symbols]

 11, 21 Cell conversion circuit 12, 22 Cell overhead assignment circuit 13, 23 ATM network 14, 24 Cell synchronization circuit 15, 25 Cell reverse conversion circuit 16 Multi-frame phase detection circuit 17, 27 Timing generation circuit 26 Multi-frame phase synchronization circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-56225 (JP, A) JP-A-8-56226 (JP, A) JP-A-7-99497 (JP, A) JP-A-6-99497 152560 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/56 H04J 3/00

Claims (4)

(57) [Claims] 1. A cell forming means for converting a signal in a synchronous transfer mode into a cell signal in an asynchronous transfer mode and outputting the signal to an asynchronous transfer mode network, and a cell signal inputted from the asynchronous transfer mode network And a decelerating means for converting the synchronous transfer mode signal into a synchronous transfer mode signal, wherein the synchronous transfer mode signal is a signal of a plurality of sequences having the same multiframe structure and having the same multiframe phase, The converting means includes means for detecting a multi-frame phase of the signals of the plurality of sequences, and means for accommodating one or a plurality of pieces of multi-frame information in one cell based on the detected multi-frame phase, The decelerating means includes means for detecting a cell phase of a cellized signal, and a required multi-frame based on the detected cell phase. Asynchronous transmission apparatus characterized by including means for inverse converting the signal of the synchronous transfer mode having a beam phase timing. 2. The signal of the plurality of streams is a signal input from a separate input terminal, and the accommodating unit includes a unit configured to separately cellify the signal input from the separate input terminal. 2. The asynchronous transmission apparatus according to claim 1, wherein said means for performing inverse conversion includes means for generating a plurality of series of signals having the same multi-frame phase from signals separately formed into cells. 3. The signal of the plurality of streams is a signal obtained by time-division multiplexing a plurality of channels having the same multi-frame structure, and the accommodating unit converts the time-division multiplexed signal into cells without separating the signals. 2. The asynchronous transmission device according to claim 1, comprising means. 4. The signal of a plurality of streams is a signal that is input from a plurality of input terminals and is a signal obtained by time-division multiplexing a plurality of channels each having the same multi-frame structure. 2. The apparatus according to claim 1, further comprising: means for individually converting the input signals into cells, and wherein the means for performing the inverse conversion includes means for generating a plurality of series of signals having the same multiframe phase from the separately cellized signals.
An asynchronous transmission device as described.