JP3212656B2 - Data processing system and microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management system for an operating system or an operating system program (hereinafter, also referred to as an OS), and more particularly to a central processing unit which controls execution of a plurality of tasks (user programs) under the management of the OS. The present invention relates to a stack control method for allocating a work stack area to each task and a single-chip microcomputer that can adopt the control method in a multitask processing system.

[0002]

2. Description of the Related Art In multitask processing, system processing is divided into units, or tasks, which can be processed independently and in parallel, and the execution is controlled while being managed by an operating system (OS). Such a multitask control OS controls the execution of the task by allocating a microprocessor or other resources to the task in response to a system call (task execution request) from the task according to the priority or the like. At this time, the OS allocates a stack area to the task. This stack area is used for transferring parameters to the subroutine, holding a return address from the subroutine, and saving and restoring register information when execution of a task is interrupted. If the stack area assigned to each task is an area unique to each task, the memory usage increases in proportion to the number of tasks registered or the number of tasks that can be registered. In particular, in a data processing system that does not support virtual storage, the memory capacity used for the stack area is significantly increased.
Japanese Patent Laid-Open No. 63-86035 discloses a technique for reducing the amount of memory used for the stack area. Japanese Patent Application Laid-Open No. 63-86035 discloses a method in which a stack area is collectively pooled, and a stack area is dynamically cut out from the pool as needed and allocated to tasks.

[0003]

However, in a method in which a stack area is dynamically cut out from a pool area in response to a task execution request and assigned to a task, the processing of the OS becomes complicated due to the dynamic control. I understood. Further, even if the stack area is dynamically cut out and controlled, it is necessary to determine the storage capacity of the pool area so that the stack area does not become insufficient. That is, the capacity of the pool area is determined after previously calculating the number of tasks to be executed simultaneously. Therefore, the memory utilization efficiency for the stack area may be reduced.

Particularly, in a system having no virtual storage, there is a physical limitation on the memory capacity that can be allocated to a task, so that it is necessary to reduce the size (storage capacity) of the stack area as small as possible. Particularly, a relatively small-scale data processing system, for example, a central processing unit and peripheral input / output (I / O) functions, a random access memory (RAM), a read-only memory (ROM), etc. are mounted on one chip. In the case of a data processing system in which the control unit is configured by a single-chip microcomputer, a plurality of tasks must be executed using an internal RAM having a limited storage capacity, and the size of the stack area is increased. The present inventor has found that it is necessary to further reduce. In addition, a method of dynamically cutting out a stack area for each task execution request in a physically limited memory area or allocating a stack area specific to each task is executable or registered. This naturally limits the number of tasks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a stack control method in a multitask processing system in which a process for allocating a stack area to a task is simple and the efficiency of using a memory for the stack area can be improved. It is in.

Another object of the present invention is to provide a multi-task processing system capable of relatively increasing the number of executable or registerable tasks in a data processing system having a limited memory area that can be allocated as a stack area. It is to provide a stack control method.

A further object of the present invention is to provide a one-chip microcomputer which can employ such a stack control method.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

The operating system according to the present invention has a stack management function for allocating one stack area to a plurality of tasks having the same priority. Therefore, one stack area is shared by a plurality of tasks having the same priority. However, a plurality of tasks that commonly use one stack area are tasks that are not executed at the same time, and tasks whose execution order can be determined in advance. That is, when tasks A, B and C share one stack area,
The execution order of the tasks A, B and C is preferably such that the task B is executed after the execution of the task A, and the task C is executed after the execution of the task B.
In other words, the shared stack area is exclusively allocated to one task (A, B or C) that is executing.

The OS according to the present invention can allocate one stack area to one task for exclusive use. For example, when the OS manages 10 tasks, the OS assigns a dedicated stack area to each of the two tasks, assigns a shared stack area to four tasks having the same priority, and assigns a shared stack area to the other tasks. One shared stack area is allocated to four tasks having the same priority. As a result, the total number of stack areas can be four even though there are ten tasks.

[0012]

Therefore, according to the present invention, even when the total number of tasks is n (n is a positive integer), the total number of stack areas can be set to m <n (m is a positive integer). The ratio of the total stack area to the total memory capacity of the random access memory to which the stack area is to be allocated can be reduced.

As a result, a built-in random access memory (RA) like a single-chip microcomputer
Even if the storage capacity of M) is limited, the storage capacity used as the stack area can be only a small amount of the total storage capacity of the RAM, so that a multi-task operating system program (OS ) Can be mounted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an operating system according to the present invention will be described.

As shown in FIG. 5, an operating system (OS) for multitask control manages a plurality of tasks P1 to Pi in parallel and controls their execution.

FIG. 6 shows an example of a task state transition diagram that can be taken by the OS when the OS manages the task.
The transition states shown in the figure are a sleep state, an executable state,
An execution state and a waiting state.

The dormant state is a state in which the task has not been started yet, that is, a state in which the execution of the task has not been requested, or a state in which the execution of the task has been completed. The executable state is a state in which a task is executable, but a state in which a processor is not allocated and waits because another high-priority task or the like is being executed. The execution state is a state in which a processor is allocated to a task and is currently being executed. The waiting state is a state in which the task is waiting for the acquisition of a resource other than the processor or the occurrence of some event.

The OS according to the present invention includes a memory management function that allows a plurality of tasks to share the same stack area. For example, as shown in FIG. 4, the OS of the present invention allocates a stack area so that a task group whose priority is the same level and whose execution order is mutually predetermined is shared by the same stack area. Control.
In FIG. 4, the stack areas B of the tasks P2, P3 and P4,
Stack area C of tasks P5, P6, and P7, task P
The stack areas D of 8, P9, and P10 are each a shared stack area.

The tasks P1 and P11 are assigned stack areas A and E, respectively, as dedicated stack areas. Then, the OS of the present invention exclusively controls the assignment of the task to the shared stack area for each shared stack area in units from the start to the end of the execution of the task.

FIG. 1 shows an example of a program flowchart of the exclusive control included in the OS of the present invention. That is, when task execution is requested,
It is determined whether another task sharing the stack area is being executed (in other words, whether another task is using the shared stack area) (S11). As a result, if it is determined that another task is not being executed, the OS enables the task to be executed (S12). On the other hand, if it is determined that another task is being executed, the OS delays the start of execution of the task, that is, the transition to the executable state (S1).
3).

FIG. 3 shows an example of the processing for delaying the start of execution of a task. For example, when the task P2 is in the execution state using the stack area B as shown in FIG. 4, the other tasks P3 and P4 sharing the same stack area
Is required, the tasks P3 and P4 are connected to a stack matrix management pointer (Bp described later) unique to the shared stack area B to form a queue. This queue, for example,
It consists of a first-in first-out (FIFO) queuing table.

In order to easily recognize the stack area to which the task requested to be executed is to be allocated, stack instruction information or stack instruction data (SPD to be described later) for each task indicating the stack area to which the task is to be allocated. Is provided. In order to determine whether or not another task is being executed, a stack management variable (Bd) for indicating whether or not the currently allocated task exists in the shared stack area has a shared stack. Provided for region B. Therefore, when a task is requested to be executed, the OS accesses the stack instruction information of the task in order to recognize the stack area to which the task is allocated. As a result, when the stack instruction information indicates, for example, the shared stack area, the stack management variable provided for the shared stack area is accessed. As a result, if it is determined that there is a task currently allocated to the stack area, the task whose execution is requested is put in a queue.
This will be described in detail with reference to FIGS.

As a part of the exclusive allocation control of tasks to the shared stack area, when considering the handling of a task whose execution has been delayed, for example, as shown in FIG. Upon completion, it is determined whether or not there is another task sharing the stack area and whose execution is delayed (S2).
1). As a result of this determination, when there is another task whose execution start is delayed, one task selected from one or more tasks whose execution start is delayed is set to the executable state. (S22).

In order to easily determine whether or not there is another task whose execution has been delayed, the value of the pointer is checked by referring to the value of the stack matrix management pointer Bp shown in FIG. It is determined whether or not it points to the task.

The OS controls which of the plurality of tasks whose execution start is delayed is selected from tasks having higher priority or longer waiting time in tasks included in the queue, or The task can be selected from those having a short execution time, or can be selected as appropriate according to the requirements of the system. In order to relatively simplify the processing for enabling one selected task to be executable, a ready task matrix management pointer for connecting executable tasks is provided, and the task is connected to this.

The above-described stack control method is effective as an operating system for a one-chip microcomputer. In this case, when a plurality of tasks to be multitasked share a stack area, a shared stack control area for exclusively allocating the stack area to the task in units of execution from the start to the end of the task. That is, a stack matrix management pointer Bp, stack instruction information SPD, and a stack management variable Bd are provided, and an operating system may be provided with a function of managing them, and the operating system may be mounted.

By configuring the operating system in this way, the following effects can be obtained. Multiple tasks share the same stack area, and the assignment of tasks to the shared stack area is controlled exclusively in a queue manner from the start to the end of task execution as a unit. A processing program for allocating a stack area to a task can be simplified as compared with a dynamic allocation control or a control using virtual memory. At the same time, since the shared stack area is set, the memory capacity for the stack area in the multitask processing system can be reduced, and the memory use efficiency can be improved because the shared stack area is used by a plurality of tasks. . This memory utilization efficiency improves as the degree of sharing with the stack area increases.

The improvement of the memory use efficiency for the stack area in the multitask processing system is achieved by limiting the number of tasks that can be executed or registered even in a data processing system in which the memory area that can be allocated as the stack area is limited. Work not to.

Furthermore, even if the memory area that can be allocated as a stack area is limited as in a one-chip microcomputer (single-chip microcomputer), various user programs or application programs that constitute tasks to be managed are provided. Enables flexible OS support.

An embodiment in which the present invention is applied to a data processing system using a one-chip microcomputer (single-chip microcomputer) will be described below.

The microcomputer 10 shown in FIG.
Although not particularly limited, a central processing unit (CPU) 11 that executes an operation program such as an operating system program (OS) or a task (a user program or an application program), and a ROM (read) that holds an operation program such as the OS or the task. A memory (only memory) 12, a RAM (random access memory) 13 used as a work area of the central processing unit 11 and a temporary storage area of data, for example, a stack area, an input / output (I / O) interface 14, It includes a timer 15, which is coupled by an address bus 16, a data bus 17, and a control bus 18. The microcomputer 10 is formed on one semiconductor substrate 1 such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The timer 15 receives pulse signals S1 to S3 generated by externally provided motors M1 to M3 via terminals T1 to T3, and counts the number of pulse signals. The I / O interface 14 includes a keyboard 5
1 is supplied to the internal data bus 17 via the terminals T4 to T10, and the data on the internal data bus 17 is supplied to the display device (display) via the terminals T14 to Tn.
52.

The operation of the data processing system of FIG. 7 will be described later in detail.

The OS includes functions such as task management, task-attached synchronization management, synchronization / communication management, time management, and interrupt management. The outline is as follows. (1) The task management (including the scheduler) is performed by the CPU (Central).
(Processing Unit) 11 manages the state of the tasks, such as the order in which the tasks are allocated to the tasks, and the activation and termination of the tasks. At this time, the tasks are allocated to the CPU in descending order of priority. (3) Synchronization and communication management has three functions of event flags, semaphores, and mailboxes, and performs synchronization and communication between tasks. (4) Time management manages time and monitors time for task execution control. (5) Interrupt management activates an interrupt handler when an interrupt occurs, and performs interrupt processing and interrupts to the task. Report the occurrence.

The present invention relates to the task management stack area allocating function of the OS.
Although the management content shown in (5) is not described in detail, it will be easily understood by those skilled in the art.

The central processing unit 11 executes and controls various tasks in accordance with a predetermined procedure using the OS stored in the ROM 12 as a core. When executing a task to be executed, the CPU 11 transmits an operation program constituting the task to the RO.
The address bus 16 is used to read and decode data from the M12.
Sends an address signal corresponding to the head address of the task. The ROM 12 corresponds to the address signal,
The program data is sent to the data bus 17. CPU
Reference numeral 11 reads and decodes the program data, and controls various arithmetic operations and peripheral circuits according to the result of the decoding. Therefore, the CPU 11 has an operation mode (supervisor mode) for executing the OS and an operation mode (user mode) for executing the task (user program). C running the above OS
It is assumed that the PU 11 is performing various task controls described below. FIG. 7 shows various registers held by the central processing unit 11, for example, 16 registers.
Control registers such as a program counter PC of 8 bits and a condition code register CCR of 8 bits, a general-purpose register group Rn used as a data register and an address register, and a top address of a stack area allocated to a task currently being executed ( A 16-bit stack pointer STKP indicating the start address) is representatively shown.

The general-purpose register group Rn includes, for example, seven registers R0 to R6 each having 16 bits. Of the seven registers R0 to R6, for example, four registers R0 to R3 store context (program) of each task.
Defined as a work register within The reason for this is to reduce the capacity of the storage area prepared as a stack area. However, all the general registers R0 to R
6 may be defined as a work register in the program. The number of the general-purpose registers Rn to be stacked can be specified when the system is constructed.

FIG. 8 shows an address map of the microcomputer 10 in the single chip mode. R
OM12 is 16 kbytes and has a hexadecimal address (H '
H'0000 to H'3FF
Close F. ROM address H'0000 to H'003
D includes interrupt vector tables, which are not described in detail because they are not directly related to the present invention. H'0
03E to H'3FFF are RAMs as shown in FIG.
13, an area 99 for storing a data table for initial setting as shown in FIG. 10 to be described later, an area 100 for storing an OS program, and tasks P1 to P11.
And an area 112 where a stack instruction data (SPD) table is stored. The SPD table includes the tasks P1 to P1.
Stack instruction data SPD provided corresponding to P11
1 to SPD11. Each of these stack instruction data S
PD1 to SPD11 store information for indicating a stack area used by each task. For example, each of the stack instruction data SPD1 to SPD11 is the bottom address of the corresponding stack area, that is, the highest address (end address) of each stack area allocated on the address map. Here, on the address map of FIG. 8, the upper side of the address indicates the larger address direction (H'FFFF direction), and the lower side of the address indicates the smaller address direction (H'0000 direction). Is considered. Further, when data in the stack area is stacked, the value of the stack pointer STKP is:
It is assumed that the value is updated to a value obtained by subtracting the number of bytes of data to be stacked from the bottom address (the highest address on the address map of the stack area).

As shown in FIG. 4, when setting each stack area for each task, each stack instruction data SPD1 to SPD
The following data is set in 11 respectively. SPD1 Bottom address of stack area A SPD2-4 Bottom address of stack area B SPD5-7 Bottom address of stack area C SPD8-10 Bottom address of stack area D SPD11 Bottom address of stack area E

Therefore, the CPU 11 outputs the address of the desired stack instruction data storage area in the stack instruction data table 112 to the address bus 16 and sends a control signal indicating a read state to the control bus 1.
8 to access the desired stack instruction data storage area. Then, the CPU 11 reads the address data output from the ROM 13 to the data bus 17 in response thereto to identify which stack the task is assigned to.

The RAM 13 stores, as shown in FIG.
When represented by a hexadecimal address, H'F
D80 to H'FF7F. Allocated to RAM addresses H'FD80 to H'FF7F. RAM
Addresses H'FD80 to H'FF7F are, as shown in FIG. 10, an OS stack area 201 of 16 bytes and areas 202 to 21 for storing task management tables TCB1 to TCB11 of 12 bytes each.
3. Stack areas A to E each having 20 bytes, areas 214 to 218 each storing stack management variables Ad to Ed each having 1 byte, and stack matrix management pointers Ap to Ep each having 2 bytes. Areas 219 to 223, an area 24 for storing the execution queue management pointer Xp, and a 247-byte work area 224 for the CPU 11 are included.

The area 214 of the stack management variables Ad to Ed and the stack matrix management pointers Ap to Ep
To 223 are shared stack control areas.

Each of the stack management variable areas 214 to 218 includes information indicating whether a corresponding stack area is used or information for specifying a task using the corresponding stack area (A to E), for example, The CPU 11 describes the task number information.

Stack matrix management pointers Ap to Ep
Is a pointer for connecting a task waiting for an empty space of the corresponding shared stack area to a queue.

As is clear from FIG. 10, the stack area (A) and the corresponding shared stack control area 214,
219 is mapped to consecutive addresses. Therefore, for example, when the execution request of the task P2 is made from another task or the keyboard 51, the CPU 11 informs the internal address bus 16 of the stack instruction data that the stack area used for the execution of the task P2 is B. S
An address indicating PD2 is output and can be recognized from the contents of stack instruction data SPD2 output to internal data bus 17. Whether the shared stack area B is used by another task is determined by the stack instruction data SPD.
The next higher address of the address pointed to by the contents of 2 is C
When the PU 11 refers (accesses), it can be recognized from the holding information Bp of the stack management variable area 215 assigned to the PU 11. Further, when the task is connected to the stack queue when another task is using the stack area B, or when the task connected to the stack queue is recognized, the CPU 11 further proceeds to the next step. The matrix may be traced by referring to the value of the stack matrix management pointer Bp of the address. Therefore, those procedures become extremely simple. Stack management variable A for stack areas A and E dedicated to one task
d and Ed and the stack matrix management pointers Ap and Ep are used to recognize that the stack area is occupied by one task in the same procedure as described above.
Therefore, if a special flag or the like indicating that the area is a dedicated stack area is provided and a procedure (program) that the CPU 11 refers to is used, the stack management variable areas 214 and 218 are used for the dedicated stack areas A and E.
And the stack matrix management pointer areas 219 and 223
It is not necessary to assign to M. By doing so, the memory capacity of the RAM 13 can be used effectively.

As shown in the address map of FIG.
When the internal register of 12 bytes is represented by a hexadecimal address, it is allocated to H'FF90 to H'FFFF. These registers correspond to registers in the I / O interface 14 and registers in the timer 15 which is a built-in peripheral circuit. These registers are not directly related to the present invention and will not be described in detail, but will be readily understood by those skilled in the art.

FIG. 11 shows an example of the task management table TCB. The task management table TCB includes a start address designation area 20 for the corresponding task, a group of various pointers 21 for connecting the task to the queue, an area 22 in which the state of the task as shown in FIG. 6 is described, and a priority of the task. And the like in which an area 23 is described. For example, the head of the queue connecting the tasks in the executable state is described in the execution queue management pointer 24 by the CPU 11. The description content is the address of the pointer 21A of the task management table in the corresponding task. Using the pointers in the respective task management tables, the CPU 11 can connect the tasks one after another. Similarly, the description of the stack queue management pointer by the CPU 11 is the address of the pointer 21B of the task management table in the corresponding task. Since one task is not actually connected to both the stack queue and the execution queue, the same area is used for the pointers 21A and 21B.

FIG. 12 functionally shows the relationship among the task, the stack area, and the stack control area. FIG. 2 representatively shows a shared stack area B and a dedicated stack area A. The fact that the stack area used by each of the tasks P2, P3 and P4 is B is recognized by the address of the RAM 13 pointed to by each of the stack instruction data SPD2, SPD3 and SPD4. The fact that the stack area used by the task P1 is A indicates that the stack indication data SPD1 corresponding to the task indicates R
It is recognized by the address of AM13. In the figure, when the task P2 is allocated to the stack area B and is in the execution state, information (task number) indicating the task P2 using the stack area B is written by the CPU 11 in the stack management variable area Bd. I have. At this time, if there is an execution request for another task P3 sharing the stack area B, the CPU 11 sends the stack matrix management pointer B
The task management table TCB3 corresponding to the task P3 in p
Is described and connected to the stack matrix management pointer Bp. Subsequently, when there is a request to execute the task P4,
The CPU 11 further sets the pointer of the task management table TCB3 to the task management table TCB4 corresponding to the task P4.
Are described to form a stack queue. On the other hand, when the execution of the task P1 is not requested, the CPU 11 describes information indicating “free” (ie, unused) in the stack management variable area Ad corresponding to the dedicated stack area A. Also, information for connecting tasks is not described in the stack matrix management pointer Ap, and the stack matrix management pointer Ap is in an “empty” state.

FIG. 13 shows a flowchart of the task allocation control to the stack area when a task execution request is made. This content corresponds to the more detailed one corresponding to FIG.

First, when there is an execution request for one of the tasks in the suspended state, the CPU 11 obtains a stack area used by the task from the stack instruction data (SPD) of the requested task (S31). . For example, in FIG. 12, when there is a request to execute task P2, C
PU11 is stack instruction data SP corresponding to task 2.
The stack area B is recognized based on the address of the RAM 13 indicated by D2.

Next, the CPU 11 sets the stack area B
Is used to obtain information for determining whether there is another task in the execution state from the stack management variable area Bd corresponding to the stack area B (S32). CPU1
1 uses the stack instruction data to refer to the stack management variable area. For example, focusing on the task P2 in FIG. 12, the CPU 11 determines that the stack instruction data SPD2
By accessing the next higher address of the address of the RAM 13 indicated by, the corresponding stack management variable area Bd is referred to.

As a result of referring to the stack management variable area, if the area is in an "empty" state, the CPU 11 determines that the stack area is unused. On the other hand, when information such as a task number is held in the area, the CPU 11 determines that the task is being used by another task (S33). For example, as shown in FIG.
In a state where information meaning the task P2 is described in the stack management variable area Bd, when the CPU 11 refers to the stack management variable area Bd in accordance with the execution request of the task P3 sharing the stack area B, the task P2 Is assigned to the stack area B. In FIG. 12, the stack management variable area Ad
Is "empty", the CPU 1 responds to the execution request of the task P1 which intends to use the stack area A.
When 1 refers to the stack management variable area Ad, it is determined that the stack area A is unused.

If it is determined in step S33 that the task is being used, the task requested to be executed this time is linked to the stack matrix management pointer (S34). Then, the task is put into a waiting state to delay the execution (step S3).
5). For example, as shown in FIG. 12, when the task P2 is in the execution state and there is an execution request for another task P3 sharing the stack area B, the CPU 11 executes the task management table corresponding to the task P3. The pointer (pointer 21B in FIG. 11) address of TCB3 is described and connected to the stack matrix management pointer Bp. Subsequently, when there is a request to execute the task P4, the CPU 11 further describes a pointer address of the task management table TCB4 corresponding to the task P4 in a pointer of the task management table TCB3 to form a stack queue.

If it is determined in step S33 that the task is unused, the CPU 11 writes the corresponding task number in the corresponding stack management variable area (S36). Then, the task is set in an executable state (S37).

In particular, according to this embodiment, tasks sharing the stack area and tasks occupying the stack area are mixed, and the stack management variables are allocated to the dedicated stack areas such as the stack areas A and D. Have been. Therefore, the stack area allocation control procedure at the time of a task execution request can be the same for the shared stack area and the dedicated stack area. Therefore, the creation of the OS program can be simplified.

FIG. 14 is a flowchart showing an example of the task allocation control at the end of the execution of the task. This content corresponds to FIG. 2 and has more detailed contents in consideration of handling of the task whose execution start is delayed and release of the stack area.

First, when the execution of the task is terminated, C
The PU 11 obtains the stack area occupied by the task from the stack instruction data (S41). Next, C
The PU 11 refers to the corresponding stack matrix management pointer based on the address of the RAM 13 indicated by the stack instruction data, and acquires information for determining whether a task is connected to the stack queue (S42). And CP
U11 determines whether there is a task management table constituting the stack queue based on the information (S11).
43).

If there is no corresponding task management table as a result of the determination in step S43, the CPU 11
Writes information meaning "empty" in the corresponding stack management variable (S44). As a result, the stack area can be allocated to a predetermined task whose execution has been requested thereafter.

If the result of the determination in step S43 indicates that there is a task management table constituting the stack queue, the CPU 11 removes one task management table included in the stack queue from the stack queue and removes the stack queue. The matrix is updated (S45). Which task management table to remove, as explained in Fig. 2,
The priority is determined in consideration of the priority of the tasks included in the stack queue, the length of the waiting time, or the length of time required for executing the tasks. Then, the CPU 11 describes the number of the task corresponding to the task management table removed from the stack queue in the corresponding stack management variable area (S46). Further, the CPU 11 adds the task management table removed from the stack queue to the execution queue this time, and makes the task corresponding to the task management table executable (S47).

Although the stack area is not particularly limited, the CPU may be used in response to a parameter transfer to a subroutine in a task, a storage area for a return address from a subroutine, or a request to execute a task having a relatively high priority. When a task that has been assigned and is in an execution state is interrupted, it is used as a save area for various register information necessary for resuming execution of the task to be interrupted. In the register information save area, the value of the program counter PC, the value held in the condition code register CCR, the value of the stack pointer STKP, the data held in the general-purpose register group Rn, and the like are saved as shown in FIG.

FIG. 15 shows an example of how the stack area is used in the task execution state. For example, task P
Focusing on the execution state of “KEI 2”,
When branching to the subroutine "SAN", the parameters "X, Y" for the subroutine are delivered to the shared stack area B to which the task P2 is allocated, and the return address from the subroutine, for example, "100"
"0 address" is held. At this time, the stack pointer ST
The KP is preset by the holding address of the stack instruction data SPD2, holds this as the start address of the stack area B, and is sequentially decremented for each stack operation. And the subroutine "KEISAN"
During the execution of the subroutine "KEISAN", if a task having a higher priority than the task P2 (using a stack area different from that of the task P2), for example, a task P1 execution request is interrupted, the subroutine "KEISAN" is used up to that time. The information of the various registers, for example, the value of the program counter PC, the condition code register CCR, the value of the stack pointer STKP, and the like are saved in the stack area B, and thereafter, the execution of the task P2 is interrupted.

Here, the method of registering a task, that is, making the task recognizable by the OS, is performed by combining the OS and an application program to construct a load module to be loaded into the ROM.
There is a method of making a task recognizable and a method of using a system call for creating or deleting a task. At this time, in the above description, the OS recognizes which task shares which stack area with the stack instruction data paired with each task. Therefore, in a system using an OS that supports the task allocation control to the shared stack area, if the number of tasks that can be registered is intended for an application program that has a sufficient capacity with respect to the capacity of the entire stack area, it is not necessarily shared. In some cases, it is not necessary to set a stack area. In such a case, all the stack areas may be dedicated areas corresponding to tasks one-to-one. When all the stack areas are dedicated areas, it is not necessary to secure a stack control area such as a stack management variable area or a stack matrix management pointer, and the corresponding stack area is simply allocated in response to a task activation request. Allocate it to the stack area. Considering this, the OS that supports the task allocation control to the shared stack area is provided with an OS such as a stack management variable area and a stack matrix management pointer when a task area registration state recognizes a shared state of the stack area by a plurality of tasks. By providing a function to secure the stack control area, it is possible to perform optimal stack area allocation control for the system.

FIG. 16 shows an example of a time chart of the OS and tasks applied to the data processing system of FIG. It should be noted that the task P1 is shown in FIG.
Through P5 are shown. Note that the stack areas and priorities of these tasks P1 to P5 are based on FIG.

When the data processing system is started,
In response, an initialization program (not shown), for example, task P11 is executed, and RAM 13 is executed.
According to the initialization data table 99 shown in FIG.
The address of the RAM 13 is initialized as shown in FIG. The last program word of the initialization program includes, for example, an instruction str_tskP1 for requesting execution of the task P1.
The OS makes the task P1 executable according to the instruction. That is, the instruction str_tsk in the task P1 is a system call instruction, that is, an instruction for calling a subroutine task start (start-task) for bringing a task in the OS into an execution state. The program flow chart shown in FIG. 13 corresponds to this subroutine.

The task P1 is regarded as the main program of the data processing system. The program includes a program for rotating the motors M1 to M3 at a predetermined speed and a program for speed adjustment. As shown, the internal program of the task P1 includes instructions str_tskP2, str_tskP3, st for requesting execution of the tasks P2, P3, and P4.
r_tskP4 is included. Therefore, task P1 requests execution of tasks P2, P3 and P4 one after another. As a result, in response to the system call instruction str_tskP2, the subroutine start-task in the OS is started, and the shared stack area B is allocated to the task P2 to make it executable. And the next system call instruction str
The subroutine start task (start_task) is started again in response to _tskP3. The task P3 shares the stack area B with the task P2, and
Since the task P2 has already been assigned to the stack area B, the task P3 is connected to the stack queue. Similarly, the system call instruction str_tskP
4 again in response to subroutine start task (sta
rt_task) is started, but since the task P4 shares the stack area B like the task P3, the task P4 is also connected to the stack queue. Therefore, in the stack queue, the task P3 and the following task P4 are connected. At this time, task P3 and task P4 are also connected to the execution queue.

After that, the task P1 sets itself to the waiting state in FIG. 6 by the system call instruction str_tskP1 in the task P1. That is, the instruction stp_tskP1
Is the subroutine sleep task in the OS (sleep_
task). When the subroutine sleep task is activated, the data in the area 22 of the task management table TCB, which stores the status of the task, is set to the data indicating the wait state, and the corresponding task is set to the wait state.

Next, the task P in the executable state
2 is executed. The task P2 is, for example, a motor M1,
The program is a program for measuring each pulse signal S1 to S3 output from M2 and M3 by the timer 15.

At the end of the program word of the task P2, a system call instruction Ext_tskP2 is written. The system call instruction Ext_tskP2 is an instruction for calling the subroutine task end (Exit-task) of the OS, and the program flowchart of FIG. 14 is executed. Therefore, when the system call instruction Ext_tskP2 is executed, the task P2 is terminated (it is put into a sleep state), and the stack matrix management pointer is examined.

In this embodiment, since the execution request of the tasks P2 to P4 has been issued from the task P1, the OS removes the task P2 from the queue and sets the task P3 to an executable state. Then, the task P3 is executed. The task P3 transmits the measurement data obtained in the task P2 to the CPU 1
1 to obtain a rotational speed data of each of the motors M1 to M3.

Next, when the execution of the task P3 is terminated (set to a sleep state) in accordance with the system call instruction Ext_tskP3, the OS removes the task P3 from the queue and sets the task P4 to an executable state. And
Task P4 is executed.

The task P4 is a program for displaying the speed data obtained in the task P3 on the display device 52. The execution of the task P4 is performed by the system call instruction Ext_
In accordance with tskP4, the process is terminated (rested). In the program of the task P4, a system call instruction wup_tskP1 is written before the system call instruction Ext_tskP4. The system call instruction wup_tsk is an instruction for calling a subroutine wakeup task (wakeup-task) in the OS, and the task placed in a waiting state is thereby made executable. Therefore, in FIG. 16, the task P1 is a task in the waiting state, and the system call instruction wup_tskP1 returns the task P1 to the executable state. That is, the data in the area 22 storing the task state in the task management table TCB1 of the task P1 is rewritten from data indicating the waiting state to data indicating the execution state.
Then, the task P1 is executed. As a result, the program in task P1 for setting the rotation speed of the motor to a predetermined value is about to be executed based on the combination of task P3.

In FIG. 16, a system call instruction istr_tskP5 is generated by an input from the keyboard 51 thereafter. This system call instruction istr_t
sk is a command issued in response to data such as an external key input, and is a task execution request command from a non-task unit. This instruction istr_tsk is a task start (start ta) for a subroutine non-task part in the OS.
sk for task-independent p
instruction) to call out (orion). By the subroutine, the execution of the task P1 is suspended, the task P1 is put into a waiting state, and the task P5 is executed. Therefore, a task execution request can be issued by an external input that does not depend on the task. The task P5 includes, for example, output signals 01 to 0 for stopping rotation of the motors M1 to M3.
3 is output from the single-chip microcomputer 10 as a program. In this way, the OS executes tasks P1 through P
5 is controlled.

According to the above embodiment, the following effects can be obtained.

(1) The same stack area is shared by a plurality of tasks, and the assignment of tasks to the shared stack area is exclusively controlled with the unit from the start to the end of task execution as one unit, so that the stack by batch memory pooling Processing for allocating a stack area to a task can be simplified as compared with dynamic area allocation control or control using virtual storage. At the same time, the memory utilization efficiency for the stack area in the multitask processing system can be improved. This memory utilization efficiency is
It increases as the degree of sharing with the stack area increases. In order to increase the degree of sharing with the stack area, it is sufficient to employ a large number of tasks whose sequence is uniquely determined, in other words, it is most suitable for controlling devices whose operation patterns are often limited. It is.

(2) As described above, if the memory use efficiency for the stack area in the multitask processing system is improved, the number of executable or registerable tasks can be increased even if the memory area that can be allocated as the stack area is limited. Can be prevented from being restricted. Therefore, even if the memory area that can be allocated as a stack area is limited as in a one-chip microcomputer,
The OS can flexibly correspond to various user programs or application programs constituting a task.

(3) When a shared stack area and a dedicated stack area are mixed, a stack control area such as a stack management variable area and a stack matrix management pointer is secured for the dedicated stack area. The same procedure as described with reference to FIGS. 13 and 14 can be employed for the task allocation control to the stack area, and the stack allocation control can be further simplified.

(4) In contrast to conventional stack area dynamic pooling control by stack area batch pooling, a stack queue makes it clear which task is being delayed by which task, and this is determined by other appropriate methods. It can also be used for process sequences.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist of the invention. No.

For example, in the above-described embodiment, a case has been described in which a task whose execution is to be delayed by the task allocation control to the shared stack area is connected by a pointer to form a stack queue and managed, but a task whose execution is to be delayed is described. A method such as array management in which the number information or the task management table address thereof is written and managed in a specific area in order can be adopted.
However, such an approach is expected to use a small amount of memory compared to the stack queue.

When considering the real-time nature of the OS or the urgent execution of a task, it is necessary to secure a stack area that can be commonly used by any task in advance and to deal with events that occur asynchronously. What is necessary is just to be able to cope with the priority execution of the task that does not become unnecessary.

Further, in realizing the task allocation control to the shared stack area, the method for enabling the OS to recognize which task shares which stack area is not limited to the description of the above-described embodiment. There are the following methods for logically or implicitly connecting a task and a stack area. (A) A task or a task group sharing a stack area is recognized by the OS using a table. (B) At the time of task registration, such as generation of a load module or task, a stack area to be used by the registered task is designated. If the same stack area as another task is designated at that time, the designation is made. Shared stack area. (C) Tasks having the same priority are automatically made to share the same stack area. (D) Another task is designated at the time of task registration, and the stack area used by the designated task is shared by the task to be registered. (E) The stack area for the task in which the task is registered is shared by the task to be registered.

In the above description, the case where the invention made by the present inventor is mainly applied to a one-chip microcomputer which is the field of application as the background has been described. Widely applicable to computer systems.

The present invention can be widely applied to a system that requires at least an OS to manage tasks and controls the execution of the tasks, subject to multitask control.

[0084]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since one task is shared by a plurality of tasks, there is an effect that the memory use efficiency for the stack area can be improved.

As a result, there is an effect that the multitask processing by the OS can be realized even in a system in which satisfactory multitask processing cannot be performed satisfactorily due to insufficient memory capacity.

In addition, even when the memory area that can be allocated as the stack area is limited, there is an effect that the limitation on the number of tasks that can be executed or registered can be relaxed.

Furthermore, by exclusively controlling the allocation of tasks to the shared stack area with the execution from the start to the end of each task as one unit, complicated memory control becomes unnecessary, and the program size is reduced. The processing can be sped up.

Further, even if the memory area that can be allocated as a stack area is limited as in a one-chip microcomputer, the OS can flexibly cope with various user programs or application programs constituting tasks to be managed. enable.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating one example of the principle of the stack control method according to the present invention, focusing on processing when a task execution request is issued;

FIG. 2 is a flowchart illustrating an example of a principle of the stack control method according to the present invention, focusing on processing at the end of execution of a task.

FIG. 3 is a diagram illustrating an example of a state where execution of a task is delayed by the process of FIG. 1;

FIG. 4 is an explanatory diagram illustrating an example of a sharing relationship of a stack area by a task;

FIG. 5 is an explanatory diagram of an example relationship between a multitask control OS and a task.

FIG. 6 is an example state transition diagram when the multitask control OS manages a task.

FIG. 7 is a block diagram showing an embodiment of a one-chip microcomputer according to the present invention.

FIG. 8 is an example address map of the microcomputer shown in FIG. 7;

FIG. 9 is a partial address map in a built-in ROM of the microcomputer shown in FIG. 7;

FIG. 10 is an address map of a built-in RAM of the microcomputer shown in FIG. 7;

FIG. 11 is an explanatory diagram of an example of a task management table.

FIG. 12 is an explanatory diagram illustrating an example of a relationship between a task, a stack area, and a stack control area;

FIG. 13 is a flowchart illustrating an example of task allocation control for a stack area when a task execution request is issued;

FIG. 14 is a flowchart illustrating an example of task allocation control focusing on the end of task execution in consideration of handling of a task whose execution start is delayed and release of a stack area.

FIG. 15 is a diagram illustrating an example of a stack area in a task execution state;

FIG. 16 is an explanatory diagram illustrating an example of a time chart of an OS execution state and a task execution state of a CPU;

[Explanation of symbols]

 OS Operating system P1 to P11 Tasks A to E Stack area 10 Microcomputer 11 Central processing unit 12 ROM 13 RAM 14 I / O interface 15 Timer SPD1 to SPDi Stack instruction data TCB1 to TCBi Task management tables Ad to Ed Stack management variables Ap to Ep stack matrix management pointer 21 pointer group 24 execution queue management pointer

Continuation of the front page (56) References JP-A-63-86035 (JP, A) JP-A-62-165243 (JP, A) JP-A-63-201730 (JP, A) JP-A-3-163630 (JP, A) , A) JP-A-60-103457 (JP, A) JP-A-63-113738 (JP, A) JP-A-1-120636 (JP, A) Osamu Morikawa, "Securing a stack area in a resident program", Interface, Vol. 16, No. 8, CQ Publishing Co., Ltd., August 1990, pp. 251-255 (Patent Office CSDB Document No .: CSNW 199800227010) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/46 G06F 12/00 G06F 9/40-9/42 JICST file (JOIS) CSDB (Japan Patent Office)

Claims (9)

(57) [Claims] 1. A central processing unit capable of executing control multiple tasks under the management by the operating system, data
A stack area to be used for
A central processing unit, wherein the central processing unit allows a plurality of tasks to share the same stack area, and is capable of exclusively controlling the assignment of tasks to the shared stack area in units from the start to the end of execution of those tasks. data processing system according to claim this <br/> and is. 2. The task allocation device according to claim 1 , wherein
As an exclusive control of only, when the execution of the task is requested, it is determined whether or not other tasks sharing the stack area is running, executing the task if it is not running
2. The data processing system according to claim 1, wherein if another task is being executed, processing for delaying execution of the task is performed. Wherein the central processing unit, the data processing according to claim 2, wherein the shared stack space to be allocated is performed is requested task, and requests from specific stack instruction information to the task System . 4. A stack management for determining whether or not the other task is being executed, by indicating that a task currently assigned to a shared stack area exists. 4. The data processing system according to claim 2, wherein the data processing is performed by referring to a variable.
M 5. The central processing unit performs a process of connecting a task whose execution start is delayed to a stack matrix management pointer unique to a shared stack area in order to delay the execution start. The data processing system according to any one of claims 2 to 4, wherein: 6. The task processing device according to claim 1, wherein the central processing unit allocates the task.
As an exclusive control, when execution of a task ends, it is determined whether or not there is another task that is sharing the stack area with that task and whose execution is delayed, and then when it is determined, further performs a process execution start is feasible for one task selected from among single or plurality of tasks is delayed
Data processing cis according to claim 2, characterized in that
Tem . 7. The central processing unit determines whether or not there is another task whose execution start is delayed by referring to the value of a stack matrix management pointer and determining whether or not there is another task. determining whether Luke not been connected to the task
7. The data processing system according to claim 6, wherein the data processing is performed by: Wherein said central processing unit, as the process that can perform one task chosen, the task,
8. The data processing system according to claim 6, wherein a process for connecting to an execution queue management pointer for forming a queue of executable tasks is performed . 9. A central processing unit and an operation of the central processing unit.
A first memory in which the operating system is stored and an operating system.
Central processing unit under the control of the
When the disk is executed, the second
And a central processing unit, comprising: a memory;
Under the management of the task system , a stack area is shared by a plurality of tasks to be multitasked , and the task uses the shared stack area exclusively from the start to the end of the execution of the task. A one-chip type microcomputer, wherein the microcomputer is assigned to the microcomputer.