JP3258975B2 - Error detection method of read data in video recording / reproducing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for detecting an error in read data in a video recording / reproducing apparatus.

[0002]

2. Description of the Related Art Images captured by a surveillance camera are
A recording device for compressing the compressed data by an image compression device and recording the compressed data on a video tape; and a reproducing device for reading the compressed data recorded on the video tape, expanding the read compressed data by an image decompression device, and outputting the expanded data. Video recording and playback devices have already been developed. In such a video recording / reproducing apparatus, there is a possibility that an error has occurred in data obtained by reading video data from a video tape by a video head during reproduction.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of detecting an error in read data in a video recording / reproducing apparatus which can easily detect that an error has occurred in read data. Aim.

Further, according to the present invention, it is possible to easily detect that an error has occurred in read data and to prevent a field in which the error has occurred from being reproduced and output. An object of the present invention is to provide a method for detecting an error in read data in a reproducing apparatus.

[0005]

SUMMARY OF THE INVENTION An error detecting method for read data in a video recording / reproducing apparatus according to the present invention comprises:
At the time of reproduction, an error of read data is detected in a video recording / reproducing apparatus which reads data from a recording medium for each block unit including a plurality of fields, stores the data in a memory, and sequentially reads data in the block from the memory to perform a reproducing process. In the method, a frame header inserted at a head position of the data of one field unit, a position separated by a predetermined number of words from the frame header, and / or a reproduction of each data of one field unit recorded on a recording medium. In some cases, the number of words from the frame header is inserted at the position where at least one error detection header can be specified in advance before the data at that position is stored in the memory, and the number of words inserted at the last position of the data in one field unit End code is included and read from the recording medium during playback. When storing the data in the memory, the frame header is checked from the data read from the recording medium, and when the frame header is detected, counting of the number of words is started, and a predetermined error detection header is inserted. When the count number corresponding to the position is reached, it is checked whether or not the error detection header exists, and if the error detection header cannot be checked, it is determined that an error has occurred.

When it is determined that an error has occurred, the pointer is returned to the address in the memory where the end code of the field immediately preceding the field is written, and the frame of the next field after the field where it is determined that the error has occurred is determined. The writing of data to the memory is stopped until the header is sent, and when the frame header of the field next to the field determined to have an error is detected, the pointer is advanced by one and the data of the field concerned is increased. Is preferably started.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR that records and reproduces images captured by a plurality of monitoring cameras will be described below with reference to the drawings.

[1] Description of Overall Configuration of Monitoring System FIG. 1 shows the overall configuration of the monitoring system.

The surveillance system comprises four video cameras (hereinafter referred to as surveillance cameras) 101 to 104 and video signals A to A obtained by these surveillance cameras 101 to 104.
D, the video multiplexer 105 for generating a time-division multiplexed video signal, a digital VTR 106 for compressing the time-division multiplexed video signal generated by the video multiplexer 105 and recording it on a video tape, and a digital VTR 106 for reproducing. And a monitor 107 for displaying a video selected by the video multiplexer 105 from the time-division multiplexed video signal.

The video multiplexer 105 outputs the video signal A of the surveillance camera 101 in a certain field period, outputs the video signal B of the surveillance camera 102 in the next field period, and outputs the video signal B of the surveillance camera 103 in the next field period. , And outputs the video signal D of the surveillance camera 104 in the next field period. I do.
The video signal obtained by time-division multiplexing the video signals from the plurality of monitoring cameras 101 to 104 in this manner is called a time-division multiplexed video signal.

In each field of the time-division multiplexed video signal output from the video multiplexer 105, camera numbers A, B, C, and D indicating which of the monitoring cameras 101 to 104 are the input video signals A to D. Are multiplexed in the vertical blanking period. Hereinafter, information multiplexed during the vertical blanking period is referred to as a VBI signal.

[0012] The time-division multiplexed video signal output from the video multiplexer 105 is sent to a digital VTR 106. In the digital VTR 106, the transmitted time-division multiplexed video signal is compressed and recorded on a video tape.

At the time of reproduction, the video multiplexer 105 reads a VBI signal for each field from a reproduction output (time-division multiplexed video signal) from the digital VTR 106, and the VBI signal is read out based on the camera number represented by the read VBI signal. Is determined as a video signal to be presented. If it is determined that the video signal is a video signal to be presented, the video of the field is stored in the image memory in the video multiplexer 105. When the video for the predetermined field is stored in the image memory, the video is read from the image memory and
Is displayed.

[2] Description of Recording Operation of Video Signal Processing Circuit of Digital VTR 106

FIG. 2 shows the configuration of the video signal processing circuit of the digital VTR 106.

At the time of recording, the video multiplexer 105
The analog video signal sent from the
Is converted into digital video data. The video data obtained by the decoder 11 is used to separate VBI information.
After the VBI data is separated by the encoding unit 12, it is sent to the difference block 13.

The VBI information separating / encoding unit 12 separates VBI data from the video data sent from the decoder 11 and sends the VBI data to a first FPGA (field programmable gate array) 14, and also converts the VBI data into a simpler signal. And sends it to the first FPGA 14.

FIG. 3 shows a specific example of encoding of VBI data.

The VBI signal included in the time division multiplexed video signal output from the multiplexer 105 is shown in FIG.
As shown in (a) and (b), they are multiplexed in the vertical blanking period of the 10th to 20th horizontal lines. The VBI signal contained in each of these horizontal lines is converted by the decoder 11 into 8 bits × 768 VBI data.

The VBI information separating / encoding unit 12 first
By slicing this VBI data at a predetermined level, as shown in FIG.
Convert to 68 data. Then, as shown in FIG. 3D, eight consecutive data are added to generate 3-bit data, and only the most significant bit is taken, thereby averaging. That is, if the added value of the eight data is 0 to 3 in decimal system, these eight data are set to 1
If the bit data is "0", and if it is 4 to 8 in decimal system, these eight data are converted to 1-bit data "1". As a result, 8-bit × 768 VBI data is converted into 1-bit × 96 VBI encoded data.

The decoding of such VBI encoded data is performed as follows. If the VBI encoded data is "1", the data is converted into eight data strings of all "1". VBI
If the encoded data is "0", the data is converted into eight data strings of all "0". Thus, first, the VBI encoded data is converted into 1 bit × 768 data. Next, 8 bits representing “0” are assigned to “0” data of 1 bit × 768 data, and “1”
8 bits representing "255" are assigned to the data of "1". As a result, a VBI of 8 bits × 768
Data is obtained.

The difference block 13 has a memory 31 and an addition / subtraction unit 32. The memory 31 stores information corresponding to the plurality of monitoring cameras 101 to 104,
Four storage areas EA, EB, EC and ED are provided corresponding to the camera numbers A, B, C and D. The memory 31 is controlled by the first FPGA 14.

FIG. 4 shows the operation at the time of recording the difference block 13.

The first FPGA 14 separates VBI information.
The camera number is decoded based on the VBI data sent from the encoding unit 12 and the camera number corresponding to the field input to the difference block 13 is determined.

The first FPGA 14 is provided for each field group consisting of fields to which the same camera number is added, which is included in the time-division multiplexed video data output from the VBI information separating / encoding unit 12. The video data is stored as basic video data in the areas EA, EB, EC, and ED corresponding to the camera numbers added to the field group in the memory 31 in a predetermined number of field cycles (for example, six vertical period cycles). At the same time, the video data is sent to the image compression / decompression circuit 15 through the addition / subtraction means 32.

In each field group consisting of fields to which the same camera number is added, which is included in the time-division multiplexed video data output from the VBI information separating / encoding unit 12, the field group in the memory 31 EA, EB, corresponding to the camera number added to
The video data of each field from the field where the video data is stored in EC and ED to the field where the video data is stored in the next area EA, EB, EC and ED is sent to the addition / subtraction means 32, The areas EA, EB,
The difference from the basic video data stored latest in EC and ED is obtained, and the obtained difference data is stored in the image compression / expansion circuit 15.
Sent to

In the example of FIG. 4, each of the monitoring cameras 101 to 10
4 are stored in the memory 31.
Area EA, EB, EC,
The video data is stored in the ED and sent to the image compression / decompression circuit 15.

The image data A1, B1, C1, D1 of the respective monitoring cameras 101 to 104 stored in the memory 31 are stored.
From the video data up to the next field stored in the memory 31, the difference between the video data stored in the memory 31 and the video data having the same camera number is calculated, and the obtained difference data is It is sent to the image compression / decompression circuit 15.

The video data (basic video data) sent to the image compression / decompression circuit 15 through the addition / subtraction means 32 is called I video data, and after the difference from the basic video data is obtained by the addition / subtraction means 32. Image compression / decompression circuit 15
Is referred to as P video data.

In the image compression / expansion circuit 15, the video data sent from the difference block 13 is compressed for each field unit by, for example, the JPEG system. The compressed video data (encoded data) obtained by the image compression / expansion circuit 15 is sent to the additional information / VBI information adding / separating unit 16.

On the other hand, the microcomputer 40 provides the additional information / VBI
I / P identification information indicating whether the compressed video data sent to the information adding / separating unit 16 is I video data or P video data, a camera number corresponding to the compressed video data, and VBI information encoded data are stored in the first data. And sends it to the additional information / VBI information adding / separating unit 16 together with the recording time information (information of the current year, month, day, minute, second).

The additional information / VBI information adding / separating unit 16 adds the I / P identification information corresponding to the compressed video data sent from the microcomputer 40 to the compressed video data obtained by the image compression / decompression circuit 15, Additional information such as a number and recording time information and VBI encoded data are added. The data to which the predetermined data has been added by the additional information / VBI information adding / separating unit 16 is the second FPGA 17.
Sent to

The second FPGA 17 has additional information / VBI
The data sent from the information adding / separating unit 16 is alternately written to the two memories 18 and 19 in units of a predetermined block including data for a plurality of fields, and each time one block of data is written to the memory, The data is read from the memory in which the writing of the data for one block is completed and sent to the formatter 20. In this example, one block is composed of 288 tracks of data including information on audio.

That is, the second FPGA 17 writes the data sent from the additional information / VBI information adding / separating unit 16 into one memory, for example, the first memory 18. When the writing of one block of data to the first memory 18 is completed, the memory for writing data is switched to the other second memory 19, and at the same time,
Reading of data from the first memory 18 is started.

The data read from the first memory 18 is sent to the formatter 20. When the reading of one block of data from the first memory 18 is completed, the reading is stopped.

Thereafter, when the writing of one block of data to the second memory 19 is completed, the memory for writing the data is switched to the first memory 18 and at the same time the second memory 19 is written.
Reading of data from the memory 19 is started. Second
The data read from the memory 19 is stored in the formatter 2
Sent to 0. When the reading of one block of data from the second memory 19 is completed, the reading is stopped. Thereafter, the same processing is repeated.

The formatter 20 converts the transmitted data into data having a data structure that can be recorded on a video tape. The data obtained by the formatter 20 is recorded on a video tape via a recording amplifier and a video head in the signal recording / reproducing unit 21. That is, as shown in FIG. 5, one block (28
Video data is recorded in units of (track). The video tape is stopped every time recording of data in units of one block is completed. The video tape runs for approximately 38 tracks from the start of the stop and stops.

The second FPGA 17 and the formatter 20 are controlled by the microcomputer 40.

[3] Description of operation during reproduction of video signal processing circuit

At the time of reproduction, data is read from the video tape by the video head in the signal recording / reproducing unit 21 for each block. The read video data is transmitted to the reproduction amplifier and formatter 2 in the signal recording / reproduction unit 21.
0 to the second FPGA 17.

The second FPGA 17 writes the sent data alternately in the two memories 18 and 19 in block units, and every time one block of data is written in the memory, one block of data is written. The data is read from the memory in which the data has been written, and the additional information
The information is sent to the information adding / separating unit 16.

The additional information / VBI information addition / separation unit 16 extracts additional information such as camera number, I / P identification information, time information, and V from the transmitted data for one field.
BI encoded data and the like are separated. The separated data is sent to the first FPGA 14 via the microcomputer 40.

The data after the predetermined data is separated by the additional information / VBI information adding / separating unit 16 is sent to the image compression / expansion circuit 15 and expanded for each field. The video data obtained by the image compression / decompression circuit 15 is sent to the difference block 13.

FIG. 6 shows the operation when the difference block 13 is reproduced.

The first FPGA 14 determines the camera number corresponding to the field input to the difference block 13 based on the camera number sent from the microcomputer 40, and determines the camera number corresponding to the field input to the difference block 13 based on the I / P identification information. It is determined whether the input field is an I image or a P image.

If the field input to the difference block 13 is an I-picture, the area EA corresponding to the camera number in the memory 31 corresponding to the field,
The video data is stored in the EB, EC, and ED, and the video data is sent to the VBI information decoding / VBI information adding unit 21 through the addition / subtraction means 32.

If the field input to the difference block 13 is a P-picture, the P-picture data (difference data) is sent to the addition / subtraction means 32, and the P-picture data corresponding to the camera number in the memory 31 corresponding to the field is sent. Areas EA, E
The sum with the I video data (basic video data) stored latest in B, EC, and ED is calculated. Then, the obtained video data is sent to the VBI information decoding / VBI information adding unit 21.

In the example of FIG. 6, the video data "A"
1 "," B1 "," C1 ", and" D1 "are stored in the areas EA, EB, EC, and ED in the memory 31 corresponding to the camera number corresponding to the field, and VBI information decoding / VBI is performed. The information is sent to the information adding unit 21.

The video data "A2-A" of the P video
1 "," B2-B1 "," C2-C1 "," D2-D
1 "is the I video data" A1 "," B1 "," C "stored latest in the areas EA, EB, EC, ED corresponding to the camera number corresponding to the field in the memory 31.
After adding 1 ”and“ D1 ”and returning to the original video,
The VBI information is sent to the VBI information decoding / VBI information adding unit 21.

VBI information decoding / VBI information adding unit 21
, The VBI encoded data separated by the additional information / VBI information adding / separating unit 16 is also sent from the first FPGA 14. The VBI information decoding / VBI information adding unit 21 outputs the VBI information transmitted from the first FPGA 14.
The encoded data is decoded by the method described above. Then, it adds the decoded VBI data corresponding to the video data to the video data sent from the difference block 13 to the VBI information decoding / VBI information adding unit 21.

VBI information decoding / VBI information adding unit 21
Thus, the video data to which the VBI data is added is returned to an analog video signal by the encoder 22, and then sent to the video multiplexer 105.

[4] Description of error processing during reproduction of video signal processing circuit

At the time of reproduction, there is a possibility that an error has occurred in data obtained by reading video data from a video tape by a video head. A method for detecting such an error and a process when an error is detected will be described.

FIG. 7 shows a format of data for one field recorded on a video tape.

The data block for one field is the first data block.
Header part 51, second header part 52, third header part 53,
Audio additional data section 54, audio data section 55
And a video data section 56. The first header section 51 has 32 words, the second header section 52 has 64 words, the third header section 53 has 64 words, the audio additional data section 54 has 32 words, and the audio data section 55 has 32 × m.
(M is an integer of 1 or more) words, the video data portion 56 is 32
× n (n is an integer of 1 or more) words,
The number of words 1 to 56 is determined so as to be 32 words × k (k is an integer) as shown in FIG. The audio additional data section 54 includes an audio data section 55
And data indicating m defining the number of words.

The first header section 51 has I / P identification information,
It includes additional information such as recording time information (year, month, day, hour, minute, and second), camera number, and the like. For example, “EXFFh” is used as the I / P identification information, and is inserted as a frame header at the head of the first header section 51.
Here, “EXFF” is 16 for “h” of “EXFFh”.
When "X" in "EXFF" is 0, it represents an I image, and when "X" is 1, it represents a P image.

The second header section 52 includes a quantization table (Q table). The third header section 53 contains VBI encoded data. At the head of the third header section 53, a first header for error detection (for example, “E4FFh”) is inserted.

At the beginning of the audio additional data section 54,
Error detection second header (for example, "E7FFh")
Is inserted. At the head of the video data section 56, a third header for error detection (for example, "D8FFh") is inserted. At the end of the video data portion 56, an end code (EOI; for example, "D9FFh") indicating the end of the video data portion is inserted.

At the time of reproduction, the second FPGA 17 converts the data sent from the formatter 20 into a frame header “EXFFh” and an error detection first header “E4FF”.
h ", a second header for error detection" E7FFh ", a third header for error detection" D8FFh "and an end code"
The data sent from the formatter 20 is written to the memory 18 or 19 while confirming D9FFh ".

The second FPGA 17 has a formatter 20
When the frame header “EXFFh” is detected from the data sent from the second FPGA 17 to the second FPGA 17, the counting of the number of words is started. Then, the first header for error detection "
When the count reaches the position corresponding to the position where “E4FFh” is inserted, it is checked whether or not the first header for error detection exists. If the first header for error detection cannot be checked, an error has occurred. Judge.

If the first header for error detection can be confirmed when the count corresponding to the position where the first header for error detection "E4FFh" is inserted is reached, the second header for error detection "E7FFh" is obtained. When the count reaches the position corresponding to the position where "" is inserted, it is confirmed whether or not the second header for error detection exists, and if the second header for error detection cannot be confirmed, an error has occurred. to decide.

If the second header for error detection can be confirmed when the count corresponding to the position where the second header for error detection "E7FFh" is inserted is reached, the third header for error detection "E7FFh" When the count reaches the position corresponding to the position where “D8FFh” is inserted, it is checked whether or not the third header for error detection is present. If the third header for error detection cannot be checked, an error has occurred. Judge.

The error detection third header “D8FF”
The count number corresponding to the position where "h" is inserted is obtained by obtaining data indicating m that defines the number of words of the audio data section 55 included in the audio additional data section 54.

When the second FPGA 17 determines that an error has occurred, the second FPGA 17 returns a pointer to the address where the end code (EOI) of the field immediately before the field is written, and returns to the field where it is determined that the error has occurred. The writing of data to the memory is stopped until the frame header of the next field is transmitted.
When the frame header of the field next to the field in which it is determined that the error has occurred is sent, the pointer is advanced by one and the writing of the data of the field is started.

[0065]

According to the present invention, it is possible to easily detect that an error has occurred in the read data.

Further, according to the present invention, it is possible to easily detect that an error has occurred in the read data and to prevent the field in which the error has occurred from being reproduced and output. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a monitoring system.

FIG. 2 is a block diagram illustrating a schematic configuration of a digital VTR.

FIG. 3 is a VBI by a VBI separation / VBI information encoding unit.
FIG. 3 is a schematic diagram for explaining a data encoding method.

FIG. 4 is a time chart showing an operation at the time of recording a difference block.

FIG. 5 is a schematic diagram showing that data is recorded on a video tape in block units.

FIG. 6 is a time chart showing an operation at the time of reproducing a difference block.

FIG. 7 is a schematic diagram showing a format for data of one field recorded on a video tape.

[Explanation of symbols]

 12 VBI separation / VBI information encoding unit 13 Difference block 14 First FPGA 15 Image compression / decompression circuit 16 Additional information / VBI information addition / separation unit 17 Second FPGA 18, 19 Memory 20 Formatter 21 Signal recording / reproducing unit 40 Microcomputer 31 memory 32 addition / subtraction means

Claims (2)

(57) [Claims] At the time of reproduction, a video recording / reproducing apparatus reads data from a recording medium for each block including a plurality of fields, stores the data in a memory, and sequentially reads data in the block from the memory to perform a reproducing process. In the error detection method of the read data, each data recorded in one field unit recorded on the recording medium is
The frame header inserted at the head position of the data in units of one field and data at a position separated from the frame header by a predetermined number of words and / or the number of words from the frame header at the time of reproduction are stored in the memory. At least one error detection header inserted at a position that can be specified beforehand and an end code inserted at the last position of the data of one field unit are included before the data is read from the recording medium during reproduction. When storing the data in the memory, the frame header is checked from the data read from the recording medium, and when the frame header is detected, counting of the number of words is started, and a predetermined error detection header is inserted. When the count corresponding to the position is reached, it is determined whether or not the error detection header exists. A method for detecting an error in read data in a video recording / reproducing apparatus, comprising: determining whether an error has occurred if a header for error detection cannot be confirmed. 2. When it is determined that an error has occurred,
Returns a pointer to the address in memory where the end code of the field immediately preceding the field was written,
Stop writing data to the memory until the frame header of the field next to the field determined to have an error is sent, and detect the frame header of the field next to the field determined to have an error 2. The method according to claim 1, wherein the pointer is advanced by one to start writing data in the field.