JP3128482B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for reducing the number of manufacturing steps in a method for manufacturing a CMOS semiconductor device.

[0002]

2. Description of the Related Art A method of manufacturing a CMOS semiconductor device of this type will be described with reference to FIGS. A reference numeral 51 shown in FIG. 13 denotes a semiconductor substrate, on which a pad oxide film 52 and a Si3 N4 film 53 are stacked and formed, and a resist film 54 having an opening is formed on the N-well formation region. After the Si 3 N 4 film 53 and the pad oxide film 52 are etched by
Is used as a mask to implant phosphorus ions (31P +) to form an N-well formation region 55.

Next, the resist film 54 is removed, and then the well is oxidized to form a LOCOS oxide film 56 for forming a well.
To form Subsequently, after the Si3N4 film 53 and the pad oxide film 52 are etched using the LOCOS oxide film 56 as a mask, boron ions (11B +) are implanted using the LOCOS oxide film 56 as a mask as shown in FIG. , A P-well formation region 57 is formed.

Next, as shown in FIG. 15, the whole surface of the substrate is well-diffused in an N 2 gas atmosphere at about 1150 ° C. for 4 hours to form an N-well region 58 and a P-well region 59. Subsequently, the LOCOS oxide film 56 on the substrate is etched, and a pad oxide film 60 and a Si3 N4 film 61 are formed thereon as shown in FIG. 16 to form P-channel and N-channel MOS transistor formation regions. After forming a resist film (not shown), the Si3N4 film 61 and the pad oxide film 60 are etched using the resist film as a mask. Then, as shown in FIG.
After forming a resist film 62 thereon, boron ions (11B
+) Is implanted to form a channel stopper layer formation region 63 in the P well region 59.

After the resist film 62 is removed, field oxidation is performed as shown in FIG.
A COS oxide film 64 is formed and a P well region 59 is formed.
A P + type channel stopper layer 65 is formed below the upper LOCOS oxide film 64. Subsequently, the Si3N4 film 61 and the pad oxide film 60 are etched using the LOCOS oxide film 64 as a mask. Then, after a gate oxide film 66 is formed by thermally oxidizing the substrate, a resist film 67 is formed on the N well region 58 as shown in FIG. 19, and boron ions (11B +)
By ion implantation for controlling the threshold voltage of the N-channel type MOS transistor below the gate oxide film 66 on the P-well region 59, a channel implantation layer 68 is formed.

Subsequently, after removing the resist film 67,
As shown in FIG. 20, a resist film 69 for masking the P-well region 59 side is formed, and ions for controlling the threshold voltage of the P-channel MOS transistor by boron ions (11B @ +) are formed in the N-well region 58. Implantation is performed to form a channel implantation layer 70. Next, the resist film 69 is removed, and a polysilicon layer for forming a gate electrode is formed on the entire surface of the substrate.
A gate electrode 71 is formed as shown in FIG. Next, after a resist film (not shown) is formed on the N-channel MOS transistor formation region, for example, phosphorus ions (31P +) or arsenic ions (75
As +) is implanted to form an N + type source / drain diffusion layer 72.
To form

Similarly, after a resist film (not shown) is formed on the P channel type MOS transistor formation region, for example, boron ions (11
B +) or boron fluoride ion (49BF2 +) was implanted to form the P + type source / drain diffusion layer 73. As described above, P-channel type and N-channel type MOS
Since two dedicated resist films are used to form the channel implantation layers 68 and 70 of the transistor, the number of manufacturing steps is disadvantageous.

Further, in order to make the threshold voltage control maskless, a method of adjusting the threshold voltage with the P-well concentration and the N-well concentration has also been used. However, this method is limited by the gate oxide film thickness and gate length, and can be used only in a specific case, and the setting of the threshold voltage is limited. In addition, the characteristics of the transistor may be degraded.

When manufacturing a CMOS semiconductor device of a multi-oxide process having gate oxide films of two different thicknesses based on such a technique, for example, four threshold voltages are set. A total of four mask alignment steps were required, two on the N-channel MOS transistor side and two on the P-channel MOS transistor side.

[0010] Therefore, the number of mask alignment steps is large, and the cost of the mask is increased, resulting in an increase in cost.

[0011]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a CMOS semiconductor device which reduces the number of manufacturing steps and facilitates setting of a threshold voltage.

[0012]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a CMO
After forming the N well region 6 and the P well region 7 on the S semiconductor substrate, the LOCO region formed on the N well region 6 is formed.
Using the S oxide film 4 as a mask, boron ions (11B +) are implanted to form a first implanted layer 8. Subsequently, the L
After the OCOS oxide film 4 is removed, the P channel type and N
A pad oxide film 9 and a Si3N4 film 10 are formed on the channel type normal level and high level MOS transistor formation regions. Then, a resist film 11 formed so as to cover the pad oxide film 9 and the Si3 N4 film 10 on the high-level MOS transistor formation region on the N-well region 6 and the P-well region 7 and a normal level on the P-well region 7 are formed. MO
Pad oxide film 9 on Si transistor formation region and Si3
After implanting boron ions (11B +) for the channel stopper layer using the N4 film 10 as a mask, the boron ions (11B +) for the second implant layer 13 are similarly implanted using the resist film 11 as a mask. It is implanted deeper than during the process, and is also implanted below the P-well region 7 through the pad oxide film 9 and the Si3 N4 film 10 on the normal level MOS transistor formation region.

Next, after removing the resist film 11, the substrate is field-oxidized to form a LOCOS oxide film 14 for element isolation and a channel stopper layer 15, and then the pad oxidation is performed using the LOCOS oxide film 14 as a mask. After etching the film 9 and the Si3N4 film 10, the substrate is thermally oxidized to form a first gate oxide film 16. Subsequently, boron ions (11B +) for the channel implantation layer 18 are formed on the entire surface of the substrate using the resist film 17 having an opening only on each of the normal level MOS transistor formation regions on the N well 6 and the P well 7 as a mask. After the implantation, using the resist film 17 as a mask, the gate oxide film on each of the normal level MOS transistor formation regions on the N-well 6 and the P-well 7 is etched. Thermally oxidize the N-well 6
And a second gate oxide film 19 having a different thickness is formed on the P well 7 and the P well 7, respectively.

The step of forming the normal level and the high level MOS transistors on the N well 6 and the P well 7, respectively, adjusts the respective threshold voltages.

[0015]

DETAILED DESCRIPTION OF THE INVENTION A multi-oxide process CM having two types of gate oxide films according to the present invention.
A method for manufacturing an OS semiconductor device will be described with reference to FIGS. 1 shown in FIG. 1 is a semiconductor substrate,
After a resist film 2 having an opening is formed on the N-well formation region, for example, phosphorus ions (31P +) are implanted at an acceleration voltage of about 160 KeV and an implantation amount of 5.0E12 to 1.0E13/cm@2 using the resist film 2 as a mask. For example, 5.0E12 means 5.0 times 10 to the 12th power.
Hereinafter, the same applies. Inject) to form an N-well formation region 3. When an N-type semiconductor substrate is used and its substrate concentration is used as it is, the ion implantation for forming the N-well is not required, so that the ion implantation step can be omitted.

Next, the resist film 2 is removed, and then the well is oxidized to form a LOC for forming a well as shown in FIG.
An OS oxide film 4 is formed. Subsequently, using the LOCOS oxide film 4 as a mask, for example, boron ions (11B +) are implanted at an acceleration voltage of about 80 KeV and a dose of 4.0E12/cm@2.
By implantation, a P-well formation region 5 is formed. In the case where a P-type semiconductor substrate is used and the substrate concentration is used as it is, the ion implantation step for forming the P-well is not required, so that the ion implantation step can be omitted.

Next, as shown in FIG. 3, the N well region 6 and the P well region 7 are formed by well diffusion over the entire surface of the substrate in an N 2 gas atmosphere at about 1150 ° C. for 4 hours.
Then, as shown in FIG. 4, using the LOCOS oxide film 4 as a mask, for example, boron ions (11B +) are implanted at an acceleration voltage of about 80 to 100 KeV, or boron fluoride ions (49BF2 +) are implanted at an acceleration voltage of about 160 KeV. A dose of 1.0E12 to 3.0E12 / cm2 is injected, and P
The first implant layer 8 is formed at the bottom of the well region 9.

Subsequently, the LOCOS oxide film 4 on the substrate
Is etched, and a pad oxide film 9 and Si3 N4 are formed thereon.
After laminating the film 10 and forming a resist film (not shown) on the P-channel type and N-channel type MOS transistor formation regions, the Si3N4 film 10 and the pad oxide film 9 are etched using the resist film as a mask ( (See FIG. 5). Then, as shown in FIG. 6, after forming a resist film 11 having an opening only on the LOCOS oxide film 14 forming region formed on the P well region 7 in a later step, the entire surface of the substrate is formed.
For example, boron ions (11B +) are implanted at an acceleration voltage of about 30 to 40 KeV and an implantation amount of 5.0E13/cm@2.
A channel stopper layer forming region 12 is formed in the P well region 7 on the substrate. Subsequently, an acceleration voltage higher than the above condition is set so that boron ions (11B +) are deeper than the above implantation through the resist film 11 and penetrate through the Si3N4 film 10 and the pad oxide film 9 which are not covered with the resist film 11. For example, an acceleration voltage of about 80 to 100 KeV and an injection amount of 1.
By implanting 0E12 to 3.0E12 / cm 2, a second implantation layer 13 is formed in the P-well region 9. The second
In many cases, the implantation layer 13 is not required, and the degree of freedom in controlling the threshold voltage increases by properly using the implantation layer 13 depending on the type of device required.

Next, after the resist film 11 is removed, field oxidation is performed as shown in FIG.
At the same time as forming the OS oxide film 14, a P + type channel stopper layer 15 is formed below the LOCOS oxide film 14 on the P well region 7. It should be noted that the injected first and second
Are diffused. Then, the LOC
The Si3N4 film 10 and the pad oxide film 9 are etched using the OS oxide film 14 as a mask. Then, as shown in FIG. 8, the substrate is thermally oxidized to about 400 to 100
A gate oxide film 16 having a thickness of 0 ° is formed.

Next, as shown in FIG. 9, openings are formed only on the normal level MOS transistor forming regions of the normal level and the high level MOS transistors formed on the N well and the P wells 6 and 7 in a later step. Resist film 1 having
Then, using the resist film 17 as a mask, for example, boron ions (11B +) are applied at an acceleration voltage of about 20 to 35K.
The channel implantation layer 18 is formed under the normal level MOS transistor formation region on the N well region 6 and the P well region 7 by eV implantation at a dose of 5.0E11 to 1.5E12 / cm2.

Subsequently, using the resist film 17 as a mask, the gate oxide film 16 on the normal level MOS transistor formation region is etched as shown in FIG. 10, and then the substrate is thermally oxidized again as shown in FIG. A gate oxide film 19 is formed as shown in FIG. Note that the normal level MOS
The thickness of the gate oxide film 19 on the transistor formation region is approximately 150 to 300 °, and the thickness of the gate oxide film 19 on the high-level MOS transistor formation region is approximately 45 °.
0 to 1200 °. After the gate oxide film 19 is formed, boron ions (11B +) are implanted, for example, using the LOCOS oxide film 14 as a mask, so that the degree of freedom in controlling the threshold voltage is further increased. The voltage is finely adjusted.

Next, a polysilicon layer for forming a gate electrode is formed on the entire surface of the substrate, and a resist film (not shown) is used as shown in FIG.
2, a gate electrode 20 is formed. Subsequently, as shown in FIG. 12, an LN diffusion layer 21 for an N-channel type high-level MOS transistor and an LP diffusion layer 22 for a P-channel type high-level MOS transistor are formed. 23, a P + diffusion layer 24 is sequentially formed.
Thus, a CMOS semiconductor device having two types of gate oxide films 19 on the N well and the P wells 6 and 7 is formed.

As described above, according to the present invention, two types of P-channel type and N-channel type MOSs of a normal level and a high level are provided.
In order to set each threshold voltage of the transistor, the N-channel type MOS transistor of the normal level is formed by ion implantation for forming a P-well (this can be omitted when a P-type substrate is used), the first implantation layer 8 and Due to the ion implantation process for forming the second implantation layer 13 and the channel implantation layer 18, the high-level N-channel MOS transistor is implanted for the P-well formation described above (this can be omitted when a P-type substrate is used). And an ion implantation process for forming the first implant layer 8, and a P-channel type MO having a normal level
The S-transistor is formed by ion implantation for forming an N-well (which can be omitted when an N-type substrate is used) and the ion-implantation step for forming a channel implantation layer 18, and the high-level P-channel MOS transistor is formed by using an N-well. The threshold voltage can be set by the ion implantation process (which can be omitted when a P-type substrate is used).
The four threshold voltages can be freely set without using four dedicated resist films as in the related art.

[0024]

As described above, according to the method of manufacturing the CMOS semiconductor device of the present invention, the threshold voltages of the P-channel type and N-channel type MOS transistors having the gate oxide films of two different thicknesses are set. In addition, four threshold voltages can be freely set without using four dedicated resist films, thereby simplifying the process flow and reducing the mask man-hour by about 20 to 30%. At the same time, throughput is improved.

Further, as compared with the conventional method of adjusting the threshold voltage with the P-well concentration and the N-well concentration, the gate oxide film thickness and the well concentration are not restricted and the transistor characteristics do not deteriorate. So what CMOS
It can also be applied to semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a CMOS semiconductor device of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 3 is a third sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the present invention;

FIG. 7 is a seventh sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention;

FIG. 8 is an eighth sectional view showing the method for manufacturing the CMOS semiconductor device according to the present invention;

FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 10 is a tenth cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention;

FIG. 11 is an eleventh sectional view showing the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 12 is a twelfth cross-sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention;

FIG. 13 is a first cross-sectional view illustrating a method for manufacturing a conventional CMOS semiconductor device.

FIG. 14 is a second cross-sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 15 is a third cross-sectional view showing a conventional method for manufacturing a CMOS semiconductor device.

FIG. 16 is a fourth cross-sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 17 is a fifth cross-sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 18 is a sixth sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 19 is a seventh sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 20 is an eighth cross-sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

FIG. 21 is a ninth cross-sectional view illustrating the method of manufacturing the conventional CMOS semiconductor device.

Claims (3)

(57) [Claims] A step of implanting one conductivity type impurity for a first implant layer into the one conductivity type semiconductor substrate using the LOCOS oxide film formed on the opposite conductivity type well region on the one conductivity type semiconductor substrate as a mask; Forming a pad oxide film and a Si3N4 film on a normal level and high level one conductivity type and reverse conductivity type MOS transistor formation region after etching the LOCOS oxide film; High level MO
Pad oxide film on Si transistor formation region and Si3 N4
Using the resist film formed so as to cover the film as a mask, the second
Implanting one conductivity type impurity for the implantation layer and shallowly implant it below the normal level MOS transistor formation region on the substrate by penetrating the pad oxide film and the Si3N4 film, and removing the resist film. process and, package on the substrate by the LOCOS oxide film as a mask to the substrate and field oxide to form a LOCOS oxide film for element isolation after
Forming a first gate oxide film by etching the silicon oxide film and the Si3N4 film and then thermally oxidizing the first gate oxide film; and forming a normal level MOS transistor on the normal level MOS transistor formation region and the reverse conductivity type well region on the substrate. Using a resist film having an opening only on the transistor formation region as a mask to inject impurities of one conductivity type for a channel implantation layer over the entire surface of the substrate;
Etching a gate oxide film on the S-transistor formation region; and thermally oxidizing the entire substrate after removing the resist film to form second gate oxide films having different thicknesses on the transistor formation region. Forming a normal level and a high level MOS transistor on the substrate and on the reverse conductivity type well region, respectively. 2. A step of implanting an impurity of the opposite conductivity type for the first implantation layer into the well of the opposite conductivity type using the LOCOS oxide film on the semiconductor substrate of one conductivity type as a mask, and etching the LOCOS oxide film. Forming a pad oxide film and a Si3N4 film on a normal-level and high-level one-conductivity-type and reverse-conductivity-type MOS transistor formation region; and a high-level MOS transistor on the one-conductivity-type substrate and the reverse-conductivity-type well region. Pad oxide film on the formation region and Si
Using a resist film formed so as to cover the 3N4 film as a mask, impurities of the opposite conductivity type for the second implantation layer are implanted, and pad oxidation is also performed below the normal level MOS transistor formation region on the opposite conductivity type well region. A shallow implantation through the film and the Si3N4 film; a step of field-oxidizing the substrate after removing the resist film to form a LOCOS oxide film for element isolation; and the substrate using the LOCOS oxide film as a mask. package of the above
Forming a first gate oxide film by etching the silicon oxide film and the Si3N4 film and then thermally oxidizing the first gate oxide film; and forming a normal level MOS transistor on the normal level MOS transistor formation region and the reverse conductivity type well region on the substrate. Implanting an impurity of the opposite conductivity type for the channel implantation layer over the entire surface of the substrate using a resist film having an opening only on the transistor formation region as a mask;
Etching a gate oxide film on the S-transistor formation region; and thermally oxidizing the entire substrate after removing the resist film to form second gate oxide films having different thicknesses on the transistor formation region. Forming a normal level and a high level MOS transistor on the substrate and on the reverse conductivity type well region, respectively. Forming a first conductivity type well region on the semiconductor substrate and a first conductivity type well region on the semiconductor substrate; and forming a first conductivity type well region in the one conductivity type well region using the LOCOS oxide film formed on the opposite conductivity type well region as a mask. Implanting one conductivity type impurity for an implantation layer, and, after etching the LOCOS oxide film, a pad oxide film and a Si3N4 film on a normal level and high level one conductivity type and reverse conductivity type MOS transistor formation region. Forming a resist film and an overlying one-conductivity-type well region over the entire surface of the reverse-conductivity-type well region and a pad oxide film and a Si3N4 film over a high-level MOS transistor formation region on the one-conductivity-type well region. Of one conductivity type for a channel stopper layer using the pad oxide film and the Si3N4 film on the normal level MOS transistor formation region as a mask. Implanting one conductivity type impurity for the second implantation layer deeper than in the implantation step using the resist film as a mask, and at the normal level MOS transistor formation region on the one conductivity type well region. Implanting also below the region through the pad oxide film and the Si3N4 film, forming the LOCOS oxide film for element isolation by removing the resist film and field-oxidizing the substrate, Pad oxidation on the one-conductivity-type and reverse-conductivity-type MOS transistor formation regions using the film as a mask
Forming a first gate oxide film by thermally oxidizing the substrate after etching the film and the Si3N4 film; and forming the first gate oxide film only on each normal level MOS transistor formation region on the one conductivity type and reverse conductivity type well regions. Using a resist film having an opening as a mask, injecting one conductivity type impurity for the channel implantation layer into the entire surface of the substrate; and using the resist film as a mask, each normal level on the one conductivity type and the opposite conductivity type well region. A step of etching a gate oxide film on the MOS transistor formation region; and, after removing the resist film, thermally oxidizing the entire surface of the substrate again to form a second film having a different thickness on the one conductivity type and the opposite conductivity type well regions. Forming a gate oxide film; and forming normal-level and high-level MOS transistors on the one conductivity type and the opposite conductivity type well regions on the substrate, respectively. Method of manufacturing a CMOS semiconductor device characterized by a step of forming.