JP3124361B2 - Memory data loading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory data loading device in a RISC processor.

[0002]

2. Description of the Related Art Generally, in a RISC processor,
When loading data from a memory, an instruction to set an address in one general-purpose register (in this instruction, an address is set by using a part of the instruction code as data, so that this instruction alone sets a target virtual address. It is necessary to execute an instruction sequence of calculating an actual virtual address using the address and a relative address based on the address and executing an instruction to load data.

FIG. 2 shows the configuration of a conventional memory data load device in such a RISC processor. In FIG. 2, a register file 1 is a portion for holding data, and instruction registers 2 and 3 are portions for storing fetched instructions. The address operation unit 4 calculates and outputs the address of the data,
The arithmetic and logical operation unit 5 is a part that performs arithmetic and logical operations using given data. The source data registers 6 and 7 are for storing data used in the arithmetic and logical operation unit 5, and the destination data register 8 is for storing the operation result of the arithmetic and logical operation unit 5.

Further, a data address line 9 is a portion for transmitting the data address calculated by the address operation unit 4 to an external data load unit (not shown), and a load data line 10 is a main storage device (not shown).
Is a part for transmitting the data loaded from the to the register file 1.

In such a conventional memory data loading device, an instruction for setting an address in one general-purpose register, an actual virtual address is calculated from the address and a relative address based on the instruction, and the data is calculated. When executing an instruction sequence consisting of instructions to be loaded, the operation was as follows.

I) An instruction for setting an address in one general-purpose register (hereinafter, referred to as a set instruction) is set in the instruction register 2, and an actual virtual address is calculated from the address and a relative address based on the address. An instruction for loading data (hereinafter referred to as a load instruction) is set in the instruction register 3.

Ii) Of the contents of the instruction register 2 (the instruction code of the set instruction), data representing an address (which is shifted to an address) is sent to the source data register 6.

Iii) The contents of the source data register 6 are sent to the arithmetic / logic operation unit 5, shifted and set in the destination data register 8.

Iv) Destination data register 8
Is written to one register in the register file 1. Here, for the first time, one of the register files 1
Since data to be used (data used as an address) is set in one of the registers, the contents of the register are set in the address operation unit 4.

V) The address operation unit 4 executes step i
The virtual address is calculated using the data obtained in v), and is output to the data address line 9.

Each of the steps i) to v) is executed in one cycle. In a conventional RISC processor, five cycles are required for memory data loading processing until a virtual address is output to the data address line 9.

[0012]

However, in such a conventional memory data load device, a shift operation is required when an address is set by the first instruction, and the shift operation is required by an arithmetic / logic operation unit. Since the execution of the next load instruction calculates the virtual address, it takes five cycles for the memory load process until the virtual address is output to the data address line as described above, and there is a problem that the memory load becomes slow. Was.

An object of the present invention is to provide a memory data loading device capable of realizing high-speed loading of memory data in a RISC processor.

[0014]

According to the present invention, there is provided a memory data load device comprising: an instruction register for storing a fetched instruction; and a content of the instruction stored in the instruction register.
Reads data representing the reference address from
A shifter that shifts a bit and outputs a reference address, and a content of the instruction stored in the instruction register.
Read the relative address to the reference address,
Relative address and the reference address output from the shifter.
To calculate and output the virtual address of the access destination from the
A dress arithmetic units, total by the address arithmetic unit
And a data address line for transmitting the calculated virtual address of the access destination to an external instruction fetch unit.

[0015]

According to the memory data load device of the present invention, when an instruction for loading data from a memory is executed, an instruction for setting an address in one general-purpose register, the address, and a relative address based on the instruction are used. , And simultaneously executes an instruction sequence composed of instructions for loading data to realize high-speed data loading from the memory.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram of one embodiment of the present invention. Similar to the circuit having the configuration of FIG. 2 shown as a conventional example, a register file 1, instruction registers 2 and 3, and an address operation unit 4 are shown. And arithmetic and logical operation unit 5
, Source data registers 6 and 7, a destination data register 8, a data address line 9, and a load data line 10.

As a characteristic part of the embodiment of the present invention, a shifter 11 is provided so that data is shifted according to a control signal and transmitted to the address operation unit 4.

Next, the operation of the memory data loading device having the above configuration will be described.

When executing an instruction sequence consisting of an instruction to set an address in one general-purpose register, an instruction to calculate an actual virtual address by using the address and a relative address based on the address, and to load data, Works like

1) A set instruction for setting an address in one general-purpose register is set in the instruction register 2, and a load instruction for calculating an actual virtual address using the address and a relative address based on the set instruction and loading data. Are set in the instruction register 3.

2) Of the contents of the instruction register 2 (the instruction code of the set instruction), data representing an address (which is shifted to an address) is sent to the source data register 6.

At the same time, data representing the address of the contents of the instruction register 2 (the instruction code of the set instruction) is sent to the address operation unit 4 as address data through the shifter 11.

3) The contents of the source data register 6 are sent to the arithmetic / logical operation unit 5, shifted and set in the destination data register 8.

At the same time, the address operation unit 4
However, the virtual address is calculated using the data obtained in the above step 2), and is output to the data address line 9.

4) Destination data register 8
Is written to one register in the register file 1.

In this way, an instruction sequence consisting of an instruction for setting an address in one general-purpose register, an instruction for calculating an actual virtual address based on the address and a relative address based on the address, and loading data is executed. is there.

In the case of this embodiment, the process can be performed in three cycles of the above steps 1) to 3) until the virtual address is output to the data address line 9. Thus, the number of cycles can be reduced by two compared to the five cycles of steps i) to v), and the speed of the data loading process can be increased.

[0029]

As described above, according to the present invention, an instruction register for storing a fetched instruction, a shifter for shifting and transmitting data in accordance with a control signal, and an instruction address operation for calculating an address of an instruction to be fetched are provided. Unit and an instruction address line for transmitting the instruction address calculated by the instruction address operation unit to an external instruction fetch unit. Therefore, an instruction for setting an address in one general-purpose register, the address, and a reference The instruction sequence for loading the memory data, which is composed of the instructions for calculating the actual virtual address with the relative address and loading the data, can be executed simultaneously, and the data can be loaded from the memory at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention.

FIG. 2 is a circuit block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Register file 2 Instruction register 3 Instruction register 4 Address operation unit 5 Arithmetic / logical operation unit 6 Source data register 7 Source data register 8 Destination data register 9 Data address line 10 Load data line 11 Shifter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-16444 (JP, A) JP-A-2-306339 (JP, A) JP-A-3-19029 (JP, A) JP-A-2- 195431 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/22-9/355

Claims (1)

(57) [Claims] An instruction register for storing a fetched instruction, and a reference based on the content of the instruction stored in the instruction register.
Read the data that represents the address that is
A shifter for outputting a reference address only shifted, from said contents of said instruction stored in said instruction register
Read the relative address to the reference address, and
Between the paired address and the reference address output by the shifter
From which the virtual address of the access destination is calculated and output.
And a temporary address of the access destination calculated by the address operation unit.
And a data address line for transmitting a virtual address to an external instruction fetch unit.