JP3194798B2 - Switch circuit with clamp function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit having a clamp function for controlling an output voltage to a predetermined value.

[0002]

2. Description of the Related Art FIG. 2 shows a switch circuit using a conventional PNP transistor. In this switch circuit, a transistor Q driven by an input signal (Vin)
2 is connected to a power supply V + via a resistor R1,
The emitter is connected to the reference potential (V-) via the resistor R2, the base of the transistor Q1 is connected to the collector of the transistor Q2, the emitter is connected to the power supply V +, and the collector is connected to the output terminal Vo. Is provided.

In such a switch circuit, the potential Vin of the input signal is set to a level such that the transistor Q2 is turned on when it is "High" and is cut off completely when it is "Low". I have.
Here, when the input potential Vin is "High", a current as shown in the following equation flows through the transistor Q2.

[0004]

(Equation 1)

[0005] A part of this current flows from the power supply V + via the resistor R1, and all the rest of the current flows through the transistor Q +.
1 base current. Here, the transistor Q1
Assuming that the current amplification factor is β, the output current Iout is β × I
_{When the} load becomes _B1 but the load connected to the output voltage terminal Vo is large, the potential of the output potential Vout approaches V +, and the transistor Q1 becomes saturated. In this case,
As the base current I _B1 increases, the apparent β of the transistor Q1 decreases. In particular, in the case of an integrated circuit, a parasitic transistor starts operating and a current flows in the substrate.

On the other hand, when the input potential Vin is "Low",
Since the transistor Q1 is cut off, the base potential of the transistor Q1 becomes V + and the transistor Q1 is cut off. Therefore, the output voltage terminal Vo
Is in an open state and has a potential determined by the connected load.

As described above, the potential of the output is changed from "High" (almost V +) to "Lo" by the potential Vin of the input signal.
w "(potential determined by the load), and the transistor Q1 operates as if it were a switching element.

However, as described above, when the transistor Q1 is saturated, a current flows in the substrate, and depending on the level, other devices may be adversely affected.
By further saturation, the transistor Q1
There is also a problem that the off-state speed of the transistor Q1 is reduced due to the excess charge accumulated in the base region of the transistor Q1.

Therefore, the above-mentioned problem has been solved by a switch circuit as shown in FIG. In this switch circuit, a diode D1 composed of a transistor is added between the base of the transistor Q1 and the collector of the transistor Q2, and a diode D2 composed of a transistor is added between the collector of the transistor Q1 and the collector of the transistor Q2 to the circuit configuration shown in FIG. Circuit.

In this configuration, the transistor Q
2 turns on and a current flows, the collector potential of the transistor Q1, that is, the output potential starts to rise,
This potential

[0011]

(Equation 2) At this point, the feedback current Ic4 starts to flow, and eventually the output potential Vout is fixed to the value obtained by the above equation (2), and the transistor Q1 does not saturate. The relationship between the currents when the transistor Q2 is turned on is as follows.

[0012]

(Equation 3) Therefore,

[0013]

(Equation 4) Is obtained. Here, assuming that β is sufficiently larger than 1, the equation (3) becomes

[0014]

(Equation 5) Becomes

[0015]

However, the above-described switch circuit has been conventionally generally used as a clamp circuit.
When adopted in C) and incorporated in a laminated structure, the following problem occurs.

First, the diode D2 shown in FIG.
In the case of an NPN transistor as shown in (a), when the transistor Q2 is turned off, the collector potential Vc of the transistor Q2 increases. At this time, when the potential of the output potential Vout is low, the reverse bias applied to the diode D2 increases, and a breakdown may occur between the emitter and base junctions of the transistor, thereby causing a malfunction.

When the diode D2 is constituted by a PNP transistor as shown in FIG. 4B, when the transistor Q2 is turned off, the collector potential Vc of the transistor Q2 increases. As in the case of the NPN transistor, when the potential of the output potential Vout is low, the reverse bias applied to the diode D2 increases. At this time,
Although the collector potential of the transistor used as the diode D2 becomes higher than the emitter potential, in some cases, there is a possibility that the emitter electrode functions as a gate, and a PMOS having an emitter and a collector as a source and a drain is formed and operates. Can cause Therefore, an object of the present invention is to provide a switch circuit having a clamp function, which is suitable for integration without forming a parasitic element.

[0018]

In order to achieve the above object, the present invention is driven by an input signal, a collector is connected to a power supply via a diode and a first resistor, and an emitter is connected via a second resistor. A first transistor connected to a reference potential and a base connected to the anode of the diode, the second transistor outputting a predetermined potential or switching to an open state in response to the driving of the first transistor. And a base connected to the collector of the first transistor, an emitter connected to the collector of the second transistor, a collector connected to the emitter of the first transistor, and In some cases, a third transistor configured to control the potential on the collector side of the second transistor to a constant potential is used. To provide a function switch circuit.

[0019]

In the switch circuit having the above configuration, when the first transistor is turned on, the collector potential of the second transistor tends to rise, but when the third transistor is turned on, a current starts to flow to the emitter. , Through the collector to the emitter of the first transistor. Also, when the first transistor is turned off,
Since the collector potential of the third transistor is always the lowest potential, the potentials of the collector and the emitter do not reverse, and malfunction due to the parasitic PMOS does not occur.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a switch circuit as an embodiment according to the present invention, and will be described. In this switch circuit, a transistor Q2 driven by an input signal (Vin) has a collector connected to the cathode of the diode D1, and an emitter connected via a resistor R2 to a reference potential (V-).
Connected to. The anode of the diode D1 is a resistor R
1 is connected to the power supply V +. The transistor Q1 has a base connected to the anode of the diode D1, an emitter connected to the power supply V +, and a collector provided with an output terminal Vo. Further, the base is connected to the collector of the transistor Q2, the emitter is connected to the collector of the transistor Q1, the collector is connected to the emitter of the transistor Q2, and the output is controlled and driven by the collector potential of the transistor Q2. A transistor Q3 is provided which branches a predetermined current from a power current and flows the reference current through a resistor R2.

In the switch circuit thus configured, when the transistor Q2 is turned on and the current flows as described above, the collector potential of the transistor Q1, that is, the output potential Vout tends to increase.

[0023]

(Equation 6) At this point, current starts to flow through the emitter of the transistor Q3. This current is fed back through the collector to the emitter of the transistor Q2. Neglecting the base currents I _B4 of the transistors Q3, the relationship of each current is given by the following equation.

[0024]

(Equation 7) Is obtained. Here, if β is sufficiently larger than 1, the expression (5) becomes the following expression.

[0025]

(Equation 8)

Equation (8) is equivalent to equation (4) shown in the conventional example. When the transistor Q2 is turned off, the collector potential Vc rises, but at the same time, the collector potential of the transistor Q3 becomes V-.

As described above, the switch circuit of this embodiment is
Since the collector potential of the transistor Q3 always becomes the lowest potential even when the transistor Q2 is turned off, the potentials of the collector and the emitter do not reverse.
A parasitic PMOS caused by inversion of the potentials of the collector and the emitter is not formed, and no malfunction occurs.

In this embodiment, a PNP transistor is used in the output stage. However, the present invention is not limited to this.
The same effect can be obtained by using an N-transistor, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0029]

As described above in detail, according to the present invention, it is possible to provide a switch circuit having a clamping function, which is suitable for integration without forming a parasitic element.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a switch circuit as an embodiment according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a switch circuit using a conventional PNP transistor.

FIG. 3 is a diagram illustrating a configuration example of a switch circuit configured to solve the problem of the switch circuit illustrated in FIG. 2;

FIG. 4 is a diagram illustrating a connection example in which a diode is configured by an NPN transistor and a PNP transistor;

[Explanation of symbols]

Q1, Q2, Q3: transistors, D1, D2: diodes, R1, R2: resistors.

Claims (1)

(57) [Claims] A first transistor driven by an input signal, a collector connected to a power supply via a diode and a first resistor, and an emitter connected to a reference potential via a second resistor; A base is connected to the anode, and outputs a predetermined potential in response to the driving of the first transistor, or switches to an open state.
A base is connected to the collector of the first transistor, an emitter is connected to the collector of the second transistor, a collector is connected to the emitter of the first transistor, and the first transistor is turned on. Sometimes the second
And a third transistor for controlling the collector-side potential of the transistor to a constant potential.